| stats.txt (10726:8a20e2a1562d) | stats.txt (10827:7f5467f2f8b8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.184750 # Number of seconds simulated 4sim_ticks 5184749789500 # Number of ticks simulated 5final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.184750 # Number of seconds simulated 4sim_ticks 5184749789500 # Number of ticks simulated 5final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 858252 # Simulator instruction rate (inst/s) 8host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34581252938 # Simulator tick rate (ticks/s) 10host_mem_usage 653812 # Number of bytes of host memory used 11host_seconds 149.93 # Real time elapsed on the host | 7host_inst_rate 812427 # Simulator instruction rate (inst/s) 8host_op_rate 1566083 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32734861616 # Simulator tick rate (ticks/s) 10host_mem_usage 599680 # Number of bytes of host memory used 11host_seconds 158.39 # Real time elapsed on the host |
| 12sim_insts 128677191 # Number of instructions simulated 13sim_ops 248045844 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 827904 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9015040 # Number of bytes read from this memory 19system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory --- 30 unchanged lines hidden (view full) --- 50system.physmem.writeBursts 173690 # Number of DRAM write bursts, including those merged in the write queue 51system.physmem.bytesReadDRAM 9865536 # Total number of bytes read from DRAM 52system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue 53system.physmem.bytesWritten 9446080 # Total number of bytes written to DRAM 54system.physmem.bytesReadSys 9871616 # Total read bytes from the system interface side 55system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side 56system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue 57system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one | 12sim_insts 128677191 # Number of instructions simulated 13sim_ops 248045844 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 827904 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9015040 # Number of bytes read from this memory 19system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory --- 30 unchanged lines hidden (view full) --- 50system.physmem.writeBursts 173690 # Number of DRAM write bursts, including those merged in the write queue 51system.physmem.bytesReadDRAM 9865536 # Total number of bytes read from DRAM 52system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue 53system.physmem.bytesWritten 9446080 # Total number of bytes written to DRAM 54system.physmem.bytesReadSys 9871616 # Total read bytes from the system interface side 55system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side 56system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue 57system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one |
| 58system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write | 58system.physmem.neitherReadNorWriteReqs 1619 # Number of requests that are neither read nor write |
| 59system.physmem.perBankRdBursts::0 9927 # Per bank write bursts 60system.physmem.perBankRdBursts::1 9220 # Per bank write bursts 61system.physmem.perBankRdBursts::2 9906 # Per bank write bursts 62system.physmem.perBankRdBursts::3 9744 # Per bank write bursts 63system.physmem.perBankRdBursts::4 9716 # Per bank write bursts 64system.physmem.perBankRdBursts::5 9338 # Per bank write bursts 65system.physmem.perBankRdBursts::6 9475 # Per bank write bursts 66system.physmem.perBankRdBursts::7 9515 # Per bank write bursts --- 187 unchanged lines hidden (view full) --- 254system.physmem.wrPerTurnAround::448-463 1 0.02% 99.68% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::480-495 4 0.08% 99.75% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::496-511 3 0.06% 99.81% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::512-527 5 0.09% 99.91% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads | 59system.physmem.perBankRdBursts::0 9927 # Per bank write bursts 60system.physmem.perBankRdBursts::1 9220 # Per bank write bursts 61system.physmem.perBankRdBursts::2 9906 # Per bank write bursts 62system.physmem.perBankRdBursts::3 9744 # Per bank write bursts 63system.physmem.perBankRdBursts::4 9716 # Per bank write bursts 64system.physmem.perBankRdBursts::5 9338 # Per bank write bursts 65system.physmem.perBankRdBursts::6 9475 # Per bank write bursts 66system.physmem.perBankRdBursts::7 9515 # Per bank write bursts --- 187 unchanged lines hidden (view full) --- 254system.physmem.wrPerTurnAround::448-463 1 0.02% 99.68% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::480-495 4 0.08% 99.75% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::496-511 3 0.06% 99.81% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::512-527 5 0.09% 99.91% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads |
| 262system.physmem.totQLat 1425327951 # Total ticks spent queuing 263system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM | 262system.physmem.totQLat 1425306951 # Total ticks spent queuing 263system.physmem.totMemAccLat 4315600701 # Total ticks spent from burst creation until serviced by the DRAM |
| 264system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers | 264system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers |
| 265system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst | 265system.physmem.avgQLat 9246.29 # Average queueing delay per DRAM burst |
| 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 267system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst | 267system.physmem.avgMemAccLat 27996.29 # Average memory access latency per DRAM burst |
| 268system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.03 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 281system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes 282system.physmem.avgGap 15810345.15 # Average gap between requests 283system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined 284system.physmem_0.actEnergy 212315040 # Energy for activate commands per rank (pJ) 285system.physmem_0.preEnergy 115846500 # Energy for precharge commands per rank (pJ) 286system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ) 287system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ) 288system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) | 268system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.03 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 281system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes 282system.physmem.avgGap 15810345.15 # Average gap between requests 283system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined 284system.physmem_0.actEnergy 212315040 # Energy for activate commands per rank (pJ) 285system.physmem_0.preEnergy 115846500 # Energy for precharge commands per rank (pJ) 286system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ) 287system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ) 288system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) |
| 289system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ) 290system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ) 291system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ) | 289system.physmem_0.actBackEnergy 133930593495 # Energy for active background per rank (pJ) 290system.physmem_0.preBackEnergy 2993365419750 # Energy for precharge background per rank (pJ) 291system.physmem_0.totalEnergy 3467346235185 # Total energy per rank (pJ) |
| 292system.physmem_0.averagePower 668.758961 # Core power per rank (mW) | 292system.physmem_0.averagePower 668.758961 # Core power per rank (mW) |
| 293system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states | 293system.physmem_0.memoryStateTime::IDLE 4979642480610 # Time in different power states |
| 294system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states 295system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 294system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states 295system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 296system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states | 296system.physmem_0.memoryStateTime::ACT 31977087390 # Time in different power states |
| 297system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 298system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 603002400 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 476182800 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 134835847830 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 2992571337000 # Energy for precharge background per rank (pJ) --- 101 unchanged lines hidden (view full) --- 406system.cpu.dcache.SoftPFReq_misses::cpu.data 403161 # number of SoftPFReq misses 407system.cpu.dcache.SoftPFReq_misses::total 403161 # number of SoftPFReq misses 408system.cpu.dcache.demand_misses::cpu.data 1231576 # number of demand (read+write) misses 409system.cpu.dcache.demand_misses::total 1231576 # number of demand (read+write) misses 410system.cpu.dcache.overall_misses::cpu.data 1634737 # number of overall misses 411system.cpu.dcache.overall_misses::total 1634737 # number of overall misses 412system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles 413system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles | 297system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 298system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 603002400 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 476182800 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 134835847830 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 2992571337000 # Energy for precharge background per rank (pJ) --- 101 unchanged lines hidden (view full) --- 406system.cpu.dcache.SoftPFReq_misses::cpu.data 403161 # number of SoftPFReq misses 407system.cpu.dcache.SoftPFReq_misses::total 403161 # number of SoftPFReq misses 408system.cpu.dcache.demand_misses::cpu.data 1231576 # number of demand (read+write) misses 409system.cpu.dcache.demand_misses::total 1231576 # number of demand (read+write) misses 410system.cpu.dcache.overall_misses::cpu.data 1634737 # number of overall misses 411system.cpu.dcache.overall_misses::total 1634737 # number of overall misses 412system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles 413system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles |
| 414system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles 415system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles 416system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles 417system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles 418system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles 419system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles | 414system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149973597 # number of WriteReq miss cycles 415system.cpu.dcache.WriteReq_miss_latency::total 12149973597 # number of WriteReq miss cycles 416system.cpu.dcache.demand_miss_latency::cpu.data 24985949815 # number of demand (read+write) miss cycles 417system.cpu.dcache.demand_miss_latency::total 24985949815 # number of demand (read+write) miss cycles 418system.cpu.dcache.overall_miss_latency::cpu.data 24985949815 # number of overall miss cycles 419system.cpu.dcache.overall_miss_latency::total 24985949815 # number of overall miss cycles |
| 420system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses) 421system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses) 422system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::total 8401894 # number of WriteReq accesses(hits+misses) 424system.cpu.dcache.SoftPFReq_accesses::cpu.data 462014 # number of SoftPFReq accesses(hits+misses) 425system.cpu.dcache.SoftPFReq_accesses::total 462014 # number of SoftPFReq accesses(hits+misses) 426system.cpu.dcache.demand_accesses::cpu.data 21323588 # number of demand (read+write) accesses 427system.cpu.dcache.demand_accesses::total 21323588 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 434system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872616 # miss rate for SoftPFReq accesses 435system.cpu.dcache.SoftPFReq_miss_rate::total 0.872616 # miss rate for SoftPFReq accesses 436system.cpu.dcache.demand_miss_rate::cpu.data 0.057757 # miss rate for demand accesses 437system.cpu.dcache.demand_miss_rate::total 0.057757 # miss rate for demand accesses 438system.cpu.dcache.overall_miss_rate::cpu.data 0.075037 # miss rate for overall accesses 439system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses 440system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency 441system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency | 420system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses) 421system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses) 422system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::total 8401894 # number of WriteReq accesses(hits+misses) 424system.cpu.dcache.SoftPFReq_accesses::cpu.data 462014 # number of SoftPFReq accesses(hits+misses) 425system.cpu.dcache.SoftPFReq_accesses::total 462014 # number of SoftPFReq accesses(hits+misses) 426system.cpu.dcache.demand_accesses::cpu.data 21323588 # number of demand (read+write) accesses 427system.cpu.dcache.demand_accesses::total 21323588 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 434system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872616 # miss rate for SoftPFReq accesses 435system.cpu.dcache.SoftPFReq_miss_rate::total 0.872616 # miss rate for SoftPFReq accesses 436system.cpu.dcache.demand_miss_rate::cpu.data 0.057757 # miss rate for demand accesses 437system.cpu.dcache.demand_miss_rate::total 0.057757 # miss rate for demand accesses 438system.cpu.dcache.overall_miss_rate::cpu.data 0.075037 # miss rate for overall accesses 439system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses 440system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency 441system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency |
| 442system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.674465 # average WriteReq miss latency 443system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.674465 # average WriteReq miss latency 444system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.768935 # average overall miss latency 445system.cpu.dcache.demand_avg_miss_latency::total 20287.768935 # average overall miss latency 446system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.372541 # average overall miss latency 447system.cpu.dcache.overall_avg_miss_latency::total 15284.372541 # average overall miss latency | 442system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.737593 # average WriteReq miss latency 443system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.737593 # average WriteReq miss latency 444system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.785581 # average overall miss latency 445system.cpu.dcache.demand_avg_miss_latency::total 20287.785581 # average overall miss latency 446system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.385082 # average overall miss latency 447system.cpu.dcache.overall_avg_miss_latency::total 15284.385082 # average overall miss latency |
| 448system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked 449system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked 451system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.301370 # average number of cycles each access was blocked 453system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 454system.cpu.dcache.fast_writes 0 # number of fast writes performed 455system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 468system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315593 # number of WriteReq MSHR misses 469system.cpu.dcache.WriteReq_mshr_misses::total 315593 # number of WriteReq MSHR misses 470system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403125 # number of SoftPFReq MSHR misses 471system.cpu.dcache.SoftPFReq_mshr_misses::total 403125 # number of SoftPFReq MSHR misses 472system.cpu.dcache.demand_mshr_misses::cpu.data 1222124 # number of demand (read+write) MSHR misses 473system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses 474system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses 475system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses | 448system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked 449system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked 451system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.301370 # average number of cycles each access was blocked 453system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 454system.cpu.dcache.fast_writes 0 # number of fast writes performed 455system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 12 unchanged lines hidden (view full) --- 468system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315593 # number of WriteReq MSHR misses 469system.cpu.dcache.WriteReq_mshr_misses::total 315593 # number of WriteReq MSHR misses 470system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403125 # number of SoftPFReq MSHR misses 471system.cpu.dcache.SoftPFReq_mshr_misses::total 403125 # number of SoftPFReq MSHR misses 472system.cpu.dcache.demand_mshr_misses::cpu.data 1222124 # number of demand (read+write) MSHR misses 473system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses 474system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses 475system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses |
| 476system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable 477system.cpu.dcache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable 478system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable 479system.cpu.dcache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable 480system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses 481system.cpu.dcache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses |
|
| 476system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles 477system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles | 482system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles 483system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles |
| 478system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117308860 # number of WriteReq MSHR miss cycles 479system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117308860 # number of WriteReq MSHR miss cycles | 484system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117329359 # number of WriteReq MSHR miss cycles 485system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117329359 # number of WriteReq MSHR miss cycles |
| 480system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles 481system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles | 486system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles 487system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles |
| 482system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586067642 # number of demand (read+write) MSHR miss cycles 483system.cpu.dcache.demand_mshr_miss_latency::total 22586067642 # number of demand (read+write) MSHR miss cycles 484system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213365142 # number of overall MSHR miss cycles 485system.cpu.dcache.overall_mshr_miss_latency::total 28213365142 # number of overall MSHR miss cycles | 488system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586088141 # number of demand (read+write) MSHR miss cycles 489system.cpu.dcache.demand_mshr_miss_latency::total 22586088141 # number of demand (read+write) MSHR miss cycles 490system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213385641 # number of overall MSHR miss cycles 491system.cpu.dcache.overall_mshr_miss_latency::total 28213385641 # number of overall MSHR miss cycles |
| 486system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles 487system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles 488system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles 489system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593293500 # number of WriteReq MSHR uncacheable cycles 490system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96957757000 # number of overall MSHR uncacheable cycles 491system.cpu.dcache.overall_mshr_uncacheable_latency::total 96957757000 # number of overall MSHR uncacheable cycles 492system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070156 # mshr miss rate for ReadReq accesses 493system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070156 # mshr miss rate for ReadReq accesses 494system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037562 # mshr miss rate for WriteReq accesses 495system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037562 # mshr miss rate for WriteReq accesses 496system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872538 # mshr miss rate for SoftPFReq accesses 497system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872538 # mshr miss rate for SoftPFReq accesses 498system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057313 # mshr miss rate for demand accesses 499system.cpu.dcache.demand_mshr_miss_rate::total 0.057313 # mshr miss rate for demand accesses 500system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074602 # mshr miss rate for overall accesses 501system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses 502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency 503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency | 492system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles 493system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles 494system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles 495system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593293500 # number of WriteReq MSHR uncacheable cycles 496system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96957757000 # number of overall MSHR uncacheable cycles 497system.cpu.dcache.overall_mshr_uncacheable_latency::total 96957757000 # number of overall MSHR uncacheable cycles 498system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070156 # mshr miss rate for ReadReq accesses 499system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070156 # mshr miss rate for ReadReq accesses 500system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037562 # mshr miss rate for WriteReq accesses 501system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037562 # mshr miss rate for WriteReq accesses 502system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872538 # mshr miss rate for SoftPFReq accesses 503system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872538 # mshr miss rate for SoftPFReq accesses 504system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057313 # mshr miss rate for demand accesses 505system.cpu.dcache.demand_mshr_miss_rate::total 0.057313 # mshr miss rate for demand accesses 506system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074602 # mshr miss rate for overall accesses 507system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses 508system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency 509system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency |
| 504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.728286 # average WriteReq mshr miss latency 505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.728286 # average WriteReq mshr miss latency | 510system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.793240 # average WriteReq mshr miss latency 511system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.793240 # average WriteReq mshr miss latency |
| 506system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency 507system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency | 512system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency 513system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency |
| 508system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18480.995089 # average overall mshr miss latency 509system.cpu.dcache.demand_avg_mshr_miss_latency::total 18480.995089 # average overall mshr miss latency 510system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.410861 # average overall mshr miss latency 511system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.410861 # average overall mshr miss latency 512system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 513system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 514system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 515system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 516system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 517system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 514system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18481.011862 # average overall mshr miss latency 515system.cpu.dcache.demand_avg_mshr_miss_latency::total 18481.011862 # average overall mshr miss latency 516system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.423474 # average overall mshr miss latency 517system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.423474 # average overall mshr miss latency 518system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 164165.785509 # average ReadReq mshr uncacheable latency 519system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164165.785509 # average ReadReq mshr uncacheable latency 520system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186353.370221 # average WriteReq mshr uncacheable latency 521system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186353.370221 # average WriteReq mshr uncacheable latency 522system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 164690.242353 # average overall mshr uncacheable latency 523system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 164690.242353 # average overall mshr uncacheable latency |
| 518system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 519system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements 520system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use 521system.cpu.dtb_walker_cache.tags.total_refs 12184 # Total number of references to valid blocks. 522system.cpu.dtb_walker_cache.tags.sampled_refs 8903 # Sample count of references to valid blocks. 523system.cpu.dtb_walker_cache.tags.avg_refs 1.368527 # Average number of references to valid blocks. 524system.cpu.dtb_walker_cache.tags.warmup_cycle 5156876909000 # Cycle when the warmup percentage was hit. 525system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.045606 # Average occupied blocks per requestor --- 101 unchanged lines hidden (view full) --- 627system.cpu.icache.overall_hits::cpu.inst 144962865 # number of overall hits 628system.cpu.icache.overall_hits::total 144962865 # number of overall hits 629system.cpu.icache.ReadReq_misses::cpu.inst 794984 # number of ReadReq misses 630system.cpu.icache.ReadReq_misses::total 794984 # number of ReadReq misses 631system.cpu.icache.demand_misses::cpu.inst 794984 # number of demand (read+write) misses 632system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses 633system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses 634system.cpu.icache.overall_misses::total 794984 # number of overall misses | 524system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 525system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements 526system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use 527system.cpu.dtb_walker_cache.tags.total_refs 12184 # Total number of references to valid blocks. 528system.cpu.dtb_walker_cache.tags.sampled_refs 8903 # Sample count of references to valid blocks. 529system.cpu.dtb_walker_cache.tags.avg_refs 1.368527 # Average number of references to valid blocks. 530system.cpu.dtb_walker_cache.tags.warmup_cycle 5156876909000 # Cycle when the warmup percentage was hit. 531system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.045606 # Average occupied blocks per requestor --- 101 unchanged lines hidden (view full) --- 633system.cpu.icache.overall_hits::cpu.inst 144962865 # number of overall hits 634system.cpu.icache.overall_hits::total 144962865 # number of overall hits 635system.cpu.icache.ReadReq_misses::cpu.inst 794984 # number of ReadReq misses 636system.cpu.icache.ReadReq_misses::total 794984 # number of ReadReq misses 637system.cpu.icache.demand_misses::cpu.inst 794984 # number of demand (read+write) misses 638system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses 639system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses 640system.cpu.icache.overall_misses::total 794984 # number of overall misses |
| 635system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253089237 # number of ReadReq miss cycles 636system.cpu.icache.ReadReq_miss_latency::total 11253089237 # number of ReadReq miss cycles 637system.cpu.icache.demand_miss_latency::cpu.inst 11253089237 # number of demand (read+write) miss cycles 638system.cpu.icache.demand_miss_latency::total 11253089237 # number of demand (read+write) miss cycles 639system.cpu.icache.overall_miss_latency::cpu.inst 11253089237 # number of overall miss cycles 640system.cpu.icache.overall_miss_latency::total 11253089237 # number of overall miss cycles | 641system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253068237 # number of ReadReq miss cycles 642system.cpu.icache.ReadReq_miss_latency::total 11253068237 # number of ReadReq miss cycles 643system.cpu.icache.demand_miss_latency::cpu.inst 11253068237 # number of demand (read+write) miss cycles 644system.cpu.icache.demand_miss_latency::total 11253068237 # number of demand (read+write) miss cycles 645system.cpu.icache.overall_miss_latency::cpu.inst 11253068237 # number of overall miss cycles 646system.cpu.icache.overall_miss_latency::total 11253068237 # number of overall miss cycles |
| 641system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses) 642system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses) 643system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses 644system.cpu.icache.demand_accesses::total 145757849 # number of demand (read+write) accesses 645system.cpu.icache.overall_accesses::cpu.inst 145757849 # number of overall (read+write) accesses 646system.cpu.icache.overall_accesses::total 145757849 # number of overall (read+write) accesses 647system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005454 # miss rate for ReadReq accesses 648system.cpu.icache.ReadReq_miss_rate::total 0.005454 # miss rate for ReadReq accesses 649system.cpu.icache.demand_miss_rate::cpu.inst 0.005454 # miss rate for demand accesses 650system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses 651system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses 652system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses | 647system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses) 648system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses) 649system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses 650system.cpu.icache.demand_accesses::total 145757849 # number of demand (read+write) accesses 651system.cpu.icache.overall_accesses::cpu.inst 145757849 # number of overall (read+write) accesses 652system.cpu.icache.overall_accesses::total 145757849 # number of overall (read+write) accesses 653system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005454 # miss rate for ReadReq accesses 654system.cpu.icache.ReadReq_miss_rate::total 0.005454 # miss rate for ReadReq accesses 655system.cpu.icache.demand_miss_rate::cpu.inst 0.005454 # miss rate for demand accesses 656system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses 657system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses 658system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses |
| 653system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.114112 # average ReadReq miss latency 654system.cpu.icache.ReadReq_avg_miss_latency::total 14155.114112 # average ReadReq miss latency 655system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency 656system.cpu.icache.demand_avg_miss_latency::total 14155.114112 # average overall miss latency 657system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency 658system.cpu.icache.overall_avg_miss_latency::total 14155.114112 # average overall miss latency | 659system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.087696 # average ReadReq miss latency 660system.cpu.icache.ReadReq_avg_miss_latency::total 14155.087696 # average ReadReq miss latency 661system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency 662system.cpu.icache.demand_avg_miss_latency::total 14155.087696 # average overall miss latency 663system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency 664system.cpu.icache.overall_avg_miss_latency::total 14155.087696 # average overall miss latency |
| 659system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 660system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 661system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 662system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 663system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 664system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 665system.cpu.icache.fast_writes 0 # number of fast writes performed 666system.cpu.icache.cache_copies 0 # number of cache copies performed 667system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794984 # number of ReadReq MSHR misses 668system.cpu.icache.ReadReq_mshr_misses::total 794984 # number of ReadReq MSHR misses 669system.cpu.icache.demand_mshr_misses::cpu.inst 794984 # number of demand (read+write) MSHR misses 670system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses 671system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses 672system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses | 665system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 666system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 667system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 668system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 669system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 670system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 671system.cpu.icache.fast_writes 0 # number of fast writes performed 672system.cpu.icache.cache_copies 0 # number of cache copies performed 673system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794984 # number of ReadReq MSHR misses 674system.cpu.icache.ReadReq_mshr_misses::total 794984 # number of ReadReq MSHR misses 675system.cpu.icache.demand_mshr_misses::cpu.inst 794984 # number of demand (read+write) MSHR misses 676system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses 677system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses 678system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses |
| 673system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055827763 # number of ReadReq MSHR miss cycles 674system.cpu.icache.ReadReq_mshr_miss_latency::total 10055827763 # number of ReadReq MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055827763 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.demand_mshr_miss_latency::total 10055827763 # number of demand (read+write) MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055827763 # number of overall MSHR miss cycles 678system.cpu.icache.overall_mshr_miss_latency::total 10055827763 # number of overall MSHR miss cycles | 679system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055806763 # number of ReadReq MSHR miss cycles 680system.cpu.icache.ReadReq_mshr_miss_latency::total 10055806763 # number of ReadReq MSHR miss cycles 681system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055806763 # number of demand (read+write) MSHR miss cycles 682system.cpu.icache.demand_mshr_miss_latency::total 10055806763 # number of demand (read+write) MSHR miss cycles 683system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055806763 # number of overall MSHR miss cycles 684system.cpu.icache.overall_mshr_miss_latency::total 10055806763 # number of overall MSHR miss cycles |
| 679system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses 680system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses 681system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses 682system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses 683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses 684system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses | 685system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses 686system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses 687system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses 688system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses 689system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses 690system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses |
| 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.094526 # average ReadReq mshr miss latency 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.094526 # average ReadReq mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency | 691system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.068111 # average ReadReq mshr miss latency 692system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.068111 # average ReadReq mshr miss latency 693system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency 694system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency 695system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency 696system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency |
| 691system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 692system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements 693system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use 694system.cpu.itb_walker_cache.tags.total_refs 7028 # Total number of references to valid blocks. 695system.cpu.itb_walker_cache.tags.sampled_refs 4451 # Sample count of references to valid blocks. 696system.cpu.itb_walker_cache.tags.avg_refs 1.578971 # Average number of references to valid blocks. 697system.cpu.itb_walker_cache.tags.warmup_cycle 5161420260000 # Cycle when the warmup percentage was hit. 698system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.061283 # Average occupied blocks per requestor --- 108 unchanged lines hidden (view full) --- 807system.cpu.l2cache.tags.data_accesses 32250710 # Number of data accesses 808system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7142 # number of ReadReq hits 809system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3328 # number of ReadReq hits 810system.cpu.l2cache.ReadReq_hits::cpu.inst 782034 # number of ReadReq hits 811system.cpu.l2cache.ReadReq_hits::cpu.data 1280353 # number of ReadReq hits 812system.cpu.l2cache.ReadReq_hits::total 2072857 # number of ReadReq hits 813system.cpu.l2cache.Writeback_hits::writebacks 1543366 # number of Writeback hits 814system.cpu.l2cache.Writeback_hits::total 1543366 # number of Writeback hits | 697system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 698system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements 699system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use 700system.cpu.itb_walker_cache.tags.total_refs 7028 # Total number of references to valid blocks. 701system.cpu.itb_walker_cache.tags.sampled_refs 4451 # Sample count of references to valid blocks. 702system.cpu.itb_walker_cache.tags.avg_refs 1.578971 # Average number of references to valid blocks. 703system.cpu.itb_walker_cache.tags.warmup_cycle 5161420260000 # Cycle when the warmup percentage was hit. 704system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.061283 # Average occupied blocks per requestor --- 108 unchanged lines hidden (view full) --- 813system.cpu.l2cache.tags.data_accesses 32250710 # Number of data accesses 814system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7142 # number of ReadReq hits 815system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3328 # number of ReadReq hits 816system.cpu.l2cache.ReadReq_hits::cpu.inst 782034 # number of ReadReq hits 817system.cpu.l2cache.ReadReq_hits::cpu.data 1280353 # number of ReadReq hits 818system.cpu.l2cache.ReadReq_hits::total 2072857 # number of ReadReq hits 819system.cpu.l2cache.Writeback_hits::writebacks 1543366 # number of Writeback hits 820system.cpu.l2cache.Writeback_hits::total 1543366 # number of Writeback hits |
| 815system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits 816system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits | 821system.cpu.l2cache.UpgradeReq_hits::cpu.data 316 # number of UpgradeReq hits 822system.cpu.l2cache.UpgradeReq_hits::total 316 # number of UpgradeReq hits |
| 817system.cpu.l2cache.ReadExReq_hits::cpu.data 200136 # number of ReadExReq hits 818system.cpu.l2cache.ReadExReq_hits::total 200136 # number of ReadExReq hits 819system.cpu.l2cache.demand_hits::cpu.dtb.walker 7142 # number of demand (read+write) hits 820system.cpu.l2cache.demand_hits::cpu.itb.walker 3328 # number of demand (read+write) hits 821system.cpu.l2cache.demand_hits::cpu.inst 782034 # number of demand (read+write) hits 822system.cpu.l2cache.demand_hits::cpu.data 1480489 # number of demand (read+write) hits 823system.cpu.l2cache.demand_hits::total 2272993 # number of demand (read+write) hits 824system.cpu.l2cache.overall_hits::cpu.dtb.walker 7142 # number of overall hits 825system.cpu.l2cache.overall_hits::cpu.itb.walker 3328 # number of overall hits 826system.cpu.l2cache.overall_hits::cpu.inst 782034 # number of overall hits 827system.cpu.l2cache.overall_hits::cpu.data 1480489 # number of overall hits 828system.cpu.l2cache.overall_hits::total 2272993 # number of overall hits 829system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 830system.cpu.l2cache.ReadReq_misses::cpu.inst 12937 # number of ReadReq misses 831system.cpu.l2cache.ReadReq_misses::cpu.data 28518 # number of ReadReq misses 832system.cpu.l2cache.ReadReq_misses::total 41460 # number of ReadReq misses | 823system.cpu.l2cache.ReadExReq_hits::cpu.data 200136 # number of ReadExReq hits 824system.cpu.l2cache.ReadExReq_hits::total 200136 # number of ReadExReq hits 825system.cpu.l2cache.demand_hits::cpu.dtb.walker 7142 # number of demand (read+write) hits 826system.cpu.l2cache.demand_hits::cpu.itb.walker 3328 # number of demand (read+write) hits 827system.cpu.l2cache.demand_hits::cpu.inst 782034 # number of demand (read+write) hits 828system.cpu.l2cache.demand_hits::cpu.data 1480489 # number of demand (read+write) hits 829system.cpu.l2cache.demand_hits::total 2272993 # number of demand (read+write) hits 830system.cpu.l2cache.overall_hits::cpu.dtb.walker 7142 # number of overall hits 831system.cpu.l2cache.overall_hits::cpu.itb.walker 3328 # number of overall hits 832system.cpu.l2cache.overall_hits::cpu.inst 782034 # number of overall hits 833system.cpu.l2cache.overall_hits::cpu.data 1480489 # number of overall hits 834system.cpu.l2cache.overall_hits::total 2272993 # number of overall hits 835system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 836system.cpu.l2cache.ReadReq_misses::cpu.inst 12937 # number of ReadReq misses 837system.cpu.l2cache.ReadReq_misses::cpu.data 28518 # number of ReadReq misses 838system.cpu.l2cache.ReadReq_misses::total 41460 # number of ReadReq misses |
| 833system.cpu.l2cache.UpgradeReq_misses::cpu.data 1357 # number of UpgradeReq misses 834system.cpu.l2cache.UpgradeReq_misses::total 1357 # number of UpgradeReq misses | 839system.cpu.l2cache.UpgradeReq_misses::cpu.data 1358 # number of UpgradeReq misses 840system.cpu.l2cache.UpgradeReq_misses::total 1358 # number of UpgradeReq misses |
| 835system.cpu.l2cache.ReadExReq_misses::cpu.data 113272 # number of ReadExReq misses 836system.cpu.l2cache.ReadExReq_misses::total 113272 # number of ReadExReq misses 837system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 838system.cpu.l2cache.demand_misses::cpu.inst 12937 # number of demand (read+write) misses 839system.cpu.l2cache.demand_misses::cpu.data 141790 # number of demand (read+write) misses 840system.cpu.l2cache.demand_misses::total 154732 # number of demand (read+write) misses 841system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 842system.cpu.l2cache.overall_misses::cpu.inst 12937 # number of overall misses 843system.cpu.l2cache.overall_misses::cpu.data 141790 # number of overall misses 844system.cpu.l2cache.overall_misses::total 154732 # number of overall misses 845system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 387750 # number of ReadReq miss cycles | 841system.cpu.l2cache.ReadExReq_misses::cpu.data 113272 # number of ReadExReq misses 842system.cpu.l2cache.ReadExReq_misses::total 113272 # number of ReadExReq misses 843system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 844system.cpu.l2cache.demand_misses::cpu.inst 12937 # number of demand (read+write) misses 845system.cpu.l2cache.demand_misses::cpu.data 141790 # number of demand (read+write) misses 846system.cpu.l2cache.demand_misses::total 154732 # number of demand (read+write) misses 847system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 848system.cpu.l2cache.overall_misses::cpu.inst 12937 # number of overall misses 849system.cpu.l2cache.overall_misses::cpu.data 141790 # number of overall misses 850system.cpu.l2cache.overall_misses::total 154732 # number of overall misses 851system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 387750 # number of ReadReq miss cycles |
| 846system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049449751 # number of ReadReq miss cycles | 852system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049428751 # number of ReadReq miss cycles |
| 847system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2341413282 # number of ReadReq miss cycles | 853system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2341413282 # number of ReadReq miss cycles |
| 848system.cpu.l2cache.ReadReq_miss_latency::total 3391250783 # number of ReadReq miss cycles 849system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21334859 # number of UpgradeReq miss cycles 850system.cpu.l2cache.UpgradeReq_miss_latency::total 21334859 # number of UpgradeReq miss cycles | 854system.cpu.l2cache.ReadReq_miss_latency::total 3391229783 # number of ReadReq miss cycles 855system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21365858 # number of UpgradeReq miss cycles 856system.cpu.l2cache.UpgradeReq_miss_latency::total 21365858 # number of UpgradeReq miss cycles |
| 851system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8652486971 # number of ReadExReq miss cycles 852system.cpu.l2cache.ReadExReq_miss_latency::total 8652486971 # number of ReadExReq miss cycles 853system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 387750 # number of demand (read+write) miss cycles | 857system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8652486971 # number of ReadExReq miss cycles 858system.cpu.l2cache.ReadExReq_miss_latency::total 8652486971 # number of ReadExReq miss cycles 859system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 387750 # number of demand (read+write) miss cycles |
| 854system.cpu.l2cache.demand_miss_latency::cpu.inst 1049449751 # number of demand (read+write) miss cycles | 860system.cpu.l2cache.demand_miss_latency::cpu.inst 1049428751 # number of demand (read+write) miss cycles |
| 855system.cpu.l2cache.demand_miss_latency::cpu.data 10993900253 # number of demand (read+write) miss cycles | 861system.cpu.l2cache.demand_miss_latency::cpu.data 10993900253 # number of demand (read+write) miss cycles |
| 856system.cpu.l2cache.demand_miss_latency::total 12043737754 # number of demand (read+write) miss cycles | 862system.cpu.l2cache.demand_miss_latency::total 12043716754 # number of demand (read+write) miss cycles |
| 857system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 387750 # number of overall miss cycles | 863system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 387750 # number of overall miss cycles |
| 858system.cpu.l2cache.overall_miss_latency::cpu.inst 1049449751 # number of overall miss cycles | 864system.cpu.l2cache.overall_miss_latency::cpu.inst 1049428751 # number of overall miss cycles |
| 859system.cpu.l2cache.overall_miss_latency::cpu.data 10993900253 # number of overall miss cycles | 865system.cpu.l2cache.overall_miss_latency::cpu.data 10993900253 # number of overall miss cycles |
| 860system.cpu.l2cache.overall_miss_latency::total 12043737754 # number of overall miss cycles | 866system.cpu.l2cache.overall_miss_latency::total 12043716754 # number of overall miss cycles |
| 861system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7142 # number of ReadReq accesses(hits+misses) 862system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3333 # number of ReadReq accesses(hits+misses) 863system.cpu.l2cache.ReadReq_accesses::cpu.inst 794971 # number of ReadReq accesses(hits+misses) 864system.cpu.l2cache.ReadReq_accesses::cpu.data 1308871 # number of ReadReq accesses(hits+misses) 865system.cpu.l2cache.ReadReq_accesses::total 2114317 # number of ReadReq accesses(hits+misses) 866system.cpu.l2cache.Writeback_accesses::writebacks 1543366 # number of Writeback accesses(hits+misses) 867system.cpu.l2cache.Writeback_accesses::total 1543366 # number of Writeback accesses(hits+misses) 868system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1674 # number of UpgradeReq accesses(hits+misses) --- 9 unchanged lines hidden (view full) --- 878system.cpu.l2cache.overall_accesses::cpu.itb.walker 3333 # number of overall (read+write) accesses 879system.cpu.l2cache.overall_accesses::cpu.inst 794971 # number of overall (read+write) accesses 880system.cpu.l2cache.overall_accesses::cpu.data 1622279 # number of overall (read+write) accesses 881system.cpu.l2cache.overall_accesses::total 2427725 # number of overall (read+write) accesses 882system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001500 # miss rate for ReadReq accesses 883system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016274 # miss rate for ReadReq accesses 884system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021788 # miss rate for ReadReq accesses 885system.cpu.l2cache.ReadReq_miss_rate::total 0.019609 # miss rate for ReadReq accesses | 867system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7142 # number of ReadReq accesses(hits+misses) 868system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3333 # number of ReadReq accesses(hits+misses) 869system.cpu.l2cache.ReadReq_accesses::cpu.inst 794971 # number of ReadReq accesses(hits+misses) 870system.cpu.l2cache.ReadReq_accesses::cpu.data 1308871 # number of ReadReq accesses(hits+misses) 871system.cpu.l2cache.ReadReq_accesses::total 2114317 # number of ReadReq accesses(hits+misses) 872system.cpu.l2cache.Writeback_accesses::writebacks 1543366 # number of Writeback accesses(hits+misses) 873system.cpu.l2cache.Writeback_accesses::total 1543366 # number of Writeback accesses(hits+misses) 874system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1674 # number of UpgradeReq accesses(hits+misses) --- 9 unchanged lines hidden (view full) --- 884system.cpu.l2cache.overall_accesses::cpu.itb.walker 3333 # number of overall (read+write) accesses 885system.cpu.l2cache.overall_accesses::cpu.inst 794971 # number of overall (read+write) accesses 886system.cpu.l2cache.overall_accesses::cpu.data 1622279 # number of overall (read+write) accesses 887system.cpu.l2cache.overall_accesses::total 2427725 # number of overall (read+write) accesses 888system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001500 # miss rate for ReadReq accesses 889system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016274 # miss rate for ReadReq accesses 890system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021788 # miss rate for ReadReq accesses 891system.cpu.l2cache.ReadReq_miss_rate::total 0.019609 # miss rate for ReadReq accesses |
| 886system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.810633 # miss rate for UpgradeReq accesses 887system.cpu.l2cache.UpgradeReq_miss_rate::total 0.810633 # miss rate for UpgradeReq accesses | 892system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.811231 # miss rate for UpgradeReq accesses 893system.cpu.l2cache.UpgradeReq_miss_rate::total 0.811231 # miss rate for UpgradeReq accesses |
| 888system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361420 # miss rate for ReadExReq accesses 889system.cpu.l2cache.ReadExReq_miss_rate::total 0.361420 # miss rate for ReadExReq accesses 890system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001500 # miss rate for demand accesses 891system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016274 # miss rate for demand accesses 892system.cpu.l2cache.demand_miss_rate::cpu.data 0.087402 # miss rate for demand accesses 893system.cpu.l2cache.demand_miss_rate::total 0.063735 # miss rate for demand accesses 894system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001500 # miss rate for overall accesses 895system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016274 # miss rate for overall accesses 896system.cpu.l2cache.overall_miss_rate::cpu.data 0.087402 # miss rate for overall accesses 897system.cpu.l2cache.overall_miss_rate::total 0.063735 # miss rate for overall accesses 898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77550 # average ReadReq miss latency | 894system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361420 # miss rate for ReadExReq accesses 895system.cpu.l2cache.ReadExReq_miss_rate::total 0.361420 # miss rate for ReadExReq accesses 896system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001500 # miss rate for demand accesses 897system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016274 # miss rate for demand accesses 898system.cpu.l2cache.demand_miss_rate::cpu.data 0.087402 # miss rate for demand accesses 899system.cpu.l2cache.demand_miss_rate::total 0.063735 # miss rate for demand accesses 900system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001500 # miss rate for overall accesses 901system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016274 # miss rate for overall accesses 902system.cpu.l2cache.overall_miss_rate::cpu.data 0.087402 # miss rate for overall accesses 903system.cpu.l2cache.overall_miss_rate::total 0.063735 # miss rate for overall accesses 904system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77550 # average ReadReq miss latency |
| 899system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81120.024040 # average ReadReq miss latency | 905system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81118.400788 # average ReadReq miss latency |
| 900system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82102.997475 # average ReadReq miss latency | 906system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82102.997475 # average ReadReq miss latency |
| 901system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.725591 # average ReadReq miss latency 902system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15722.077377 # average UpgradeReq miss latency 903system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15722.077377 # average UpgradeReq miss latency | 907system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.219079 # average ReadReq miss latency 908system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15733.326951 # average UpgradeReq miss latency 909system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15733.326951 # average UpgradeReq miss latency |
| 904system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76386.812019 # average ReadExReq miss latency 905system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76386.812019 # average ReadExReq miss latency 906system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency | 910system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76386.812019 # average ReadExReq miss latency 911system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76386.812019 # average ReadExReq miss latency 912system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency |
| 907system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency | 913system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency |
| 908system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency | 914system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency |
| 909system.cpu.l2cache.demand_avg_miss_latency::total 77836.115051 # average overall miss latency | 915system.cpu.l2cache.demand_avg_miss_latency::total 77835.979332 # average overall miss latency |
| 910system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency | 916system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency |
| 911system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency | 917system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency |
| 912system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency | 918system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency |
| 913system.cpu.l2cache.overall_avg_miss_latency::total 77836.115051 # average overall miss latency | 919system.cpu.l2cache.overall_avg_miss_latency::total 77835.979332 # average overall miss latency |
| 914system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 915system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 916system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 917system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 918system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 919system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 920system.cpu.l2cache.fast_writes 0 # number of fast writes performed 921system.cpu.l2cache.cache_copies 0 # number of cache copies performed 922system.cpu.l2cache.writebacks::writebacks 80303 # number of writebacks 923system.cpu.l2cache.writebacks::total 80303 # number of writebacks 924system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 925system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12937 # number of ReadReq MSHR misses 926system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses 927system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses | 920system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 921system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 922system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 923system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 924system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 925system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 926system.cpu.l2cache.fast_writes 0 # number of fast writes performed 927system.cpu.l2cache.cache_copies 0 # number of cache copies performed 928system.cpu.l2cache.writebacks::writebacks 80303 # number of writebacks 929system.cpu.l2cache.writebacks::total 80303 # number of writebacks 930system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 931system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12937 # number of ReadReq MSHR misses 932system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses 933system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses |
| 928system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1357 # number of UpgradeReq MSHR misses 929system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses | 934system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1358 # number of UpgradeReq MSHR misses 935system.cpu.l2cache.UpgradeReq_mshr_misses::total 1358 # number of UpgradeReq MSHR misses |
| 930system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses 931system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses 932system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 933system.cpu.l2cache.demand_mshr_misses::cpu.inst 12937 # number of demand (read+write) MSHR misses 934system.cpu.l2cache.demand_mshr_misses::cpu.data 141790 # number of demand (read+write) MSHR misses 935system.cpu.l2cache.demand_mshr_misses::total 154732 # number of demand (read+write) MSHR misses 936system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 937system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses 938system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses 939system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses | 936system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses 937system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses 938system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 939system.cpu.l2cache.demand_mshr_misses::cpu.inst 12937 # number of demand (read+write) MSHR misses 940system.cpu.l2cache.demand_mshr_misses::cpu.data 141790 # number of demand (read+write) MSHR misses 941system.cpu.l2cache.demand_mshr_misses::total 154732 # number of demand (read+write) MSHR misses 942system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 943system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses 944system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses 945system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses |
| 946system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable 947system.cpu.l2cache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable 948system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable 949system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable 950system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses 951system.cpu.l2cache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses |
|
| 940system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles | 952system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles |
| 941system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles | 953system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887274749 # number of ReadReq MSHR miss cycles |
| 942system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles | 954system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles |
| 943system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872181717 # number of ReadReq MSHR miss cycles 944system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles 945system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # number of UpgradeReq MSHR miss cycles | 955system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872160717 # number of ReadReq MSHR miss cycles 956system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24705840 # number of UpgradeReq MSHR miss cycles 957system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24705840 # number of UpgradeReq MSHR miss cycles |
| 946system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles 947system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles 948system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles | 958system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles 959system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles 960system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles |
| 949system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887295749 # number of demand (read+write) MSHR miss cycles | 961system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887274749 # number of demand (read+write) MSHR miss cycles |
| 950system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles | 962system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles |
| 951system.cpu.l2cache.demand_mshr_miss_latency::total 10108406746 # number of demand (read+write) MSHR miss cycles | 963system.cpu.l2cache.demand_mshr_miss_latency::total 10108385746 # number of demand (read+write) MSHR miss cycles |
| 952system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles | 964system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles |
| 953system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles | 965system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887274749 # number of overall MSHR miss cycles |
| 954system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles | 966system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles |
| 955system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles | 967system.cpu.l2cache.overall_mshr_miss_latency::total 10108385746 # number of overall MSHR miss cycles |
| 956system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles 957system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles 958system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles 959system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411090500 # number of WriteReq MSHR uncacheable cycles 960system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88554571000 # number of overall MSHR uncacheable cycles 961system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88554571000 # number of overall MSHR uncacheable cycles 962system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for ReadReq accesses 963system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses 964system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses 965system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses | 968system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles 969system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles 970system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles 971system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411090500 # number of WriteReq MSHR uncacheable cycles 972system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88554571000 # number of overall MSHR uncacheable cycles 973system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88554571000 # number of overall MSHR uncacheable cycles 974system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for ReadReq accesses 975system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses 976system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses 977system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses |
| 966system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.810633 # mshr miss rate for UpgradeReq accesses 967system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.810633 # mshr miss rate for UpgradeReq accesses | 978system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811231 # mshr miss rate for UpgradeReq accesses 979system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811231 # mshr miss rate for UpgradeReq accesses |
| 968system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses 969system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses 970system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses 971system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for demand accesses 972system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for demand accesses 973system.cpu.l2cache.demand_mshr_miss_rate::total 0.063735 # mshr miss rate for demand accesses 974system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for overall accesses 975system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for overall accesses 976system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses 977system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses 978system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency | 980system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses 981system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses 982system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses 983system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for demand accesses 984system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for demand accesses 985system.cpu.l2cache.demand_mshr_miss_rate::total 0.063735 # mshr miss rate for demand accesses 986system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for overall accesses 987system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for overall accesses 988system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses 989system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses 990system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency |
| 979system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68585.896962 # average ReadReq mshr miss latency | 991system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68584.273711 # average ReadReq mshr miss latency |
| 980system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency | 992system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency |
| 981system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.970019 # average ReadReq mshr miss latency 982system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18193.322771 # average UpgradeReq mshr miss latency 983system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18193.322771 # average UpgradeReq mshr miss latency | 993system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.463507 # average ReadReq mshr miss latency 994system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18192.812960 # average UpgradeReq mshr miss latency 995system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18192.812960 # average UpgradeReq mshr miss latency |
| 984system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency 985system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency 986system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency | 996system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency 997system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency 998system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency |
| 987system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency | 999system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency |
| 988system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency | 1000system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency |
| 989system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency | 1001system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency |
| 990system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency | 1002system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency |
| 991system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency | 1003system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency |
| 992system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency | 1004system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency |
| 993system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency 994system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 995system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 996system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 997system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 998system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 999system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency | 1005system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency 1006system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149863.747625 # average ReadReq mshr uncacheable latency 1007system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149863.747625 # average ReadReq mshr uncacheable latency 1008system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173260.311871 # average WriteReq mshr uncacheable latency 1009system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173260.311871 # average WriteReq mshr uncacheable latency 1010system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150416.781604 # average overall mshr uncacheable latency 1011system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150416.781604 # average overall mshr uncacheable latency |
| 1000system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1001system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution 1002system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution 1003system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution 1004system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution 1005system.cpu.toL2Bus.trans_dist::Writeback 1543366 # Transaction distribution 1006system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46773 # Transaction distribution 1007system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # Transaction distribution 1008system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution 1009system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution 1010system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution | 1012system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1013system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution 1014system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution 1015system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution 1016system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution 1017system.cpu.toL2Bus.trans_dist::Writeback 1543366 # Transaction distribution 1018system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46773 # Transaction distribution 1019system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # Transaction distribution 1020system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution 1021system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution 1022system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution |
| 1023system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution |
|
| 1011system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes) 1012system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes) 1013system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes) 1014system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20349 # Packet count per connected master and slave (bytes) 1015system.cpu.toL2Bus.pkt_count::total 7586177 # Packet count per connected master and slave (bytes) 1016system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50878144 # Cumulative packet size per connected master and slave (bytes) 1017system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204018925 # Cumulative packet size per connected master and slave (bytes) 1018system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes) 1019system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes) 1020system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes) | 1024system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes) 1025system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes) 1026system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes) 1027system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20349 # Packet count per connected master and slave (bytes) 1028system.cpu.toL2Bus.pkt_count::total 7586177 # Packet count per connected master and slave (bytes) 1029system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50878144 # Cumulative packet size per connected master and slave (bytes) 1030system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204018925 # Cumulative packet size per connected master and slave (bytes) 1031system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes) 1032system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes) 1033system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes) |
| 1021system.cpu.toL2Bus.snoops 54167 # Total snoops (count) 1022system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram 1023system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram 1024system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram | 1034system.cpu.toL2Bus.snoops 55819 # Total snoops (count) 1035system.cpu.toL2Bus.snoop_fanout::samples 4616997 # Request fanout histogram 1036system.cpu.toL2Bus.snoop_fanout::mean 3.010670 # Request fanout histogram 1037system.cpu.toL2Bus.snoop_fanout::stdev 0.102742 # Request fanout histogram |
| 1025system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1026system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1027system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1028system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1038system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1039system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1040system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1041system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1029system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram 1030system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram | 1042system.cpu.toL2Bus.snoop_fanout::3 4567735 98.93% 98.93% # Request fanout histogram 1043system.cpu.toL2Bus.snoop_fanout::4 49262 1.07% 100.00% # Request fanout histogram |
| 1031system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1032system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1033system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 1044system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1045system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1046system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 1034system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram | 1047system.cpu.toL2Bus.snoop_fanout::total 4616997 # Request fanout histogram |
| 1035system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks) 1036system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1037system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks) 1038system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1039system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks) 1040system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1048system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks) 1049system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1050system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks) 1051system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1052system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks) 1053system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1041system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks) | 1054system.cpu.toL2Bus.respLayer1.occupancy 3047835587 # Layer occupancy (ticks) |
| 1042system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1043system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks) 1044system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1045system.cpu.toL2Bus.respLayer3.occupancy 15136500 # Layer occupancy (ticks) 1046system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1047system.iobus.trans_dist::ReadReq 228399 # Transaction distribution 1048system.iobus.trans_dist::ReadResp 228399 # Transaction distribution 1049system.iobus.trans_dist::WriteReq 57726 # Transaction distribution --- 194 unchanged lines hidden (view full) --- 1244system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1245system.membus.trans_dist::ReadReq 617109 # Transaction distribution 1246system.membus.trans_dist::ReadResp 617109 # Transaction distribution 1247system.membus.trans_dist::WriteReq 13916 # Transaction distribution 1248system.membus.trans_dist::WriteResp 13916 # Transaction distribution 1249system.membus.trans_dist::Writeback 126970 # Transaction distribution 1250system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1251system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution | 1055system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1056system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks) 1057system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1058system.cpu.toL2Bus.respLayer3.occupancy 15136500 # Layer occupancy (ticks) 1059system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1060system.iobus.trans_dist::ReadReq 228399 # Transaction distribution 1061system.iobus.trans_dist::ReadResp 228399 # Transaction distribution 1062system.iobus.trans_dist::WriteReq 57726 # Transaction distribution --- 194 unchanged lines hidden (view full) --- 1257system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1258system.membus.trans_dist::ReadReq 617109 # Transaction distribution 1259system.membus.trans_dist::ReadResp 617109 # Transaction distribution 1260system.membus.trans_dist::WriteReq 13916 # Transaction distribution 1261system.membus.trans_dist::WriteResp 13916 # Transaction distribution 1262system.membus.trans_dist::Writeback 126970 # Transaction distribution 1263system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1264system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 1252system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution 1253system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution | 1265system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution 1266system.membus.trans_dist::UpgradeResp 1637 # Transaction distribution |
| 1254system.membus.trans_dist::ReadExReq 112993 # Transaction distribution 1255system.membus.trans_dist::ReadExResp 112993 # Transaction distribution 1256system.membus.trans_dist::MessageReq 1652 # Transaction distribution 1257system.membus.trans_dist::MessageResp 1652 # Transaction distribution 1258system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) 1259system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) 1260system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes) 1261system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) | 1267system.membus.trans_dist::ReadExReq 112993 # Transaction distribution 1268system.membus.trans_dist::ReadExResp 112993 # Transaction distribution 1269system.membus.trans_dist::MessageReq 1652 # Transaction distribution 1270system.membus.trans_dist::MessageResp 1652 # Transaction distribution 1271system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) 1272system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) 1273system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes) 1274system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) |
| 1262system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes) 1263system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes) | 1275system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392332 # Packet count per connected master and slave (bytes) 1276system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569788 # Packet count per connected master and slave (bytes) |
| 1264system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes) 1265system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes) | 1277system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes) 1278system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes) |
| 1266system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes) | 1279system.membus.pkt_count::total 1714479 # Packet count per connected master and slave (bytes) |
| 1267system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) 1268system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) 1269system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes) 1270system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) 1271system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14982656 # Cumulative packet size per connected master and slave (bytes) 1272system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16628141 # Cumulative packet size per connected master and slave (bytes) 1273system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1274system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) 1275system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes) 1276system.membus.snoops 1583 # Total snoops (count) | 1280system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) 1281system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) 1282system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes) 1283system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) 1284system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14982656 # Cumulative packet size per connected master and slave (bytes) 1285system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16628141 # Cumulative packet size per connected master and slave (bytes) 1286system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1287system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) 1288system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes) 1289system.membus.snoops 1583 # Total snoops (count) |
| 1277system.membus.snoop_fanout::samples 331203 # Request fanout histogram 1278system.membus.snoop_fanout::mean 1 # Request fanout histogram 1279system.membus.snoop_fanout::stdev 0 # Request fanout histogram | 1290system.membus.snoop_fanout::samples 921584 # Request fanout histogram 1291system.membus.snoop_fanout::mean 1.001793 # Request fanout histogram 1292system.membus.snoop_fanout::stdev 0.042301 # Request fanout histogram |
| 1280system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1281system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1293system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1294system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1282system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram 1283system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram | 1295system.membus.snoop_fanout::1 919932 99.82% 99.82% # Request fanout histogram 1296system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram |
| 1284system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1285system.membus.snoop_fanout::min_value 1 # Request fanout histogram | 1297system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1298system.membus.snoop_fanout::min_value 1 # Request fanout histogram |
| 1286system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1287system.membus.snoop_fanout::total 331203 # Request fanout histogram | 1299system.membus.snoop_fanout::max_value 2 # Request fanout histogram 1300system.membus.snoop_fanout::total 921584 # Request fanout histogram |
| 1288system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks) 1289system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1290system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks) 1291system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1292system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) 1293system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1301system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks) 1302system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1303system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks) 1304system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1305system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) 1306system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1294system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks) | 1307system.membus.reqLayer3.occupancy 1034075968 # Layer occupancy (ticks) |
| 1295system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1296system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) 1297system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 1308system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1309system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) 1310system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1298system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks) | 1311system.membus.respLayer2.occupancy 2159262414 # Layer occupancy (ticks) |
| 1299system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1300system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks) 1301system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1302system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1303system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1304system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1305system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1306system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1307system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1308system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1309system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1310system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1311system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1312system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1313system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1314 1315---------- End Simulation Statistics ---------- | 1312system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1313system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks) 1314system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1315system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1316system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1317system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1318system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1319system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1320system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1321system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1322system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1323system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1324system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1325system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1326system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1327 1328---------- End Simulation Statistics ---------- |