| stats.txt (10645:cd95d4d51659) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.188464 # Number of seconds simulated 4sim_ticks 5188464227000 # Number of ticks simulated 5final_tick 5188464227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.184750 # Number of seconds simulated 4sim_ticks 5184749789500 # Number of ticks simulated 5final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 671592 # Simulator instruction rate (inst/s) 8host_op_rate 1294539 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27056983658 # Simulator tick rate (ticks/s) 10host_mem_usage 641928 # Number of bytes of host memory used 11host_seconds 191.76 # Real time elapsed on the host 12sim_insts 128784844 # Number of instructions simulated 13sim_ops 248241672 # Number of ops (including micro ops) simulated | 7host_inst_rate 858252 # Simulator instruction rate (inst/s) 8host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34581252938 # Simulator tick rate (ticks/s) 10host_mem_usage 653812 # Number of bytes of host memory used 11host_seconds 149.93 # Real time elapsed on the host 12sim_insts 128677191 # Number of instructions simulated 13sim_ops 248045844 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory | |
| 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.inst 828672 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9042304 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.inst 827904 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9015040 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | 19system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 9899712 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 828672 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 828672 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8125568 # Number of bytes written to this memory 25system.physmem.bytes_written::total 8125568 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory | 20system.physmem.bytes_read::total 9871616 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 827904 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 827904 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 8126080 # Number of bytes written to this memory 24system.physmem.bytes_written::total 8126080 # Number of bytes written to this memory |
| 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 25system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.inst 12948 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141286 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.inst 12936 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.data 140860 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | 28system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::total 154683 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 126962 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 126962 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) | 29system.physmem.num_reads::total 154244 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 126970 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 126970 # Number of write requests responded to by this memory |
| 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) | 32system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) |
| 36system.physmem.bw_read::cpu.inst 159714 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 1742771 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5464 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 1908024 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 159714 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 159714 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1566083 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1566083 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1566083 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) | 33system.physmem.bw_read::cpu.inst 159681 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.data 1738761 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::total 1903972 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_inst_read::cpu.inst 159681 # Instruction read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::total 159681 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_write::writebacks 1567304 # Write bandwidth from this memory (bytes/s) 40system.physmem.bw_write::total 1567304 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_total::writebacks 1567304 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) | 42system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::cpu.inst 159714 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 1742771 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5464 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 3474107 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 154683 # Number of read requests accepted 52system.physmem.writeReqs 173682 # Number of write requests accepted 53system.physmem.readBursts 154683 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 173682 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 9893504 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue 57system.physmem.bytesWritten 10954816 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 9899712 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 11115648 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 2485 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 1609 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 10173 # Per bank write bursts 64system.physmem.perBankRdBursts::1 9740 # Per bank write bursts 65system.physmem.perBankRdBursts::2 9593 # Per bank write bursts 66system.physmem.perBankRdBursts::3 9430 # Per bank write bursts 67system.physmem.perBankRdBursts::4 10001 # Per bank write bursts 68system.physmem.perBankRdBursts::5 9691 # Per bank write bursts 69system.physmem.perBankRdBursts::6 9399 # Per bank write bursts 70system.physmem.perBankRdBursts::7 9276 # Per bank write bursts 71system.physmem.perBankRdBursts::8 9154 # Per bank write bursts 72system.physmem.perBankRdBursts::9 9223 # Per bank write bursts 73system.physmem.perBankRdBursts::10 9471 # Per bank write bursts 74system.physmem.perBankRdBursts::11 9338 # Per bank write bursts 75system.physmem.perBankRdBursts::12 9899 # Per bank write bursts 76system.physmem.perBankRdBursts::13 10266 # Per bank write bursts 77system.physmem.perBankRdBursts::14 9992 # Per bank write bursts 78system.physmem.perBankRdBursts::15 9940 # Per bank write bursts 79system.physmem.perBankWrBursts::0 11451 # Per bank write bursts 80system.physmem.perBankWrBursts::1 10885 # Per bank write bursts 81system.physmem.perBankWrBursts::2 11361 # Per bank write bursts 82system.physmem.perBankWrBursts::3 10717 # Per bank write bursts 83system.physmem.perBankWrBursts::4 11001 # Per bank write bursts 84system.physmem.perBankWrBursts::5 10578 # Per bank write bursts 85system.physmem.perBankWrBursts::6 10603 # Per bank write bursts 86system.physmem.perBankWrBursts::7 9872 # Per bank write bursts 87system.physmem.perBankWrBursts::8 10400 # Per bank write bursts 88system.physmem.perBankWrBursts::9 10659 # Per bank write bursts 89system.physmem.perBankWrBursts::10 10851 # Per bank write bursts 90system.physmem.perBankWrBursts::11 10912 # Per bank write bursts 91system.physmem.perBankWrBursts::12 10837 # Per bank write bursts 92system.physmem.perBankWrBursts::13 10879 # Per bank write bursts 93system.physmem.perBankWrBursts::14 9964 # Per bank write bursts 94system.physmem.perBankWrBursts::15 10199 # Per bank write bursts | 43system.physmem.bw_total::cpu.inst 159681 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.data 1738761 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::total 3471276 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.readReqs 154244 # Number of read requests accepted 48system.physmem.writeReqs 173690 # Number of write requests accepted 49system.physmem.readBursts 154244 # Number of DRAM read bursts, including those serviced by the write queue 50system.physmem.writeBursts 173690 # Number of DRAM write bursts, including those merged in the write queue 51system.physmem.bytesReadDRAM 9865536 # Total number of bytes read from DRAM 52system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue 53system.physmem.bytesWritten 9446080 # Total number of bytes written to DRAM 54system.physmem.bytesReadSys 9871616 # Total read bytes from the system interface side 55system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side 56system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue 57system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one 58system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write 59system.physmem.perBankRdBursts::0 9927 # Per bank write bursts 60system.physmem.perBankRdBursts::1 9220 # Per bank write bursts 61system.physmem.perBankRdBursts::2 9906 # Per bank write bursts 62system.physmem.perBankRdBursts::3 9744 # Per bank write bursts 63system.physmem.perBankRdBursts::4 9716 # Per bank write bursts 64system.physmem.perBankRdBursts::5 9338 # Per bank write bursts 65system.physmem.perBankRdBursts::6 9475 # Per bank write bursts 66system.physmem.perBankRdBursts::7 9515 # Per bank write bursts 67system.physmem.perBankRdBursts::8 8926 # Per bank write bursts 68system.physmem.perBankRdBursts::9 9405 # Per bank write bursts 69system.physmem.perBankRdBursts::10 9702 # Per bank write bursts 70system.physmem.perBankRdBursts::11 9402 # Per bank write bursts 71system.physmem.perBankRdBursts::12 9788 # Per bank write bursts 72system.physmem.perBankRdBursts::13 10193 # Per bank write bursts 73system.physmem.perBankRdBursts::14 9798 # Per bank write bursts 74system.physmem.perBankRdBursts::15 10094 # Per bank write bursts 75system.physmem.perBankWrBursts::0 9407 # Per bank write bursts 76system.physmem.perBankWrBursts::1 8748 # Per bank write bursts 77system.physmem.perBankWrBursts::2 9677 # Per bank write bursts 78system.physmem.perBankWrBursts::3 9718 # Per bank write bursts 79system.physmem.perBankWrBursts::4 9428 # Per bank write bursts 80system.physmem.perBankWrBursts::5 9072 # Per bank write bursts 81system.physmem.perBankWrBursts::6 8868 # Per bank write bursts 82system.physmem.perBankWrBursts::7 9192 # Per bank write bursts 83system.physmem.perBankWrBursts::8 8615 # Per bank write bursts 84system.physmem.perBankWrBursts::9 8711 # Per bank write bursts 85system.physmem.perBankWrBursts::10 9601 # Per bank write bursts 86system.physmem.perBankWrBursts::11 9113 # Per bank write bursts 87system.physmem.perBankWrBursts::12 9702 # Per bank write bursts 88system.physmem.perBankWrBursts::13 9421 # Per bank write bursts 89system.physmem.perBankWrBursts::14 9363 # Per bank write bursts 90system.physmem.perBankWrBursts::15 8959 # Per bank write bursts |
| 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 91system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 96system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 97system.physmem.totGap 5188464163500 # Total gap between requests | 92system.physmem.numWrRetry 68 # Number of times write queue was full causing retry 93system.physmem.totGap 5184749726000 # Total gap between requests |
| 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) | 94system.physmem.readPktSize::0 0 # Read request sizes (log2) 95system.physmem.readPktSize::1 0 # Read request sizes (log2) 96system.physmem.readPktSize::2 0 # Read request sizes (log2) 97system.physmem.readPktSize::3 0 # Read request sizes (log2) 98system.physmem.readPktSize::4 0 # Read request sizes (log2) 99system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 104system.physmem.readPktSize::6 154683 # Read request sizes (log2) | 100system.physmem.readPktSize::6 154244 # Read request sizes (log2) |
| 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) | 101system.physmem.writePktSize::0 0 # Write request sizes (log2) 102system.physmem.writePktSize::1 0 # Write request sizes (log2) 103system.physmem.writePktSize::2 0 # Write request sizes (log2) 104system.physmem.writePktSize::3 0 # Write request sizes (log2) 105system.physmem.writePktSize::4 0 # Write request sizes (log2) 106system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 111system.physmem.writePktSize::6 173682 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 151354 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 2788 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 61 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see | 107system.physmem.writePktSize::6 173690 # Write request sizes (log2) 108system.physmem.rdQLenPdf::0 150873 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 2864 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 32 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 32 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see |
| 127system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 123system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 147system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::15 2688 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 5143 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 8699 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 9820 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 10213 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 11279 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 11696 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 12708 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 12272 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 12858 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 11610 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 11043 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 9612 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 8840 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 7385 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 7046 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 6960 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 6830 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 422 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 379 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 262 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 234 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 225 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 58562 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 356.003142 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 207.252442 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 358.966719 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 19491 33.28% 33.28% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 13719 23.43% 56.71% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 5713 9.76% 66.46% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 3485 5.95% 72.42% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 2346 4.01% 76.42% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 1652 2.82% 79.24% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1138 1.94% 81.19% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1007 1.72% 82.91% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 10011 17.09% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 58562 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 6360 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 24.303774 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 600.449814 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 6359 99.98% 99.98% # Reads before turning the bus around for writes | 155system.physmem.wrQLenPdf::15 1720 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::16 2028 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::17 5197 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::18 5607 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::19 5381 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::20 5544 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::21 5616 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::22 6039 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::23 7751 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::24 6327 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::25 6715 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::26 8321 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::27 6359 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::28 6074 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::29 9044 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::31 6942 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::33 1383 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::34 1065 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::35 1664 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::36 3046 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::37 3049 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::38 2409 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::39 2529 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::40 3647 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::41 2755 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::42 2403 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::43 2146 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::44 2360 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::45 2108 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::46 1639 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::47 1559 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::48 1250 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::49 853 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::50 400 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::51 368 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::53 460 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::55 213 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::58 238 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::60 120 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::63 127 # What write queue length does an incoming req see 204system.physmem.bytesPerActivate::samples 57050 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::mean 338.502226 # Bytes accessed per row activation 206system.physmem.bytesPerActivate::gmean 199.067588 # Bytes accessed per row activation 207system.physmem.bytesPerActivate::stdev 346.604467 # Bytes accessed per row activation 208system.physmem.bytesPerActivate::0-127 19329 33.88% 33.88% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::128-255 13844 24.27% 58.15% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::256-383 5928 10.39% 68.54% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::384-511 3298 5.78% 74.32% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::512-639 2346 4.11% 78.43% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::640-767 1576 2.76% 81.19% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::768-895 1245 2.18% 83.38% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::896-1023 971 1.70% 85.08% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::1024-1151 8513 14.92% 100.00% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::total 57050 # Bytes accessed per row activation 218system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::mean 29.117303 # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::stdev 658.027323 # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::0-2047 5293 99.98% 99.98% # Reads before turning the bus around for writes |
| 226system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes | 222system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 227system.physmem.rdPerTurnAround::total 6360 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 6360 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 26.913365 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 21.548238 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 26.273775 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 4929 77.50% 77.50% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 43 0.68% 78.18% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 22 0.35% 78.52% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 287 4.51% 83.03% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 171 2.69% 85.72% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 54 0.85% 86.57% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 36 0.57% 87.14% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 31 0.49% 87.63% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 174 2.74% 90.36% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 19 0.30% 90.66% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 20 0.31% 90.97% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 9 0.14% 91.12% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 42 0.66% 91.78% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 19 0.30% 92.08% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 8 0.13% 92.20% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 53 0.83% 93.03% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 89 1.40% 94.43% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::84-87 11 0.17% 94.61% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::88-91 4 0.06% 94.67% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::92-95 14 0.22% 94.89% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 158 2.48% 97.37% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 4 0.06% 97.44% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 9 0.14% 97.58% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::108-111 4 0.06% 97.64% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 23 0.36% 98.00% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 5 0.08% 98.08% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::120-123 8 0.13% 98.21% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 4 0.06% 98.27% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 28 0.44% 98.71% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 11 0.17% 98.88% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 1 0.02% 98.90% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 9 0.14% 99.04% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 14 0.22% 99.26% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::148-151 8 0.13% 99.39% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::156-159 4 0.06% 99.45% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::160-163 7 0.11% 99.56% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::168-171 2 0.03% 99.59% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::176-179 6 0.09% 99.69% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::180-183 3 0.05% 99.73% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::188-191 4 0.06% 99.80% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::192-195 1 0.02% 99.81% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::200-203 3 0.05% 99.86% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::208-211 1 0.02% 99.87% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::212-215 1 0.02% 99.89% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::216-219 2 0.03% 99.92% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::224-227 3 0.05% 99.98% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::total 6360 # Writes before turning the bus around for reads 281system.physmem.totQLat 1439298500 # Total ticks spent queuing 282system.physmem.totMemAccLat 4337786000 # Total ticks spent from burst creation until serviced by the DRAM 283system.physmem.totBusLat 772930000 # Total ticks spent in databus transfers 284system.physmem.avgQLat 9310.67 # Average queueing delay per DRAM burst | 223system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes 224system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::mean 27.879675 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::gmean 19.284410 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::stdev 52.982511 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::16-31 4909 92.73% 92.73% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-47 99 1.87% 94.60% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::48-63 16 0.30% 94.90% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::64-79 5 0.09% 94.99% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::80-95 10 0.19% 95.18% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::96-111 12 0.23% 95.41% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::112-127 21 0.40% 95.81% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::128-143 16 0.30% 96.11% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::144-159 28 0.53% 96.64% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::160-175 6 0.11% 96.75% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::176-191 43 0.81% 97.56% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::192-207 33 0.62% 98.19% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::208-223 9 0.17% 98.36% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::224-239 4 0.08% 98.43% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::240-255 1 0.02% 98.45% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::256-271 3 0.06% 98.51% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::272-287 2 0.04% 98.55% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::288-303 9 0.17% 98.72% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::304-319 7 0.13% 98.85% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::320-335 3 0.06% 98.90% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::336-351 17 0.32% 99.23% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::352-367 15 0.28% 99.51% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::368-383 2 0.04% 99.55% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::384-399 3 0.06% 99.60% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::400-415 2 0.04% 99.64% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::416-431 1 0.02% 99.66% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::448-463 1 0.02% 99.68% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::480-495 4 0.08% 99.75% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::496-511 3 0.06% 99.81% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::512-527 5 0.09% 99.91% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads 262system.physmem.totQLat 1425327951 # Total ticks spent queuing 263system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst |
| 285system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 286system.physmem.avgMemAccLat 28060.67 # Average memory access latency per DRAM burst 287system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s 288system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s 289system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s | 267system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst 268system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s |
| 290system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s 291system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 292system.physmem.busUtil 0.03 # Data bus utilization in percentage 293system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads | 271system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.03 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads |
| 294system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes | 275system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes |
| 295system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 276system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 296system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing 297system.physmem.readRowHits 127137 # Number of row buffer hits during reads 298system.physmem.writeRowHits 140055 # Number of row buffer hits during writes 299system.physmem.readRowHitRate 82.24 # Row buffer hit rate for reads 300system.physmem.writeRowHitRate 81.81 # Row buffer hit rate for writes 301system.physmem.avgGap 15800904.98 # Average gap between requests 302system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined 303system.physmem_0.actEnergy 219436560 # Energy for activate commands per rank (pJ) 304system.physmem_0.preEnergy 119732250 # Energy for precharge commands per rank (pJ) 305system.physmem_0.readEnergy 602963400 # Energy for read commands per rank (pJ) 306system.physmem_0.writeEnergy 560312640 # Energy for write commands per rank (pJ) 307system.physmem_0.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) 308system.physmem_0.actBackEnergy 133861007610 # Energy for active background per rank (pJ) 309system.physmem_0.preBackEnergy 2995654884750 # Energy for precharge background per rank (pJ) 310system.physmem_0.totalEnergy 3469903395930 # Total energy per rank (pJ) 311system.physmem_0.averagePower 668.773100 # Core power per rank (mW) 312system.physmem_0.memoryStateTime::IDLE 4983444491000 # Time in different power states 313system.physmem_0.memoryStateTime::REF 173254120000 # Time in different power states | 277system.physmem.avgWrQLen 22.98 # Average write queue length when enqueuing 278system.physmem.readRowHits 126892 # Number of row buffer hits during reads 279system.physmem.writeRowHits 117801 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes 282system.physmem.avgGap 15810345.15 # Average gap between requests 283system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined 284system.physmem_0.actEnergy 212315040 # Energy for activate commands per rank (pJ) 285system.physmem_0.preEnergy 115846500 # Energy for precharge commands per rank (pJ) 286system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ) 287system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ) 288system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) 289system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ) 290system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ) 291system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ) 292system.physmem_0.averagePower 668.758961 # Core power per rank (mW) 293system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states 294system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states |
| 314system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 295system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 315system.physmem_0.memoryStateTime::ACT 31762771500 # Time in different power states | 296system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states |
| 316system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 297system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 317system.physmem_1.actEnergy 223292160 # Energy for activate commands per rank (pJ) 318system.physmem_1.preEnergy 121836000 # Energy for precharge commands per rank (pJ) 319system.physmem_1.readEnergy 602799600 # Energy for read commands per rank (pJ) 320system.physmem_1.writeEnergy 548862480 # Energy for write commands per rank (pJ) 321system.physmem_1.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) 322system.physmem_1.actBackEnergy 134523004185 # Energy for active background per rank (pJ) 323system.physmem_1.preBackEnergy 2995074186000 # Energy for precharge background per rank (pJ) 324system.physmem_1.totalEnergy 3469979039145 # Total energy per rank (pJ) 325system.physmem_1.averagePower 668.787680 # Core power per rank (mW) 326system.physmem_1.memoryStateTime::IDLE 4982479156750 # Time in different power states 327system.physmem_1.memoryStateTime::REF 173254120000 # Time in different power states | 298system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 603002400 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 476182800 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 134835847830 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 2992571337000 # Energy for precharge background per rank (pJ) 305system.physmem_1.totalEnergy 3467467313340 # Total energy per rank (pJ) 306system.physmem_1.averagePower 668.782314 # Core power per rank (mW) 307system.physmem_1.memoryStateTime::IDLE 4978313509331 # Time in different power states 308system.physmem_1.memoryStateTime::REF 173130100000 # Time in different power states |
| 328system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 309system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 329system.physmem_1.memoryStateTime::ACT 32730835250 # Time in different power states | 310system.physmem_1.memoryStateTime::ACT 33303731919 # Time in different power states |
| 330system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 331system.cpu_clk_domain.clock 500 # Clock period in ticks 332system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 311system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 312system.cpu_clk_domain.clock 500 # Clock period in ticks 313system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 333system.cpu.numCycles 10376928454 # number of cpu cycles simulated | 314system.cpu.numCycles 10369499579 # number of cpu cycles simulated |
| 334system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 335system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 315system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 316system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 336system.cpu.committedInsts 128784844 # Number of instructions committed 337system.cpu.committedOps 248241672 # Number of ops (including micro ops) committed 338system.cpu.num_int_alu_accesses 232811079 # Number of integer alu accesses | 317system.cpu.committedInsts 128677191 # Number of instructions committed 318system.cpu.committedOps 248045844 # Number of ops (including micro ops) committed 319system.cpu.num_int_alu_accesses 232619140 # Number of integer alu accesses |
| 339system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses | 320system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses |
| 340system.cpu.num_func_calls 2318021 # number of times a function call or return occured 341system.cpu.num_conditional_control_insts 23218427 # number of instructions that are conditional controls 342system.cpu.num_int_insts 232811079 # number of integer instructions | 321system.cpu.num_func_calls 2317433 # number of times a function call or return occured 322system.cpu.num_conditional_control_insts 23196735 # number of instructions that are conditional controls 323system.cpu.num_int_insts 232619140 # number of integer instructions |
| 343system.cpu.num_fp_insts 48 # number of float instructions | 324system.cpu.num_fp_insts 48 # number of float instructions |
| 344system.cpu.num_int_register_reads 436120957 # number of times the integer registers were read 345system.cpu.num_int_register_writes 198544312 # number of times the integer registers were written | 325system.cpu.num_int_register_reads 435790308 # number of times the integer registers were read 326system.cpu.num_int_register_writes 198379629 # number of times the integer registers were written |
| 346system.cpu.num_fp_register_reads 48 # number of times the floating registers were read 347system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 327system.cpu.num_fp_register_reads 48 # number of times the floating registers were read 328system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 348system.cpu.num_cc_register_reads 133281322 # number of times the CC registers were read 349system.cpu.num_cc_register_writes 95783918 # number of times the CC registers were written 350system.cpu.num_mem_refs 22376754 # number of memory refs 351system.cpu.num_load_insts 13962110 # Number of load instructions 352system.cpu.num_store_insts 8414644 # Number of store instructions 353system.cpu.num_idle_cycles 9778737102.998116 # Number of idle cycles 354system.cpu.num_busy_cycles 598191351.001885 # Number of busy cycles 355system.cpu.not_idle_fraction 0.057646 # Percentage of non-idle cycles 356system.cpu.idle_fraction 0.942354 # Percentage of idle cycles 357system.cpu.Branches 26395735 # Number of branches fetched 358system.cpu.op_class::No_OpClass 172520 0.07% 0.07% # Class of executed instruction 359system.cpu.op_class::IntAlu 225434965 90.81% 90.88% # Class of executed instruction 360system.cpu.op_class::IntMult 140546 0.06% 90.94% # Class of executed instruction 361system.cpu.op_class::IntDiv 123415 0.05% 90.99% # Class of executed instruction | 329system.cpu.num_cc_register_reads 133146964 # number of times the CC registers were read 330system.cpu.num_cc_register_writes 95675934 # number of times the CC registers were written 331system.cpu.num_mem_refs 22361713 # number of memory refs 332system.cpu.num_load_insts 13951833 # Number of load instructions 333system.cpu.num_store_insts 8409880 # Number of store instructions 334system.cpu.num_idle_cycles 9769324889.998116 # Number of idle cycles 335system.cpu.num_busy_cycles 600174689.001884 # Number of busy cycles 336system.cpu.not_idle_fraction 0.057879 # Percentage of non-idle cycles 337system.cpu.idle_fraction 0.942121 # Percentage of idle cycles 338system.cpu.Branches 26373024 # Number of branches fetched 339system.cpu.op_class::No_OpClass 172503 0.07% 0.07% # Class of executed instruction 340system.cpu.op_class::IntAlu 225254349 90.81% 90.88% # Class of executed instruction 341system.cpu.op_class::IntMult 140413 0.06% 90.94% # Class of executed instruction 342system.cpu.op_class::IntDiv 123366 0.05% 90.99% # Class of executed instruction |
| 362system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction 363system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction 364system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction 365system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction 366system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction 367system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction 368system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction 369system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 380system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction 381system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction 382system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction 383system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction 384system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction 385system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction 386system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction 387system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction | 343system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction 344system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction 345system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction 346system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction 347system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction 348system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction 349system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction 350system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 361system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction 362system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction 363system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction 364system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction 365system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction 366system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction 367system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction 368system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction |
| 388system.cpu.op_class::MemRead 13957123 5.62% 96.61% # Class of executed instruction 389system.cpu.op_class::MemWrite 8414644 3.39% 100.00% # Class of executed instruction | 369system.cpu.op_class::MemRead 13946864 5.62% 96.61% # Class of executed instruction 370system.cpu.op_class::MemWrite 8409880 3.39% 100.00% # Class of executed instruction |
| 390system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 391system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 371system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 372system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 392system.cpu.op_class::total 248243229 # Class of executed instruction | 373system.cpu.op_class::total 248047391 # Class of executed instruction |
| 393system.cpu.kern.inst.arm 0 # number of arm instructions executed 394system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 374system.cpu.kern.inst.arm 0 # number of arm instructions executed 375system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 395system.cpu.dcache.tags.replacements 1624253 # number of replacements 396system.cpu.dcache.tags.tagsinuse 511.996840 # Cycle average of tags in use 397system.cpu.dcache.tags.total_refs 20159481 # Total number of references to valid blocks. 398system.cpu.dcache.tags.sampled_refs 1624765 # Sample count of references to valid blocks. 399system.cpu.dcache.tags.avg_refs 12.407629 # Average number of references to valid blocks. 400system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. 401system.cpu.dcache.tags.occ_blocks::cpu.data 511.996840 # Average occupied blocks per requestor | 376system.cpu.dcache.tags.replacements 1622522 # number of replacements 377system.cpu.dcache.tags.tagsinuse 511.996992 # Cycle average of tags in use 378system.cpu.dcache.tags.total_refs 20153045 # Total number of references to valid blocks. 379system.cpu.dcache.tags.sampled_refs 1623034 # Sample count of references to valid blocks. 380system.cpu.dcache.tags.avg_refs 12.416896 # Average number of references to valid blocks. 381system.cpu.dcache.tags.warmup_cycle 54942250 # Cycle when the warmup percentage was hit. 382system.cpu.dcache.tags.occ_blocks::cpu.data 511.996992 # Average occupied blocks per requestor |
| 402system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 403system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 404system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 383system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 384system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 385system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 405system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 406system.cpu.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id 407system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id 408system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 386system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id 387system.cpu.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id 388system.cpu.dcache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id |
| 409system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 389system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 410system.cpu.dcache.tags.tag_accesses 88800329 # Number of tag accesses 411system.cpu.dcache.tags.data_accesses 88800329 # Number of data accesses 412system.cpu.dcache.ReadReq_hits::cpu.data 12017170 # number of ReadReq hits 413system.cpu.dcache.ReadReq_hits::total 12017170 # number of ReadReq hits 414system.cpu.dcache.WriteReq_hits::cpu.data 8080876 # number of WriteReq hits 415system.cpu.dcache.WriteReq_hits::total 8080876 # number of WriteReq hits 416system.cpu.dcache.SoftPFReq_hits::cpu.data 59251 # number of SoftPFReq hits 417system.cpu.dcache.SoftPFReq_hits::total 59251 # number of SoftPFReq hits 418system.cpu.dcache.demand_hits::cpu.data 20098046 # number of demand (read+write) hits 419system.cpu.dcache.demand_hits::total 20098046 # number of demand (read+write) hits 420system.cpu.dcache.overall_hits::cpu.data 20157297 # number of overall hits 421system.cpu.dcache.overall_hits::total 20157297 # number of overall hits 422system.cpu.dcache.ReadReq_misses::cpu.data 908286 # number of ReadReq misses 423system.cpu.dcache.ReadReq_misses::total 908286 # number of ReadReq misses 424system.cpu.dcache.WriteReq_misses::cpu.data 325792 # number of WriteReq misses 425system.cpu.dcache.WriteReq_misses::total 325792 # number of WriteReq misses 426system.cpu.dcache.SoftPFReq_misses::cpu.data 402501 # number of SoftPFReq misses 427system.cpu.dcache.SoftPFReq_misses::total 402501 # number of SoftPFReq misses 428system.cpu.dcache.demand_misses::cpu.data 1234078 # number of demand (read+write) misses 429system.cpu.dcache.demand_misses::total 1234078 # number of demand (read+write) misses 430system.cpu.dcache.overall_misses::cpu.data 1636579 # number of overall misses 431system.cpu.dcache.overall_misses::total 1636579 # number of overall misses 432system.cpu.dcache.ReadReq_miss_latency::cpu.data 12749281750 # number of ReadReq miss cycles 433system.cpu.dcache.ReadReq_miss_latency::total 12749281750 # number of ReadReq miss cycles 434system.cpu.dcache.WriteReq_miss_latency::cpu.data 11335230829 # number of WriteReq miss cycles 435system.cpu.dcache.WriteReq_miss_latency::total 11335230829 # number of WriteReq miss cycles 436system.cpu.dcache.demand_miss_latency::cpu.data 24084512579 # number of demand (read+write) miss cycles 437system.cpu.dcache.demand_miss_latency::total 24084512579 # number of demand (read+write) miss cycles 438system.cpu.dcache.overall_miss_latency::cpu.data 24084512579 # number of overall miss cycles 439system.cpu.dcache.overall_miss_latency::total 24084512579 # number of overall miss cycles 440system.cpu.dcache.ReadReq_accesses::cpu.data 12925456 # number of ReadReq accesses(hits+misses) 441system.cpu.dcache.ReadReq_accesses::total 12925456 # number of ReadReq accesses(hits+misses) 442system.cpu.dcache.WriteReq_accesses::cpu.data 8406668 # number of WriteReq accesses(hits+misses) 443system.cpu.dcache.WriteReq_accesses::total 8406668 # number of WriteReq accesses(hits+misses) 444system.cpu.dcache.SoftPFReq_accesses::cpu.data 461752 # number of SoftPFReq accesses(hits+misses) 445system.cpu.dcache.SoftPFReq_accesses::total 461752 # number of SoftPFReq accesses(hits+misses) 446system.cpu.dcache.demand_accesses::cpu.data 21332124 # number of demand (read+write) accesses 447system.cpu.dcache.demand_accesses::total 21332124 # number of demand (read+write) accesses 448system.cpu.dcache.overall_accesses::cpu.data 21793876 # number of overall (read+write) accesses 449system.cpu.dcache.overall_accesses::total 21793876 # number of overall (read+write) accesses 450system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070271 # miss rate for ReadReq accesses 451system.cpu.dcache.ReadReq_miss_rate::total 0.070271 # miss rate for ReadReq accesses 452system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038754 # miss rate for WriteReq accesses 453system.cpu.dcache.WriteReq_miss_rate::total 0.038754 # miss rate for WriteReq accesses 454system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871682 # miss rate for SoftPFReq accesses 455system.cpu.dcache.SoftPFReq_miss_rate::total 0.871682 # miss rate for SoftPFReq accesses 456system.cpu.dcache.demand_miss_rate::cpu.data 0.057851 # miss rate for demand accesses 457system.cpu.dcache.demand_miss_rate::total 0.057851 # miss rate for demand accesses 458system.cpu.dcache.overall_miss_rate::cpu.data 0.075094 # miss rate for overall accesses 459system.cpu.dcache.overall_miss_rate::total 0.075094 # miss rate for overall accesses 460system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14036.637964 # average ReadReq miss latency 461system.cpu.dcache.ReadReq_avg_miss_latency::total 14036.637964 # average ReadReq miss latency 462system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34792.845831 # average WriteReq miss latency 463system.cpu.dcache.WriteReq_avg_miss_latency::total 34792.845831 # average WriteReq miss latency 464system.cpu.dcache.demand_avg_miss_latency::cpu.data 19516.199607 # average overall miss latency 465system.cpu.dcache.demand_avg_miss_latency::total 19516.199607 # average overall miss latency 466system.cpu.dcache.overall_avg_miss_latency::cpu.data 14716.376404 # average overall miss latency 467system.cpu.dcache.overall_avg_miss_latency::total 14716.376404 # average overall miss latency 468system.cpu.dcache.blocked_cycles::no_mshrs 9103 # number of cycles access was blocked | 390system.cpu.dcache.tags.tag_accesses 88765477 # Number of tag accesses 391system.cpu.dcache.tags.data_accesses 88765477 # Number of data accesses 392system.cpu.dcache.ReadReq_hits::cpu.data 12014873 # number of ReadReq hits 393system.cpu.dcache.ReadReq_hits::total 12014873 # number of ReadReq hits 394system.cpu.dcache.WriteReq_hits::cpu.data 8077139 # number of WriteReq hits 395system.cpu.dcache.WriteReq_hits::total 8077139 # number of WriteReq hits 396system.cpu.dcache.SoftPFReq_hits::cpu.data 58853 # number of SoftPFReq hits 397system.cpu.dcache.SoftPFReq_hits::total 58853 # number of SoftPFReq hits 398system.cpu.dcache.demand_hits::cpu.data 20092012 # number of demand (read+write) hits 399system.cpu.dcache.demand_hits::total 20092012 # number of demand (read+write) hits 400system.cpu.dcache.overall_hits::cpu.data 20150865 # number of overall hits 401system.cpu.dcache.overall_hits::total 20150865 # number of overall hits 402system.cpu.dcache.ReadReq_misses::cpu.data 906821 # number of ReadReq misses 403system.cpu.dcache.ReadReq_misses::total 906821 # number of ReadReq misses 404system.cpu.dcache.WriteReq_misses::cpu.data 324755 # number of WriteReq misses 405system.cpu.dcache.WriteReq_misses::total 324755 # number of WriteReq misses 406system.cpu.dcache.SoftPFReq_misses::cpu.data 403161 # number of SoftPFReq misses 407system.cpu.dcache.SoftPFReq_misses::total 403161 # number of SoftPFReq misses 408system.cpu.dcache.demand_misses::cpu.data 1231576 # number of demand (read+write) misses 409system.cpu.dcache.demand_misses::total 1231576 # number of demand (read+write) misses 410system.cpu.dcache.overall_misses::cpu.data 1634737 # number of overall misses 411system.cpu.dcache.overall_misses::total 1634737 # number of overall misses 412system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles 413system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles 414system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles 415system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles 416system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles 417system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles 418system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles 419system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles 420system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses) 421system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses) 422system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::total 8401894 # number of WriteReq accesses(hits+misses) 424system.cpu.dcache.SoftPFReq_accesses::cpu.data 462014 # number of SoftPFReq accesses(hits+misses) 425system.cpu.dcache.SoftPFReq_accesses::total 462014 # number of SoftPFReq accesses(hits+misses) 426system.cpu.dcache.demand_accesses::cpu.data 21323588 # number of demand (read+write) accesses 427system.cpu.dcache.demand_accesses::total 21323588 # number of demand (read+write) accesses 428system.cpu.dcache.overall_accesses::cpu.data 21785602 # number of overall (read+write) accesses 429system.cpu.dcache.overall_accesses::total 21785602 # number of overall (read+write) accesses 430system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070178 # miss rate for ReadReq accesses 431system.cpu.dcache.ReadReq_miss_rate::total 0.070178 # miss rate for ReadReq accesses 432system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038653 # miss rate for WriteReq accesses 433system.cpu.dcache.WriteReq_miss_rate::total 0.038653 # miss rate for WriteReq accesses 434system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872616 # miss rate for SoftPFReq accesses 435system.cpu.dcache.SoftPFReq_miss_rate::total 0.872616 # miss rate for SoftPFReq accesses 436system.cpu.dcache.demand_miss_rate::cpu.data 0.057757 # miss rate for demand accesses 437system.cpu.dcache.demand_miss_rate::total 0.057757 # miss rate for demand accesses 438system.cpu.dcache.overall_miss_rate::cpu.data 0.075037 # miss rate for overall accesses 439system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses 440system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency 441system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency 442system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.674465 # average WriteReq miss latency 443system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.674465 # average WriteReq miss latency 444system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.768935 # average overall miss latency 445system.cpu.dcache.demand_avg_miss_latency::total 20287.768935 # average overall miss latency 446system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.372541 # average overall miss latency 447system.cpu.dcache.overall_avg_miss_latency::total 15284.372541 # average overall miss latency 448system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked |
| 469system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 449system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 470system.cpu.dcache.blocked::no_mshrs 96 # number of cycles access was blocked | 450system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked |
| 471system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 451system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 472system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.822917 # average number of cycles each access was blocked | 452system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.301370 # average number of cycles each access was blocked |
| 473system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 474system.cpu.dcache.fast_writes 0 # number of fast writes performed 475system.cpu.dcache.cache_copies 0 # number of cache copies performed | 453system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 454system.cpu.dcache.fast_writes 0 # number of fast writes performed 455system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 476system.cpu.dcache.writebacks::writebacks 1540563 # number of writebacks 477system.cpu.dcache.writebacks::total 1540563 # number of writebacks | 456system.cpu.dcache.writebacks::writebacks 1539491 # number of writebacks 457system.cpu.dcache.writebacks::total 1539491 # number of writebacks |
| 478system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits 479system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits | 458system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits 459system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits |
| 480system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9246 # number of WriteReq MSHR hits 481system.cpu.dcache.WriteReq_mshr_hits::total 9246 # number of WriteReq MSHR hits 482system.cpu.dcache.demand_mshr_hits::cpu.data 9536 # number of demand (read+write) MSHR hits 483system.cpu.dcache.demand_mshr_hits::total 9536 # number of demand (read+write) MSHR hits 484system.cpu.dcache.overall_mshr_hits::cpu.data 9536 # number of overall MSHR hits 485system.cpu.dcache.overall_mshr_hits::total 9536 # number of overall MSHR hits 486system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907996 # number of ReadReq MSHR misses 487system.cpu.dcache.ReadReq_mshr_misses::total 907996 # number of ReadReq MSHR misses 488system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316546 # number of WriteReq MSHR misses 489system.cpu.dcache.WriteReq_mshr_misses::total 316546 # number of WriteReq MSHR misses 490system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402467 # number of SoftPFReq MSHR misses 491system.cpu.dcache.SoftPFReq_mshr_misses::total 402467 # number of SoftPFReq MSHR misses 492system.cpu.dcache.demand_mshr_misses::cpu.data 1224542 # number of demand (read+write) MSHR misses 493system.cpu.dcache.demand_mshr_misses::total 1224542 # number of demand (read+write) MSHR misses 494system.cpu.dcache.overall_mshr_misses::cpu.data 1627009 # number of overall MSHR misses 495system.cpu.dcache.overall_mshr_misses::total 1627009 # number of overall MSHR misses 496system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10925755250 # number of ReadReq MSHR miss cycles 497system.cpu.dcache.ReadReq_mshr_miss_latency::total 10925755250 # number of ReadReq MSHR miss cycles 498system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10200095361 # number of WriteReq MSHR miss cycles 499system.cpu.dcache.WriteReq_mshr_miss_latency::total 10200095361 # number of WriteReq MSHR miss cycles 500system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5340766250 # number of SoftPFReq MSHR miss cycles 501system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5340766250 # number of SoftPFReq MSHR miss cycles 502system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21125850611 # number of demand (read+write) MSHR miss cycles 503system.cpu.dcache.demand_mshr_miss_latency::total 21125850611 # number of demand (read+write) MSHR miss cycles 504system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26466616861 # number of overall MSHR miss cycles 505system.cpu.dcache.overall_mshr_miss_latency::total 26466616861 # number of overall MSHR miss cycles 506system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94247525000 # number of ReadReq MSHR uncacheable cycles 507system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94247525000 # number of ReadReq MSHR uncacheable cycles 508system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568413500 # number of WriteReq MSHR uncacheable cycles 509system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568413500 # number of WriteReq MSHR uncacheable cycles 510system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815938500 # number of overall MSHR uncacheable cycles 511system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815938500 # number of overall MSHR uncacheable cycles 512system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070249 # mshr miss rate for ReadReq accesses 513system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070249 # mshr miss rate for ReadReq accesses 514system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037654 # mshr miss rate for WriteReq accesses 515system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037654 # mshr miss rate for WriteReq accesses 516system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871609 # mshr miss rate for SoftPFReq accesses 517system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871609 # mshr miss rate for SoftPFReq accesses 518system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057404 # mshr miss rate for demand accesses 519system.cpu.dcache.demand_mshr_miss_rate::total 0.057404 # mshr miss rate for demand accesses 520system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074654 # mshr miss rate for overall accesses 521system.cpu.dcache.overall_mshr_miss_rate::total 0.074654 # mshr miss rate for overall accesses 522system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.823107 # average ReadReq mshr miss latency 523system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.823107 # average ReadReq mshr miss latency 524system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32223.106155 # average WriteReq mshr miss latency 525system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32223.106155 # average WriteReq mshr miss latency 526system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.072453 # average SoftPFReq mshr miss latency 527system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.072453 # average SoftPFReq mshr miss latency 528system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17252.042487 # average overall mshr miss latency 529system.cpu.dcache.demand_avg_mshr_miss_latency::total 17252.042487 # average overall mshr miss latency 530system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16267.037774 # average overall mshr miss latency 531system.cpu.dcache.overall_avg_mshr_miss_latency::total 16267.037774 # average overall mshr miss latency | 460system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9162 # number of WriteReq MSHR hits 461system.cpu.dcache.WriteReq_mshr_hits::total 9162 # number of WriteReq MSHR hits 462system.cpu.dcache.demand_mshr_hits::cpu.data 9452 # number of demand (read+write) MSHR hits 463system.cpu.dcache.demand_mshr_hits::total 9452 # number of demand (read+write) MSHR hits 464system.cpu.dcache.overall_mshr_hits::cpu.data 9452 # number of overall MSHR hits 465system.cpu.dcache.overall_mshr_hits::total 9452 # number of overall MSHR hits 466system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906531 # number of ReadReq MSHR misses 467system.cpu.dcache.ReadReq_mshr_misses::total 906531 # number of ReadReq MSHR misses 468system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315593 # number of WriteReq MSHR misses 469system.cpu.dcache.WriteReq_mshr_misses::total 315593 # number of WriteReq MSHR misses 470system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403125 # number of SoftPFReq MSHR misses 471system.cpu.dcache.SoftPFReq_mshr_misses::total 403125 # number of SoftPFReq MSHR misses 472system.cpu.dcache.demand_mshr_misses::cpu.data 1222124 # number of demand (read+write) MSHR misses 473system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses 474system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses 475system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses 476system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles 477system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles 478system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117308860 # number of WriteReq MSHR miss cycles 479system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117308860 # number of WriteReq MSHR miss cycles 480system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles 481system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles 482system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586067642 # number of demand (read+write) MSHR miss cycles 483system.cpu.dcache.demand_mshr_miss_latency::total 22586067642 # number of demand (read+write) MSHR miss cycles 484system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213365142 # number of overall MSHR miss cycles 485system.cpu.dcache.overall_mshr_miss_latency::total 28213365142 # number of overall MSHR miss cycles 486system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles 487system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles 488system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles 489system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593293500 # number of WriteReq MSHR uncacheable cycles 490system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96957757000 # number of overall MSHR uncacheable cycles 491system.cpu.dcache.overall_mshr_uncacheable_latency::total 96957757000 # number of overall MSHR uncacheable cycles 492system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070156 # mshr miss rate for ReadReq accesses 493system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070156 # mshr miss rate for ReadReq accesses 494system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037562 # mshr miss rate for WriteReq accesses 495system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037562 # mshr miss rate for WriteReq accesses 496system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872538 # mshr miss rate for SoftPFReq accesses 497system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872538 # mshr miss rate for SoftPFReq accesses 498system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057313 # mshr miss rate for demand accesses 499system.cpu.dcache.demand_mshr_miss_rate::total 0.057313 # mshr miss rate for demand accesses 500system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074602 # mshr miss rate for overall accesses 501system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses 502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency 503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency 504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.728286 # average WriteReq mshr miss latency 505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.728286 # average WriteReq mshr miss latency 506system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency 507system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency 508system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18480.995089 # average overall mshr miss latency 509system.cpu.dcache.demand_avg_mshr_miss_latency::total 18480.995089 # average overall mshr miss latency 510system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.410861 # average overall mshr miss latency 511system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.410861 # average overall mshr miss latency |
| 532system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 533system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 534system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 535system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 536system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 537system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 538system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 512system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 513system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 514system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 515system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 516system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 517system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 518system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 539system.cpu.dtb_walker_cache.tags.replacements 7518 # number of replacements 540system.cpu.dtb_walker_cache.tags.tagsinuse 5.053105 # Cycle average of tags in use 541system.cpu.dtb_walker_cache.tags.total_refs 13360 # Total number of references to valid blocks. 542system.cpu.dtb_walker_cache.tags.sampled_refs 7533 # Sample count of references to valid blocks. 543system.cpu.dtb_walker_cache.tags.avg_refs 1.773530 # Average number of references to valid blocks. 544system.cpu.dtb_walker_cache.tags.warmup_cycle 5157758038000 # Cycle when the warmup percentage was hit. 545system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053105 # Average occupied blocks per requestor 546system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315819 # Average percentage of cache occupancy 547system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315819 # Average percentage of cache occupancy | 519system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements 520system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use 521system.cpu.dtb_walker_cache.tags.total_refs 12184 # Total number of references to valid blocks. 522system.cpu.dtb_walker_cache.tags.sampled_refs 8903 # Sample count of references to valid blocks. 523system.cpu.dtb_walker_cache.tags.avg_refs 1.368527 # Average number of references to valid blocks. 524system.cpu.dtb_walker_cache.tags.warmup_cycle 5156876909000 # Cycle when the warmup percentage was hit. 525system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.045606 # Average occupied blocks per requestor 526system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315350 # Average percentage of cache occupancy 527system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315350 # Average percentage of cache occupancy |
| 548system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 549system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id | 528system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 529system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id |
| 550system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id 551system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id | 530system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 531system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id |
| 552system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id | 532system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id |
| 553system.cpu.dtb_walker_cache.tags.tag_accesses 52972 # Number of tag accesses 554system.cpu.dtb_walker_cache.tags.data_accesses 52972 # Number of data accesses 555system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13370 # number of ReadReq hits 556system.cpu.dtb_walker_cache.ReadReq_hits::total 13370 # number of ReadReq hits 557system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13370 # number of demand (read+write) hits 558system.cpu.dtb_walker_cache.demand_hits::total 13370 # number of demand (read+write) hits 559system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13370 # number of overall hits 560system.cpu.dtb_walker_cache.overall_hits::total 13370 # number of overall hits 561system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8744 # number of ReadReq misses 562system.cpu.dtb_walker_cache.ReadReq_misses::total 8744 # number of ReadReq misses 563system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8744 # number of demand (read+write) misses 564system.cpu.dtb_walker_cache.demand_misses::total 8744 # number of demand (read+write) misses 565system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8744 # number of overall misses 566system.cpu.dtb_walker_cache.overall_misses::total 8744 # number of overall misses 567system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92278000 # number of ReadReq miss cycles 568system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92278000 # number of ReadReq miss cycles 569system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92278000 # number of demand (read+write) miss cycles 570system.cpu.dtb_walker_cache.demand_miss_latency::total 92278000 # number of demand (read+write) miss cycles 571system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92278000 # number of overall miss cycles 572system.cpu.dtb_walker_cache.overall_miss_latency::total 92278000 # number of overall miss cycles 573system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22114 # number of ReadReq accesses(hits+misses) 574system.cpu.dtb_walker_cache.ReadReq_accesses::total 22114 # number of ReadReq accesses(hits+misses) 575system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22114 # number of demand (read+write) accesses 576system.cpu.dtb_walker_cache.demand_accesses::total 22114 # number of demand (read+write) accesses 577system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22114 # number of overall (read+write) accesses 578system.cpu.dtb_walker_cache.overall_accesses::total 22114 # number of overall (read+write) accesses 579system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395406 # miss rate for ReadReq accesses 580system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395406 # miss rate for ReadReq accesses 581system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395406 # miss rate for demand accesses 582system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395406 # miss rate for demand accesses 583system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395406 # miss rate for overall accesses 584system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395406 # miss rate for overall accesses 585system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.293687 # average ReadReq miss latency 586system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.293687 # average ReadReq miss latency 587system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency 588system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.293687 # average overall miss latency 589system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency 590system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.293687 # average overall miss latency | 533system.cpu.dtb_walker_cache.tags.tag_accesses 54641 # Number of tag accesses 534system.cpu.dtb_walker_cache.tags.data_accesses 54641 # Number of data accesses 535system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12184 # number of ReadReq hits 536system.cpu.dtb_walker_cache.ReadReq_hits::total 12184 # number of ReadReq hits 537system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12184 # number of demand (read+write) hits 538system.cpu.dtb_walker_cache.demand_hits::total 12184 # number of demand (read+write) hits 539system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12184 # number of overall hits 540system.cpu.dtb_walker_cache.overall_hits::total 12184 # number of overall hits 541system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 10091 # number of ReadReq misses 542system.cpu.dtb_walker_cache.ReadReq_misses::total 10091 # number of ReadReq misses 543system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 10091 # number of demand (read+write) misses 544system.cpu.dtb_walker_cache.demand_misses::total 10091 # number of demand (read+write) misses 545system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 10091 # number of overall misses 546system.cpu.dtb_walker_cache.overall_misses::total 10091 # number of overall misses 547system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 104642000 # number of ReadReq miss cycles 548system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 104642000 # number of ReadReq miss cycles 549system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 104642000 # number of demand (read+write) miss cycles 550system.cpu.dtb_walker_cache.demand_miss_latency::total 104642000 # number of demand (read+write) miss cycles 551system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 104642000 # number of overall miss cycles 552system.cpu.dtb_walker_cache.overall_miss_latency::total 104642000 # number of overall miss cycles 553system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22275 # number of ReadReq accesses(hits+misses) 554system.cpu.dtb_walker_cache.ReadReq_accesses::total 22275 # number of ReadReq accesses(hits+misses) 555system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22275 # number of demand (read+write) accesses 556system.cpu.dtb_walker_cache.demand_accesses::total 22275 # number of demand (read+write) accesses 557system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22275 # number of overall (read+write) accesses 558system.cpu.dtb_walker_cache.overall_accesses::total 22275 # number of overall (read+write) accesses 559system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.453019 # miss rate for ReadReq accesses 560system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.453019 # miss rate for ReadReq accesses 561system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.453019 # miss rate for demand accesses 562system.cpu.dtb_walker_cache.demand_miss_rate::total 0.453019 # miss rate for demand accesses 563system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.453019 # miss rate for overall accesses 564system.cpu.dtb_walker_cache.overall_miss_rate::total 0.453019 # miss rate for overall accesses 565system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10369.834506 # average ReadReq miss latency 566system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10369.834506 # average ReadReq miss latency 567system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency 568system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10369.834506 # average overall miss latency 569system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency 570system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10369.834506 # average overall miss latency |
| 591system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 592system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 593system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 594system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 595system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 596system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 597system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 598system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 571system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 572system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 573system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 574system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 575system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 576system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 577system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 578system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 599system.cpu.dtb_walker_cache.writebacks::writebacks 2885 # number of writebacks 600system.cpu.dtb_walker_cache.writebacks::total 2885 # number of writebacks 601system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8744 # number of ReadReq MSHR misses 602system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8744 # number of ReadReq MSHR misses 603system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8744 # number of demand (read+write) MSHR misses 604system.cpu.dtb_walker_cache.demand_mshr_misses::total 8744 # number of demand (read+write) MSHR misses 605system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8744 # number of overall MSHR misses 606system.cpu.dtb_walker_cache.overall_mshr_misses::total 8744 # number of overall MSHR misses 607system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74789500 # number of ReadReq MSHR miss cycles 608system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74789500 # number of ReadReq MSHR miss cycles 609system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74789500 # number of demand (read+write) MSHR miss cycles 610system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74789500 # number of demand (read+write) MSHR miss cycles 611system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74789500 # number of overall MSHR miss cycles 612system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74789500 # number of overall MSHR miss cycles 613system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for ReadReq accesses 614system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395406 # mshr miss rate for ReadReq accesses 615system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for demand accesses 616system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395406 # mshr miss rate for demand accesses 617system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for overall accesses 618system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395406 # mshr miss rate for overall accesses 619system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average ReadReq mshr miss latency 620system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.236505 # average ReadReq mshr miss latency 621system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency 622system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency 623system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency 624system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency | 579system.cpu.dtb_walker_cache.writebacks::writebacks 3116 # number of writebacks 580system.cpu.dtb_walker_cache.writebacks::total 3116 # number of writebacks 581system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 10091 # number of ReadReq MSHR misses 582system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 10091 # number of ReadReq MSHR misses 583system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 10091 # number of demand (read+write) MSHR misses 584system.cpu.dtb_walker_cache.demand_mshr_misses::total 10091 # number of demand (read+write) MSHR misses 585system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 10091 # number of overall MSHR misses 586system.cpu.dtb_walker_cache.overall_mshr_misses::total 10091 # number of overall MSHR misses 587system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 89505500 # number of ReadReq MSHR miss cycles 588system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 89505500 # number of ReadReq MSHR miss cycles 589system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 89505500 # number of demand (read+write) MSHR miss cycles 590system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 89505500 # number of demand (read+write) MSHR miss cycles 591system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 89505500 # number of overall MSHR miss cycles 592system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 89505500 # number of overall MSHR miss cycles 593system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for ReadReq accesses 594system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.453019 # mshr miss rate for ReadReq accesses 595system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for demand accesses 596system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.453019 # mshr miss rate for demand accesses 597system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for overall accesses 598system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.453019 # mshr miss rate for overall accesses 599system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average ReadReq mshr miss latency 600system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8869.834506 # average ReadReq mshr miss latency 601system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency 602system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency 603system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency 604system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency |
| 625system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 605system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 626system.cpu.icache.tags.replacements 794079 # number of replacements 627system.cpu.icache.tags.tagsinuse 510.347189 # Cycle average of tags in use 628system.cpu.icache.tags.total_refs 145115978 # Total number of references to valid blocks. 629system.cpu.icache.tags.sampled_refs 794591 # Sample count of references to valid blocks. 630system.cpu.icache.tags.avg_refs 182.629778 # Average number of references to valid blocks. 631system.cpu.icache.tags.warmup_cycle 161164789250 # Cycle when the warmup percentage was hit. 632system.cpu.icache.tags.occ_blocks::cpu.inst 510.347189 # Average occupied blocks per requestor 633system.cpu.icache.tags.occ_percent::cpu.inst 0.996772 # Average percentage of cache occupancy 634system.cpu.icache.tags.occ_percent::total 0.996772 # Average percentage of cache occupancy | 606system.cpu.icache.tags.replacements 794465 # number of replacements 607system.cpu.icache.tags.tagsinuse 510.329327 # Cycle average of tags in use 608system.cpu.icache.tags.total_refs 144962865 # Total number of references to valid blocks. 609system.cpu.icache.tags.sampled_refs 794977 # Sample count of references to valid blocks. 610system.cpu.icache.tags.avg_refs 182.348502 # Average number of references to valid blocks. 611system.cpu.icache.tags.warmup_cycle 161575846250 # Cycle when the warmup percentage was hit. 612system.cpu.icache.tags.occ_blocks::cpu.inst 510.329327 # Average occupied blocks per requestor 613system.cpu.icache.tags.occ_percent::cpu.inst 0.996737 # Average percentage of cache occupancy 614system.cpu.icache.tags.occ_percent::total 0.996737 # Average percentage of cache occupancy |
| 635system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 615system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 636system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 637system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id 638system.cpu.icache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id | 616system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 617system.cpu.icache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id 618system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id |
| 639system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 640system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 619system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id 620system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 641system.cpu.icache.tags.tag_accesses 146705174 # Number of tag accesses 642system.cpu.icache.tags.data_accesses 146705174 # Number of data accesses 643system.cpu.icache.ReadReq_hits::cpu.inst 145115978 # number of ReadReq hits 644system.cpu.icache.ReadReq_hits::total 145115978 # number of ReadReq hits 645system.cpu.icache.demand_hits::cpu.inst 145115978 # number of demand (read+write) hits 646system.cpu.icache.demand_hits::total 145115978 # number of demand (read+write) hits 647system.cpu.icache.overall_hits::cpu.inst 145115978 # number of overall hits 648system.cpu.icache.overall_hits::total 145115978 # number of overall hits 649system.cpu.icache.ReadReq_misses::cpu.inst 794598 # number of ReadReq misses 650system.cpu.icache.ReadReq_misses::total 794598 # number of ReadReq misses 651system.cpu.icache.demand_misses::cpu.inst 794598 # number of demand (read+write) misses 652system.cpu.icache.demand_misses::total 794598 # number of demand (read+write) misses 653system.cpu.icache.overall_misses::cpu.inst 794598 # number of overall misses 654system.cpu.icache.overall_misses::total 794598 # number of overall misses 655system.cpu.icache.ReadReq_miss_latency::cpu.inst 11149966366 # number of ReadReq miss cycles 656system.cpu.icache.ReadReq_miss_latency::total 11149966366 # number of ReadReq miss cycles 657system.cpu.icache.demand_miss_latency::cpu.inst 11149966366 # number of demand (read+write) miss cycles 658system.cpu.icache.demand_miss_latency::total 11149966366 # number of demand (read+write) miss cycles 659system.cpu.icache.overall_miss_latency::cpu.inst 11149966366 # number of overall miss cycles 660system.cpu.icache.overall_miss_latency::total 11149966366 # number of overall miss cycles 661system.cpu.icache.ReadReq_accesses::cpu.inst 145910576 # number of ReadReq accesses(hits+misses) 662system.cpu.icache.ReadReq_accesses::total 145910576 # number of ReadReq accesses(hits+misses) 663system.cpu.icache.demand_accesses::cpu.inst 145910576 # number of demand (read+write) accesses 664system.cpu.icache.demand_accesses::total 145910576 # number of demand (read+write) accesses 665system.cpu.icache.overall_accesses::cpu.inst 145910576 # number of overall (read+write) accesses 666system.cpu.icache.overall_accesses::total 145910576 # number of overall (read+write) accesses 667system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005446 # miss rate for ReadReq accesses 668system.cpu.icache.ReadReq_miss_rate::total 0.005446 # miss rate for ReadReq accesses 669system.cpu.icache.demand_miss_rate::cpu.inst 0.005446 # miss rate for demand accesses 670system.cpu.icache.demand_miss_rate::total 0.005446 # miss rate for demand accesses 671system.cpu.icache.overall_miss_rate::cpu.inst 0.005446 # miss rate for overall accesses 672system.cpu.icache.overall_miss_rate::total 0.005446 # miss rate for overall accesses 673system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14032.210459 # average ReadReq miss latency 674system.cpu.icache.ReadReq_avg_miss_latency::total 14032.210459 # average ReadReq miss latency 675system.cpu.icache.demand_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency 676system.cpu.icache.demand_avg_miss_latency::total 14032.210459 # average overall miss latency 677system.cpu.icache.overall_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency 678system.cpu.icache.overall_avg_miss_latency::total 14032.210459 # average overall miss latency | 621system.cpu.icache.tags.tag_accesses 146552833 # Number of tag accesses 622system.cpu.icache.tags.data_accesses 146552833 # Number of data accesses 623system.cpu.icache.ReadReq_hits::cpu.inst 144962865 # number of ReadReq hits 624system.cpu.icache.ReadReq_hits::total 144962865 # number of ReadReq hits 625system.cpu.icache.demand_hits::cpu.inst 144962865 # number of demand (read+write) hits 626system.cpu.icache.demand_hits::total 144962865 # number of demand (read+write) hits 627system.cpu.icache.overall_hits::cpu.inst 144962865 # number of overall hits 628system.cpu.icache.overall_hits::total 144962865 # number of overall hits 629system.cpu.icache.ReadReq_misses::cpu.inst 794984 # number of ReadReq misses 630system.cpu.icache.ReadReq_misses::total 794984 # number of ReadReq misses 631system.cpu.icache.demand_misses::cpu.inst 794984 # number of demand (read+write) misses 632system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses 633system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses 634system.cpu.icache.overall_misses::total 794984 # number of overall misses 635system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253089237 # number of ReadReq miss cycles 636system.cpu.icache.ReadReq_miss_latency::total 11253089237 # number of ReadReq miss cycles 637system.cpu.icache.demand_miss_latency::cpu.inst 11253089237 # number of demand (read+write) miss cycles 638system.cpu.icache.demand_miss_latency::total 11253089237 # number of demand (read+write) miss cycles 639system.cpu.icache.overall_miss_latency::cpu.inst 11253089237 # number of overall miss cycles 640system.cpu.icache.overall_miss_latency::total 11253089237 # number of overall miss cycles 641system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses) 642system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses) 643system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses 644system.cpu.icache.demand_accesses::total 145757849 # number of demand (read+write) accesses 645system.cpu.icache.overall_accesses::cpu.inst 145757849 # number of overall (read+write) accesses 646system.cpu.icache.overall_accesses::total 145757849 # number of overall (read+write) accesses 647system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005454 # miss rate for ReadReq accesses 648system.cpu.icache.ReadReq_miss_rate::total 0.005454 # miss rate for ReadReq accesses 649system.cpu.icache.demand_miss_rate::cpu.inst 0.005454 # miss rate for demand accesses 650system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses 651system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses 652system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses 653system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.114112 # average ReadReq miss latency 654system.cpu.icache.ReadReq_avg_miss_latency::total 14155.114112 # average ReadReq miss latency 655system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency 656system.cpu.icache.demand_avg_miss_latency::total 14155.114112 # average overall miss latency 657system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency 658system.cpu.icache.overall_avg_miss_latency::total 14155.114112 # average overall miss latency |
| 679system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 680system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 681system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 682system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 683system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 684system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 685system.cpu.icache.fast_writes 0 # number of fast writes performed 686system.cpu.icache.cache_copies 0 # number of cache copies performed | 659system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 660system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 661system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 662system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 663system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 664system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 665system.cpu.icache.fast_writes 0 # number of fast writes performed 666system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 687system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794598 # number of ReadReq MSHR misses 688system.cpu.icache.ReadReq_mshr_misses::total 794598 # number of ReadReq MSHR misses 689system.cpu.icache.demand_mshr_misses::cpu.inst 794598 # number of demand (read+write) MSHR misses 690system.cpu.icache.demand_mshr_misses::total 794598 # number of demand (read+write) MSHR misses 691system.cpu.icache.overall_mshr_misses::cpu.inst 794598 # number of overall MSHR misses 692system.cpu.icache.overall_mshr_misses::total 794598 # number of overall MSHR misses 693system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9555900634 # number of ReadReq MSHR miss cycles 694system.cpu.icache.ReadReq_mshr_miss_latency::total 9555900634 # number of ReadReq MSHR miss cycles 695system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9555900634 # number of demand (read+write) MSHR miss cycles 696system.cpu.icache.demand_mshr_miss_latency::total 9555900634 # number of demand (read+write) MSHR miss cycles 697system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9555900634 # number of overall MSHR miss cycles 698system.cpu.icache.overall_mshr_miss_latency::total 9555900634 # number of overall MSHR miss cycles 699system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for ReadReq accesses 700system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005446 # mshr miss rate for ReadReq accesses 701system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for demand accesses 702system.cpu.icache.demand_mshr_miss_rate::total 0.005446 # mshr miss rate for demand accesses 703system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for overall accesses 704system.cpu.icache.overall_mshr_miss_rate::total 0.005446 # mshr miss rate for overall accesses 705system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.081911 # average ReadReq mshr miss latency 706system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.081911 # average ReadReq mshr miss latency 707system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency 708system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency 709system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency 710system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency | 667system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794984 # number of ReadReq MSHR misses 668system.cpu.icache.ReadReq_mshr_misses::total 794984 # number of ReadReq MSHR misses 669system.cpu.icache.demand_mshr_misses::cpu.inst 794984 # number of demand (read+write) MSHR misses 670system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses 671system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses 672system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses 673system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055827763 # number of ReadReq MSHR miss cycles 674system.cpu.icache.ReadReq_mshr_miss_latency::total 10055827763 # number of ReadReq MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055827763 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.demand_mshr_miss_latency::total 10055827763 # number of demand (read+write) MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055827763 # number of overall MSHR miss cycles 678system.cpu.icache.overall_mshr_miss_latency::total 10055827763 # number of overall MSHR miss cycles 679system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses 680system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses 681system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses 682system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses 683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses 684system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.094526 # average ReadReq mshr miss latency 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.094526 # average ReadReq mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency |
| 711system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 691system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 712system.cpu.itb_walker_cache.tags.replacements 3473 # number of replacements 713system.cpu.itb_walker_cache.tags.tagsinuse 3.069566 # Cycle average of tags in use 714system.cpu.itb_walker_cache.tags.total_refs 7987 # Total number of references to valid blocks. 715system.cpu.itb_walker_cache.tags.sampled_refs 3486 # Sample count of references to valid blocks. 716system.cpu.itb_walker_cache.tags.avg_refs 2.291165 # Average number of references to valid blocks. 717system.cpu.itb_walker_cache.tags.warmup_cycle 5161163241000 # Cycle when the warmup percentage was hit. 718system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069566 # Average occupied blocks per requestor 719system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191848 # Average percentage of cache occupancy 720system.cpu.itb_walker_cache.tags.occ_percent::total 0.191848 # Average percentage of cache occupancy 721system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id | 692system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements 693system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use 694system.cpu.itb_walker_cache.tags.total_refs 7028 # Total number of references to valid blocks. 695system.cpu.itb_walker_cache.tags.sampled_refs 4451 # Sample count of references to valid blocks. 696system.cpu.itb_walker_cache.tags.avg_refs 1.578971 # Average number of references to valid blocks. 697system.cpu.itb_walker_cache.tags.warmup_cycle 5161420260000 # Cycle when the warmup percentage was hit. 698system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.061283 # Average occupied blocks per requestor 699system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191330 # Average percentage of cache occupancy 700system.cpu.itb_walker_cache.tags.occ_percent::total 0.191330 # Average percentage of cache occupancy 701system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id |
| 722system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id | 702system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id |
| 723system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 724system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 725system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 726system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 727system.cpu.itb_walker_cache.tags.tag_accesses 28991 # Number of tag accesses 728system.cpu.itb_walker_cache.tags.data_accesses 28991 # Number of data accesses 729system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7985 # number of ReadReq hits 730system.cpu.itb_walker_cache.ReadReq_hits::total 7985 # number of ReadReq hits | 703system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 704system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 705system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 706system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id 707system.cpu.itb_walker_cache.tags.tag_accesses 29974 # Number of tag accesses 708system.cpu.itb_walker_cache.tags.data_accesses 29974 # Number of data accesses 709system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7029 # number of ReadReq hits 710system.cpu.itb_walker_cache.ReadReq_hits::total 7029 # number of ReadReq hits |
| 731system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 732system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 711system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 712system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 733system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7987 # number of demand (read+write) hits 734system.cpu.itb_walker_cache.demand_hits::total 7987 # number of demand (read+write) hits 735system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7987 # number of overall hits 736system.cpu.itb_walker_cache.overall_hits::total 7987 # number of overall hits 737system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4339 # number of ReadReq misses 738system.cpu.itb_walker_cache.ReadReq_misses::total 4339 # number of ReadReq misses 739system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4339 # number of demand (read+write) misses 740system.cpu.itb_walker_cache.demand_misses::total 4339 # number of demand (read+write) misses 741system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4339 # number of overall misses 742system.cpu.itb_walker_cache.overall_misses::total 4339 # number of overall misses 743system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42562750 # number of ReadReq miss cycles 744system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42562750 # number of ReadReq miss cycles 745system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42562750 # number of demand (read+write) miss cycles 746system.cpu.itb_walker_cache.demand_miss_latency::total 42562750 # number of demand (read+write) miss cycles 747system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42562750 # number of overall miss cycles 748system.cpu.itb_walker_cache.overall_miss_latency::total 42562750 # number of overall miss cycles 749system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12324 # number of ReadReq accesses(hits+misses) 750system.cpu.itb_walker_cache.ReadReq_accesses::total 12324 # number of ReadReq accesses(hits+misses) | 713system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7031 # number of demand (read+write) hits 714system.cpu.itb_walker_cache.demand_hits::total 7031 # number of demand (read+write) hits 715system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7031 # number of overall hits 716system.cpu.itb_walker_cache.overall_hits::total 7031 # number of overall hits 717system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 5304 # number of ReadReq misses 718system.cpu.itb_walker_cache.ReadReq_misses::total 5304 # number of ReadReq misses 719system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 5304 # number of demand (read+write) misses 720system.cpu.itb_walker_cache.demand_misses::total 5304 # number of demand (read+write) misses 721system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 5304 # number of overall misses 722system.cpu.itb_walker_cache.overall_misses::total 5304 # number of overall misses 723system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51550250 # number of ReadReq miss cycles 724system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51550250 # number of ReadReq miss cycles 725system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51550250 # number of demand (read+write) miss cycles 726system.cpu.itb_walker_cache.demand_miss_latency::total 51550250 # number of demand (read+write) miss cycles 727system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51550250 # number of overall miss cycles 728system.cpu.itb_walker_cache.overall_miss_latency::total 51550250 # number of overall miss cycles 729system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12333 # number of ReadReq accesses(hits+misses) 730system.cpu.itb_walker_cache.ReadReq_accesses::total 12333 # number of ReadReq accesses(hits+misses) |
| 751system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 752system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 731system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 732system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 753system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12326 # number of demand (read+write) accesses 754system.cpu.itb_walker_cache.demand_accesses::total 12326 # number of demand (read+write) accesses 755system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12326 # number of overall (read+write) accesses 756system.cpu.itb_walker_cache.overall_accesses::total 12326 # number of overall (read+write) accesses 757system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352077 # miss rate for ReadReq accesses 758system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352077 # miss rate for ReadReq accesses 759system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352020 # miss rate for demand accesses 760system.cpu.itb_walker_cache.demand_miss_rate::total 0.352020 # miss rate for demand accesses 761system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352020 # miss rate for overall accesses 762system.cpu.itb_walker_cache.overall_miss_rate::total 0.352020 # miss rate for overall accesses 763system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9809.345471 # average ReadReq miss latency 764system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9809.345471 # average ReadReq miss latency 765system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency 766system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9809.345471 # average overall miss latency 767system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency 768system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9809.345471 # average overall miss latency | 733system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12335 # number of demand (read+write) accesses 734system.cpu.itb_walker_cache.demand_accesses::total 12335 # number of demand (read+write) accesses 735system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12335 # number of overall (read+write) accesses 736system.cpu.itb_walker_cache.overall_accesses::total 12335 # number of overall (read+write) accesses 737system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.430066 # miss rate for ReadReq accesses 738system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.430066 # miss rate for ReadReq accesses 739system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.429996 # miss rate for demand accesses 740system.cpu.itb_walker_cache.demand_miss_rate::total 0.429996 # miss rate for demand accesses 741system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.429996 # miss rate for overall accesses 742system.cpu.itb_walker_cache.overall_miss_rate::total 0.429996 # miss rate for overall accesses 743system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9719.127074 # average ReadReq miss latency 744system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9719.127074 # average ReadReq miss latency 745system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency 746system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9719.127074 # average overall miss latency 747system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency 748system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9719.127074 # average overall miss latency |
| 769system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 770system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 771system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 772system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 773system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 774system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 776system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 749system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 750system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 751system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 752system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 753system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 754system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 755system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 756system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 777system.cpu.itb_walker_cache.writebacks::writebacks 618 # number of writebacks 778system.cpu.itb_walker_cache.writebacks::total 618 # number of writebacks 779system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4339 # number of ReadReq MSHR misses 780system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4339 # number of ReadReq MSHR misses 781system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4339 # number of demand (read+write) MSHR misses 782system.cpu.itb_walker_cache.demand_mshr_misses::total 4339 # number of demand (read+write) MSHR misses 783system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4339 # number of overall MSHR misses 784system.cpu.itb_walker_cache.overall_mshr_misses::total 4339 # number of overall MSHR misses 785system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33883250 # number of ReadReq MSHR miss cycles 786system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33883250 # number of ReadReq MSHR miss cycles 787system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33883250 # number of demand (read+write) MSHR miss cycles 788system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33883250 # number of demand (read+write) MSHR miss cycles 789system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33883250 # number of overall MSHR miss cycles 790system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33883250 # number of overall MSHR miss cycles 791system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352077 # mshr miss rate for ReadReq accesses 792system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352077 # mshr miss rate for ReadReq accesses 793system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for demand accesses 794system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352020 # mshr miss rate for demand accesses 795system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for overall accesses 796system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352020 # mshr miss rate for overall accesses 797system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average ReadReq mshr miss latency 798system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7808.999770 # average ReadReq mshr miss latency 799system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency 800system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency 801system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency 802system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency | 757system.cpu.itb_walker_cache.writebacks::writebacks 759 # number of writebacks 758system.cpu.itb_walker_cache.writebacks::total 759 # number of writebacks 759system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 5304 # number of ReadReq MSHR misses 760system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 5304 # number of ReadReq MSHR misses 761system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 5304 # number of demand (read+write) MSHR misses 762system.cpu.itb_walker_cache.demand_mshr_misses::total 5304 # number of demand (read+write) MSHR misses 763system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 5304 # number of overall MSHR misses 764system.cpu.itb_walker_cache.overall_mshr_misses::total 5304 # number of overall MSHR misses 765system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 43592750 # number of ReadReq MSHR miss cycles 766system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 43592750 # number of ReadReq MSHR miss cycles 767system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 43592750 # number of demand (read+write) MSHR miss cycles 768system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 43592750 # number of demand (read+write) MSHR miss cycles 769system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 43592750 # number of overall MSHR miss cycles 770system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 43592750 # number of overall MSHR miss cycles 771system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.430066 # mshr miss rate for ReadReq accesses 772system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.430066 # mshr miss rate for ReadReq accesses 773system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.429996 # mshr miss rate for demand accesses 774system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.429996 # mshr miss rate for demand accesses 775system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.429996 # mshr miss rate for overall accesses 776system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.429996 # mshr miss rate for overall accesses 777system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average ReadReq mshr miss latency 778system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8218.844268 # average ReadReq mshr miss latency 779system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency 780system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency 781system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency 782system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency |
| 803system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 783system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 804system.cpu.l2cache.tags.replacements 87360 # number of replacements 805system.cpu.l2cache.tags.tagsinuse 64748.911122 # Cycle average of tags in use 806system.cpu.l2cache.tags.total_refs 3495788 # Total number of references to valid blocks. 807system.cpu.l2cache.tags.sampled_refs 152066 # Sample count of references to valid blocks. 808system.cpu.l2cache.tags.avg_refs 22.988623 # Average number of references to valid blocks. | 784system.cpu.l2cache.tags.replacements 87146 # number of replacements 785system.cpu.l2cache.tags.tagsinuse 64741.188816 # Cycle average of tags in use 786system.cpu.l2cache.tags.total_refs 3494549 # Total number of references to valid blocks. 787system.cpu.l2cache.tags.sampled_refs 151845 # Sample count of references to valid blocks. 788system.cpu.l2cache.tags.avg_refs 23.013922 # Average number of references to valid blocks. |
| 809system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 789system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 810system.cpu.l2cache.tags.occ_blocks::writebacks 50325.123938 # Average occupied blocks per requestor 811system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006393 # Average occupied blocks per requestor 812system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141290 # Average occupied blocks per requestor 813system.cpu.l2cache.tags.occ_blocks::cpu.inst 3224.854795 # Average occupied blocks per requestor 814system.cpu.l2cache.tags.occ_blocks::cpu.data 11198.784706 # Average occupied blocks per requestor 815system.cpu.l2cache.tags.occ_percent::writebacks 0.767900 # Average percentage of cache occupancy 816system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy | 790system.cpu.l2cache.tags.occ_blocks::writebacks 50454.801369 # Average occupied blocks per requestor 791system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141667 # Average occupied blocks per requestor 792system.cpu.l2cache.tags.occ_blocks::cpu.inst 3260.512095 # Average occupied blocks per requestor 793system.cpu.l2cache.tags.occ_blocks::cpu.data 11025.733685 # Average occupied blocks per requestor 794system.cpu.l2cache.tags.occ_percent::writebacks 0.769879 # Average percentage of cache occupancy |
| 817system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 795system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 818system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049207 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_percent::cpu.data 0.170880 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::total 0.987990 # Average percentage of cache occupancy 821system.cpu.l2cache.tags.occ_task_id_blocks::1024 64706 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id 823system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2949 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5093 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56562 # Occupied blocks per task id 827system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987335 # Percentage of cache occupancy per task id 828system.cpu.l2cache.tags.tag_accesses 32257665 # Number of tag accesses 829system.cpu.l2cache.tags.data_accesses 32257665 # Number of data accesses 830system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6357 # number of ReadReq hits 831system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2756 # number of ReadReq hits 832system.cpu.l2cache.ReadReq_hits::cpu.inst 781636 # number of ReadReq hits 833system.cpu.l2cache.ReadReq_hits::cpu.data 1281044 # number of ReadReq hits 834system.cpu.l2cache.ReadReq_hits::total 2071793 # number of ReadReq hits 835system.cpu.l2cache.Writeback_hits::writebacks 1544066 # number of Writeback hits 836system.cpu.l2cache.Writeback_hits::total 1544066 # number of Writeback hits 837system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits 838system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits 839system.cpu.l2cache.ReadExReq_hits::cpu.data 200764 # number of ReadExReq hits 840system.cpu.l2cache.ReadExReq_hits::total 200764 # number of ReadExReq hits 841system.cpu.l2cache.demand_hits::cpu.dtb.walker 6357 # number of demand (read+write) hits 842system.cpu.l2cache.demand_hits::cpu.itb.walker 2756 # number of demand (read+write) hits 843system.cpu.l2cache.demand_hits::cpu.inst 781636 # number of demand (read+write) hits 844system.cpu.l2cache.demand_hits::cpu.data 1481808 # number of demand (read+write) hits 845system.cpu.l2cache.demand_hits::total 2272557 # number of demand (read+write) hits 846system.cpu.l2cache.overall_hits::cpu.dtb.walker 6357 # number of overall hits 847system.cpu.l2cache.overall_hits::cpu.itb.walker 2756 # number of overall hits 848system.cpu.l2cache.overall_hits::cpu.inst 781636 # number of overall hits 849system.cpu.l2cache.overall_hits::cpu.data 1481808 # number of overall hits 850system.cpu.l2cache.overall_hits::total 2272557 # number of overall hits 851system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses | 796system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049751 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::cpu.data 0.168239 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_percent::total 0.987872 # Average percentage of cache occupancy 799system.cpu.l2cache.tags.occ_task_id_blocks::1024 64699 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2964 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5133 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56510 # Occupied blocks per task id 805system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987228 # Percentage of cache occupancy per task id 806system.cpu.l2cache.tags.tag_accesses 32250710 # Number of tag accesses 807system.cpu.l2cache.tags.data_accesses 32250710 # Number of data accesses 808system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7142 # number of ReadReq hits 809system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3328 # number of ReadReq hits 810system.cpu.l2cache.ReadReq_hits::cpu.inst 782034 # number of ReadReq hits 811system.cpu.l2cache.ReadReq_hits::cpu.data 1280353 # number of ReadReq hits 812system.cpu.l2cache.ReadReq_hits::total 2072857 # number of ReadReq hits 813system.cpu.l2cache.Writeback_hits::writebacks 1543366 # number of Writeback hits 814system.cpu.l2cache.Writeback_hits::total 1543366 # number of Writeback hits 815system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits 816system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits 817system.cpu.l2cache.ReadExReq_hits::cpu.data 200136 # number of ReadExReq hits 818system.cpu.l2cache.ReadExReq_hits::total 200136 # number of ReadExReq hits 819system.cpu.l2cache.demand_hits::cpu.dtb.walker 7142 # number of demand (read+write) hits 820system.cpu.l2cache.demand_hits::cpu.itb.walker 3328 # number of demand (read+write) hits 821system.cpu.l2cache.demand_hits::cpu.inst 782034 # number of demand (read+write) hits 822system.cpu.l2cache.demand_hits::cpu.data 1480489 # number of demand (read+write) hits 823system.cpu.l2cache.demand_hits::total 2272993 # number of demand (read+write) hits 824system.cpu.l2cache.overall_hits::cpu.dtb.walker 7142 # number of overall hits 825system.cpu.l2cache.overall_hits::cpu.itb.walker 3328 # number of overall hits 826system.cpu.l2cache.overall_hits::cpu.inst 782034 # number of overall hits 827system.cpu.l2cache.overall_hits::cpu.data 1480489 # number of overall hits 828system.cpu.l2cache.overall_hits::total 2272993 # number of overall hits |
| 852system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses | 829system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses |
| 853system.cpu.l2cache.ReadReq_misses::cpu.inst 12949 # number of ReadReq misses 854system.cpu.l2cache.ReadReq_misses::cpu.data 28624 # number of ReadReq misses 855system.cpu.l2cache.ReadReq_misses::total 41579 # number of ReadReq misses 856system.cpu.l2cache.UpgradeReq_misses::cpu.data 1347 # number of UpgradeReq misses 857system.cpu.l2cache.UpgradeReq_misses::total 1347 # number of UpgradeReq misses 858system.cpu.l2cache.ReadExReq_misses::cpu.data 113593 # number of ReadExReq misses 859system.cpu.l2cache.ReadExReq_misses::total 113593 # number of ReadExReq misses 860system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses | 830system.cpu.l2cache.ReadReq_misses::cpu.inst 12937 # number of ReadReq misses 831system.cpu.l2cache.ReadReq_misses::cpu.data 28518 # number of ReadReq misses 832system.cpu.l2cache.ReadReq_misses::total 41460 # number of ReadReq misses 833system.cpu.l2cache.UpgradeReq_misses::cpu.data 1357 # number of UpgradeReq misses 834system.cpu.l2cache.UpgradeReq_misses::total 1357 # number of UpgradeReq misses 835system.cpu.l2cache.ReadExReq_misses::cpu.data 113272 # number of ReadExReq misses 836system.cpu.l2cache.ReadExReq_misses::total 113272 # number of ReadExReq misses |
| 861system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses | 837system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses |
| 862system.cpu.l2cache.demand_misses::cpu.inst 12949 # number of demand (read+write) misses 863system.cpu.l2cache.demand_misses::cpu.data 142217 # number of demand (read+write) misses 864system.cpu.l2cache.demand_misses::total 155172 # number of demand (read+write) misses 865system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses | 838system.cpu.l2cache.demand_misses::cpu.inst 12937 # number of demand (read+write) misses 839system.cpu.l2cache.demand_misses::cpu.data 141790 # number of demand (read+write) misses 840system.cpu.l2cache.demand_misses::total 154732 # number of demand (read+write) misses |
| 866system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses | 841system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses |
| 867system.cpu.l2cache.overall_misses::cpu.inst 12949 # number of overall misses 868system.cpu.l2cache.overall_misses::cpu.data 142217 # number of overall misses 869system.cpu.l2cache.overall_misses::total 155172 # number of overall misses 870system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles 871system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 405750 # number of ReadReq miss cycles 872system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 944829500 # number of ReadReq miss cycles 873system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2144751500 # number of ReadReq miss cycles 874system.cpu.l2cache.ReadReq_miss_latency::total 3090076000 # number of ReadReq miss cycles 875system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16383859 # number of UpgradeReq miss cycles 876system.cpu.l2cache.UpgradeReq_miss_latency::total 16383859 # number of UpgradeReq miss cycles 877system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7839721470 # number of ReadExReq miss cycles 878system.cpu.l2cache.ReadExReq_miss_latency::total 7839721470 # number of ReadExReq miss cycles 879system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles 880system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 405750 # number of demand (read+write) miss cycles 881system.cpu.l2cache.demand_miss_latency::cpu.inst 944829500 # number of demand (read+write) miss cycles 882system.cpu.l2cache.demand_miss_latency::cpu.data 9984472970 # number of demand (read+write) miss cycles 883system.cpu.l2cache.demand_miss_latency::total 10929797470 # number of demand (read+write) miss cycles 884system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles 885system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 405750 # number of overall miss cycles 886system.cpu.l2cache.overall_miss_latency::cpu.inst 944829500 # number of overall miss cycles 887system.cpu.l2cache.overall_miss_latency::cpu.data 9984472970 # number of overall miss cycles 888system.cpu.l2cache.overall_miss_latency::total 10929797470 # number of overall miss cycles 889system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6358 # number of ReadReq accesses(hits+misses) 890system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2761 # number of ReadReq accesses(hits+misses) 891system.cpu.l2cache.ReadReq_accesses::cpu.inst 794585 # number of ReadReq accesses(hits+misses) 892system.cpu.l2cache.ReadReq_accesses::cpu.data 1309668 # number of ReadReq accesses(hits+misses) 893system.cpu.l2cache.ReadReq_accesses::total 2113372 # number of ReadReq accesses(hits+misses) 894system.cpu.l2cache.Writeback_accesses::writebacks 1544066 # number of Writeback accesses(hits+misses) 895system.cpu.l2cache.Writeback_accesses::total 1544066 # number of Writeback accesses(hits+misses) 896system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1668 # number of UpgradeReq accesses(hits+misses) 897system.cpu.l2cache.UpgradeReq_accesses::total 1668 # number of UpgradeReq accesses(hits+misses) 898system.cpu.l2cache.ReadExReq_accesses::cpu.data 314357 # number of ReadExReq accesses(hits+misses) 899system.cpu.l2cache.ReadExReq_accesses::total 314357 # number of ReadExReq accesses(hits+misses) 900system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6358 # number of demand (read+write) accesses 901system.cpu.l2cache.demand_accesses::cpu.itb.walker 2761 # number of demand (read+write) accesses 902system.cpu.l2cache.demand_accesses::cpu.inst 794585 # number of demand (read+write) accesses 903system.cpu.l2cache.demand_accesses::cpu.data 1624025 # number of demand (read+write) accesses 904system.cpu.l2cache.demand_accesses::total 2427729 # number of demand (read+write) accesses 905system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6358 # number of overall (read+write) accesses 906system.cpu.l2cache.overall_accesses::cpu.itb.walker 2761 # number of overall (read+write) accesses 907system.cpu.l2cache.overall_accesses::cpu.inst 794585 # number of overall (read+write) accesses 908system.cpu.l2cache.overall_accesses::cpu.data 1624025 # number of overall (read+write) accesses 909system.cpu.l2cache.overall_accesses::total 2427729 # number of overall (read+write) accesses 910system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000157 # miss rate for ReadReq accesses 911system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001811 # miss rate for ReadReq accesses 912system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses 913system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021856 # miss rate for ReadReq accesses 914system.cpu.l2cache.ReadReq_miss_rate::total 0.019674 # miss rate for ReadReq accesses 915system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807554 # miss rate for UpgradeReq accesses 916system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807554 # miss rate for UpgradeReq accesses 917system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361350 # miss rate for ReadExReq accesses 918system.cpu.l2cache.ReadExReq_miss_rate::total 0.361350 # miss rate for ReadExReq accesses 919system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000157 # miss rate for demand accesses 920system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001811 # miss rate for demand accesses 921system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses 922system.cpu.l2cache.demand_miss_rate::cpu.data 0.087571 # miss rate for demand accesses 923system.cpu.l2cache.demand_miss_rate::total 0.063917 # miss rate for demand accesses 924system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000157 # miss rate for overall accesses 925system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001811 # miss rate for overall accesses 926system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses 927system.cpu.l2cache.overall_miss_rate::cpu.data 0.087571 # miss rate for overall accesses 928system.cpu.l2cache.overall_miss_rate::total 0.063917 # miss rate for overall accesses 929system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency 930system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81150 # average ReadReq miss latency 931system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72965.441347 # average ReadReq miss latency 932system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74928.434181 # average ReadReq miss latency 933system.cpu.l2cache.ReadReq_avg_miss_latency::total 74318.189471 # average ReadReq miss latency 934system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12163.221232 # average UpgradeReq miss latency 935system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12163.221232 # average UpgradeReq miss latency 936system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69015.885398 # average ReadExReq miss latency 937system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69015.885398 # average ReadExReq miss latency 938system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 939system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81150 # average overall miss latency 940system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72965.441347 # average overall miss latency 941system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70205.903443 # average overall miss latency 942system.cpu.l2cache.demand_avg_miss_latency::total 70436.660416 # average overall miss latency 943system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 944system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81150 # average overall miss latency 945system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72965.441347 # average overall miss latency 946system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70205.903443 # average overall miss latency 947system.cpu.l2cache.overall_avg_miss_latency::total 70436.660416 # average overall miss latency | 842system.cpu.l2cache.overall_misses::cpu.inst 12937 # number of overall misses 843system.cpu.l2cache.overall_misses::cpu.data 141790 # number of overall misses 844system.cpu.l2cache.overall_misses::total 154732 # number of overall misses 845system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 387750 # number of ReadReq miss cycles 846system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049449751 # number of ReadReq miss cycles 847system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2341413282 # number of ReadReq miss cycles 848system.cpu.l2cache.ReadReq_miss_latency::total 3391250783 # number of ReadReq miss cycles 849system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21334859 # number of UpgradeReq miss cycles 850system.cpu.l2cache.UpgradeReq_miss_latency::total 21334859 # number of UpgradeReq miss cycles 851system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8652486971 # number of ReadExReq miss cycles 852system.cpu.l2cache.ReadExReq_miss_latency::total 8652486971 # number of ReadExReq miss cycles 853system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 387750 # number of demand (read+write) miss cycles 854system.cpu.l2cache.demand_miss_latency::cpu.inst 1049449751 # number of demand (read+write) miss cycles 855system.cpu.l2cache.demand_miss_latency::cpu.data 10993900253 # number of demand (read+write) miss cycles 856system.cpu.l2cache.demand_miss_latency::total 12043737754 # number of demand (read+write) miss cycles 857system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 387750 # number of overall miss cycles 858system.cpu.l2cache.overall_miss_latency::cpu.inst 1049449751 # number of overall miss cycles 859system.cpu.l2cache.overall_miss_latency::cpu.data 10993900253 # number of overall miss cycles 860system.cpu.l2cache.overall_miss_latency::total 12043737754 # number of overall miss cycles 861system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7142 # number of ReadReq accesses(hits+misses) 862system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3333 # number of ReadReq accesses(hits+misses) 863system.cpu.l2cache.ReadReq_accesses::cpu.inst 794971 # number of ReadReq accesses(hits+misses) 864system.cpu.l2cache.ReadReq_accesses::cpu.data 1308871 # number of ReadReq accesses(hits+misses) 865system.cpu.l2cache.ReadReq_accesses::total 2114317 # number of ReadReq accesses(hits+misses) 866system.cpu.l2cache.Writeback_accesses::writebacks 1543366 # number of Writeback accesses(hits+misses) 867system.cpu.l2cache.Writeback_accesses::total 1543366 # number of Writeback accesses(hits+misses) 868system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1674 # number of UpgradeReq accesses(hits+misses) 869system.cpu.l2cache.UpgradeReq_accesses::total 1674 # number of UpgradeReq accesses(hits+misses) 870system.cpu.l2cache.ReadExReq_accesses::cpu.data 313408 # number of ReadExReq accesses(hits+misses) 871system.cpu.l2cache.ReadExReq_accesses::total 313408 # number of ReadExReq accesses(hits+misses) 872system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7142 # number of demand (read+write) accesses 873system.cpu.l2cache.demand_accesses::cpu.itb.walker 3333 # number of demand (read+write) accesses 874system.cpu.l2cache.demand_accesses::cpu.inst 794971 # number of demand (read+write) accesses 875system.cpu.l2cache.demand_accesses::cpu.data 1622279 # number of demand (read+write) accesses 876system.cpu.l2cache.demand_accesses::total 2427725 # number of demand (read+write) accesses 877system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7142 # number of overall (read+write) accesses 878system.cpu.l2cache.overall_accesses::cpu.itb.walker 3333 # number of overall (read+write) accesses 879system.cpu.l2cache.overall_accesses::cpu.inst 794971 # number of overall (read+write) accesses 880system.cpu.l2cache.overall_accesses::cpu.data 1622279 # number of overall (read+write) accesses 881system.cpu.l2cache.overall_accesses::total 2427725 # number of overall (read+write) accesses 882system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001500 # miss rate for ReadReq accesses 883system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016274 # miss rate for ReadReq accesses 884system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021788 # miss rate for ReadReq accesses 885system.cpu.l2cache.ReadReq_miss_rate::total 0.019609 # miss rate for ReadReq accesses 886system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.810633 # miss rate for UpgradeReq accesses 887system.cpu.l2cache.UpgradeReq_miss_rate::total 0.810633 # miss rate for UpgradeReq accesses 888system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361420 # miss rate for ReadExReq accesses 889system.cpu.l2cache.ReadExReq_miss_rate::total 0.361420 # miss rate for ReadExReq accesses 890system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001500 # miss rate for demand accesses 891system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016274 # miss rate for demand accesses 892system.cpu.l2cache.demand_miss_rate::cpu.data 0.087402 # miss rate for demand accesses 893system.cpu.l2cache.demand_miss_rate::total 0.063735 # miss rate for demand accesses 894system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001500 # miss rate for overall accesses 895system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016274 # miss rate for overall accesses 896system.cpu.l2cache.overall_miss_rate::cpu.data 0.087402 # miss rate for overall accesses 897system.cpu.l2cache.overall_miss_rate::total 0.063735 # miss rate for overall accesses 898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77550 # average ReadReq miss latency 899system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81120.024040 # average ReadReq miss latency 900system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82102.997475 # average ReadReq miss latency 901system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.725591 # average ReadReq miss latency 902system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15722.077377 # average UpgradeReq miss latency 903system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15722.077377 # average UpgradeReq miss latency 904system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76386.812019 # average ReadExReq miss latency 905system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76386.812019 # average ReadExReq miss latency 906system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency 907system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency 908system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency 909system.cpu.l2cache.demand_avg_miss_latency::total 77836.115051 # average overall miss latency 910system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency 911system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency 912system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency 913system.cpu.l2cache.overall_avg_miss_latency::total 77836.115051 # average overall miss latency |
| 948system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 949system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 950system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 951system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 952system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 953system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 954system.cpu.l2cache.fast_writes 0 # number of fast writes performed 955system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 914system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 915system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 916system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 917system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 918system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 919system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 920system.cpu.l2cache.fast_writes 0 # number of fast writes performed 921system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 956system.cpu.l2cache.writebacks::writebacks 80295 # number of writebacks 957system.cpu.l2cache.writebacks::total 80295 # number of writebacks 958system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses | 922system.cpu.l2cache.writebacks::writebacks 80303 # number of writebacks 923system.cpu.l2cache.writebacks::total 80303 # number of writebacks |
| 959system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses | 924system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses |
| 960system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12949 # number of ReadReq MSHR misses 961system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28624 # number of ReadReq MSHR misses 962system.cpu.l2cache.ReadReq_mshr_misses::total 41579 # number of ReadReq MSHR misses 963system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1347 # number of UpgradeReq MSHR misses 964system.cpu.l2cache.UpgradeReq_mshr_misses::total 1347 # number of UpgradeReq MSHR misses 965system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113593 # number of ReadExReq MSHR misses 966system.cpu.l2cache.ReadExReq_mshr_misses::total 113593 # number of ReadExReq MSHR misses 967system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses | 925system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12937 # number of ReadReq MSHR misses 926system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses 927system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses 928system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1357 # number of UpgradeReq MSHR misses 929system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses 930system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses 931system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses |
| 968system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses | 932system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses |
| 969system.cpu.l2cache.demand_mshr_misses::cpu.inst 12949 # number of demand (read+write) MSHR misses 970system.cpu.l2cache.demand_mshr_misses::cpu.data 142217 # number of demand (read+write) MSHR misses 971system.cpu.l2cache.demand_mshr_misses::total 155172 # number of demand (read+write) MSHR misses 972system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses | 933system.cpu.l2cache.demand_mshr_misses::cpu.inst 12937 # number of demand (read+write) MSHR misses 934system.cpu.l2cache.demand_mshr_misses::cpu.data 141790 # number of demand (read+write) MSHR misses 935system.cpu.l2cache.demand_mshr_misses::total 154732 # number of demand (read+write) MSHR misses |
| 973system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses | 936system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses |
| 974system.cpu.l2cache.overall_mshr_misses::cpu.inst 12949 # number of overall MSHR misses 975system.cpu.l2cache.overall_mshr_misses::cpu.data 142217 # number of overall MSHR misses 976system.cpu.l2cache.overall_mshr_misses::total 155172 # number of overall MSHR misses 977system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles 978system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 342750 # number of ReadReq MSHR miss cycles 979system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 782620000 # number of ReadReq MSHR miss cycles 980system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1786397500 # number of ReadReq MSHR miss cycles 981system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2569436500 # number of ReadReq MSHR miss cycles 982system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14401829 # number of UpgradeReq MSHR miss cycles 983system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14401829 # number of UpgradeReq MSHR miss cycles 984system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6419846030 # number of ReadExReq MSHR miss cycles 985system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6419846030 # number of ReadExReq MSHR miss cycles 986system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles 987system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 342750 # number of demand (read+write) MSHR miss cycles 988system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 782620000 # number of demand (read+write) MSHR miss cycles 989system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8206243530 # number of demand (read+write) MSHR miss cycles 990system.cpu.l2cache.demand_mshr_miss_latency::total 8989282530 # number of demand (read+write) MSHR miss cycles 991system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles 992system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 342750 # number of overall MSHR miss cycles 993system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 782620000 # number of overall MSHR miss cycles 994system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8206243530 # number of overall MSHR miss cycles 995system.cpu.l2cache.overall_mshr_miss_latency::total 8989282530 # number of overall MSHR miss cycles 996system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86686810500 # number of ReadReq MSHR uncacheable cycles 997system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86686810500 # number of ReadReq MSHR uncacheable cycles 998system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284500 # number of WriteReq MSHR uncacheable cycles 999system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284500 # number of WriteReq MSHR uncacheable cycles 1000system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088095000 # number of overall MSHR uncacheable cycles 1001system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088095000 # number of overall MSHR uncacheable cycles 1002system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses 1003system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for ReadReq accesses 1004system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses 1005system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021856 # mshr miss rate for ReadReq accesses 1006system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019674 # mshr miss rate for ReadReq accesses 1007system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807554 # mshr miss rate for UpgradeReq accesses 1008system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807554 # mshr miss rate for UpgradeReq accesses 1009system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361350 # mshr miss rate for ReadExReq accesses 1010system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361350 # mshr miss rate for ReadExReq accesses 1011system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses 1012system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for demand accesses 1013system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses 1014system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for demand accesses 1015system.cpu.l2cache.demand_mshr_miss_rate::total 0.063917 # mshr miss rate for demand accesses 1016system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses 1017system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for overall accesses 1018system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses 1019system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for overall accesses 1020system.cpu.l2cache.overall_mshr_miss_rate::total 0.063917 # mshr miss rate for overall accesses 1021system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency 1022system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68550 # average ReadReq mshr miss latency 1023system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60438.643911 # average ReadReq mshr miss latency 1024system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62409.079793 # average ReadReq mshr miss latency 1025system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61796.495827 # average ReadReq mshr miss latency 1026system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.780995 # average UpgradeReq mshr miss latency 1027system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.780995 # average UpgradeReq mshr miss latency 1028system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56516.211650 # average ReadExReq mshr miss latency 1029system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56516.211650 # average ReadExReq mshr miss latency 1030system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1031system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency 1032system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency 1033system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency 1034system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency 1035system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1036system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency 1037system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency 1038system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency 1039system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency | 937system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses 938system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses 939system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses 940system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles 941system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles 942system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles 943system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872181717 # number of ReadReq MSHR miss cycles 944system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles 945system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # number of UpgradeReq MSHR miss cycles 946system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles 947system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles 948system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles 949system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887295749 # number of demand (read+write) MSHR miss cycles 950system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles 951system.cpu.l2cache.demand_mshr_miss_latency::total 10108406746 # number of demand (read+write) MSHR miss cycles 952system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles 953system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles 954system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles 955system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles 956system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles 957system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles 958system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles 959system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411090500 # number of WriteReq MSHR uncacheable cycles 960system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88554571000 # number of overall MSHR uncacheable cycles 961system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88554571000 # number of overall MSHR uncacheable cycles 962system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for ReadReq accesses 963system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses 964system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses 965system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses 966system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.810633 # mshr miss rate for UpgradeReq accesses 967system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.810633 # mshr miss rate for UpgradeReq accesses 968system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses 969system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses 970system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses 971system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for demand accesses 972system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for demand accesses 973system.cpu.l2cache.demand_mshr_miss_rate::total 0.063735 # mshr miss rate for demand accesses 974system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for overall accesses 975system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for overall accesses 976system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses 977system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses 978system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency 979system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68585.896962 # average ReadReq mshr miss latency 980system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency 981system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.970019 # average ReadReq mshr miss latency 982system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18193.322771 # average UpgradeReq mshr miss latency 983system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18193.322771 # average UpgradeReq mshr miss latency 984system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency 985system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency 986system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency 987system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency 988system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency 989system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency 990system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency 991system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency 992system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency 993system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency |
| 1040system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1041system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1042system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1043system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1044system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1045system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1046system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 994system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 995system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 996system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 997system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 998system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 999system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1000system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1047system.cpu.toL2Bus.trans_dist::ReadReq 2700583 # Transaction distribution 1048system.cpu.toL2Bus.trans_dist::ReadResp 2700055 # Transaction distribution 1049system.cpu.toL2Bus.trans_dist::WriteReq 13918 # Transaction distribution 1050system.cpu.toL2Bus.trans_dist::WriteResp 13918 # Transaction distribution 1051system.cpu.toL2Bus.trans_dist::Writeback 1544066 # Transaction distribution 1052system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1053system.cpu.toL2Bus.trans_dist::UpgradeReq 2197 # Transaction distribution 1054system.cpu.toL2Bus.trans_dist::UpgradeResp 2197 # Transaction distribution 1055system.cpu.toL2Bus.trans_dist::ReadExReq 314362 # Transaction distribution 1056system.cpu.toL2Bus.trans_dist::ReadExResp 314362 # Transaction distribution 1057system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589183 # Packet count per connected master and slave (bytes) 1058system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5984618 # Packet count per connected master and slave (bytes) 1059system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7718 # Packet count per connected master and slave (bytes) 1060system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17987 # Packet count per connected master and slave (bytes) 1061system.cpu.toL2Bus.pkt_count::total 7599506 # Packet count per connected master and slave (bytes) 1062system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50853440 # Cumulative packet size per connected master and slave (bytes) 1063system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204220931 # Cumulative packet size per connected master and slave (bytes) 1064system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 216256 # Cumulative packet size per connected master and slave (bytes) 1065system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 591552 # Cumulative packet size per connected master and slave (bytes) 1066system.cpu.toL2Bus.pkt_size::total 255882179 # Cumulative packet size per connected master and slave (bytes) 1067system.cpu.toL2Bus.snoops 53190 # Total snoops (count) 1068system.cpu.toL2Bus.snoop_fanout::samples 4026335 # Request fanout histogram 1069system.cpu.toL2Bus.snoop_fanout::mean 3.011814 # Request fanout histogram 1070system.cpu.toL2Bus.snoop_fanout::stdev 0.108047 # Request fanout histogram | 1001system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution 1002system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution 1003system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution 1004system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution 1005system.cpu.toL2Bus.trans_dist::Writeback 1543366 # Transaction distribution 1006system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46773 # Transaction distribution 1007system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # Transaction distribution 1008system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution 1009system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution 1010system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution 1011system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes) 1012system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes) 1013system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes) 1014system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20349 # Packet count per connected master and slave (bytes) 1015system.cpu.toL2Bus.pkt_count::total 7586177 # Packet count per connected master and slave (bytes) 1016system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50878144 # Cumulative packet size per connected master and slave (bytes) 1017system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204018925 # Cumulative packet size per connected master and slave (bytes) 1018system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes) 1019system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes) 1020system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes) 1021system.cpu.toL2Bus.snoops 54167 # Total snoops (count) 1022system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram 1023system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram 1024system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram |
| 1071system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1072system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1073system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1074system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1025system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1026system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1027system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1028system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1075system.cpu.toL2Bus.snoop_fanout::3 3978769 98.82% 98.82% # Request fanout histogram 1076system.cpu.toL2Bus.snoop_fanout::4 47566 1.18% 100.00% # Request fanout histogram | 1029system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram 1030system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram |
| 1077system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1078system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1079system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 1031system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1032system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1033system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 1080system.cpu.toL2Bus.snoop_fanout::total 4026335 # Request fanout histogram 1081system.cpu.toL2Bus.reqLayer0.occupancy 3838165000 # Layer occupancy (ticks) | 1034system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram 1035system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks) |
| 1082system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1036system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1083system.cpu.toL2Bus.snoopLayer0.occupancy 477000 # Layer occupancy (ticks) | 1037system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks) |
| 1084system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1038system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1085system.cpu.toL2Bus.respLayer0.occupancy 1194331866 # Layer occupancy (ticks) | 1039system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks) |
| 1086system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1040system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1087system.cpu.toL2Bus.respLayer1.occupancy 3057201859 # Layer occupancy (ticks) | 1041system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks) |
| 1088system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1042system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1089system.cpu.toL2Bus.respLayer2.occupancy 6509250 # Layer occupancy (ticks) | 1043system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks) |
| 1090system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1044system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1091system.cpu.toL2Bus.respLayer3.occupancy 13116250 # Layer occupancy (ticks) | 1045system.cpu.toL2Bus.respLayer3.occupancy 15136500 # Layer occupancy (ticks) |
| 1092system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1046system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1093system.iobus.trans_dist::ReadReq 230298 # Transaction distribution 1094system.iobus.trans_dist::ReadResp 230298 # Transaction distribution | 1047system.iobus.trans_dist::ReadReq 228399 # Transaction distribution 1048system.iobus.trans_dist::ReadResp 228399 # Transaction distribution |
| 1095system.iobus.trans_dist::WriteReq 57726 # Transaction distribution 1096system.iobus.trans_dist::WriteResp 11006 # Transaction distribution 1097system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution | 1049system.iobus.trans_dist::WriteReq 57726 # Transaction distribution 1050system.iobus.trans_dist::WriteResp 11006 # Transaction distribution 1051system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 1098system.iobus.trans_dist::MessageReq 1653 # Transaction distribution 1099system.iobus.trans_dist::MessageResp 1653 # Transaction distribution | 1052system.iobus.trans_dist::MessageReq 1652 # Transaction distribution 1053system.iobus.trans_dist::MessageResp 1652 # Transaction distribution |
| 1100system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1101system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1102system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1103system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1104system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1105system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 1106system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1107system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) | 1054system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1055system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1056system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1057system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1058system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1059system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 1060system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1061system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) |
| 1108system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) | 1062system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 432904 # Packet count per connected master and slave (bytes) |
| 1109system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1110system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1111system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1112system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 1113system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1114system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1115system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1116system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1117system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) | 1063system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1064system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1065system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1066system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 1067system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1068system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1069system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1070system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1071system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) |
| 1118system.iobus.pkt_count_system.bridge.master::total 480916 # Packet count per connected master and slave (bytes) 1119system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) 1120system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) 1121system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3306 # Packet count per connected master and slave (bytes) 1122system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3306 # Packet count per connected master and slave (bytes) 1123system.iobus.pkt_count::total 579354 # Packet count per connected master and slave (bytes) | 1072system.iobus.pkt_count_system.bridge.master::total 477136 # Packet count per connected master and slave (bytes) 1073system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95114 # Packet count per connected master and slave (bytes) 1074system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes) 1075system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) 1076system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) 1077system.iobus.pkt_count::total 575554 # Packet count per connected master and slave (bytes) |
| 1124system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1125system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1126system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1127system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1128system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1129system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1130system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1131system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) | 1078system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1079system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1080system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1081system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1082system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1083system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1084system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1085system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) |
| 1132system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) | 1086system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 216452 # Cumulative packet size per connected master and slave (bytes) |
| 1133system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1134system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1135system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1136system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 1137system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1138system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1139system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1140system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1141system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) | 1087system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1088system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1089system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1090system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 1091system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1092system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1093system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1094system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1095system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) |
| 1142system.iobus.pkt_size_system.bridge.master::total 246738 # Cumulative packet size per connected master and slave (bytes) 1143system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) 1144system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) 1145system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6612 # Cumulative packet size per connected master and slave (bytes) 1146system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6612 # Cumulative packet size per connected master and slave (bytes) 1147system.iobus.pkt_size::total 3280662 # Cumulative packet size per connected master and slave (bytes) 1148system.iobus.reqLayer0.occupancy 3941856 # Layer occupancy (ticks) | 1096system.iobus.pkt_size_system.bridge.master::total 244848 # Cumulative packet size per connected master and slave (bytes) 1097system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027240 # Cumulative packet size per connected master and slave (bytes) 1098system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027240 # Cumulative packet size per connected master and slave (bytes) 1099system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) 1100system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) 1101system.iobus.pkt_size::total 3278696 # Cumulative packet size per connected master and slave (bytes) 1102system.iobus.reqLayer0.occupancy 3940536 # Layer occupancy (ticks) |
| 1149system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1150system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1151system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1152system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1153system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1154system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 1155system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1156system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1157system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1158system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1159system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1160system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) 1161system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1162system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1163system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1164system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1165system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) | 1103system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1104system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1105system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1106system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1107system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1108system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 1109system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1110system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1111system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1112system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1113system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1114system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) 1115system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1116system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1117system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1118system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1119system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) |
| 1166system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) | 1120system.iobus.reqLayer9.occupancy 216453000 # Layer occupancy (ticks) |
| 1167system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1168system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1169system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1170system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1171system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1172system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) 1173system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1174system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) 1175system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1176system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1177system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1178system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1179system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1180system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1181system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1182system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1183system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) | 1121system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1122system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1123system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1124system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1125system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1126system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) 1127system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1128system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) 1129system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1130system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1131system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1132system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1133system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1134system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1135system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1136system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1137system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) |
| 1184system.iobus.reqLayer19.occupancy 448396611 # Layer occupancy (ticks) | 1138system.iobus.reqLayer19.occupancy 257203754 # Layer occupancy (ticks) |
| 1185system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1186system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1187system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) | 1139system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1140system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1141system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) |
| 1188system.iobus.respLayer0.occupancy 469910000 # Layer occupancy (ticks) | 1142system.iobus.respLayer0.occupancy 466130000 # Layer occupancy (ticks) |
| 1189system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1143system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1190system.iobus.respLayer1.occupancy 52232002 # Layer occupancy (ticks) | 1144system.iobus.respLayer1.occupancy 50194752 # Layer occupancy (ticks) |
| 1191system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1145system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1192system.iobus.respLayer2.occupancy 1653000 # Layer occupancy (ticks) | 1146system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) |
| 1193system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) | 1147system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1194system.iocache.tags.replacements 47511 # number of replacements 1195system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use | 1148system.iocache.tags.replacements 47502 # number of replacements 1149system.iocache.tags.tagsinuse 0.095966 # Cycle average of tags in use |
| 1196system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1150system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1197system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. | 1151system.iocache.tags.sampled_refs 47518 # Sample count of references to valid blocks. |
| 1198system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1152system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1199system.iocache.tags.warmup_cycle 5045849712000 # Cycle when the warmup percentage was hit. 1200system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor 1201system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy 1202system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy | 1153system.iocache.tags.warmup_cycle 5046161981000 # Cycle when the warmup percentage was hit. 1154system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095966 # Average occupied blocks per requestor 1155system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005998 # Average percentage of cache occupancy 1156system.iocache.tags.occ_percent::total 0.005998 # Average percentage of cache occupancy |
| 1203system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1204system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1205system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1157system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1158system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1159system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1206system.iocache.tags.tag_accesses 428094 # Number of tag accesses 1207system.iocache.tags.data_accesses 428094 # Number of data accesses 1208system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses 1209system.iocache.ReadReq_misses::total 846 # number of ReadReq misses | 1160system.iocache.tags.tag_accesses 428013 # Number of tag accesses 1161system.iocache.tags.data_accesses 428013 # Number of data accesses 1162system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses 1163system.iocache.ReadReq_misses::total 837 # number of ReadReq misses |
| 1210system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 1211system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses | 1164system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 1165system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses |
| 1212system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses 1213system.iocache.demand_misses::total 846 # number of demand (read+write) misses 1214system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses 1215system.iocache.overall_misses::total 846 # number of overall misses 1216system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144419686 # number of ReadReq miss cycles 1217system.iocache.ReadReq_miss_latency::total 144419686 # number of ReadReq miss cycles 1218system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361743923 # number of WriteInvalidateReq miss cycles 1219system.iocache.WriteInvalidateReq_miss_latency::total 12361743923 # number of WriteInvalidateReq miss cycles 1220system.iocache.demand_miss_latency::pc.south_bridge.ide 144419686 # number of demand (read+write) miss cycles 1221system.iocache.demand_miss_latency::total 144419686 # number of demand (read+write) miss cycles 1222system.iocache.overall_miss_latency::pc.south_bridge.ide 144419686 # number of overall miss cycles 1223system.iocache.overall_miss_latency::total 144419686 # number of overall miss cycles 1224system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) 1225system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) | 1166system.iocache.demand_misses::pc.south_bridge.ide 837 # number of demand (read+write) misses 1167system.iocache.demand_misses::total 837 # number of demand (read+write) misses 1168system.iocache.overall_misses::pc.south_bridge.ide 837 # number of overall misses 1169system.iocache.overall_misses::total 837 # number of overall misses 1170system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132288440 # number of ReadReq miss cycles 1171system.iocache.ReadReq_miss_latency::total 132288440 # number of ReadReq miss cycles 1172system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8590965562 # number of WriteInvalidateReq miss cycles 1173system.iocache.WriteInvalidateReq_miss_latency::total 8590965562 # number of WriteInvalidateReq miss cycles 1174system.iocache.demand_miss_latency::pc.south_bridge.ide 132288440 # number of demand (read+write) miss cycles 1175system.iocache.demand_miss_latency::total 132288440 # number of demand (read+write) miss cycles 1176system.iocache.overall_miss_latency::pc.south_bridge.ide 132288440 # number of overall miss cycles 1177system.iocache.overall_miss_latency::total 132288440 # number of overall miss cycles 1178system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses) 1179system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) |
| 1226system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1227system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) | 1180system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1181system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) |
| 1228system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses 1229system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses 1230system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses 1231system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses | 1182system.iocache.demand_accesses::pc.south_bridge.ide 837 # number of demand (read+write) accesses 1183system.iocache.demand_accesses::total 837 # number of demand (read+write) accesses 1184system.iocache.overall_accesses::pc.south_bridge.ide 837 # number of overall (read+write) accesses 1185system.iocache.overall_accesses::total 837 # number of overall (read+write) accesses |
| 1232system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1233system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1234system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 1235system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1236system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1237system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1238system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1239system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1186system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1187system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1188system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 1189system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1190system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1191system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1192system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1193system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1240system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average ReadReq miss latency 1241system.iocache.ReadReq_avg_miss_latency::total 170708.848700 # average ReadReq miss latency 1242system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264592.121640 # average WriteInvalidateReq miss latency 1243system.iocache.WriteInvalidateReq_avg_miss_latency::total 264592.121640 # average WriteInvalidateReq miss latency 1244system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency 1245system.iocache.demand_avg_miss_latency::total 170708.848700 # average overall miss latency 1246system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency 1247system.iocache.overall_avg_miss_latency::total 170708.848700 # average overall miss latency 1248system.iocache.blocked_cycles::no_mshrs 70486 # number of cycles access was blocked | 1194system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average ReadReq miss latency 1195system.iocache.ReadReq_avg_miss_latency::total 158050.704898 # average ReadReq miss latency 1196system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183881.968365 # average WriteInvalidateReq miss latency 1197system.iocache.WriteInvalidateReq_avg_miss_latency::total 183881.968365 # average WriteInvalidateReq miss latency 1198system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency 1199system.iocache.demand_avg_miss_latency::total 158050.704898 # average overall miss latency 1200system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency 1201system.iocache.overall_avg_miss_latency::total 158050.704898 # average overall miss latency 1202system.iocache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked |
| 1249system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1203system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1250system.iocache.blocked::no_mshrs 9156 # number of cycles access was blocked | 1204system.iocache.blocked::no_mshrs 4442 # number of cycles access was blocked |
| 1251system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1205system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1252system.iocache.avg_blocked_cycles::no_mshrs 7.698340 # average number of cycles each access was blocked | 1206system.iocache.avg_blocked_cycles::no_mshrs 6.674246 # average number of cycles each access was blocked |
| 1253system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1254system.iocache.fast_writes 0 # number of fast writes performed 1255system.iocache.cache_copies 0 # number of cache copies performed 1256system.iocache.writebacks::writebacks 46667 # number of writebacks 1257system.iocache.writebacks::total 46667 # number of writebacks | 1207system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1208system.iocache.fast_writes 0 # number of fast writes performed 1209system.iocache.cache_copies 0 # number of cache copies performed 1210system.iocache.writebacks::writebacks 46667 # number of writebacks 1211system.iocache.writebacks::total 46667 # number of writebacks |
| 1258system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses 1259system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses | 1212system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses 1213system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses |
| 1260system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 1261system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses | 1214system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 1215system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses |
| 1262system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses 1263system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses 1264system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses 1265system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses 1266system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of ReadReq MSHR miss cycles 1267system.iocache.ReadReq_mshr_miss_latency::total 100401686 # number of ReadReq MSHR miss cycles 1268system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9932299927 # number of WriteInvalidateReq MSHR miss cycles 1269system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9932299927 # number of WriteInvalidateReq MSHR miss cycles 1270system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of demand (read+write) MSHR miss cycles 1271system.iocache.demand_mshr_miss_latency::total 100401686 # number of demand (read+write) MSHR miss cycles 1272system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of overall MSHR miss cycles 1273system.iocache.overall_mshr_miss_latency::total 100401686 # number of overall MSHR miss cycles | 1216system.iocache.demand_mshr_misses::pc.south_bridge.ide 837 # number of demand (read+write) MSHR misses 1217system.iocache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses 1218system.iocache.overall_mshr_misses::pc.south_bridge.ide 837 # number of overall MSHR misses 1219system.iocache.overall_mshr_misses::total 837 # number of overall MSHR misses 1220system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of ReadReq MSHR miss cycles 1221system.iocache.ReadReq_mshr_miss_latency::total 88419930 # number of ReadReq MSHR miss cycles 1222system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6161511576 # number of WriteInvalidateReq MSHR miss cycles 1223system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6161511576 # number of WriteInvalidateReq MSHR miss cycles 1224system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of demand (read+write) MSHR miss cycles 1225system.iocache.demand_mshr_miss_latency::total 88419930 # number of demand (read+write) MSHR miss cycles 1226system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of overall MSHR miss cycles 1227system.iocache.overall_mshr_miss_latency::total 88419930 # number of overall MSHR miss cycles |
| 1274system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1275system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1276system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1277system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1278system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1279system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1280system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1281system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1228system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1229system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1230system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1231system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1232system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1233system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1234system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1235system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1282system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average ReadReq mshr miss latency 1283system.iocache.ReadReq_avg_mshr_miss_latency::total 118678.115839 # average ReadReq mshr miss latency 1284system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212592.036109 # average WriteInvalidateReq mshr miss latency 1285system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212592.036109 # average WriteInvalidateReq mshr miss latency 1286system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency 1287system.iocache.demand_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency 1288system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency 1289system.iocache.overall_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency | 1236system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average ReadReq mshr miss latency 1237system.iocache.ReadReq_avg_mshr_miss_latency::total 105639.103943 # average ReadReq mshr miss latency 1238system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131881.669007 # average WriteInvalidateReq mshr miss latency 1239system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131881.669007 # average WriteInvalidateReq mshr miss latency 1240system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency 1241system.iocache.demand_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency 1242system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency 1243system.iocache.overall_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency |
| 1290system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1244system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1291system.membus.trans_dist::ReadReq 624018 # Transaction distribution 1292system.membus.trans_dist::ReadResp 624018 # Transaction distribution 1293system.membus.trans_dist::WriteReq 13918 # Transaction distribution 1294system.membus.trans_dist::WriteResp 13918 # Transaction distribution 1295system.membus.trans_dist::Writeback 126962 # Transaction distribution | 1245system.membus.trans_dist::ReadReq 617109 # Transaction distribution 1246system.membus.trans_dist::ReadResp 617109 # Transaction distribution 1247system.membus.trans_dist::WriteReq 13916 # Transaction distribution 1248system.membus.trans_dist::WriteResp 13916 # Transaction distribution 1249system.membus.trans_dist::Writeback 126970 # Transaction distribution |
| 1296system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1297system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution | 1250system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1251system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 1298system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution 1299system.membus.trans_dist::UpgradeResp 1627 # Transaction distribution 1300system.membus.trans_dist::ReadExReq 113313 # Transaction distribution 1301system.membus.trans_dist::ReadExResp 113313 # Transaction distribution 1302system.membus.trans_dist::MessageReq 1653 # Transaction distribution 1303system.membus.trans_dist::MessageResp 1653 # Transaction distribution 1304system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes) 1305system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes) 1306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480916 # Packet count per connected master and slave (bytes) 1307system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710106 # Packet count per connected master and slave (bytes) 1308system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393192 # Packet count per connected master and slave (bytes) 1309system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584214 # Packet count per connected master and slave (bytes) 1310system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141396 # Packet count per connected master and slave (bytes) 1311system.membus.pkt_count_system.iocache.mem_side::total 141396 # Packet count per connected master and slave (bytes) 1312system.membus.pkt_count::total 1728916 # Packet count per connected master and slave (bytes) 1313system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes) 1314system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes) 1315system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246738 # Cumulative packet size per connected master and slave (bytes) 1316system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420209 # Cumulative packet size per connected master and slave (bytes) 1317system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15010240 # Cumulative packet size per connected master and slave (bytes) 1318system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16677187 # Cumulative packet size per connected master and slave (bytes) | 1252system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution 1253system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution 1254system.membus.trans_dist::ReadExReq 112993 # Transaction distribution 1255system.membus.trans_dist::ReadExResp 112993 # Transaction distribution 1256system.membus.trans_dist::MessageReq 1652 # Transaction distribution 1257system.membus.trans_dist::MessageResp 1652 # Transaction distribution 1258system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) 1259system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) 1260system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes) 1261system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) 1262system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes) 1263system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes) 1264system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes) 1265system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes) 1266system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes) 1267system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) 1268system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) 1269system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes) 1270system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) 1271system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14982656 # Cumulative packet size per connected master and slave (bytes) 1272system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16628141 # Cumulative packet size per connected master and slave (bytes) |
| 1319system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1320system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) | 1273system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1274system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) |
| 1321system.membus.pkt_size::total 22688919 # Cumulative packet size per connected master and slave (bytes) 1322system.membus.snoops 1602 # Total snoops (count) 1323system.membus.snoop_fanout::samples 331576 # Request fanout histogram | 1275system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes) 1276system.membus.snoops 1583 # Total snoops (count) 1277system.membus.snoop_fanout::samples 331203 # Request fanout histogram |
| 1324system.membus.snoop_fanout::mean 1 # Request fanout histogram 1325system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1326system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1327system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1278system.membus.snoop_fanout::mean 1 # Request fanout histogram 1279system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1280system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1281system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1328system.membus.snoop_fanout::1 331576 100.00% 100.00% # Request fanout histogram | 1282system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram |
| 1329system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1330system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1331system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1332system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1283system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1284system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1285system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1286system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1333system.membus.snoop_fanout::total 331576 # Request fanout histogram 1334system.membus.reqLayer0.occupancy 257309000 # Layer occupancy (ticks) | 1287system.membus.snoop_fanout::total 331203 # Request fanout histogram 1288system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks) |
| 1335system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1289system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1336system.membus.reqLayer1.occupancy 358083500 # Layer occupancy (ticks) | 1290system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks) |
| 1337system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1291system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1338system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks) | 1292system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) |
| 1339system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1293system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1340system.membus.reqLayer3.occupancy 1729903000 # Layer occupancy (ticks) | 1294system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks) |
| 1341system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) | 1295system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 1342system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks) | 1296system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) |
| 1343system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 1297system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1344system.membus.respLayer2.occupancy 2619799141 # Layer occupancy (ticks) 1345system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1346system.membus.respLayer4.occupancy 54348998 # Layer occupancy (ticks) | 1298system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks) 1299system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1300system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks) |
| 1347system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1348system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1349system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1350system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1351system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1352system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1353system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1354system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1355system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1356system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1357system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1358system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1359system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1360 1361---------- End Simulation Statistics ---------- | 1301system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1302system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1303system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1304system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1305system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1306system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1307system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1308system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1309system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1310system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1311system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1312system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1313system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1314 1315---------- End Simulation Statistics ---------- |