| stats.txt (10628:c9b7e0c69f88) | stats.txt (10639:469cf1ea40f5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.192453 # Number of seconds simulated 4sim_ticks 5192452884000 # Number of ticks simulated 5final_tick 5192452884000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.188454 # Number of seconds simulated 4sim_ticks 5188454477000 # Number of ticks simulated 5final_tick 5188454477000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 836744 # Simulator instruction rate (inst/s) 8host_op_rate 1613002 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33830425760 # Simulator tick rate (ticks/s) 10host_mem_usage 654168 # Number of bytes of host memory used 11host_seconds 153.48 # Real time elapsed on the host 12sim_insts 128427413 # Number of instructions simulated 13sim_ops 247571076 # Number of ops (including micro ops) simulated | 7host_inst_rate 1005236 # Simulator instruction rate (inst/s) 8host_op_rate 1937641 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40503850527 # Simulator tick rate (ticks/s) 10host_mem_usage 596712 # Number of bytes of host memory used 11host_seconds 128.10 # Real time elapsed on the host 12sim_insts 128768549 # Number of instructions simulated 13sim_ops 248207575 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9039104 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.inst 828736 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9035840 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 9895360 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8137984 # Number of bytes written to this memory 25system.physmem.bytes_written::total 8137984 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory | 21system.physmem.bytes_read::total 9893312 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 828736 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 828736 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8124416 # Number of bytes written to this memory 25system.physmem.bytes_written::total 8124416 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141236 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.inst 12949 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141185 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::total 154615 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 127156 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 127156 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) | 31system.physmem.num_reads::total 154583 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 126944 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 126944 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) |
| 36system.physmem.bw_read::cpu.inst 159357 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 1740816 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 1905720 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 159357 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 159357 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1567272 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1567272 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1567272 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) | 36system.physmem.bw_read::cpu.inst 159727 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 1741528 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5464 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 1906794 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 159727 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 159727 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1565864 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1565864 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1565864 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) | 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::cpu.inst 159357 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 1740816 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5460 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 3472991 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 154615 # Number of read requests accepted 52system.physmem.writeReqs 173876 # Number of write requests accepted 53system.physmem.readBursts 154615 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 173876 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 9886592 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue 57system.physmem.bytesWritten 10962560 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 9895360 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 11128064 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 2557 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 1589 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 10281 # Per bank write bursts 64system.physmem.perBankRdBursts::1 9591 # Per bank write bursts 65system.physmem.perBankRdBursts::2 10028 # Per bank write bursts 66system.physmem.perBankRdBursts::3 9674 # Per bank write bursts 67system.physmem.perBankRdBursts::4 9945 # Per bank write bursts 68system.physmem.perBankRdBursts::5 9558 # Per bank write bursts 69system.physmem.perBankRdBursts::6 9523 # Per bank write bursts 70system.physmem.perBankRdBursts::7 9498 # Per bank write bursts 71system.physmem.perBankRdBursts::8 9124 # Per bank write bursts 72system.physmem.perBankRdBursts::9 8990 # Per bank write bursts 73system.physmem.perBankRdBursts::10 9390 # Per bank write bursts 74system.physmem.perBankRdBursts::11 9205 # Per bank write bursts 75system.physmem.perBankRdBursts::12 9557 # Per bank write bursts 76system.physmem.perBankRdBursts::13 10069 # Per bank write bursts 77system.physmem.perBankRdBursts::14 10020 # Per bank write bursts 78system.physmem.perBankRdBursts::15 10025 # Per bank write bursts 79system.physmem.perBankWrBursts::0 10769 # Per bank write bursts 80system.physmem.perBankWrBursts::1 10634 # Per bank write bursts 81system.physmem.perBankWrBursts::2 10541 # Per bank write bursts 82system.physmem.perBankWrBursts::3 10043 # Per bank write bursts 83system.physmem.perBankWrBursts::4 11026 # Per bank write bursts 84system.physmem.perBankWrBursts::5 9713 # Per bank write bursts 85system.physmem.perBankWrBursts::6 10229 # Per bank write bursts 86system.physmem.perBankWrBursts::7 10822 # Per bank write bursts 87system.physmem.perBankWrBursts::8 11151 # Per bank write bursts 88system.physmem.perBankWrBursts::9 11218 # Per bank write bursts 89system.physmem.perBankWrBursts::10 10861 # Per bank write bursts 90system.physmem.perBankWrBursts::11 10308 # Per bank write bursts 91system.physmem.perBankWrBursts::12 10862 # Per bank write bursts 92system.physmem.perBankWrBursts::13 11716 # Per bank write bursts 93system.physmem.perBankWrBursts::14 11104 # Per bank write bursts 94system.physmem.perBankWrBursts::15 10293 # Per bank write bursts | 47system.physmem.bw_total::cpu.inst 159727 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 1741528 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5464 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 3472658 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 154583 # Number of read requests accepted 52system.physmem.writeReqs 173664 # Number of write requests accepted 53system.physmem.readBursts 154583 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 173664 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 9885440 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue 57system.physmem.bytesWritten 10960768 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 9893312 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 11114496 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 2370 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 1582 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 10392 # Per bank write bursts 64system.physmem.perBankRdBursts::1 9723 # Per bank write bursts 65system.physmem.perBankRdBursts::2 9455 # Per bank write bursts 66system.physmem.perBankRdBursts::3 9480 # Per bank write bursts 67system.physmem.perBankRdBursts::4 9901 # Per bank write bursts 68system.physmem.perBankRdBursts::5 9535 # Per bank write bursts 69system.physmem.perBankRdBursts::6 9436 # Per bank write bursts 70system.physmem.perBankRdBursts::7 9264 # Per bank write bursts 71system.physmem.perBankRdBursts::8 9069 # Per bank write bursts 72system.physmem.perBankRdBursts::9 9032 # Per bank write bursts 73system.physmem.perBankRdBursts::10 9333 # Per bank write bursts 74system.physmem.perBankRdBursts::11 9426 # Per bank write bursts 75system.physmem.perBankRdBursts::12 9943 # Per bank write bursts 76system.physmem.perBankRdBursts::13 10317 # Per bank write bursts 77system.physmem.perBankRdBursts::14 10185 # Per bank write bursts 78system.physmem.perBankRdBursts::15 9969 # Per bank write bursts 79system.physmem.perBankWrBursts::0 11290 # Per bank write bursts 80system.physmem.perBankWrBursts::1 10662 # Per bank write bursts 81system.physmem.perBankWrBursts::2 11268 # Per bank write bursts 82system.physmem.perBankWrBursts::3 10649 # Per bank write bursts 83system.physmem.perBankWrBursts::4 10537 # Per bank write bursts 84system.physmem.perBankWrBursts::5 10374 # Per bank write bursts 85system.physmem.perBankWrBursts::6 10316 # Per bank write bursts 86system.physmem.perBankWrBursts::7 10238 # Per bank write bursts 87system.physmem.perBankWrBursts::8 10391 # Per bank write bursts 88system.physmem.perBankWrBursts::9 10158 # Per bank write bursts 89system.physmem.perBankWrBursts::10 10967 # Per bank write bursts 90system.physmem.perBankWrBursts::11 11299 # Per bank write bursts 91system.physmem.perBankWrBursts::12 11272 # Per bank write bursts 92system.physmem.perBankWrBursts::13 11296 # Per bank write bursts 93system.physmem.perBankWrBursts::14 10371 # Per bank write bursts 94system.physmem.perBankWrBursts::15 10174 # Per bank write bursts |
| 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 97system.physmem.totGap 5192452820500 # Total gap between requests | 97system.physmem.totGap 5188454413500 # Total gap between requests |
| 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) | 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 104system.physmem.readPktSize::6 154615 # Read request sizes (log2) | 104system.physmem.readPktSize::6 154583 # Read request sizes (log2) |
| 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) | 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 111system.physmem.writePktSize::6 173876 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 151192 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 2858 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 51 # What read queue length does an incoming req see | 111system.physmem.writePktSize::6 173664 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 151266 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 2754 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 58 # What read queue length does an incoming req see |
| 116system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 116system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::15 2714 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 5087 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 8567 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 9777 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 10086 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 11162 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 11557 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 12608 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 12143 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 12879 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 11627 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 11021 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 9719 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 8989 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 7506 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 7120 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 6974 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 6856 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 470 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 426 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 392 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 310 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 249 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 252 # What write queue length does an incoming req see | 159system.physmem.wrQLenPdf::15 2704 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 5147 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 8659 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 9857 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 10197 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 11221 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 11668 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 12698 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 12293 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 12864 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 11643 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 11117 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 9667 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 8924 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 7393 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 7022 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 6786 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 379 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 345 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 332 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 291 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 255 # What write queue length does an incoming req see |
| 185system.physmem.wrQLenPdf::41 243 # What write queue length does an incoming req see | 185system.physmem.wrQLenPdf::41 243 # What write queue length does an incoming req see |
| 186system.physmem.wrQLenPdf::42 245 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 231 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 185 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 176 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 158 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 146 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 142 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 90 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 72 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 48 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 60024 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 347.345862 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 200.231116 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 357.371422 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 21054 35.08% 35.08% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 13721 22.86% 57.94% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 5818 9.69% 67.63% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 3428 5.71% 73.34% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 2258 3.76% 77.10% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 1594 2.66% 79.76% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1149 1.91% 81.67% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 996 1.66% 83.33% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 10006 16.67% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 60024 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 6317 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 24.452430 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 602.471336 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 6316 99.98% 99.98% # Reads before turning the bus around for writes | 186system.physmem.wrQLenPdf::42 221 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 167 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 141 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 131 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 126 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 105 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 73 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 58761 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 354.761560 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 206.245927 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 358.668619 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 19719 33.56% 33.56% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 13641 23.21% 56.77% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 5790 9.85% 66.63% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 3461 5.89% 72.52% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 2363 4.02% 76.54% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 1647 2.80% 79.34% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1118 1.90% 81.24% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1023 1.74% 82.98% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 9999 17.02% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 58761 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 6350 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 24.321575 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 600.921026 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 6349 99.98% 99.98% # Reads before turning the bus around for writes |
| 226system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes | 226system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 227system.physmem.rdPerTurnAround::total 6317 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 6317 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 27.115719 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 21.572083 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 27.245873 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-23 4954 78.42% 78.42% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::24-31 303 4.80% 83.22% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::32-39 227 3.59% 86.81% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::40-47 68 1.08% 87.89% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::48-55 174 2.75% 90.64% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::56-63 37 0.59% 91.23% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::64-71 45 0.71% 91.94% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::72-79 56 0.89% 92.83% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::80-87 90 1.42% 94.25% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::88-95 19 0.30% 94.55% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::96-103 157 2.49% 97.04% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::104-111 22 0.35% 97.39% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::112-119 27 0.43% 97.82% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::120-127 21 0.33% 98.15% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::128-135 36 0.57% 98.72% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::136-143 11 0.17% 98.89% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::144-151 22 0.35% 99.24% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::152-159 8 0.13% 99.37% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::160-167 14 0.22% 99.59% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::176-183 6 0.09% 99.68% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::184-191 5 0.08% 99.76% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::208-215 1 0.02% 99.79% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::216-223 4 0.06% 99.86% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::224-231 3 0.05% 99.91% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::232-239 1 0.02% 99.92% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::240-247 1 0.02% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::248-255 3 0.05% 99.98% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 6317 # Writes before turning the bus around for reads 262system.physmem.totQLat 1525176500 # Total ticks spent queuing 263system.physmem.totMemAccLat 4421639000 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 772390000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 9873.10 # Average queueing delay per DRAM burst | 227system.physmem.rdPerTurnAround::total 6350 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 6350 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 26.970394 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 21.564885 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 26.510023 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 4926 77.57% 77.57% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 38 0.60% 78.17% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 20 0.31% 78.49% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 294 4.63% 83.12% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 158 2.49% 85.61% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 56 0.88% 86.49% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 42 0.66% 87.15% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 42 0.66% 87.81% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 172 2.71% 90.52% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 12 0.19% 90.71% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 18 0.28% 90.99% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 13 0.20% 91.20% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 29 0.46% 91.65% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 15 0.24% 91.89% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 10 0.16% 92.05% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 51 0.80% 92.85% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 104 1.64% 94.49% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::84-87 11 0.17% 94.66% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::88-91 7 0.11% 94.77% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::92-95 15 0.24% 95.01% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 146 2.30% 97.31% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 5 0.08% 97.39% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 14 0.22% 97.61% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::108-111 3 0.05% 97.65% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 26 0.41% 98.06% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 2 0.03% 98.09% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::120-123 6 0.09% 98.19% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 1 0.02% 98.20% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 29 0.46% 98.66% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 4 0.06% 98.72% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 1 0.02% 98.74% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 9 0.14% 98.88% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 18 0.28% 99.17% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::148-151 10 0.16% 99.32% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::152-155 2 0.03% 99.35% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::156-159 1 0.02% 99.37% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::160-163 5 0.08% 99.45% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::164-167 5 0.08% 99.53% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::168-171 2 0.03% 99.56% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::172-175 2 0.03% 99.59% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::176-179 6 0.09% 99.69% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::184-187 1 0.02% 99.70% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::188-191 3 0.05% 99.75% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::192-195 1 0.02% 99.76% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::200-203 7 0.11% 99.87% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::204-207 2 0.03% 99.91% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::216-219 1 0.02% 99.92% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::220-223 2 0.03% 99.95% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::224-227 1 0.02% 99.97% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::228-231 1 0.02% 99.98% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::total 6350 # Writes before turning the bus around for reads 284system.physmem.totQLat 1440123750 # Total ticks spent queuing 285system.physmem.totMemAccLat 4336248750 # Total ticks spent from burst creation until serviced by the DRAM 286system.physmem.totBusLat 772300000 # Total ticks spent in databus transfers 287system.physmem.avgQLat 9323.60 # Average queueing delay per DRAM burst |
| 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 288system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 267system.physmem.avgMemAccLat 28623.10 # Average memory access latency per DRAM burst 268system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s | 289system.physmem.avgMemAccLat 28073.60 # Average memory access latency per DRAM burst 290system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s |
| 269system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.03 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 276system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 291system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s 292system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s 293system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s 294system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 295system.physmem.busUtil 0.03 # Data bus utilization in percentage 296system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 297system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 298system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 277system.physmem.avgWrQLen 25.96 # Average write queue length when enqueuing 278system.physmem.readRowHits 125716 # Number of row buffer hits during reads 279system.physmem.writeRowHits 140027 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 81.38 # Row buffer hit rate for reads | 299system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing 300system.physmem.readRowHits 126965 # Number of row buffer hits during reads 301system.physmem.writeRowHits 139995 # Number of row buffer hits during writes 302system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads |
| 281system.physmem.writeRowHitRate 81.73 # Row buffer hit rate for writes | 303system.physmem.writeRowHitRate 81.73 # Row buffer hit rate for writes |
| 282system.physmem.avgGap 15806986.56 # Average gap between requests 283system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined 284system.physmem_0.actEnergy 224879760 # Energy for activate commands per rank (pJ) 285system.physmem_0.preEnergy 122702250 # Energy for precharge commands per rank (pJ) 286system.physmem_0.readEnergy 609164400 # Energy for read commands per rank (pJ) 287system.physmem_0.writeEnergy 542874960 # Energy for write commands per rank (pJ) 288system.physmem_0.refreshEnergy 339145441440 # Energy for refresh commands per rank (pJ) 289system.physmem_0.actBackEnergy 134202799845 # Energy for active background per rank (pJ) 290system.physmem_0.preBackEnergy 2997747003000 # Energy for precharge background per rank (pJ) 291system.physmem_0.totalEnergy 3472594865655 # Total energy per rank (pJ) 292system.physmem_0.averagePower 668.777986 # Core power per rank (mW) 293system.physmem_0.memoryStateTime::IDLE 4986908920500 # Time in different power states 294system.physmem_0.memoryStateTime::REF 173387240000 # Time in different power states | 304system.physmem.avgGap 15806555.47 # Average gap between requests 305system.physmem.pageHitRate 81.95 # Row buffer hit rate, read and write combined 306system.physmem_0.actEnergy 220290840 # Energy for activate commands per rank (pJ) 307system.physmem_0.preEnergy 120198375 # Energy for precharge commands per rank (pJ) 308system.physmem_0.readEnergy 602050800 # Energy for read commands per rank (pJ) 309system.physmem_0.writeEnergy 552964320 # Energy for write commands per rank (pJ) 310system.physmem_0.refreshEnergy 338884550160 # Energy for refresh commands per rank (pJ) 311system.physmem_0.actBackEnergy 134005273470 # Energy for active background per rank (pJ) 312system.physmem_0.preBackEnergy 2995523664000 # Energy for precharge background per rank (pJ) 313system.physmem_0.totalEnergy 3469908991965 # Total energy per rank (pJ) 314system.physmem_0.averagePower 668.775183 # Core power per rank (mW) 315system.physmem_0.memoryStateTime::IDLE 4983224613500 # Time in different power states 316system.physmem_0.memoryStateTime::REF 173253860000 # Time in different power states |
| 295system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 317system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 296system.physmem_0.memoryStateTime::ACT 32151782000 # Time in different power states | 318system.physmem_0.memoryStateTime::ACT 31975122750 # Time in different power states |
| 297system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 319system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 298system.physmem_1.actEnergy 228901680 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 124896750 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 595756200 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 567084240 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 339145441440 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 134282501235 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 2997677089500 # Energy for precharge background per rank (pJ) 305system.physmem_1.totalEnergy 3472621671045 # Total energy per rank (pJ) 306system.physmem_1.averagePower 668.783148 # Core power per rank (mW) 307system.physmem_1.memoryStateTime::IDLE 4986802992250 # Time in different power states 308system.physmem_1.memoryStateTime::REF 173387240000 # Time in different power states | 320system.physmem_1.actEnergy 223942320 # Energy for activate commands per rank (pJ) 321system.physmem_1.preEnergy 122190750 # Energy for precharge commands per rank (pJ) 322system.physmem_1.readEnergy 602729400 # Energy for read commands per rank (pJ) 323system.physmem_1.writeEnergy 556813440 # Energy for write commands per rank (pJ) 324system.physmem_1.refreshEnergy 338884550160 # Energy for refresh commands per rank (pJ) 325system.physmem_1.actBackEnergy 134550538605 # Energy for active background per rank (pJ) 326system.physmem_1.preBackEnergy 2995045361250 # Energy for precharge background per rank (pJ) 327system.physmem_1.totalEnergy 3469986125925 # Total energy per rank (pJ) 328system.physmem_1.averagePower 668.790049 # Core power per rank (mW) 329system.physmem_1.memoryStateTime::IDLE 4982425910500 # Time in different power states 330system.physmem_1.memoryStateTime::REF 173253860000 # Time in different power states |
| 309system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 331system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 310system.physmem_1.memoryStateTime::ACT 32262536750 # Time in different power states | 332system.physmem_1.memoryStateTime::ACT 32774591500 # Time in different power states |
| 311system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 312system.cpu_clk_domain.clock 500 # Clock period in ticks 313system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 333system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 334system.cpu_clk_domain.clock 500 # Clock period in ticks 335system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 314system.cpu.numCycles 10384905768 # number of cpu cycles simulated | 336system.cpu.numCycles 10376908954 # number of cpu cycles simulated |
| 315system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 316system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 337system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 338system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 317system.cpu.committedInsts 128427413 # Number of instructions committed 318system.cpu.committedOps 247571076 # Number of ops (including micro ops) committed 319system.cpu.num_int_alu_accesses 232151918 # Number of integer alu accesses | 339system.cpu.committedInsts 128768549 # Number of instructions committed 340system.cpu.committedOps 248207575 # Number of ops (including micro ops) committed 341system.cpu.num_int_alu_accesses 232776792 # Number of integer alu accesses |
| 320system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses | 342system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses |
| 321system.cpu.num_func_calls 2302537 # number of times a function call or return occured 322system.cpu.num_conditional_control_insts 23180236 # number of instructions that are conditional controls 323system.cpu.num_int_insts 232151918 # number of integer instructions | 343system.cpu.num_func_calls 2318393 # number of times a function call or return occured 344system.cpu.num_conditional_control_insts 23210237 # number of instructions that are conditional controls 345system.cpu.num_int_insts 232776792 # number of integer instructions |
| 324system.cpu.num_fp_insts 0 # number of float instructions | 346system.cpu.num_fp_insts 0 # number of float instructions |
| 325system.cpu.num_int_register_reads 434861886 # number of times the integer registers were read 326system.cpu.num_int_register_writes 198003963 # number of times the integer registers were written | 347system.cpu.num_int_register_reads 436093789 # number of times the integer registers were read 348system.cpu.num_int_register_writes 198513181 # number of times the integer registers were written |
| 327system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 328system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 349system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 350system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 329system.cpu.num_cc_register_reads 132886732 # number of times the CC registers were read 330system.cpu.num_cc_register_writes 95589498 # number of times the CC registers were written 331system.cpu.num_mem_refs 22270580 # number of memory refs 332system.cpu.num_load_insts 13896035 # Number of load instructions 333system.cpu.num_store_insts 8374545 # Number of store instructions 334system.cpu.num_idle_cycles 9787798534.998116 # Number of idle cycles 335system.cpu.num_busy_cycles 597107233.001885 # Number of busy cycles 336system.cpu.not_idle_fraction 0.057498 # Percentage of non-idle cycles 337system.cpu.idle_fraction 0.942502 # Percentage of idle cycles 338system.cpu.Branches 26321851 # Number of branches fetched 339system.cpu.op_class::No_OpClass 175044 0.07% 0.07% # Class of executed instruction 340system.cpu.op_class::IntAlu 224863247 90.83% 90.90% # Class of executed instruction 341system.cpu.op_class::IntMult 140296 0.06% 90.95% # Class of executed instruction 342system.cpu.op_class::IntDiv 123429 0.05% 91.00% # Class of executed instruction 343system.cpu.op_class::FloatAdd 0 0.00% 91.00% # Class of executed instruction 344system.cpu.op_class::FloatCmp 0 0.00% 91.00% # Class of executed instruction 345system.cpu.op_class::FloatCvt 0 0.00% 91.00% # Class of executed instruction 346system.cpu.op_class::FloatMult 0 0.00% 91.00% # Class of executed instruction 347system.cpu.op_class::FloatDiv 0 0.00% 91.00% # Class of executed instruction 348system.cpu.op_class::FloatSqrt 0 0.00% 91.00% # Class of executed instruction 349system.cpu.op_class::SimdAdd 0 0.00% 91.00% # Class of executed instruction 350system.cpu.op_class::SimdAddAcc 0 0.00% 91.00% # Class of executed instruction 351system.cpu.op_class::SimdAlu 0 0.00% 91.00% # Class of executed instruction 352system.cpu.op_class::SimdCmp 0 0.00% 91.00% # Class of executed instruction 353system.cpu.op_class::SimdCvt 0 0.00% 91.00% # Class of executed instruction 354system.cpu.op_class::SimdMisc 0 0.00% 91.00% # Class of executed instruction 355system.cpu.op_class::SimdMult 0 0.00% 91.00% # Class of executed instruction 356system.cpu.op_class::SimdMultAcc 0 0.00% 91.00% # Class of executed instruction 357system.cpu.op_class::SimdShift 0 0.00% 91.00% # Class of executed instruction 358system.cpu.op_class::SimdShiftAcc 0 0.00% 91.00% # Class of executed instruction 359system.cpu.op_class::SimdSqrt 0 0.00% 91.00% # Class of executed instruction 360system.cpu.op_class::SimdFloatAdd 0 0.00% 91.00% # Class of executed instruction 361system.cpu.op_class::SimdFloatAlu 0 0.00% 91.00% # Class of executed instruction 362system.cpu.op_class::SimdFloatCmp 0 0.00% 91.00% # Class of executed instruction 363system.cpu.op_class::SimdFloatCvt 0 0.00% 91.00% # Class of executed instruction 364system.cpu.op_class::SimdFloatDiv 0 0.00% 91.00% # Class of executed instruction 365system.cpu.op_class::SimdFloatMisc 0 0.00% 91.00% # Class of executed instruction 366system.cpu.op_class::SimdFloatMult 0 0.00% 91.00% # Class of executed instruction 367system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.00% # Class of executed instruction 368system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.00% # Class of executed instruction 369system.cpu.op_class::MemRead 13896035 5.61% 96.62% # Class of executed instruction 370system.cpu.op_class::MemWrite 8374545 3.38% 100.00% # Class of executed instruction | 351system.cpu.num_cc_register_reads 133234655 # number of times the CC registers were read 352system.cpu.num_cc_register_writes 95751573 # number of times the CC registers were written 353system.cpu.num_mem_refs 22383387 # number of memory refs 354system.cpu.num_load_insts 13964107 # Number of load instructions 355system.cpu.num_store_insts 8419280 # Number of store instructions 356system.cpu.num_idle_cycles 9778785583.998116 # Number of idle cycles 357system.cpu.num_busy_cycles 598123370.001885 # Number of busy cycles 358system.cpu.not_idle_fraction 0.057640 # Percentage of non-idle cycles 359system.cpu.idle_fraction 0.942360 # Percentage of idle cycles 360system.cpu.Branches 26388104 # Number of branches fetched 361system.cpu.op_class::No_OpClass 172612 0.07% 0.07% # Class of executed instruction 362system.cpu.op_class::IntAlu 225394100 90.81% 90.88% # Class of executed instruction 363system.cpu.op_class::IntMult 140617 0.06% 90.93% # Class of executed instruction 364system.cpu.op_class::IntDiv 123416 0.05% 90.98% # Class of executed instruction 365system.cpu.op_class::FloatAdd 0 0.00% 90.98% # Class of executed instruction 366system.cpu.op_class::FloatCmp 0 0.00% 90.98% # Class of executed instruction 367system.cpu.op_class::FloatCvt 0 0.00% 90.98% # Class of executed instruction 368system.cpu.op_class::FloatMult 0 0.00% 90.98% # Class of executed instruction 369system.cpu.op_class::FloatDiv 0 0.00% 90.98% # Class of executed instruction 370system.cpu.op_class::FloatSqrt 0 0.00% 90.98% # Class of executed instruction 371system.cpu.op_class::SimdAdd 0 0.00% 90.98% # Class of executed instruction 372system.cpu.op_class::SimdAddAcc 0 0.00% 90.98% # Class of executed instruction 373system.cpu.op_class::SimdAlu 0 0.00% 90.98% # Class of executed instruction 374system.cpu.op_class::SimdCmp 0 0.00% 90.98% # Class of executed instruction 375system.cpu.op_class::SimdCvt 0 0.00% 90.98% # Class of executed instruction 376system.cpu.op_class::SimdMisc 0 0.00% 90.98% # Class of executed instruction 377system.cpu.op_class::SimdMult 0 0.00% 90.98% # Class of executed instruction 378system.cpu.op_class::SimdMultAcc 0 0.00% 90.98% # Class of executed instruction 379system.cpu.op_class::SimdShift 0 0.00% 90.98% # Class of executed instruction 380system.cpu.op_class::SimdShiftAcc 0 0.00% 90.98% # Class of executed instruction 381system.cpu.op_class::SimdSqrt 0 0.00% 90.98% # Class of executed instruction 382system.cpu.op_class::SimdFloatAdd 0 0.00% 90.98% # Class of executed instruction 383system.cpu.op_class::SimdFloatAlu 0 0.00% 90.98% # Class of executed instruction 384system.cpu.op_class::SimdFloatCmp 0 0.00% 90.98% # Class of executed instruction 385system.cpu.op_class::SimdFloatCvt 0 0.00% 90.98% # Class of executed instruction 386system.cpu.op_class::SimdFloatDiv 0 0.00% 90.98% # Class of executed instruction 387system.cpu.op_class::SimdFloatMisc 0 0.00% 90.98% # Class of executed instruction 388system.cpu.op_class::SimdFloatMult 0 0.00% 90.98% # Class of executed instruction 389system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.98% # Class of executed instruction 390system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.98% # Class of executed instruction 391system.cpu.op_class::MemRead 13959118 5.62% 96.61% # Class of executed instruction 392system.cpu.op_class::MemWrite 8419280 3.39% 100.00% # Class of executed instruction |
| 371system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 372system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 393system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 394system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 373system.cpu.op_class::total 247572596 # Class of executed instruction | 395system.cpu.op_class::total 248209143 # Class of executed instruction |
| 374system.cpu.kern.inst.arm 0 # number of arm instructions executed 375system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 396system.cpu.kern.inst.arm 0 # number of arm instructions executed 397system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 376system.cpu.dcache.tags.replacements 1622236 # number of replacements 377system.cpu.dcache.tags.tagsinuse 511.996968 # Cycle average of tags in use 378system.cpu.dcache.tags.total_refs 20050453 # Total number of references to valid blocks. 379system.cpu.dcache.tags.sampled_refs 1622748 # Sample count of references to valid blocks. 380system.cpu.dcache.tags.avg_refs 12.355864 # Average number of references to valid blocks. | 398system.cpu.dcache.tags.replacements 1623444 # number of replacements 399system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 400system.cpu.dcache.tags.total_refs 20166944 # Total number of references to valid blocks. 401system.cpu.dcache.tags.sampled_refs 1623956 # Sample count of references to valid blocks. 402system.cpu.dcache.tags.avg_refs 12.418405 # Average number of references to valid blocks. |
| 381system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. | 403system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. |
| 382system.cpu.dcache.tags.occ_blocks::cpu.data 511.996968 # Average occupied blocks per requestor | 404system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor |
| 383system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 384system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 385system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 405system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 406system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 407system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 386system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id 387system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 388system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id 389system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 408system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 409system.cpu.dcache.tags.age_task_id_blocks_1024::1 326 # Occupied blocks per task id 410system.cpu.dcache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id |
| 390system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 411system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 391system.cpu.dcache.tags.tag_accesses 88354150 # Number of tag accesses 392system.cpu.dcache.tags.data_accesses 88354150 # Number of data accesses 393system.cpu.dcache.ReadReq_hits::cpu.data 11949885 # number of ReadReq hits 394system.cpu.dcache.ReadReq_hits::total 11949885 # number of ReadReq hits 395system.cpu.dcache.WriteReq_hits::cpu.data 8039029 # number of WriteReq hits 396system.cpu.dcache.WriteReq_hits::total 8039029 # number of WriteReq hits 397system.cpu.dcache.SoftPFReq_hits::cpu.data 59358 # number of SoftPFReq hits 398system.cpu.dcache.SoftPFReq_hits::total 59358 # number of SoftPFReq hits 399system.cpu.dcache.demand_hits::cpu.data 19988914 # number of demand (read+write) hits 400system.cpu.dcache.demand_hits::total 19988914 # number of demand (read+write) hits 401system.cpu.dcache.overall_hits::cpu.data 20048272 # number of overall hits 402system.cpu.dcache.overall_hits::total 20048272 # number of overall hits 403system.cpu.dcache.ReadReq_misses::cpu.data 907019 # number of ReadReq misses 404system.cpu.dcache.ReadReq_misses::total 907019 # number of ReadReq misses 405system.cpu.dcache.WriteReq_misses::cpu.data 325091 # number of WriteReq misses 406system.cpu.dcache.WriteReq_misses::total 325091 # number of WriteReq misses 407system.cpu.dcache.SoftPFReq_misses::cpu.data 402457 # number of SoftPFReq misses 408system.cpu.dcache.SoftPFReq_misses::total 402457 # number of SoftPFReq misses 409system.cpu.dcache.demand_misses::cpu.data 1232110 # number of demand (read+write) misses 410system.cpu.dcache.demand_misses::total 1232110 # number of demand (read+write) misses 411system.cpu.dcache.overall_misses::cpu.data 1634567 # number of overall misses 412system.cpu.dcache.overall_misses::total 1634567 # number of overall misses 413system.cpu.dcache.ReadReq_miss_latency::cpu.data 12730749000 # number of ReadReq miss cycles 414system.cpu.dcache.ReadReq_miss_latency::total 12730749000 # number of ReadReq miss cycles 415system.cpu.dcache.WriteReq_miss_latency::cpu.data 11380492066 # number of WriteReq miss cycles 416system.cpu.dcache.WriteReq_miss_latency::total 11380492066 # number of WriteReq miss cycles 417system.cpu.dcache.demand_miss_latency::cpu.data 24111241066 # number of demand (read+write) miss cycles 418system.cpu.dcache.demand_miss_latency::total 24111241066 # number of demand (read+write) miss cycles 419system.cpu.dcache.overall_miss_latency::cpu.data 24111241066 # number of overall miss cycles 420system.cpu.dcache.overall_miss_latency::total 24111241066 # number of overall miss cycles 421system.cpu.dcache.ReadReq_accesses::cpu.data 12856904 # number of ReadReq accesses(hits+misses) 422system.cpu.dcache.ReadReq_accesses::total 12856904 # number of ReadReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::cpu.data 8364120 # number of WriteReq accesses(hits+misses) 424system.cpu.dcache.WriteReq_accesses::total 8364120 # number of WriteReq accesses(hits+misses) 425system.cpu.dcache.SoftPFReq_accesses::cpu.data 461815 # number of SoftPFReq accesses(hits+misses) 426system.cpu.dcache.SoftPFReq_accesses::total 461815 # number of SoftPFReq accesses(hits+misses) 427system.cpu.dcache.demand_accesses::cpu.data 21221024 # number of demand (read+write) accesses 428system.cpu.dcache.demand_accesses::total 21221024 # number of demand (read+write) accesses 429system.cpu.dcache.overall_accesses::cpu.data 21682839 # number of overall (read+write) accesses 430system.cpu.dcache.overall_accesses::total 21682839 # number of overall (read+write) accesses 431system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070547 # miss rate for ReadReq accesses 432system.cpu.dcache.ReadReq_miss_rate::total 0.070547 # miss rate for ReadReq accesses 433system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038867 # miss rate for WriteReq accesses 434system.cpu.dcache.WriteReq_miss_rate::total 0.038867 # miss rate for WriteReq accesses 435system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871468 # miss rate for SoftPFReq accesses 436system.cpu.dcache.SoftPFReq_miss_rate::total 0.871468 # miss rate for SoftPFReq accesses 437system.cpu.dcache.demand_miss_rate::cpu.data 0.058061 # miss rate for demand accesses 438system.cpu.dcache.demand_miss_rate::total 0.058061 # miss rate for demand accesses 439system.cpu.dcache.overall_miss_rate::cpu.data 0.075385 # miss rate for overall accesses 440system.cpu.dcache.overall_miss_rate::total 0.075385 # miss rate for overall accesses 441system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14035.812921 # average ReadReq miss latency 442system.cpu.dcache.ReadReq_avg_miss_latency::total 14035.812921 # average ReadReq miss latency 443system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35007.096678 # average WriteReq miss latency 444system.cpu.dcache.WriteReq_avg_miss_latency::total 35007.096678 # average WriteReq miss latency 445system.cpu.dcache.demand_avg_miss_latency::cpu.data 19569.065316 # average overall miss latency 446system.cpu.dcache.demand_avg_miss_latency::total 19569.065316 # average overall miss latency 447system.cpu.dcache.overall_avg_miss_latency::cpu.data 14750.842924 # average overall miss latency 448system.cpu.dcache.overall_avg_miss_latency::total 14750.842924 # average overall miss latency 449system.cpu.dcache.blocked_cycles::no_mshrs 6388 # number of cycles access was blocked | 412system.cpu.dcache.tags.tag_accesses 88826058 # Number of tag accesses 413system.cpu.dcache.tags.data_accesses 88826058 # Number of data accesses 414system.cpu.dcache.ReadReq_hits::cpu.data 12020150 # number of ReadReq hits 415system.cpu.dcache.ReadReq_hits::total 12020150 # number of ReadReq hits 416system.cpu.dcache.WriteReq_hits::cpu.data 8085355 # number of WriteReq hits 417system.cpu.dcache.WriteReq_hits::total 8085355 # number of WriteReq hits 418system.cpu.dcache.SoftPFReq_hits::cpu.data 59272 # number of SoftPFReq hits 419system.cpu.dcache.SoftPFReq_hits::total 59272 # number of SoftPFReq hits 420system.cpu.dcache.demand_hits::cpu.data 20105505 # number of demand (read+write) hits 421system.cpu.dcache.demand_hits::total 20105505 # number of demand (read+write) hits 422system.cpu.dcache.overall_hits::cpu.data 20164777 # number of overall hits 423system.cpu.dcache.overall_hits::total 20164777 # number of overall hits 424system.cpu.dcache.ReadReq_misses::cpu.data 907010 # number of ReadReq misses 425system.cpu.dcache.ReadReq_misses::total 907010 # number of ReadReq misses 426system.cpu.dcache.WriteReq_misses::cpu.data 325954 # number of WriteReq misses 427system.cpu.dcache.WriteReq_misses::total 325954 # number of WriteReq misses 428system.cpu.dcache.SoftPFReq_misses::cpu.data 402776 # number of SoftPFReq misses 429system.cpu.dcache.SoftPFReq_misses::total 402776 # number of SoftPFReq misses 430system.cpu.dcache.demand_misses::cpu.data 1232964 # number of demand (read+write) misses 431system.cpu.dcache.demand_misses::total 1232964 # number of demand (read+write) misses 432system.cpu.dcache.overall_misses::cpu.data 1635740 # number of overall misses 433system.cpu.dcache.overall_misses::total 1635740 # number of overall misses 434system.cpu.dcache.ReadReq_miss_latency::cpu.data 12729308500 # number of ReadReq miss cycles 435system.cpu.dcache.ReadReq_miss_latency::total 12729308500 # number of ReadReq miss cycles 436system.cpu.dcache.WriteReq_miss_latency::cpu.data 11333106054 # number of WriteReq miss cycles 437system.cpu.dcache.WriteReq_miss_latency::total 11333106054 # number of WriteReq miss cycles 438system.cpu.dcache.demand_miss_latency::cpu.data 24062414554 # number of demand (read+write) miss cycles 439system.cpu.dcache.demand_miss_latency::total 24062414554 # number of demand (read+write) miss cycles 440system.cpu.dcache.overall_miss_latency::cpu.data 24062414554 # number of overall miss cycles 441system.cpu.dcache.overall_miss_latency::total 24062414554 # number of overall miss cycles 442system.cpu.dcache.ReadReq_accesses::cpu.data 12927160 # number of ReadReq accesses(hits+misses) 443system.cpu.dcache.ReadReq_accesses::total 12927160 # number of ReadReq accesses(hits+misses) 444system.cpu.dcache.WriteReq_accesses::cpu.data 8411309 # number of WriteReq accesses(hits+misses) 445system.cpu.dcache.WriteReq_accesses::total 8411309 # number of WriteReq accesses(hits+misses) 446system.cpu.dcache.SoftPFReq_accesses::cpu.data 462048 # number of SoftPFReq accesses(hits+misses) 447system.cpu.dcache.SoftPFReq_accesses::total 462048 # number of SoftPFReq accesses(hits+misses) 448system.cpu.dcache.demand_accesses::cpu.data 21338469 # number of demand (read+write) accesses 449system.cpu.dcache.demand_accesses::total 21338469 # number of demand (read+write) accesses 450system.cpu.dcache.overall_accesses::cpu.data 21800517 # number of overall (read+write) accesses 451system.cpu.dcache.overall_accesses::total 21800517 # number of overall (read+write) accesses 452system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070163 # miss rate for ReadReq accesses 453system.cpu.dcache.ReadReq_miss_rate::total 0.070163 # miss rate for ReadReq accesses 454system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038752 # miss rate for WriteReq accesses 455system.cpu.dcache.WriteReq_miss_rate::total 0.038752 # miss rate for WriteReq accesses 456system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871719 # miss rate for SoftPFReq accesses 457system.cpu.dcache.SoftPFReq_miss_rate::total 0.871719 # miss rate for SoftPFReq accesses 458system.cpu.dcache.demand_miss_rate::cpu.data 0.057781 # miss rate for demand accesses 459system.cpu.dcache.demand_miss_rate::total 0.057781 # miss rate for demand accesses 460system.cpu.dcache.overall_miss_rate::cpu.data 0.075032 # miss rate for overall accesses 461system.cpu.dcache.overall_miss_rate::total 0.075032 # miss rate for overall accesses 462system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14034.364009 # average ReadReq miss latency 463system.cpu.dcache.ReadReq_avg_miss_latency::total 14034.364009 # average ReadReq miss latency 464system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34769.035060 # average WriteReq miss latency 465system.cpu.dcache.WriteReq_avg_miss_latency::total 34769.035060 # average WriteReq miss latency 466system.cpu.dcache.demand_avg_miss_latency::cpu.data 19515.910078 # average overall miss latency 467system.cpu.dcache.demand_avg_miss_latency::total 19515.910078 # average overall miss latency 468system.cpu.dcache.overall_avg_miss_latency::cpu.data 14710.415197 # average overall miss latency 469system.cpu.dcache.overall_avg_miss_latency::total 14710.415197 # average overall miss latency 470system.cpu.dcache.blocked_cycles::no_mshrs 9503 # number of cycles access was blocked |
| 450system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 471system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 451system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked | 472system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked |
| 452system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 473system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 453system.cpu.dcache.avg_blocked_cycles::no_mshrs 87.506849 # average number of cycles each access was blocked | 474system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.293478 # average number of cycles each access was blocked |
| 454system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 455system.cpu.dcache.fast_writes 0 # number of fast writes performed 456system.cpu.dcache.cache_copies 0 # number of cache copies performed | 475system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 476system.cpu.dcache.fast_writes 0 # number of fast writes performed 477system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 457system.cpu.dcache.writebacks::writebacks 1539114 # number of writebacks 458system.cpu.dcache.writebacks::total 1539114 # number of writebacks 459system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits 460system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits 461system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9270 # number of WriteReq MSHR hits 462system.cpu.dcache.WriteReq_mshr_hits::total 9270 # number of WriteReq MSHR hits 463system.cpu.dcache.demand_mshr_hits::cpu.data 9557 # number of demand (read+write) MSHR hits 464system.cpu.dcache.demand_mshr_hits::total 9557 # number of demand (read+write) MSHR hits 465system.cpu.dcache.overall_mshr_hits::cpu.data 9557 # number of overall MSHR hits 466system.cpu.dcache.overall_mshr_hits::total 9557 # number of overall MSHR hits 467system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906732 # number of ReadReq MSHR misses 468system.cpu.dcache.ReadReq_mshr_misses::total 906732 # number of ReadReq MSHR misses 469system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315821 # number of WriteReq MSHR misses 470system.cpu.dcache.WriteReq_mshr_misses::total 315821 # number of WriteReq MSHR misses 471system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402422 # number of SoftPFReq MSHR misses 472system.cpu.dcache.SoftPFReq_mshr_misses::total 402422 # number of SoftPFReq MSHR misses 473system.cpu.dcache.demand_mshr_misses::cpu.data 1222553 # number of demand (read+write) MSHR misses 474system.cpu.dcache.demand_mshr_misses::total 1222553 # number of demand (read+write) MSHR misses 475system.cpu.dcache.overall_mshr_misses::cpu.data 1624975 # number of overall MSHR misses 476system.cpu.dcache.overall_mshr_misses::total 1624975 # number of overall MSHR misses 477system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10909979000 # number of ReadReq MSHR miss cycles 478system.cpu.dcache.ReadReq_mshr_miss_latency::total 10909979000 # number of ReadReq MSHR miss cycles 479system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10244477888 # number of WriteReq MSHR miss cycles 480system.cpu.dcache.WriteReq_mshr_miss_latency::total 10244477888 # number of WriteReq MSHR miss cycles 481system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5364351750 # number of SoftPFReq MSHR miss cycles 482system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5364351750 # number of SoftPFReq MSHR miss cycles 483system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21154456888 # number of demand (read+write) MSHR miss cycles 484system.cpu.dcache.demand_mshr_miss_latency::total 21154456888 # number of demand (read+write) MSHR miss cycles 485system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26518808638 # number of overall MSHR miss cycles 486system.cpu.dcache.overall_mshr_miss_latency::total 26518808638 # number of overall MSHR miss cycles 487system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles 488system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles 489system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561567000 # number of WriteReq MSHR uncacheable cycles 490system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561567000 # number of WriteReq MSHR uncacheable cycles 491system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96801940000 # number of overall MSHR uncacheable cycles 492system.cpu.dcache.overall_mshr_uncacheable_latency::total 96801940000 # number of overall MSHR uncacheable cycles 493system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070525 # mshr miss rate for ReadReq accesses 494system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070525 # mshr miss rate for ReadReq accesses 495system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037759 # mshr miss rate for WriteReq accesses 496system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037759 # mshr miss rate for WriteReq accesses 497system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871392 # mshr miss rate for SoftPFReq accesses 498system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871392 # mshr miss rate for SoftPFReq accesses 499system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057610 # mshr miss rate for demand accesses 500system.cpu.dcache.demand_mshr_miss_rate::total 0.057610 # mshr miss rate for demand accesses 501system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074943 # mshr miss rate for overall accesses 502system.cpu.dcache.overall_mshr_miss_rate::total 0.074943 # mshr miss rate for overall accesses 503system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.198047 # average ReadReq mshr miss latency 504system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.198047 # average ReadReq mshr miss latency 505system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.608291 # average WriteReq mshr miss latency 506system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.608291 # average WriteReq mshr miss latency 507system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13330.165225 # average SoftPFReq mshr miss latency 508system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13330.165225 # average SoftPFReq mshr miss latency 509system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17303.509041 # average overall mshr miss latency 510system.cpu.dcache.demand_avg_mshr_miss_latency::total 17303.509041 # average overall mshr miss latency 511system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16319.517924 # average overall mshr miss latency 512system.cpu.dcache.overall_avg_mshr_miss_latency::total 16319.517924 # average overall mshr miss latency | 478system.cpu.dcache.writebacks::writebacks 1539984 # number of writebacks 479system.cpu.dcache.writebacks::total 1539984 # number of writebacks 480system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits 481system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits 482system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9259 # number of WriteReq MSHR hits 483system.cpu.dcache.WriteReq_mshr_hits::total 9259 # number of WriteReq MSHR hits 484system.cpu.dcache.demand_mshr_hits::cpu.data 9549 # number of demand (read+write) MSHR hits 485system.cpu.dcache.demand_mshr_hits::total 9549 # number of demand (read+write) MSHR hits 486system.cpu.dcache.overall_mshr_hits::cpu.data 9549 # number of overall MSHR hits 487system.cpu.dcache.overall_mshr_hits::total 9549 # number of overall MSHR hits 488system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906720 # number of ReadReq MSHR misses 489system.cpu.dcache.ReadReq_mshr_misses::total 906720 # number of ReadReq MSHR misses 490system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316695 # number of WriteReq MSHR misses 491system.cpu.dcache.WriteReq_mshr_misses::total 316695 # number of WriteReq MSHR misses 492system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402742 # number of SoftPFReq MSHR misses 493system.cpu.dcache.SoftPFReq_mshr_misses::total 402742 # number of SoftPFReq MSHR misses 494system.cpu.dcache.demand_mshr_misses::cpu.data 1223415 # number of demand (read+write) MSHR misses 495system.cpu.dcache.demand_mshr_misses::total 1223415 # number of demand (read+write) MSHR misses 496system.cpu.dcache.overall_mshr_misses::cpu.data 1626157 # number of overall MSHR misses 497system.cpu.dcache.overall_mshr_misses::total 1626157 # number of overall MSHR misses 498system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10908565500 # number of ReadReq MSHR miss cycles 499system.cpu.dcache.ReadReq_mshr_miss_latency::total 10908565500 # number of ReadReq MSHR miss cycles 500system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10195656140 # number of WriteReq MSHR miss cycles 501system.cpu.dcache.WriteReq_mshr_miss_latency::total 10195656140 # number of WriteReq MSHR miss cycles 502system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5345944000 # number of SoftPFReq MSHR miss cycles 503system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5345944000 # number of SoftPFReq MSHR miss cycles 504system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21104221640 # number of demand (read+write) MSHR miss cycles 505system.cpu.dcache.demand_mshr_miss_latency::total 21104221640 # number of demand (read+write) MSHR miss cycles 506system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26450165640 # number of overall MSHR miss cycles 507system.cpu.dcache.overall_mshr_miss_latency::total 26450165640 # number of overall MSHR miss cycles 508system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94247525000 # number of ReadReq MSHR uncacheable cycles 509system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94247525000 # number of ReadReq MSHR uncacheable cycles 510system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568414500 # number of WriteReq MSHR uncacheable cycles 511system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568414500 # number of WriteReq MSHR uncacheable cycles 512system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815939500 # number of overall MSHR uncacheable cycles 513system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815939500 # number of overall MSHR uncacheable cycles 514system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070141 # mshr miss rate for ReadReq accesses 515system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070141 # mshr miss rate for ReadReq accesses 516system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037651 # mshr miss rate for WriteReq accesses 517system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037651 # mshr miss rate for WriteReq accesses 518system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871645 # mshr miss rate for SoftPFReq accesses 519system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871645 # mshr miss rate for SoftPFReq accesses 520system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057334 # mshr miss rate for demand accesses 521system.cpu.dcache.demand_mshr_miss_rate::total 0.057334 # mshr miss rate for demand accesses 522system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074593 # mshr miss rate for overall accesses 523system.cpu.dcache.overall_mshr_miss_rate::total 0.074593 # mshr miss rate for overall accesses 524system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12030.798372 # average ReadReq mshr miss latency 525system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12030.798372 # average ReadReq mshr miss latency 526system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32193.928354 # average WriteReq mshr miss latency 527system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32193.928354 # average WriteReq mshr miss latency 528system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13273.867637 # average SoftPFReq mshr miss latency 529system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13273.867637 # average SoftPFReq mshr miss latency 530system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17250.255751 # average overall mshr miss latency 531system.cpu.dcache.demand_avg_mshr_miss_latency::total 17250.255751 # average overall mshr miss latency 532system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16265.444013 # average overall mshr miss latency 533system.cpu.dcache.overall_avg_mshr_miss_latency::total 16265.444013 # average overall mshr miss latency |
| 513system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 514system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 515system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 516system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 517system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 518system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 519system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 534system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 535system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 536system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 537system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 538system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 539system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 540system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 520system.cpu.dtb_walker_cache.tags.replacements 7361 # number of replacements 521system.cpu.dtb_walker_cache.tags.tagsinuse 5.061574 # Cycle average of tags in use 522system.cpu.dtb_walker_cache.tags.total_refs 13446 # Total number of references to valid blocks. 523system.cpu.dtb_walker_cache.tags.sampled_refs 7376 # Sample count of references to valid blocks. 524system.cpu.dtb_walker_cache.tags.avg_refs 1.822939 # Average number of references to valid blocks. 525system.cpu.dtb_walker_cache.tags.warmup_cycle 5159721667000 # Cycle when the warmup percentage was hit. 526system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061574 # Average occupied blocks per requestor 527system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316348 # Average percentage of cache occupancy 528system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316348 # Average percentage of cache occupancy 529system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 530system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 531system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 532system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id 533system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 534system.cpu.dtb_walker_cache.tags.tag_accesses 52616 # Number of tag accesses 535system.cpu.dtb_walker_cache.tags.data_accesses 52616 # Number of data accesses 536system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13447 # number of ReadReq hits 537system.cpu.dtb_walker_cache.ReadReq_hits::total 13447 # number of ReadReq hits 538system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13447 # number of demand (read+write) hits 539system.cpu.dtb_walker_cache.demand_hits::total 13447 # number of demand (read+write) hits 540system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13447 # number of overall hits 541system.cpu.dtb_walker_cache.overall_hits::total 13447 # number of overall hits 542system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8574 # number of ReadReq misses 543system.cpu.dtb_walker_cache.ReadReq_misses::total 8574 # number of ReadReq misses 544system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8574 # number of demand (read+write) misses 545system.cpu.dtb_walker_cache.demand_misses::total 8574 # number of demand (read+write) misses 546system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8574 # number of overall misses 547system.cpu.dtb_walker_cache.overall_misses::total 8574 # number of overall misses 548system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 90024000 # number of ReadReq miss cycles 549system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 90024000 # number of ReadReq miss cycles 550system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 90024000 # number of demand (read+write) miss cycles 551system.cpu.dtb_walker_cache.demand_miss_latency::total 90024000 # number of demand (read+write) miss cycles 552system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 90024000 # number of overall miss cycles 553system.cpu.dtb_walker_cache.overall_miss_latency::total 90024000 # number of overall miss cycles 554system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22021 # number of ReadReq accesses(hits+misses) 555system.cpu.dtb_walker_cache.ReadReq_accesses::total 22021 # number of ReadReq accesses(hits+misses) 556system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22021 # number of demand (read+write) accesses 557system.cpu.dtb_walker_cache.demand_accesses::total 22021 # number of demand (read+write) accesses 558system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22021 # number of overall (read+write) accesses 559system.cpu.dtb_walker_cache.overall_accesses::total 22021 # number of overall (read+write) accesses 560system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.389356 # miss rate for ReadReq accesses 561system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.389356 # miss rate for ReadReq accesses 562system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.389356 # miss rate for demand accesses 563system.cpu.dtb_walker_cache.demand_miss_rate::total 0.389356 # miss rate for demand accesses 564system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.389356 # miss rate for overall accesses 565system.cpu.dtb_walker_cache.overall_miss_rate::total 0.389356 # miss rate for overall accesses 566system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10499.650105 # average ReadReq miss latency 567system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10499.650105 # average ReadReq miss latency 568system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10499.650105 # average overall miss latency 569system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10499.650105 # average overall miss latency 570system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10499.650105 # average overall miss latency 571system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10499.650105 # average overall miss latency | 541system.cpu.dtb_walker_cache.tags.replacements 8115 # number of replacements 542system.cpu.dtb_walker_cache.tags.tagsinuse 5.053285 # Cycle average of tags in use 543system.cpu.dtb_walker_cache.tags.total_refs 13021 # Total number of references to valid blocks. 544system.cpu.dtb_walker_cache.tags.sampled_refs 8129 # Sample count of references to valid blocks. 545system.cpu.dtb_walker_cache.tags.avg_refs 1.601796 # Average number of references to valid blocks. 546system.cpu.dtb_walker_cache.tags.warmup_cycle 5157393413000 # Cycle when the warmup percentage was hit. 547system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053285 # Average occupied blocks per requestor 548system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315830 # Average percentage of cache occupancy 549system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315830 # Average percentage of cache occupancy 550system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 551system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 552system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 553system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 554system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 555system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id 556system.cpu.dtb_walker_cache.tags.tag_accesses 54039 # Number of tag accesses 557system.cpu.dtb_walker_cache.tags.data_accesses 54039 # Number of data accesses 558system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13023 # number of ReadReq hits 559system.cpu.dtb_walker_cache.ReadReq_hits::total 13023 # number of ReadReq hits 560system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13023 # number of demand (read+write) hits 561system.cpu.dtb_walker_cache.demand_hits::total 13023 # number of demand (read+write) hits 562system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13023 # number of overall hits 563system.cpu.dtb_walker_cache.overall_hits::total 13023 # number of overall hits 564system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9331 # number of ReadReq misses 565system.cpu.dtb_walker_cache.ReadReq_misses::total 9331 # number of ReadReq misses 566system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9331 # number of demand (read+write) misses 567system.cpu.dtb_walker_cache.demand_misses::total 9331 # number of demand (read+write) misses 568system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9331 # number of overall misses 569system.cpu.dtb_walker_cache.overall_misses::total 9331 # number of overall misses 570system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97236000 # number of ReadReq miss cycles 571system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97236000 # number of ReadReq miss cycles 572system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97236000 # number of demand (read+write) miss cycles 573system.cpu.dtb_walker_cache.demand_miss_latency::total 97236000 # number of demand (read+write) miss cycles 574system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97236000 # number of overall miss cycles 575system.cpu.dtb_walker_cache.overall_miss_latency::total 97236000 # number of overall miss cycles 576system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22354 # number of ReadReq accesses(hits+misses) 577system.cpu.dtb_walker_cache.ReadReq_accesses::total 22354 # number of ReadReq accesses(hits+misses) 578system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22354 # number of demand (read+write) accesses 579system.cpu.dtb_walker_cache.demand_accesses::total 22354 # number of demand (read+write) accesses 580system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22354 # number of overall (read+write) accesses 581system.cpu.dtb_walker_cache.overall_accesses::total 22354 # number of overall (read+write) accesses 582system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.417420 # miss rate for ReadReq accesses 583system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.417420 # miss rate for ReadReq accesses 584system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.417420 # miss rate for demand accesses 585system.cpu.dtb_walker_cache.demand_miss_rate::total 0.417420 # miss rate for demand accesses 586system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.417420 # miss rate for overall accesses 587system.cpu.dtb_walker_cache.overall_miss_rate::total 0.417420 # miss rate for overall accesses 588system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10420.748044 # average ReadReq miss latency 589system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10420.748044 # average ReadReq miss latency 590system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10420.748044 # average overall miss latency 591system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10420.748044 # average overall miss latency 592system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10420.748044 # average overall miss latency 593system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10420.748044 # average overall miss latency |
| 572system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 573system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 574system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 575system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 576system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 577system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 578system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 579system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 594system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 595system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 596system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 597system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 598system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 599system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 600system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 601system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 580system.cpu.dtb_walker_cache.writebacks::writebacks 2787 # number of writebacks 581system.cpu.dtb_walker_cache.writebacks::total 2787 # number of writebacks 582system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8574 # number of ReadReq MSHR misses 583system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8574 # number of ReadReq MSHR misses 584system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8574 # number of demand (read+write) MSHR misses 585system.cpu.dtb_walker_cache.demand_mshr_misses::total 8574 # number of demand (read+write) MSHR misses 586system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8574 # number of overall MSHR misses 587system.cpu.dtb_walker_cache.overall_mshr_misses::total 8574 # number of overall MSHR misses 588system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 72875500 # number of ReadReq MSHR miss cycles 589system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 72875500 # number of ReadReq MSHR miss cycles 590system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 72875500 # number of demand (read+write) MSHR miss cycles 591system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 72875500 # number of demand (read+write) MSHR miss cycles 592system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 72875500 # number of overall MSHR miss cycles 593system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 72875500 # number of overall MSHR miss cycles 594system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for ReadReq accesses 595system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.389356 # mshr miss rate for ReadReq accesses 596system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for demand accesses 597system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.389356 # mshr miss rate for demand accesses 598system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.389356 # mshr miss rate for overall accesses 599system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.389356 # mshr miss rate for overall accesses 600system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average ReadReq mshr miss latency 601system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8499.591789 # average ReadReq mshr miss latency 602system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average overall mshr miss latency 603system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8499.591789 # average overall mshr miss latency 604system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8499.591789 # average overall mshr miss latency 605system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8499.591789 # average overall mshr miss latency | 602system.cpu.dtb_walker_cache.writebacks::writebacks 3011 # number of writebacks 603system.cpu.dtb_walker_cache.writebacks::total 3011 # number of writebacks 604system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9331 # number of ReadReq MSHR misses 605system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9331 # number of ReadReq MSHR misses 606system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9331 # number of demand (read+write) MSHR misses 607system.cpu.dtb_walker_cache.demand_mshr_misses::total 9331 # number of demand (read+write) MSHR misses 608system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9331 # number of overall MSHR misses 609system.cpu.dtb_walker_cache.overall_mshr_misses::total 9331 # number of overall MSHR misses 610system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 78573500 # number of ReadReq MSHR miss cycles 611system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 78573500 # number of ReadReq MSHR miss cycles 612system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 78573500 # number of demand (read+write) MSHR miss cycles 613system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 78573500 # number of demand (read+write) MSHR miss cycles 614system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 78573500 # number of overall MSHR miss cycles 615system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 78573500 # number of overall MSHR miss cycles 616system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for ReadReq accesses 617system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.417420 # mshr miss rate for ReadReq accesses 618system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for demand accesses 619system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.417420 # mshr miss rate for demand accesses 620system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.417420 # mshr miss rate for overall accesses 621system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.417420 # mshr miss rate for overall accesses 622system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average ReadReq mshr miss latency 623system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8420.694459 # average ReadReq mshr miss latency 624system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average overall mshr miss latency 625system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8420.694459 # average overall mshr miss latency 626system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8420.694459 # average overall mshr miss latency 627system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8420.694459 # average overall mshr miss latency |
| 606system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 628system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 607system.cpu.icache.tags.replacements 793260 # number of replacements 608system.cpu.icache.tags.tagsinuse 510.348682 # Cycle average of tags in use 609system.cpu.icache.tags.total_refs 144679610 # Total number of references to valid blocks. 610system.cpu.icache.tags.sampled_refs 793772 # Sample count of references to valid blocks. 611system.cpu.icache.tags.avg_refs 182.268473 # Average number of references to valid blocks. 612system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit. 613system.cpu.icache.tags.occ_blocks::cpu.inst 510.348682 # Average occupied blocks per requestor 614system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy 615system.cpu.icache.tags.occ_percent::total 0.996775 # Average percentage of cache occupancy | 629system.cpu.icache.tags.replacements 793710 # number of replacements 630system.cpu.icache.tags.tagsinuse 510.347195 # Cycle average of tags in use 631system.cpu.icache.tags.total_refs 145088955 # Total number of references to valid blocks. 632system.cpu.icache.tags.sampled_refs 794222 # Sample count of references to valid blocks. 633system.cpu.icache.tags.avg_refs 182.680604 # Average number of references to valid blocks. 634system.cpu.icache.tags.warmup_cycle 161164789250 # Cycle when the warmup percentage was hit. 635system.cpu.icache.tags.occ_blocks::cpu.inst 510.347195 # Average occupied blocks per requestor 636system.cpu.icache.tags.occ_percent::cpu.inst 0.996772 # Average percentage of cache occupancy 637system.cpu.icache.tags.occ_percent::total 0.996772 # Average percentage of cache occupancy |
| 616system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 638system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 617system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 618system.cpu.icache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id 619system.cpu.icache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id 620system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id | 639system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 640system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 641system.cpu.icache.tags.age_task_id_blocks_1024::2 310 # Occupied blocks per task id 642system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id |
| 621system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 643system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 622system.cpu.icache.tags.tag_accesses 146267168 # Number of tag accesses 623system.cpu.icache.tags.data_accesses 146267168 # Number of data accesses 624system.cpu.icache.ReadReq_hits::cpu.inst 144679610 # number of ReadReq hits 625system.cpu.icache.ReadReq_hits::total 144679610 # number of ReadReq hits 626system.cpu.icache.demand_hits::cpu.inst 144679610 # number of demand (read+write) hits 627system.cpu.icache.demand_hits::total 144679610 # number of demand (read+write) hits 628system.cpu.icache.overall_hits::cpu.inst 144679610 # number of overall hits 629system.cpu.icache.overall_hits::total 144679610 # number of overall hits 630system.cpu.icache.ReadReq_misses::cpu.inst 793779 # number of ReadReq misses 631system.cpu.icache.ReadReq_misses::total 793779 # number of ReadReq misses 632system.cpu.icache.demand_misses::cpu.inst 793779 # number of demand (read+write) misses 633system.cpu.icache.demand_misses::total 793779 # number of demand (read+write) misses 634system.cpu.icache.overall_misses::cpu.inst 793779 # number of overall misses 635system.cpu.icache.overall_misses::total 793779 # number of overall misses 636system.cpu.icache.ReadReq_miss_latency::cpu.inst 11142507120 # number of ReadReq miss cycles 637system.cpu.icache.ReadReq_miss_latency::total 11142507120 # number of ReadReq miss cycles 638system.cpu.icache.demand_miss_latency::cpu.inst 11142507120 # number of demand (read+write) miss cycles 639system.cpu.icache.demand_miss_latency::total 11142507120 # number of demand (read+write) miss cycles 640system.cpu.icache.overall_miss_latency::cpu.inst 11142507120 # number of overall miss cycles 641system.cpu.icache.overall_miss_latency::total 11142507120 # number of overall miss cycles 642system.cpu.icache.ReadReq_accesses::cpu.inst 145473389 # number of ReadReq accesses(hits+misses) 643system.cpu.icache.ReadReq_accesses::total 145473389 # number of ReadReq accesses(hits+misses) 644system.cpu.icache.demand_accesses::cpu.inst 145473389 # number of demand (read+write) accesses 645system.cpu.icache.demand_accesses::total 145473389 # number of demand (read+write) accesses 646system.cpu.icache.overall_accesses::cpu.inst 145473389 # number of overall (read+write) accesses 647system.cpu.icache.overall_accesses::total 145473389 # number of overall (read+write) accesses 648system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005457 # miss rate for ReadReq accesses 649system.cpu.icache.ReadReq_miss_rate::total 0.005457 # miss rate for ReadReq accesses 650system.cpu.icache.demand_miss_rate::cpu.inst 0.005457 # miss rate for demand accesses 651system.cpu.icache.demand_miss_rate::total 0.005457 # miss rate for demand accesses 652system.cpu.icache.overall_miss_rate::cpu.inst 0.005457 # miss rate for overall accesses 653system.cpu.icache.overall_miss_rate::total 0.005457 # miss rate for overall accesses 654system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14037.291387 # average ReadReq miss latency 655system.cpu.icache.ReadReq_avg_miss_latency::total 14037.291387 # average ReadReq miss latency 656system.cpu.icache.demand_avg_miss_latency::cpu.inst 14037.291387 # average overall miss latency 657system.cpu.icache.demand_avg_miss_latency::total 14037.291387 # average overall miss latency 658system.cpu.icache.overall_avg_miss_latency::cpu.inst 14037.291387 # average overall miss latency 659system.cpu.icache.overall_avg_miss_latency::total 14037.291387 # average overall miss latency | 644system.cpu.icache.tags.tag_accesses 146677413 # Number of tag accesses 645system.cpu.icache.tags.data_accesses 146677413 # Number of data accesses 646system.cpu.icache.ReadReq_hits::cpu.inst 145088955 # number of ReadReq hits 647system.cpu.icache.ReadReq_hits::total 145088955 # number of ReadReq hits 648system.cpu.icache.demand_hits::cpu.inst 145088955 # number of demand (read+write) hits 649system.cpu.icache.demand_hits::total 145088955 # number of demand (read+write) hits 650system.cpu.icache.overall_hits::cpu.inst 145088955 # number of overall hits 651system.cpu.icache.overall_hits::total 145088955 # number of overall hits 652system.cpu.icache.ReadReq_misses::cpu.inst 794229 # number of ReadReq misses 653system.cpu.icache.ReadReq_misses::total 794229 # number of ReadReq misses 654system.cpu.icache.demand_misses::cpu.inst 794229 # number of demand (read+write) misses 655system.cpu.icache.demand_misses::total 794229 # number of demand (read+write) misses 656system.cpu.icache.overall_misses::cpu.inst 794229 # number of overall misses 657system.cpu.icache.overall_misses::total 794229 # number of overall misses 658system.cpu.icache.ReadReq_miss_latency::cpu.inst 11146745615 # number of ReadReq miss cycles 659system.cpu.icache.ReadReq_miss_latency::total 11146745615 # number of ReadReq miss cycles 660system.cpu.icache.demand_miss_latency::cpu.inst 11146745615 # number of demand (read+write) miss cycles 661system.cpu.icache.demand_miss_latency::total 11146745615 # number of demand (read+write) miss cycles 662system.cpu.icache.overall_miss_latency::cpu.inst 11146745615 # number of overall miss cycles 663system.cpu.icache.overall_miss_latency::total 11146745615 # number of overall miss cycles 664system.cpu.icache.ReadReq_accesses::cpu.inst 145883184 # number of ReadReq accesses(hits+misses) 665system.cpu.icache.ReadReq_accesses::total 145883184 # number of ReadReq accesses(hits+misses) 666system.cpu.icache.demand_accesses::cpu.inst 145883184 # number of demand (read+write) accesses 667system.cpu.icache.demand_accesses::total 145883184 # number of demand (read+write) accesses 668system.cpu.icache.overall_accesses::cpu.inst 145883184 # number of overall (read+write) accesses 669system.cpu.icache.overall_accesses::total 145883184 # number of overall (read+write) accesses 670system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005444 # miss rate for ReadReq accesses 671system.cpu.icache.ReadReq_miss_rate::total 0.005444 # miss rate for ReadReq accesses 672system.cpu.icache.demand_miss_rate::cpu.inst 0.005444 # miss rate for demand accesses 673system.cpu.icache.demand_miss_rate::total 0.005444 # miss rate for demand accesses 674system.cpu.icache.overall_miss_rate::cpu.inst 0.005444 # miss rate for overall accesses 675system.cpu.icache.overall_miss_rate::total 0.005444 # miss rate for overall accesses 676system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14034.674653 # average ReadReq miss latency 677system.cpu.icache.ReadReq_avg_miss_latency::total 14034.674653 # average ReadReq miss latency 678system.cpu.icache.demand_avg_miss_latency::cpu.inst 14034.674653 # average overall miss latency 679system.cpu.icache.demand_avg_miss_latency::total 14034.674653 # average overall miss latency 680system.cpu.icache.overall_avg_miss_latency::cpu.inst 14034.674653 # average overall miss latency 681system.cpu.icache.overall_avg_miss_latency::total 14034.674653 # average overall miss latency |
| 660system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 661system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 662system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 663system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 664system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 665system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 666system.cpu.icache.fast_writes 0 # number of fast writes performed 667system.cpu.icache.cache_copies 0 # number of cache copies performed | 682system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 683system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 684system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 685system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 686system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 687system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 688system.cpu.icache.fast_writes 0 # number of fast writes performed 689system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 668system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793779 # number of ReadReq MSHR misses 669system.cpu.icache.ReadReq_mshr_misses::total 793779 # number of ReadReq MSHR misses 670system.cpu.icache.demand_mshr_misses::cpu.inst 793779 # number of demand (read+write) MSHR misses 671system.cpu.icache.demand_mshr_misses::total 793779 # number of demand (read+write) MSHR misses 672system.cpu.icache.overall_mshr_misses::cpu.inst 793779 # number of overall MSHR misses 673system.cpu.icache.overall_mshr_misses::total 793779 # number of overall MSHR misses 674system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9550046380 # number of ReadReq MSHR miss cycles 675system.cpu.icache.ReadReq_mshr_miss_latency::total 9550046380 # number of ReadReq MSHR miss cycles 676system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9550046380 # number of demand (read+write) MSHR miss cycles 677system.cpu.icache.demand_mshr_miss_latency::total 9550046380 # number of demand (read+write) MSHR miss cycles 678system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9550046380 # number of overall MSHR miss cycles 679system.cpu.icache.overall_mshr_miss_latency::total 9550046380 # number of overall MSHR miss cycles 680system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for ReadReq accesses 681system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005457 # mshr miss rate for ReadReq accesses 682system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for demand accesses 683system.cpu.icache.demand_mshr_miss_rate::total 0.005457 # mshr miss rate for demand accesses 684system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for overall accesses 685system.cpu.icache.overall_mshr_miss_rate::total 0.005457 # mshr miss rate for overall accesses 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12031.114932 # average ReadReq mshr miss latency 687system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12031.114932 # average ReadReq mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12031.114932 # average overall mshr miss latency 689system.cpu.icache.demand_avg_mshr_miss_latency::total 12031.114932 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12031.114932 # average overall mshr miss latency 691system.cpu.icache.overall_avg_mshr_miss_latency::total 12031.114932 # average overall mshr miss latency | 690system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794229 # number of ReadReq MSHR misses 691system.cpu.icache.ReadReq_mshr_misses::total 794229 # number of ReadReq MSHR misses 692system.cpu.icache.demand_mshr_misses::cpu.inst 794229 # number of demand (read+write) MSHR misses 693system.cpu.icache.demand_mshr_misses::total 794229 # number of demand (read+write) MSHR misses 694system.cpu.icache.overall_mshr_misses::cpu.inst 794229 # number of overall MSHR misses 695system.cpu.icache.overall_mshr_misses::total 794229 # number of overall MSHR misses 696system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9553400385 # number of ReadReq MSHR miss cycles 697system.cpu.icache.ReadReq_mshr_miss_latency::total 9553400385 # number of ReadReq MSHR miss cycles 698system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9553400385 # number of demand (read+write) MSHR miss cycles 699system.cpu.icache.demand_mshr_miss_latency::total 9553400385 # number of demand (read+write) MSHR miss cycles 700system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9553400385 # number of overall MSHR miss cycles 701system.cpu.icache.overall_mshr_miss_latency::total 9553400385 # number of overall MSHR miss cycles 702system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for ReadReq accesses 703system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005444 # mshr miss rate for ReadReq accesses 704system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for demand accesses 705system.cpu.icache.demand_mshr_miss_rate::total 0.005444 # mshr miss rate for demand accesses 706system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for overall accesses 707system.cpu.icache.overall_mshr_miss_rate::total 0.005444 # mshr miss rate for overall accesses 708system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12028.521226 # average ReadReq mshr miss latency 709system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12028.521226 # average ReadReq mshr miss latency 710system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12028.521226 # average overall mshr miss latency 711system.cpu.icache.demand_avg_mshr_miss_latency::total 12028.521226 # average overall mshr miss latency 712system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12028.521226 # average overall mshr miss latency 713system.cpu.icache.overall_avg_mshr_miss_latency::total 12028.521226 # average overall mshr miss latency |
| 692system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 714system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 693system.cpu.itb_walker_cache.tags.replacements 3392 # number of replacements 694system.cpu.itb_walker_cache.tags.tagsinuse 3.080377 # Cycle average of tags in use 695system.cpu.itb_walker_cache.tags.total_refs 8023 # Total number of references to valid blocks. 696system.cpu.itb_walker_cache.tags.sampled_refs 3405 # Sample count of references to valid blocks. 697system.cpu.itb_walker_cache.tags.avg_refs 2.356241 # Average number of references to valid blocks. 698system.cpu.itb_walker_cache.tags.warmup_cycle 5161936228000 # Cycle when the warmup percentage was hit. 699system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.080377 # Average occupied blocks per requestor 700system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192524 # Average percentage of cache occupancy 701system.cpu.itb_walker_cache.tags.occ_percent::total 0.192524 # Average percentage of cache occupancy 702system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 703system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 704system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 705system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id | 715system.cpu.itb_walker_cache.tags.replacements 4028 # number of replacements 716system.cpu.itb_walker_cache.tags.tagsinuse 3.070596 # Cycle average of tags in use 717system.cpu.itb_walker_cache.tags.total_refs 7432 # Total number of references to valid blocks. 718system.cpu.itb_walker_cache.tags.sampled_refs 4039 # Sample count of references to valid blocks. 719system.cpu.itb_walker_cache.tags.avg_refs 1.840059 # Average number of references to valid blocks. 720system.cpu.itb_walker_cache.tags.warmup_cycle 5161717779000 # Cycle when the warmup percentage was hit. 721system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.070596 # Average occupied blocks per requestor 722system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191912 # Average percentage of cache occupancy 723system.cpu.itb_walker_cache.tags.occ_percent::total 0.191912 # Average percentage of cache occupancy 724system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id 725system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 726system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 727system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id |
| 706system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 728system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id |
| 707system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 708system.cpu.itb_walker_cache.tags.tag_accesses 28882 # Number of tag accesses 709system.cpu.itb_walker_cache.tags.data_accesses 28882 # Number of data accesses 710system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8043 # number of ReadReq hits 711system.cpu.itb_walker_cache.ReadReq_hits::total 8043 # number of ReadReq hits | 729system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id 730system.cpu.itb_walker_cache.tags.tag_accesses 29565 # Number of tag accesses 731system.cpu.itb_walker_cache.tags.data_accesses 29565 # Number of data accesses 732system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7435 # number of ReadReq hits 733system.cpu.itb_walker_cache.ReadReq_hits::total 7435 # number of ReadReq hits |
| 712system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 713system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 734system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 735system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 714system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8045 # number of demand (read+write) hits 715system.cpu.itb_walker_cache.demand_hits::total 8045 # number of demand (read+write) hits 716system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8045 # number of overall hits 717system.cpu.itb_walker_cache.overall_hits::total 8045 # number of overall hits 718system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4264 # number of ReadReq misses 719system.cpu.itb_walker_cache.ReadReq_misses::total 4264 # number of ReadReq misses 720system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4264 # number of demand (read+write) misses 721system.cpu.itb_walker_cache.demand_misses::total 4264 # number of demand (read+write) misses 722system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4264 # number of overall misses 723system.cpu.itb_walker_cache.overall_misses::total 4264 # number of overall misses 724system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 41583500 # number of ReadReq miss cycles 725system.cpu.itb_walker_cache.ReadReq_miss_latency::total 41583500 # number of ReadReq miss cycles 726system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 41583500 # number of demand (read+write) miss cycles 727system.cpu.itb_walker_cache.demand_miss_latency::total 41583500 # number of demand (read+write) miss cycles 728system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 41583500 # number of overall miss cycles 729system.cpu.itb_walker_cache.overall_miss_latency::total 41583500 # number of overall miss cycles 730system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12307 # number of ReadReq accesses(hits+misses) 731system.cpu.itb_walker_cache.ReadReq_accesses::total 12307 # number of ReadReq accesses(hits+misses) | 736system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7437 # number of demand (read+write) hits 737system.cpu.itb_walker_cache.demand_hits::total 7437 # number of demand (read+write) hits 738system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7437 # number of overall hits 739system.cpu.itb_walker_cache.overall_hits::total 7437 # number of overall hits 740system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4897 # number of ReadReq misses 741system.cpu.itb_walker_cache.ReadReq_misses::total 4897 # number of ReadReq misses 742system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4897 # number of demand (read+write) misses 743system.cpu.itb_walker_cache.demand_misses::total 4897 # number of demand (read+write) misses 744system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4897 # number of overall misses 745system.cpu.itb_walker_cache.overall_misses::total 4897 # number of overall misses 746system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48969750 # number of ReadReq miss cycles 747system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48969750 # number of ReadReq miss cycles 748system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48969750 # number of demand (read+write) miss cycles 749system.cpu.itb_walker_cache.demand_miss_latency::total 48969750 # number of demand (read+write) miss cycles 750system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48969750 # number of overall miss cycles 751system.cpu.itb_walker_cache.overall_miss_latency::total 48969750 # number of overall miss cycles 752system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12332 # number of ReadReq accesses(hits+misses) 753system.cpu.itb_walker_cache.ReadReq_accesses::total 12332 # number of ReadReq accesses(hits+misses) |
| 732system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 733system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 754system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 755system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 734system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12309 # number of demand (read+write) accesses 735system.cpu.itb_walker_cache.demand_accesses::total 12309 # number of demand (read+write) accesses 736system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12309 # number of overall (read+write) accesses 737system.cpu.itb_walker_cache.overall_accesses::total 12309 # number of overall (read+write) accesses 738system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.346469 # miss rate for ReadReq accesses 739system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.346469 # miss rate for ReadReq accesses 740system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.346413 # miss rate for demand accesses 741system.cpu.itb_walker_cache.demand_miss_rate::total 0.346413 # miss rate for demand accesses 742system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.346413 # miss rate for overall accesses 743system.cpu.itb_walker_cache.overall_miss_rate::total 0.346413 # miss rate for overall accesses 744system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9752.227955 # average ReadReq miss latency 745system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9752.227955 # average ReadReq miss latency 746system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9752.227955 # average overall miss latency 747system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9752.227955 # average overall miss latency 748system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9752.227955 # average overall miss latency 749system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9752.227955 # average overall miss latency | 756system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12334 # number of demand (read+write) accesses 757system.cpu.itb_walker_cache.demand_accesses::total 12334 # number of demand (read+write) accesses 758system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12334 # number of overall (read+write) accesses 759system.cpu.itb_walker_cache.overall_accesses::total 12334 # number of overall (read+write) accesses 760system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.397097 # miss rate for ReadReq accesses 761system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.397097 # miss rate for ReadReq accesses 762system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.397033 # miss rate for demand accesses 763system.cpu.itb_walker_cache.demand_miss_rate::total 0.397033 # miss rate for demand accesses 764system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.397033 # miss rate for overall accesses 765system.cpu.itb_walker_cache.overall_miss_rate::total 0.397033 # miss rate for overall accesses 766system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9999.948948 # average ReadReq miss latency 767system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9999.948948 # average ReadReq miss latency 768system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9999.948948 # average overall miss latency 769system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9999.948948 # average overall miss latency 770system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9999.948948 # average overall miss latency 771system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9999.948948 # average overall miss latency |
| 750system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 751system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 752system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 753system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 754system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 755system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 756system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 757system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 772system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 773system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 774system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 775system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 776system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 777system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 778system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 779system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 758system.cpu.itb_walker_cache.writebacks::writebacks 713 # number of writebacks 759system.cpu.itb_walker_cache.writebacks::total 713 # number of writebacks 760system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4264 # number of ReadReq MSHR misses 761system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4264 # number of ReadReq MSHR misses 762system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4264 # number of demand (read+write) MSHR misses 763system.cpu.itb_walker_cache.demand_mshr_misses::total 4264 # number of demand (read+write) MSHR misses 764system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4264 # number of overall MSHR misses 765system.cpu.itb_walker_cache.overall_mshr_misses::total 4264 # number of overall MSHR misses 766system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33053500 # number of ReadReq MSHR miss cycles 767system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33053500 # number of ReadReq MSHR miss cycles 768system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33053500 # number of demand (read+write) MSHR miss cycles 769system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33053500 # number of demand (read+write) MSHR miss cycles 770system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33053500 # number of overall MSHR miss cycles 771system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33053500 # number of overall MSHR miss cycles 772system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.346469 # mshr miss rate for ReadReq accesses 773system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.346469 # mshr miss rate for ReadReq accesses 774system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.346413 # mshr miss rate for demand accesses 775system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.346413 # mshr miss rate for demand accesses 776system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.346413 # mshr miss rate for overall accesses 777system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.346413 # mshr miss rate for overall accesses 778system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7751.758912 # average ReadReq mshr miss latency 779system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7751.758912 # average ReadReq mshr miss latency 780system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7751.758912 # average overall mshr miss latency 781system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7751.758912 # average overall mshr miss latency 782system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7751.758912 # average overall mshr miss latency 783system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7751.758912 # average overall mshr miss latency | 780system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks 781system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks 782system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4897 # number of ReadReq MSHR misses 783system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4897 # number of ReadReq MSHR misses 784system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4897 # number of demand (read+write) MSHR misses 785system.cpu.itb_walker_cache.demand_mshr_misses::total 4897 # number of demand (read+write) MSHR misses 786system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4897 # number of overall MSHR misses 787system.cpu.itb_walker_cache.overall_mshr_misses::total 4897 # number of overall MSHR misses 788system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39174250 # number of ReadReq MSHR miss cycles 789system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39174250 # number of ReadReq MSHR miss cycles 790system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39174250 # number of demand (read+write) MSHR miss cycles 791system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39174250 # number of demand (read+write) MSHR miss cycles 792system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39174250 # number of overall MSHR miss cycles 793system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39174250 # number of overall MSHR miss cycles 794system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.397097 # mshr miss rate for ReadReq accesses 795system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.397097 # mshr miss rate for ReadReq accesses 796system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.397033 # mshr miss rate for demand accesses 797system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.397033 # mshr miss rate for demand accesses 798system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.397033 # mshr miss rate for overall accesses 799system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.397033 # mshr miss rate for overall accesses 800system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average ReadReq mshr miss latency 801system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7999.642638 # average ReadReq mshr miss latency 802system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average overall mshr miss latency 803system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7999.642638 # average overall mshr miss latency 804system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7999.642638 # average overall mshr miss latency 805system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7999.642638 # average overall mshr miss latency |
| 784system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 806system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 785system.cpu.l2cache.tags.replacements 87367 # number of replacements 786system.cpu.l2cache.tags.tagsinuse 64711.001958 # Cycle average of tags in use 787system.cpu.l2cache.tags.total_refs 3492751 # Total number of references to valid blocks. 788system.cpu.l2cache.tags.sampled_refs 152091 # Sample count of references to valid blocks. 789system.cpu.l2cache.tags.avg_refs 22.964876 # Average number of references to valid blocks. | 807system.cpu.l2cache.tags.replacements 87241 # number of replacements 808system.cpu.l2cache.tags.tagsinuse 64748.665455 # Cycle average of tags in use 809system.cpu.l2cache.tags.total_refs 3494859 # Total number of references to valid blocks. 810system.cpu.l2cache.tags.sampled_refs 151936 # Sample count of references to valid blocks. 811system.cpu.l2cache.tags.avg_refs 23.002179 # Average number of references to valid blocks. |
| 790system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 812system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 791system.cpu.l2cache.tags.occ_blocks::writebacks 50199.140845 # Average occupied blocks per requestor 792system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.014318 # Average occupied blocks per requestor 793system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141821 # Average occupied blocks per requestor 794system.cpu.l2cache.tags.occ_blocks::cpu.inst 3238.410068 # Average occupied blocks per requestor 795system.cpu.l2cache.tags.occ_blocks::cpu.data 11273.294906 # Average occupied blocks per requestor 796system.cpu.l2cache.tags.occ_percent::writebacks 0.765978 # Average percentage of cache occupancy | 813system.cpu.l2cache.tags.occ_blocks::writebacks 50323.834449 # Average occupied blocks per requestor 814system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006391 # Average occupied blocks per requestor 815system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141287 # Average occupied blocks per requestor 816system.cpu.l2cache.tags.occ_blocks::cpu.inst 3224.989333 # Average occupied blocks per requestor 817system.cpu.l2cache.tags.occ_blocks::cpu.data 11199.693995 # Average occupied blocks per requestor 818system.cpu.l2cache.tags.occ_percent::writebacks 0.767881 # Average percentage of cache occupancy |
| 797system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 819system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 820system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 799system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049414 # Average percentage of cache occupancy 800system.cpu.l2cache.tags.occ_percent::cpu.data 0.172017 # Average percentage of cache occupancy 801system.cpu.l2cache.tags.occ_percent::total 0.987412 # Average percentage of cache occupancy 802system.cpu.l2cache.tags.occ_task_id_blocks::1024 64724 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 805system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2777 # Occupied blocks per task id 806system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4943 # Occupied blocks per task id 807system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56808 # Occupied blocks per task id 808system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id 809system.cpu.l2cache.tags.tag_accesses 32220272 # Number of tag accesses 810system.cpu.l2cache.tags.data_accesses 32220272 # Number of data accesses 811system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6177 # number of ReadReq hits 812system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2685 # number of ReadReq hits 813system.cpu.l2cache.ReadReq_hits::cpu.inst 780836 # number of ReadReq hits 814system.cpu.l2cache.ReadReq_hits::cpu.data 1279767 # number of ReadReq hits 815system.cpu.l2cache.ReadReq_hits::total 2069465 # number of ReadReq hits 816system.cpu.l2cache.Writeback_hits::writebacks 1542614 # number of Writeback hits 817system.cpu.l2cache.Writeback_hits::total 1542614 # number of Writeback hits 818system.cpu.l2cache.UpgradeReq_hits::cpu.data 313 # number of UpgradeReq hits 819system.cpu.l2cache.UpgradeReq_hits::total 313 # number of UpgradeReq hits 820system.cpu.l2cache.ReadExReq_hits::cpu.data 200061 # number of ReadExReq hits 821system.cpu.l2cache.ReadExReq_hits::total 200061 # number of ReadExReq hits 822system.cpu.l2cache.demand_hits::cpu.dtb.walker 6177 # number of demand (read+write) hits 823system.cpu.l2cache.demand_hits::cpu.itb.walker 2685 # number of demand (read+write) hits 824system.cpu.l2cache.demand_hits::cpu.inst 780836 # number of demand (read+write) hits 825system.cpu.l2cache.demand_hits::cpu.data 1479828 # number of demand (read+write) hits 826system.cpu.l2cache.demand_hits::total 2269526 # number of demand (read+write) hits 827system.cpu.l2cache.overall_hits::cpu.dtb.walker 6177 # number of overall hits 828system.cpu.l2cache.overall_hits::cpu.itb.walker 2685 # number of overall hits 829system.cpu.l2cache.overall_hits::cpu.inst 780836 # number of overall hits 830system.cpu.l2cache.overall_hits::cpu.data 1479828 # number of overall hits 831system.cpu.l2cache.overall_hits::total 2269526 # number of overall hits 832system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses | 821system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049209 # Average percentage of cache occupancy 822system.cpu.l2cache.tags.occ_percent::cpu.data 0.170894 # Average percentage of cache occupancy 823system.cpu.l2cache.tags.occ_percent::total 0.987986 # Average percentage of cache occupancy 824system.cpu.l2cache.tags.occ_task_id_blocks::1024 64695 # Occupied blocks per task id 825system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id 826system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 827system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3016 # Occupied blocks per task id 828system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5015 # Occupied blocks per task id 829system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56538 # Occupied blocks per task id 830system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987167 # Percentage of cache occupancy per task id 831system.cpu.l2cache.tags.tag_accesses 32251607 # Number of tag accesses 832system.cpu.l2cache.tags.data_accesses 32251607 # Number of data accesses 833system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6647 # number of ReadReq hits 834system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3226 # number of ReadReq hits 835system.cpu.l2cache.ReadReq_hits::cpu.inst 781266 # number of ReadReq hits 836system.cpu.l2cache.ReadReq_hits::cpu.data 1280034 # number of ReadReq hits 837system.cpu.l2cache.ReadReq_hits::total 2071173 # number of ReadReq hits 838system.cpu.l2cache.Writeback_hits::writebacks 1543797 # number of Writeback hits 839system.cpu.l2cache.Writeback_hits::total 1543797 # number of Writeback hits 840system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits 841system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits 842system.cpu.l2cache.ReadExReq_hits::cpu.data 201020 # number of ReadExReq hits 843system.cpu.l2cache.ReadExReq_hits::total 201020 # number of ReadExReq hits 844system.cpu.l2cache.demand_hits::cpu.dtb.walker 6647 # number of demand (read+write) hits 845system.cpu.l2cache.demand_hits::cpu.itb.walker 3226 # number of demand (read+write) hits 846system.cpu.l2cache.demand_hits::cpu.inst 781266 # number of demand (read+write) hits 847system.cpu.l2cache.demand_hits::cpu.data 1481054 # number of demand (read+write) hits 848system.cpu.l2cache.demand_hits::total 2272193 # number of demand (read+write) hits 849system.cpu.l2cache.overall_hits::cpu.dtb.walker 6647 # number of overall hits 850system.cpu.l2cache.overall_hits::cpu.itb.walker 3226 # number of overall hits 851system.cpu.l2cache.overall_hits::cpu.inst 781266 # number of overall hits 852system.cpu.l2cache.overall_hits::cpu.data 1481054 # number of overall hits 853system.cpu.l2cache.overall_hits::total 2272193 # number of overall hits 854system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses |
| 833system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses | 855system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses |
| 834system.cpu.l2cache.ReadReq_misses::cpu.inst 12930 # number of ReadReq misses 835system.cpu.l2cache.ReadReq_misses::cpu.data 28590 # number of ReadReq misses 836system.cpu.l2cache.ReadReq_misses::total 41527 # number of ReadReq misses 837system.cpu.l2cache.UpgradeReq_misses::cpu.data 1330 # number of UpgradeReq misses 838system.cpu.l2cache.UpgradeReq_misses::total 1330 # number of UpgradeReq misses 839system.cpu.l2cache.ReadExReq_misses::cpu.data 113574 # number of ReadExReq misses 840system.cpu.l2cache.ReadExReq_misses::total 113574 # number of ReadExReq misses 841system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses | 856system.cpu.l2cache.ReadReq_misses::cpu.inst 12950 # number of ReadReq misses 857system.cpu.l2cache.ReadReq_misses::cpu.data 28613 # number of ReadReq misses 858system.cpu.l2cache.ReadReq_misses::total 41569 # number of ReadReq misses 859system.cpu.l2cache.UpgradeReq_misses::cpu.data 1320 # number of UpgradeReq misses 860system.cpu.l2cache.UpgradeReq_misses::total 1320 # number of UpgradeReq misses 861system.cpu.l2cache.ReadExReq_misses::cpu.data 113503 # number of ReadExReq misses 862system.cpu.l2cache.ReadExReq_misses::total 113503 # number of ReadExReq misses 863system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses |
| 842system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses | 864system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses |
| 843system.cpu.l2cache.demand_misses::cpu.inst 12930 # number of demand (read+write) misses 844system.cpu.l2cache.demand_misses::cpu.data 142164 # number of demand (read+write) misses 845system.cpu.l2cache.demand_misses::total 155101 # number of demand (read+write) misses 846system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses | 865system.cpu.l2cache.demand_misses::cpu.inst 12950 # number of demand (read+write) misses 866system.cpu.l2cache.demand_misses::cpu.data 142116 # number of demand (read+write) misses 867system.cpu.l2cache.demand_misses::total 155072 # number of demand (read+write) misses 868system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses |
| 847system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses | 869system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses |
| 848system.cpu.l2cache.overall_misses::cpu.inst 12930 # number of overall misses 849system.cpu.l2cache.overall_misses::cpu.data 142164 # number of overall misses 850system.cpu.l2cache.overall_misses::total 155101 # number of overall misses 851system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 136250 # number of ReadReq miss cycles 852system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 365000 # number of ReadReq miss cycles 853system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 947782000 # number of ReadReq miss cycles 854system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2166641250 # number of ReadReq miss cycles 855system.cpu.l2cache.ReadReq_miss_latency::total 3114924500 # number of ReadReq miss cycles 856system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16195366 # number of UpgradeReq miss cycles 857system.cpu.l2cache.UpgradeReq_miss_latency::total 16195366 # number of UpgradeReq miss cycles 858system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7892320723 # number of ReadExReq miss cycles 859system.cpu.l2cache.ReadExReq_miss_latency::total 7892320723 # number of ReadExReq miss cycles 860system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 136250 # number of demand (read+write) miss cycles 861system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 365000 # number of demand (read+write) miss cycles 862system.cpu.l2cache.demand_miss_latency::cpu.inst 947782000 # number of demand (read+write) miss cycles 863system.cpu.l2cache.demand_miss_latency::cpu.data 10058961973 # number of demand (read+write) miss cycles 864system.cpu.l2cache.demand_miss_latency::total 11007245223 # number of demand (read+write) miss cycles 865system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 136250 # number of overall miss cycles 866system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 365000 # number of overall miss cycles 867system.cpu.l2cache.overall_miss_latency::cpu.inst 947782000 # number of overall miss cycles 868system.cpu.l2cache.overall_miss_latency::cpu.data 10058961973 # number of overall miss cycles 869system.cpu.l2cache.overall_miss_latency::total 11007245223 # number of overall miss cycles 870system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6179 # number of ReadReq accesses(hits+misses) 871system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2690 # number of ReadReq accesses(hits+misses) 872system.cpu.l2cache.ReadReq_accesses::cpu.inst 793766 # number of ReadReq accesses(hits+misses) 873system.cpu.l2cache.ReadReq_accesses::cpu.data 1308357 # number of ReadReq accesses(hits+misses) 874system.cpu.l2cache.ReadReq_accesses::total 2110992 # number of ReadReq accesses(hits+misses) 875system.cpu.l2cache.Writeback_accesses::writebacks 1542614 # number of Writeback accesses(hits+misses) 876system.cpu.l2cache.Writeback_accesses::total 1542614 # number of Writeback accesses(hits+misses) 877system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1643 # number of UpgradeReq accesses(hits+misses) 878system.cpu.l2cache.UpgradeReq_accesses::total 1643 # number of UpgradeReq accesses(hits+misses) 879system.cpu.l2cache.ReadExReq_accesses::cpu.data 313635 # number of ReadExReq accesses(hits+misses) 880system.cpu.l2cache.ReadExReq_accesses::total 313635 # number of ReadExReq accesses(hits+misses) 881system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6179 # number of demand (read+write) accesses 882system.cpu.l2cache.demand_accesses::cpu.itb.walker 2690 # number of demand (read+write) accesses 883system.cpu.l2cache.demand_accesses::cpu.inst 793766 # number of demand (read+write) accesses 884system.cpu.l2cache.demand_accesses::cpu.data 1621992 # number of demand (read+write) accesses 885system.cpu.l2cache.demand_accesses::total 2424627 # number of demand (read+write) accesses 886system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6179 # number of overall (read+write) accesses 887system.cpu.l2cache.overall_accesses::cpu.itb.walker 2690 # number of overall (read+write) accesses 888system.cpu.l2cache.overall_accesses::cpu.inst 793766 # number of overall (read+write) accesses 889system.cpu.l2cache.overall_accesses::cpu.data 1621992 # number of overall (read+write) accesses 890system.cpu.l2cache.overall_accesses::total 2424627 # number of overall (read+write) accesses 891system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000324 # miss rate for ReadReq accesses 892system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001859 # miss rate for ReadReq accesses 893system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016289 # miss rate for ReadReq accesses 894system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021852 # miss rate for ReadReq accesses 895system.cpu.l2cache.ReadReq_miss_rate::total 0.019672 # miss rate for ReadReq accesses 896system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.809495 # miss rate for UpgradeReq accesses 897system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809495 # miss rate for UpgradeReq accesses 898system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362122 # miss rate for ReadExReq accesses 899system.cpu.l2cache.ReadExReq_miss_rate::total 0.362122 # miss rate for ReadExReq accesses 900system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000324 # miss rate for demand accesses 901system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001859 # miss rate for demand accesses 902system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016289 # miss rate for demand accesses 903system.cpu.l2cache.demand_miss_rate::cpu.data 0.087648 # miss rate for demand accesses 904system.cpu.l2cache.demand_miss_rate::total 0.063969 # miss rate for demand accesses 905system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000324 # miss rate for overall accesses 906system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001859 # miss rate for overall accesses 907system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016289 # miss rate for overall accesses 908system.cpu.l2cache.overall_miss_rate::cpu.data 0.087648 # miss rate for overall accesses 909system.cpu.l2cache.overall_miss_rate::total 0.063969 # miss rate for overall accesses 910system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68125 # average ReadReq miss latency 911system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 73000 # average ReadReq miss latency 912system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73301.005414 # average ReadReq miss latency 913system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75783.184680 # average ReadReq miss latency 914system.cpu.l2cache.ReadReq_avg_miss_latency::total 75009.620247 # average ReadReq miss latency 915system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12176.966917 # average UpgradeReq miss latency 916system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12176.966917 # average UpgradeReq miss latency 917system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69490.558781 # average ReadExReq miss latency 918system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69490.558781 # average ReadExReq miss latency 919system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68125 # average overall miss latency 920system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency 921system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73301.005414 # average overall miss latency 922system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70756.042127 # average overall miss latency 923system.cpu.l2cache.demand_avg_miss_latency::total 70968.241488 # average overall miss latency 924system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68125 # average overall miss latency 925system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency 926system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73301.005414 # average overall miss latency 927system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70756.042127 # average overall miss latency 928system.cpu.l2cache.overall_avg_miss_latency::total 70968.241488 # average overall miss latency | 870system.cpu.l2cache.overall_misses::cpu.inst 12950 # number of overall misses 871system.cpu.l2cache.overall_misses::cpu.data 142116 # number of overall misses 872system.cpu.l2cache.overall_misses::total 155072 # number of overall misses 873system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles 874system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 350750 # number of ReadReq miss cycles 875system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 946380250 # number of ReadReq miss cycles 876system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2143813000 # number of ReadReq miss cycles 877system.cpu.l2cache.ReadReq_miss_latency::total 3090633250 # number of ReadReq miss cycles 878system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15722387 # number of UpgradeReq miss cycles 879system.cpu.l2cache.UpgradeReq_miss_latency::total 15722387 # number of UpgradeReq miss cycles 880system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7833269720 # number of ReadExReq miss cycles 881system.cpu.l2cache.ReadExReq_miss_latency::total 7833269720 # number of ReadExReq miss cycles 882system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles 883system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 350750 # number of demand (read+write) miss cycles 884system.cpu.l2cache.demand_miss_latency::cpu.inst 946380250 # number of demand (read+write) miss cycles 885system.cpu.l2cache.demand_miss_latency::cpu.data 9977082720 # number of demand (read+write) miss cycles 886system.cpu.l2cache.demand_miss_latency::total 10923902970 # number of demand (read+write) miss cycles 887system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles 888system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 350750 # number of overall miss cycles 889system.cpu.l2cache.overall_miss_latency::cpu.inst 946380250 # number of overall miss cycles 890system.cpu.l2cache.overall_miss_latency::cpu.data 9977082720 # number of overall miss cycles 891system.cpu.l2cache.overall_miss_latency::total 10923902970 # number of overall miss cycles 892system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6648 # number of ReadReq accesses(hits+misses) 893system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3231 # number of ReadReq accesses(hits+misses) 894system.cpu.l2cache.ReadReq_accesses::cpu.inst 794216 # number of ReadReq accesses(hits+misses) 895system.cpu.l2cache.ReadReq_accesses::cpu.data 1308647 # number of ReadReq accesses(hits+misses) 896system.cpu.l2cache.ReadReq_accesses::total 2112742 # number of ReadReq accesses(hits+misses) 897system.cpu.l2cache.Writeback_accesses::writebacks 1543797 # number of Writeback accesses(hits+misses) 898system.cpu.l2cache.Writeback_accesses::total 1543797 # number of Writeback accesses(hits+misses) 899system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1634 # number of UpgradeReq accesses(hits+misses) 900system.cpu.l2cache.UpgradeReq_accesses::total 1634 # number of UpgradeReq accesses(hits+misses) 901system.cpu.l2cache.ReadExReq_accesses::cpu.data 314523 # number of ReadExReq accesses(hits+misses) 902system.cpu.l2cache.ReadExReq_accesses::total 314523 # number of ReadExReq accesses(hits+misses) 903system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6648 # number of demand (read+write) accesses 904system.cpu.l2cache.demand_accesses::cpu.itb.walker 3231 # number of demand (read+write) accesses 905system.cpu.l2cache.demand_accesses::cpu.inst 794216 # number of demand (read+write) accesses 906system.cpu.l2cache.demand_accesses::cpu.data 1623170 # number of demand (read+write) accesses 907system.cpu.l2cache.demand_accesses::total 2427265 # number of demand (read+write) accesses 908system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6648 # number of overall (read+write) accesses 909system.cpu.l2cache.overall_accesses::cpu.itb.walker 3231 # number of overall (read+write) accesses 910system.cpu.l2cache.overall_accesses::cpu.inst 794216 # number of overall (read+write) accesses 911system.cpu.l2cache.overall_accesses::cpu.data 1623170 # number of overall (read+write) accesses 912system.cpu.l2cache.overall_accesses::total 2427265 # number of overall (read+write) accesses 913system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadReq accesses 914system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001548 # miss rate for ReadReq accesses 915system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016305 # miss rate for ReadReq accesses 916system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021865 # miss rate for ReadReq accesses 917system.cpu.l2cache.ReadReq_miss_rate::total 0.019675 # miss rate for ReadReq accesses 918system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807834 # miss rate for UpgradeReq accesses 919system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807834 # miss rate for UpgradeReq accesses 920system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360873 # miss rate for ReadExReq accesses 921system.cpu.l2cache.ReadExReq_miss_rate::total 0.360873 # miss rate for ReadExReq accesses 922system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses 923system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001548 # miss rate for demand accesses 924system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016305 # miss rate for demand accesses 925system.cpu.l2cache.demand_miss_rate::cpu.data 0.087555 # miss rate for demand accesses 926system.cpu.l2cache.demand_miss_rate::total 0.063888 # miss rate for demand accesses 927system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses 928system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001548 # miss rate for overall accesses 929system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016305 # miss rate for overall accesses 930system.cpu.l2cache.overall_miss_rate::cpu.data 0.087555 # miss rate for overall accesses 931system.cpu.l2cache.overall_miss_rate::total 0.063888 # miss rate for overall accesses 932system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency 933system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 70150 # average ReadReq miss latency 934system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73079.555985 # average ReadReq miss latency 935system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74924.439940 # average ReadReq miss latency 936system.cpu.l2cache.ReadReq_avg_miss_latency::total 74349.473165 # average ReadReq miss latency 937system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11910.899242 # average UpgradeReq miss latency 938system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11910.899242 # average UpgradeReq miss latency 939system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69013.768094 # average ReadExReq miss latency 940system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69013.768094 # average ReadExReq miss latency 941system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 942system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency 943system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73079.555985 # average overall miss latency 944system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70203.796335 # average overall miss latency 945system.cpu.l2cache.demand_avg_miss_latency::total 70444.070948 # average overall miss latency 946system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 947system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency 948system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73079.555985 # average overall miss latency 949system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70203.796335 # average overall miss latency 950system.cpu.l2cache.overall_avg_miss_latency::total 70444.070948 # average overall miss latency |
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| 937system.cpu.l2cache.writebacks::writebacks 80489 # number of writebacks 938system.cpu.l2cache.writebacks::total 80489 # number of writebacks 939system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2 # number of ReadReq MSHR misses | 959system.cpu.l2cache.writebacks::writebacks 80277 # number of writebacks 960system.cpu.l2cache.writebacks::total 80277 # number of writebacks 961system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses |
| 940system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses | 962system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses |
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| 949system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses | 971system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses |
| 950system.cpu.l2cache.demand_mshr_misses::cpu.inst 12930 # number of demand (read+write) MSHR misses 951system.cpu.l2cache.demand_mshr_misses::cpu.data 142164 # number of demand (read+write) MSHR misses 952system.cpu.l2cache.demand_mshr_misses::total 155101 # number of demand (read+write) MSHR misses 953system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2 # number of overall MSHR misses | 972system.cpu.l2cache.demand_mshr_misses::cpu.inst 12950 # number of demand (read+write) MSHR misses 973system.cpu.l2cache.demand_mshr_misses::cpu.data 142116 # number of demand (read+write) MSHR misses 974system.cpu.l2cache.demand_mshr_misses::total 155072 # number of demand (read+write) MSHR misses 975system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses |
| 954system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses | 976system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses |
| 955system.cpu.l2cache.overall_mshr_misses::cpu.inst 12930 # number of overall MSHR misses 956system.cpu.l2cache.overall_mshr_misses::cpu.data 142164 # number of overall MSHR misses 957system.cpu.l2cache.overall_mshr_misses::total 155101 # number of overall MSHR misses 958system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 111250 # number of ReadReq MSHR miss cycles 959system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301500 # number of ReadReq MSHR miss cycles 960system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 785787500 # number of ReadReq MSHR miss cycles 961system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1808339250 # number of ReadReq MSHR miss cycles 962system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2594539500 # number of ReadReq MSHR miss cycles 963system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14221312 # number of UpgradeReq MSHR miss cycles 964system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14221312 # number of UpgradeReq MSHR miss cycles 965system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6472690277 # number of ReadExReq MSHR miss cycles 966system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6472690277 # number of ReadExReq MSHR miss cycles 967system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 111250 # number of demand (read+write) MSHR miss cycles 968system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301500 # number of demand (read+write) MSHR miss cycles 969system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 785787500 # number of demand (read+write) MSHR miss cycles 970system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8281029527 # number of demand (read+write) MSHR miss cycles 971system.cpu.l2cache.demand_mshr_miss_latency::total 9067229777 # number of demand (read+write) MSHR miss cycles 972system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 111250 # number of overall MSHR miss cycles 973system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles 974system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 785787500 # number of overall MSHR miss cycles 975system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8281029527 # number of overall MSHR miss cycles 976system.cpu.l2cache.overall_mshr_miss_latency::total 9067229777 # number of overall MSHR miss cycles 977system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86680074500 # number of ReadReq MSHR uncacheable cycles 978system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86680074500 # number of ReadReq MSHR uncacheable cycles 979system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2394785000 # number of WriteReq MSHR uncacheable cycles 980system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2394785000 # number of WriteReq MSHR uncacheable cycles 981system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89074859500 # number of overall MSHR uncacheable cycles 982system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89074859500 # number of overall MSHR uncacheable cycles 983system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for ReadReq accesses 984system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001859 # mshr miss rate for ReadReq accesses 985system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016289 # mshr miss rate for ReadReq accesses 986system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021852 # mshr miss rate for ReadReq accesses 987system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019672 # mshr miss rate for ReadReq accesses 988system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809495 # mshr miss rate for UpgradeReq accesses 989system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809495 # mshr miss rate for UpgradeReq accesses 990system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362122 # mshr miss rate for ReadExReq accesses 991system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362122 # mshr miss rate for ReadExReq accesses 992system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000324 # mshr miss rate for demand accesses 993system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001859 # 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average ReadReq mshr miss latency 1004system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60772.428461 # average ReadReq mshr miss latency 1005system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63250.760756 # average ReadReq mshr miss latency 1006system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62478.375515 # average ReadReq mshr miss latency 1007system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10692.715789 # average UpgradeReq mshr miss latency 1008system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10692.715789 # average UpgradeReq mshr miss latency 1009system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56990.951072 # average ReadExReq mshr miss latency 1010system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56990.951072 # average ReadExReq mshr miss latency 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency 1012system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency 1013system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60772.428461 # average overall mshr miss latency 1014system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58249.834888 # average overall mshr miss latency 1015system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58460.163229 # average overall mshr miss latency 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency 1017system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency 1018system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60772.428461 # average overall mshr miss latency 1019system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58249.834888 # average overall mshr miss latency 1020system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58460.163229 # average overall mshr miss latency | 977system.cpu.l2cache.overall_mshr_misses::cpu.inst 12950 # number of overall MSHR misses 978system.cpu.l2cache.overall_mshr_misses::cpu.data 142116 # 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number of ReadExReq MSHR miss cycles 989system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles 990system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles 991system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 784145750 # number of demand (read+write) MSHR miss cycles 992system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8200092280 # number of demand (read+write) MSHR miss cycles 993system.cpu.l2cache.demand_mshr_miss_latency::total 8984602030 # number of demand (read+write) MSHR miss cycles 994system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles 995system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles 996system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 784145750 # number of overall MSHR miss cycles 997system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8200092280 # number of overall MSHR miss cycles 998system.cpu.l2cache.overall_mshr_miss_latency::total 8984602030 # number of overall MSHR miss cycles 999system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86686810500 # number of ReadReq MSHR uncacheable cycles 1000system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86686810500 # number of ReadReq MSHR uncacheable cycles 1001system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284000 # number of WriteReq MSHR uncacheable cycles 1002system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284000 # number of WriteReq MSHR uncacheable cycles 1003system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088094500 # number of overall MSHR uncacheable cycles 1004system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088094500 # number of overall MSHR uncacheable cycles 1005system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for ReadReq accesses 1006system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for ReadReq accesses 1007system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for ReadReq accesses 1008system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021865 # mshr miss rate for ReadReq accesses 1009system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019675 # mshr miss rate for ReadReq accesses 1010system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807834 # mshr miss rate for UpgradeReq accesses 1011system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807834 # mshr miss rate for UpgradeReq accesses 1012system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360873 # mshr miss rate for ReadExReq accesses 1013system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360873 # mshr miss rate for ReadExReq accesses 1014system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for demand accesses 1015system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for demand accesses 1016system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for demand accesses 1017system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087555 # mshr miss rate for demand accesses 1018system.cpu.l2cache.demand_mshr_miss_rate::total 0.063888 # mshr miss rate for demand accesses 1019system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000150 # mshr miss rate for overall accesses 1020system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001548 # mshr miss rate for overall accesses 1021system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016305 # mshr miss rate for overall accesses 1022system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087555 # mshr miss rate for overall accesses 1023system.cpu.l2cache.overall_mshr_miss_rate::total 0.063888 # mshr miss rate for overall accesses 1024system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency 1025system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency 1026system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60551.795367 # average ReadReq mshr miss latency 1027system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62403.854891 # average ReadReq mshr miss latency 1028system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61826.631625 # average ReadReq mshr miss latency 1029system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10702.122727 # average UpgradeReq mshr miss latency 1030system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10702.122727 # average UpgradeReq mshr miss latency 1031system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56514.195924 # average ReadExReq mshr miss latency 1032system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56514.195924 # average ReadExReq mshr miss latency 1033system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1034system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency 1035system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60551.795367 # average overall mshr miss latency 1036system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57699.993526 # average overall mshr miss latency 1037system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57938.261130 # average overall mshr miss latency 1038system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1039system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency 1040system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60551.795367 # average overall mshr miss latency 1041system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57699.993526 # average overall mshr miss latency 1042system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57938.261130 # average overall mshr miss latency |
| 1021system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1022system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1023system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1024system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1025system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1026system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1027system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1043system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1044system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1045system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1046system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1047system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1048system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1049system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1028system.cpu.toL2Bus.trans_dist::ReadReq 2698168 # Transaction distribution 1029system.cpu.toL2Bus.trans_dist::ReadResp 2697644 # Transaction distribution 1030system.cpu.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution 1031system.cpu.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution 1032system.cpu.toL2Bus.trans_dist::Writeback 1542614 # Transaction distribution | 1050system.cpu.toL2Bus.trans_dist::ReadReq 2700360 # Transaction distribution 1051system.cpu.toL2Bus.trans_dist::ReadResp 2699834 # Transaction distribution 1052system.cpu.toL2Bus.trans_dist::WriteReq 13918 # Transaction distribution 1053system.cpu.toL2Bus.trans_dist::WriteResp 13918 # Transaction distribution 1054system.cpu.toL2Bus.trans_dist::Writeback 1543797 # Transaction distribution |
| 1033system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution | 1055system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution |
| 1034system.cpu.toL2Bus.trans_dist::UpgradeReq 2194 # Transaction distribution 1035system.cpu.toL2Bus.trans_dist::UpgradeResp 2194 # Transaction distribution 1036system.cpu.toL2Bus.trans_dist::ReadExReq 313640 # Transaction distribution 1037system.cpu.toL2Bus.trans_dist::ReadExResp 313640 # Transaction distribution 1038system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1587545 # Packet count per connected master and slave (bytes) 1039system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5978947 # Packet count per connected master and slave (bytes) 1040system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7667 # Packet count per connected master and slave (bytes) 1041system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17540 # Packet count per connected master and slave (bytes) 1042system.cpu.toL2Bus.pkt_count::total 7591699 # Packet count per connected master and slave (bytes) 1043system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50801024 # Cumulative packet size per connected master and slave (bytes) 1044system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203997643 # Cumulative packet size per connected master and slave (bytes) 1045system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 217792 # Cumulative packet size per connected master and slave (bytes) 1046system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 573824 # Cumulative packet size per connected master and slave (bytes) 1047system.cpu.toL2Bus.pkt_size::total 255590283 # Cumulative packet size per connected master and slave (bytes) 1048system.cpu.toL2Bus.snoops 53203 # Total snoops (count) 1049system.cpu.toL2Bus.snoop_fanout::samples 4021775 # Request fanout histogram 1050system.cpu.toL2Bus.snoop_fanout::mean 3.011825 # Request fanout histogram 1051system.cpu.toL2Bus.snoop_fanout::stdev 0.108096 # Request fanout histogram | 1056system.cpu.toL2Bus.trans_dist::UpgradeReq 2180 # Transaction distribution 1057system.cpu.toL2Bus.trans_dist::UpgradeResp 2180 # Transaction distribution 1058system.cpu.toL2Bus.trans_dist::ReadExReq 314528 # Transaction distribution 1059system.cpu.toL2Bus.trans_dist::ReadExResp 314528 # Transaction distribution 1060system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1588445 # Packet count per connected master and slave (bytes) 1061system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5982302 # Packet count per connected master and slave (bytes) 1062system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8930 # Packet count per connected master and slave (bytes) 1063system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18990 # Packet count per connected master and slave (bytes) 1064system.cpu.toL2Bus.pkt_count::total 7598667 # Packet count per connected master and slave (bytes) 1065system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50829824 # Cumulative packet size per connected master and slave (bytes) 1066system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204129411 # Cumulative packet size per connected master and slave (bytes) 1067system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 258112 # Cumulative packet size per connected master and slave (bytes) 1068system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 618176 # Cumulative packet size per connected master and slave (bytes) 1069system.cpu.toL2Bus.pkt_size::total 255835523 # Cumulative packet size per connected master and slave (bytes) 1070system.cpu.toL2Bus.snoops 53618 # Total snoops (count) 1071system.cpu.toL2Bus.snoop_fanout::samples 4025992 # Request fanout histogram 1072system.cpu.toL2Bus.snoop_fanout::mean 3.011815 # Request fanout histogram 1073system.cpu.toL2Bus.snoop_fanout::stdev 0.108054 # Request fanout histogram |
| 1052system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1053system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1054system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1055system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1074system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1075system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1076system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1077system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1056system.cpu.toL2Bus.snoop_fanout::3 3974219 98.82% 98.82% # Request fanout histogram 1057system.cpu.toL2Bus.snoop_fanout::4 47556 1.18% 100.00% # Request fanout histogram | 1078system.cpu.toL2Bus.snoop_fanout::3 3978424 98.82% 98.82% # Request fanout histogram 1079system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram |
| 1058system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1059system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1060system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 1080system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1081system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1082system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 1061system.cpu.toL2Bus.snoop_fanout::total 4021775 # Request fanout histogram 1062system.cpu.toL2Bus.reqLayer0.occupancy 3834392000 # Layer occupancy (ticks) | 1083system.cpu.toL2Bus.snoop_fanout::total 4025992 # Request fanout histogram 1084system.cpu.toL2Bus.reqLayer0.occupancy 3837723500 # Layer occupancy (ticks) |
| 1063system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1085system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1064system.cpu.toL2Bus.snoopLayer0.occupancy 468000 # Layer occupancy (ticks) | 1086system.cpu.toL2Bus.snoopLayer0.occupancy 483000 # Layer occupancy (ticks) |
| 1065system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1087system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1066system.cpu.toL2Bus.respLayer0.occupancy 1193119870 # Layer occupancy (ticks) | 1088system.cpu.toL2Bus.respLayer0.occupancy 1193787115 # Layer occupancy (ticks) |
| 1067system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1089system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1068system.cpu.toL2Bus.respLayer1.occupancy 3054097839 # Layer occupancy (ticks) | 1090system.cpu.toL2Bus.respLayer1.occupancy 3055897582 # Layer occupancy (ticks) |
| 1069system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1091system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1070system.cpu.toL2Bus.respLayer2.occupancy 6397000 # Layer occupancy (ticks) | 1092system.cpu.toL2Bus.respLayer2.occupancy 7346250 # Layer occupancy (ticks) |
| 1071system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1093system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1072system.cpu.toL2Bus.respLayer3.occupancy 12861250 # Layer occupancy (ticks) | 1094system.cpu.toL2Bus.respLayer3.occupancy 13996750 # Layer occupancy (ticks) |
| 1073system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1095system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1074system.iobus.trans_dist::ReadReq 230256 # Transaction distribution 1075system.iobus.trans_dist::ReadResp 230256 # Transaction distribution 1076system.iobus.trans_dist::WriteReq 57694 # Transaction distribution 1077system.iobus.trans_dist::WriteResp 10974 # Transaction distribution | 1096system.iobus.trans_dist::ReadReq 230300 # Transaction distribution 1097system.iobus.trans_dist::ReadResp 230300 # Transaction distribution 1098system.iobus.trans_dist::WriteReq 57726 # Transaction distribution 1099system.iobus.trans_dist::WriteResp 11006 # Transaction distribution |
| 1078system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution | 1100system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 1079system.iobus.trans_dist::MessageReq 1654 # Transaction distribution 1080system.iobus.trans_dist::MessageResp 1654 # Transaction distribution | 1101system.iobus.trans_dist::MessageReq 1653 # Transaction distribution 1102system.iobus.trans_dist::MessageResp 1653 # Transaction distribution |
| 1081system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1082system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1083system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1084system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1085system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1086system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 1087system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1088system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1089system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) 1090system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1091system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1092system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) | 1103system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1104system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1105system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1106system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1107system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1108system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 1109system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1110system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1111system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) 1112system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1113system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1114system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) |
| 1093system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) | 1115system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) |
| 1094system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1095system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1096system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1097system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1098system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) | 1116system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1117system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1118system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1119system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1120system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) |
| 1099system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) 1100system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) 1101system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) 1102system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) 1103system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) 1104system.iobus.pkt_count::total 579208 # Packet count per connected master and slave (bytes) | 1121system.iobus.pkt_count_system.bridge.master::total 480916 # Packet count per connected master and slave (bytes) 1122system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95136 # Packet count per connected master and slave (bytes) 1123system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95136 # Packet count per connected master and slave (bytes) 1124system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3306 # Packet count per connected master and slave (bytes) 1125system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3306 # Packet count per connected master and slave (bytes) 1126system.iobus.pkt_count::total 579358 # Packet count per connected master and slave (bytes) |
| 1105system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1106system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1107system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1108system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1109system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1110system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1111system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1112system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1113system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 1114system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1115system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1116system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) | 1127system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1128system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1129system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1130system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1131system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1132system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1133system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1134system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1135system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 1136system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1137system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1138system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) |
| 1117system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) | 1139system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) |
| 1118system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1119system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1120system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1121system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1122system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) | 1140system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1141system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1142system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1143system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1144system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) |
| 1123system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) 1124system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) 1125system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) 1126system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) 1127system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) 1128system.iobus.pkt_size::total 3280522 # Cumulative packet size per connected master and slave (bytes) 1129system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) | 1145system.iobus.pkt_size_system.bridge.master::total 246738 # Cumulative packet size per connected master and slave (bytes) 1146system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027328 # Cumulative packet size per connected master and slave (bytes) 1147system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027328 # Cumulative packet size per connected master and slave (bytes) 1148system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6612 # Cumulative packet size per connected master and slave (bytes) 1149system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6612 # Cumulative packet size per connected master and slave (bytes) 1150system.iobus.pkt_size::total 3280678 # Cumulative packet size per connected master and slave (bytes) 1151system.iobus.reqLayer0.occupancy 3941856 # Layer occupancy (ticks) |
| 1130system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1131system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1132system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1133system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1134system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1135system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 1136system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1137system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) --- 9 unchanged lines hidden (view full) --- 1147system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) 1148system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1149system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1150system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1151system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1152system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1153system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) 1154system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) | 1152system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1153system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1154system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1155system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1156system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1157system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 1158system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1159system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) --- 9 unchanged lines hidden (view full) --- 1169system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) 1170system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1171system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1172system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1173system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1174system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1175system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) 1176system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) |
| 1155system.iobus.reqLayer14.occupancy 20719000 # Layer occupancy (ticks) | 1177system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) |
| 1156system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1157system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1158system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1159system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1160system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1161system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1162system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1163system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1164system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) | 1178system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1179system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1180system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1181system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1182system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1183system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1184system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1185system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1186system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) |
| 1165system.iobus.reqLayer19.occupancy 448430581 # Layer occupancy (ticks) | 1187system.iobus.reqLayer19.occupancy 448381627 # Layer occupancy (ticks) |
| 1166system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1167system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1168system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) | 1188system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1189system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1190system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) |
| 1169system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) | 1191system.iobus.respLayer0.occupancy 469910000 # Layer occupancy (ticks) |
| 1170system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1192system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1171system.iobus.respLayer1.occupancy 52212002 # Layer occupancy (ticks) | 1193system.iobus.respLayer1.occupancy 52236750 # Layer occupancy (ticks) |
| 1172system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 1194system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 1173system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) | 1195system.iobus.respLayer2.occupancy 1653000 # Layer occupancy (ticks) |
| 1174system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) | 1196system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1175system.iocache.tags.replacements 47501 # number of replacements 1176system.iocache.tags.tagsinuse 0.119711 # Cycle average of tags in use | 1197system.iocache.tags.replacements 47513 # number of replacements 1198system.iocache.tags.tagsinuse 0.108235 # Cycle average of tags in use |
| 1177system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1199system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1178system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. | 1200system.iocache.tags.sampled_refs 47529 # Sample count of references to valid blocks. |
| 1179system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1201system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1180system.iocache.tags.warmup_cycle 5045856556000 # Cycle when the warmup percentage was hit. 1181system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.119711 # Average occupied blocks per requestor 1182system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007482 # Average percentage of cache occupancy 1183system.iocache.tags.occ_percent::total 0.007482 # Average percentage of cache occupancy | 1202system.iocache.tags.warmup_cycle 5045848693000 # Cycle when the warmup percentage was hit. 1203system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108235 # Average occupied blocks per requestor 1204system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006765 # Average percentage of cache occupancy 1205system.iocache.tags.occ_percent::total 0.006765 # Average percentage of cache occupancy |
| 1184system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1185system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1186system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1206system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1207system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1208system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1187system.iocache.tags.tag_accesses 428004 # Number of tag accesses 1188system.iocache.tags.data_accesses 428004 # Number of data accesses 1189system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses 1190system.iocache.ReadReq_misses::total 836 # number of ReadReq misses | 1209system.iocache.tags.tag_accesses 428112 # Number of tag accesses 1210system.iocache.tags.data_accesses 428112 # Number of data accesses 1211system.iocache.ReadReq_misses::pc.south_bridge.ide 848 # number of ReadReq misses 1212system.iocache.ReadReq_misses::total 848 # number of ReadReq misses |
| 1191system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 1192system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses | 1213system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 1214system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses |
| 1193system.iocache.demand_misses::pc.south_bridge.ide 836 # number of demand (read+write) misses 1194system.iocache.demand_misses::total 836 # number of demand (read+write) misses 1195system.iocache.overall_misses::pc.south_bridge.ide 836 # number of overall misses 1196system.iocache.overall_misses::total 836 # number of overall misses 1197system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143698686 # number of ReadReq miss cycles 1198system.iocache.ReadReq_miss_latency::total 143698686 # number of ReadReq miss cycles 1199system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361223893 # number of WriteInvalidateReq miss cycles 1200system.iocache.WriteInvalidateReq_miss_latency::total 12361223893 # number of WriteInvalidateReq miss cycles 1201system.iocache.demand_miss_latency::pc.south_bridge.ide 143698686 # number of demand (read+write) miss cycles 1202system.iocache.demand_miss_latency::total 143698686 # number of demand (read+write) miss cycles 1203system.iocache.overall_miss_latency::pc.south_bridge.ide 143698686 # number of overall miss cycles 1204system.iocache.overall_miss_latency::total 143698686 # number of overall miss cycles 1205system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) 1206system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) | 1215system.iocache.demand_misses::pc.south_bridge.ide 848 # number of demand (read+write) misses 1216system.iocache.demand_misses::total 848 # number of demand (read+write) misses 1217system.iocache.overall_misses::pc.south_bridge.ide 848 # number of overall misses 1218system.iocache.overall_misses::total 848 # number of overall misses 1219system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144284936 # number of ReadReq miss cycles 1220system.iocache.ReadReq_miss_latency::total 144284936 # number of ReadReq miss cycles 1221system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12370106941 # number of WriteInvalidateReq miss cycles 1222system.iocache.WriteInvalidateReq_miss_latency::total 12370106941 # number of WriteInvalidateReq miss cycles 1223system.iocache.demand_miss_latency::pc.south_bridge.ide 144284936 # number of demand (read+write) miss cycles 1224system.iocache.demand_miss_latency::total 144284936 # number of demand (read+write) miss cycles 1225system.iocache.overall_miss_latency::pc.south_bridge.ide 144284936 # number of overall miss cycles 1226system.iocache.overall_miss_latency::total 144284936 # number of overall miss cycles 1227system.iocache.ReadReq_accesses::pc.south_bridge.ide 848 # number of ReadReq accesses(hits+misses) 1228system.iocache.ReadReq_accesses::total 848 # number of ReadReq accesses(hits+misses) |
| 1207system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1208system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) | 1229system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1230system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) |
| 1209system.iocache.demand_accesses::pc.south_bridge.ide 836 # number of demand (read+write) accesses 1210system.iocache.demand_accesses::total 836 # number of demand (read+write) accesses 1211system.iocache.overall_accesses::pc.south_bridge.ide 836 # number of overall (read+write) accesses 1212system.iocache.overall_accesses::total 836 # number of overall (read+write) accesses | 1231system.iocache.demand_accesses::pc.south_bridge.ide 848 # number of demand (read+write) accesses 1232system.iocache.demand_accesses::total 848 # number of demand (read+write) accesses 1233system.iocache.overall_accesses::pc.south_bridge.ide 848 # number of overall (read+write) accesses 1234system.iocache.overall_accesses::total 848 # number of overall (read+write) accesses |
| 1213system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1214system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1215system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 1216system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1217system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1218system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1219system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1220system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1235system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1236system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1237system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 1238system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1239system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1240system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1241system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1242system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1221system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average ReadReq miss latency 1222system.iocache.ReadReq_avg_miss_latency::total 171888.380383 # average ReadReq miss latency 1223system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264580.990860 # average WriteInvalidateReq miss latency 1224system.iocache.WriteInvalidateReq_avg_miss_latency::total 264580.990860 # average WriteInvalidateReq miss latency 1225system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average overall miss latency 1226system.iocache.demand_avg_miss_latency::total 171888.380383 # average overall miss latency 1227system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 171888.380383 # average overall miss latency 1228system.iocache.overall_avg_miss_latency::total 171888.380383 # average overall miss latency 1229system.iocache.blocked_cycles::no_mshrs 70511 # number of cycles access was blocked | 1243system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average ReadReq miss latency 1244system.iocache.ReadReq_avg_miss_latency::total 170147.330189 # average ReadReq miss latency 1245system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264771.124593 # average WriteInvalidateReq miss latency 1246system.iocache.WriteInvalidateReq_avg_miss_latency::total 264771.124593 # average WriteInvalidateReq miss latency 1247system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average overall miss latency 1248system.iocache.demand_avg_miss_latency::total 170147.330189 # average overall miss latency 1249system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170147.330189 # average overall miss latency 1250system.iocache.overall_avg_miss_latency::total 170147.330189 # average overall miss latency 1251system.iocache.blocked_cycles::no_mshrs 70958 # number of cycles access was blocked |
| 1230system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1252system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1231system.iocache.blocked::no_mshrs 9153 # number of cycles access was blocked | 1253system.iocache.blocked::no_mshrs 9208 # number of cycles access was blocked |
| 1232system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1254system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1233system.iocache.avg_blocked_cycles::no_mshrs 7.703594 # average number of cycles each access was blocked | 1255system.iocache.avg_blocked_cycles::no_mshrs 7.706125 # average number of cycles each access was blocked |
| 1234system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1235system.iocache.fast_writes 0 # number of fast writes performed 1236system.iocache.cache_copies 0 # number of cache copies performed 1237system.iocache.writebacks::writebacks 46667 # number of writebacks 1238system.iocache.writebacks::total 46667 # number of writebacks | 1256system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1257system.iocache.fast_writes 0 # number of fast writes performed 1258system.iocache.cache_copies 0 # number of cache copies performed 1259system.iocache.writebacks::writebacks 46667 # number of writebacks 1260system.iocache.writebacks::total 46667 # number of writebacks |
| 1239system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses 1240system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses | 1261system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 848 # number of ReadReq MSHR misses 1262system.iocache.ReadReq_mshr_misses::total 848 # number of ReadReq MSHR misses |
| 1241system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 1242system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses | 1263system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 1264system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses |
| 1243system.iocache.demand_mshr_misses::pc.south_bridge.ide 836 # number of demand (read+write) MSHR misses 1244system.iocache.demand_mshr_misses::total 836 # number of demand (read+write) MSHR misses 1245system.iocache.overall_mshr_misses::pc.south_bridge.ide 836 # number of overall MSHR misses 1246system.iocache.overall_mshr_misses::total 836 # number of overall MSHR misses 1247system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of ReadReq MSHR miss cycles 1248system.iocache.ReadReq_mshr_miss_latency::total 100200686 # number of ReadReq MSHR miss cycles 1249system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9931779897 # number of WriteInvalidateReq MSHR miss cycles 1250system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9931779897 # number of WriteInvalidateReq MSHR miss cycles 1251system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of demand (read+write) MSHR miss cycles 1252system.iocache.demand_mshr_miss_latency::total 100200686 # number of demand (read+write) MSHR miss cycles 1253system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100200686 # number of overall MSHR miss cycles 1254system.iocache.overall_mshr_miss_latency::total 100200686 # number of overall MSHR miss cycles | 1265system.iocache.demand_mshr_misses::pc.south_bridge.ide 848 # number of demand (read+write) MSHR misses 1266system.iocache.demand_mshr_misses::total 848 # number of demand (read+write) MSHR misses 1267system.iocache.overall_mshr_misses::pc.south_bridge.ide 848 # number of overall MSHR misses 1268system.iocache.overall_mshr_misses::total 848 # number of overall MSHR misses 1269system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of ReadReq MSHR miss cycles 1270system.iocache.ReadReq_mshr_miss_latency::total 100162436 # number of ReadReq MSHR miss cycles 1271system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9940666941 # number of WriteInvalidateReq MSHR miss cycles 1272system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9940666941 # number of WriteInvalidateReq MSHR miss cycles 1273system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of demand (read+write) MSHR miss cycles 1274system.iocache.demand_mshr_miss_latency::total 100162436 # number of demand (read+write) MSHR miss cycles 1275system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100162436 # number of overall MSHR miss cycles 1276system.iocache.overall_mshr_miss_latency::total 100162436 # number of overall MSHR miss cycles |
| 1255system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1256system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1257system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1258system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1259system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1260system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1261system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1262system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1277system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1278system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1279system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1280system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1281system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1282system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1283system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1284system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1263system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average ReadReq mshr miss latency 1264system.iocache.ReadReq_avg_mshr_miss_latency::total 119857.279904 # average ReadReq mshr miss latency 1265system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212580.905330 # average WriteInvalidateReq mshr miss latency 1266system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212580.905330 # average WriteInvalidateReq mshr miss latency 1267system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average overall mshr miss latency 1268system.iocache.demand_avg_mshr_miss_latency::total 119857.279904 # average overall mshr miss latency 1269system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 119857.279904 # average overall mshr miss latency 1270system.iocache.overall_avg_mshr_miss_latency::total 119857.279904 # average overall mshr miss latency | 1285system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average ReadReq mshr miss latency 1286system.iocache.ReadReq_avg_mshr_miss_latency::total 118116.080189 # average ReadReq mshr miss latency 1287system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212771.124593 # average WriteInvalidateReq mshr miss latency 1288system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212771.124593 # average WriteInvalidateReq mshr miss latency 1289system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average overall mshr miss latency 1290system.iocache.demand_avg_mshr_miss_latency::total 118116.080189 # average overall mshr miss latency 1291system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118116.080189 # average overall mshr miss latency 1292system.iocache.overall_avg_mshr_miss_latency::total 118116.080189 # average overall mshr miss latency |
| 1271system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1293system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1272system.membus.trans_dist::ReadReq 623924 # Transaction distribution 1273system.membus.trans_dist::ReadResp 623924 # Transaction distribution 1274system.membus.trans_dist::WriteReq 13888 # Transaction distribution 1275system.membus.trans_dist::WriteResp 13888 # Transaction distribution 1276system.membus.trans_dist::Writeback 127156 # Transaction distribution | 1294system.membus.trans_dist::ReadReq 624010 # Transaction distribution 1295system.membus.trans_dist::ReadResp 624010 # Transaction distribution 1296system.membus.trans_dist::WriteReq 13918 # Transaction distribution 1297system.membus.trans_dist::WriteResp 13918 # Transaction distribution 1298system.membus.trans_dist::Writeback 126944 # Transaction distribution |
| 1277system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1278system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution | 1299system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1300system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 1279system.membus.trans_dist::UpgradeReq 2158 # Transaction distribution 1280system.membus.trans_dist::UpgradeResp 1607 # Transaction distribution 1281system.membus.trans_dist::ReadExReq 113297 # Transaction distribution 1282system.membus.trans_dist::ReadExResp 113297 # Transaction distribution 1283system.membus.trans_dist::MessageReq 1654 # Transaction distribution 1284system.membus.trans_dist::MessageResp 1654 # Transaction distribution 1285system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) 1286system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) 1287system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) 1288system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) 1289system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393232 # Packet count per connected master and slave (bytes) 1290system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584130 # Packet count per connected master and slave (bytes) 1291system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141386 # Packet count per connected master and slave (bytes) 1292system.membus.pkt_count_system.iocache.mem_side::total 141386 # Packet count per connected master and slave (bytes) 1293system.membus.pkt_count::total 1728824 # Packet count per connected master and slave (bytes) 1294system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) 1295system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) 1296system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) 1297system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) 1298system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15018304 # Cumulative packet size per connected master and slave (bytes) 1299system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16685195 # Cumulative packet size per connected master and slave (bytes) | 1301system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution 1302system.membus.trans_dist::UpgradeResp 1600 # Transaction distribution 1303system.membus.trans_dist::ReadExReq 113223 # Transaction distribution 1304system.membus.trans_dist::ReadExResp 113223 # Transaction distribution 1305system.membus.trans_dist::MessageReq 1653 # Transaction distribution 1306system.membus.trans_dist::MessageResp 1653 # Transaction distribution 1307system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes) 1308system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes) 1309system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480916 # Packet count per connected master and slave (bytes) 1310system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710106 # Packet count per connected master and slave (bytes) 1311system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392937 # Packet count per connected master and slave (bytes) 1312system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1583959 # Packet count per connected master and slave (bytes) 1313system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141398 # Packet count per connected master and slave (bytes) 1314system.membus.pkt_count_system.iocache.mem_side::total 141398 # Packet count per connected master and slave (bytes) 1315system.membus.pkt_count::total 1728663 # Packet count per connected master and slave (bytes) 1316system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes) 1317system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes) 1318system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246738 # Cumulative packet size per connected master and slave (bytes) 1319system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420209 # Cumulative packet size per connected master and slave (bytes) 1320system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15002688 # Cumulative packet size per connected master and slave (bytes) 1321system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16669635 # Cumulative packet size per connected master and slave (bytes) |
| 1300system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1301system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) | 1322system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) 1323system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) |
| 1302system.membus.pkt_size::total 22696931 # Cumulative packet size per connected master and slave (bytes) 1303system.membus.snoops 1614 # Total snoops (count) 1304system.membus.snoop_fanout::samples 331694 # Request fanout histogram | 1324system.membus.pkt_size::total 22681367 # Cumulative packet size per connected master and slave (bytes) 1325system.membus.snoops 1621 # Total snoops (count) 1326system.membus.snoop_fanout::samples 331450 # Request fanout histogram |
| 1305system.membus.snoop_fanout::mean 1 # Request fanout histogram 1306system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1307system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1308system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1327system.membus.snoop_fanout::mean 1 # Request fanout histogram 1328system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1329system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1330system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1309system.membus.snoop_fanout::1 331694 100.00% 100.00% # Request fanout histogram | 1331system.membus.snoop_fanout::1 331450 100.00% 100.00% # Request fanout histogram |
| 1310system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1311system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1312system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1313system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1332system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1333system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1334system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1335system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1314system.membus.snoop_fanout::total 331694 # Request fanout histogram 1315system.membus.reqLayer0.occupancy 257197500 # Layer occupancy (ticks) | 1336system.membus.snoop_fanout::total 331450 # Request fanout histogram 1337system.membus.reqLayer0.occupancy 257308500 # Layer occupancy (ticks) |
| 1316system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1338system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1317system.membus.reqLayer1.occupancy 358100500 # Layer occupancy (ticks) | 1339system.membus.reqLayer1.occupancy 358085000 # Layer occupancy (ticks) |
| 1318system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 1340system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 1319system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) | 1341system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks) |
| 1320system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1342system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1321system.membus.reqLayer3.occupancy 1731913000 # Layer occupancy (ticks) | 1343system.membus.reqLayer3.occupancy 1729709500 # Layer occupancy (ticks) |
| 1322system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) | 1344system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 1323system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) | 1345system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks) |
| 1324system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 1346system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1325system.membus.respLayer2.occupancy 2619410411 # Layer occupancy (ticks) | 1347system.membus.respLayer2.occupancy 2618865668 # Layer occupancy (ticks) |
| 1326system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 1348system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 1327system.membus.respLayer4.occupancy 54258998 # Layer occupancy (ticks) | 1349system.membus.respLayer4.occupancy 54365250 # Layer occupancy (ticks) |
| 1328system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1329system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1330system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1331system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1332system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1333system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1334system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1335system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1336system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1337system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1338system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1339system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1340system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1341 1342---------- End Simulation Statistics ---------- | 1350system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1351system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1352system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1353system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1354system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1355system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1356system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1357system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1358system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1359system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1360system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1361system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1362system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1363 1364---------- End Simulation Statistics ---------- |