| stats.txt (10549:6317351a288c) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.194411 # Number of seconds simulated 4sim_ticks 5194410635000 # Number of ticks simulated 5final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.196466 # Number of seconds simulated 4sim_ticks 5196466347000 # Number of ticks simulated 5final_tick 5196466347000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1318005 # Simulator instruction rate (inst/s) 8host_op_rate 2540682 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 53310327218 # Simulator tick rate (ticks/s) 10host_mem_usage 594964 # Number of bytes of host memory used 11host_seconds 97.44 # Real time elapsed on the host 12sim_insts 128422722 # Number of instructions simulated 13sim_ops 247557000 # Number of ops (including micro ops) simulated | 7host_inst_rate 596082 # Simulator instruction rate (inst/s) 8host_op_rate 1149061 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24120553188 # Simulator tick rate (ticks/s) 10host_mem_usage 596696 # Number of bytes of host memory used 11host_seconds 215.44 # Real time elapsed on the host 12sim_insts 128418244 # Number of instructions simulated 13sim_ops 247550593 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.inst 828416 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9035072 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory 26system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory | 21system.physmem.bytes_read::total 9892224 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 828416 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 828416 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8113920 # Number of bytes written to this memory 25system.physmem.bytes_written::total 8113920 # Number of bytes written to this memory |
| 27system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.inst 12944 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141173 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory | 31system.physmem.num_reads::total 154566 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 126780 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 126780 # Number of write requests responded to by this memory |
| 36system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 991416 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s) | 36system.physmem.bw_read::cpu.inst 159419 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 1738695 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5456 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 1903644 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 159419 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 159419 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1561430 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1561430 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1561430 # Total bandwidth to/from this memory (bytes/s) |
| 48system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) | 45system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) |
| 50system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 155585 # Number of read requests accepted 55system.physmem.writeReqs 127186 # Number of write requests accepted 56system.physmem.readBursts 155585 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 127186 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 9942720 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 14720 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8138624 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 9957440 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 8139904 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 230 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 1629 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10087 # Per bank write bursts 67system.physmem.perBankRdBursts::1 9924 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10111 # Per bank write bursts 69system.physmem.perBankRdBursts::3 9612 # Per bank write bursts 70system.physmem.perBankRdBursts::4 10046 # Per bank write bursts 71system.physmem.perBankRdBursts::5 9507 # Per bank write bursts 72system.physmem.perBankRdBursts::6 9544 # Per bank write bursts 73system.physmem.perBankRdBursts::7 9545 # Per bank write bursts 74system.physmem.perBankRdBursts::8 9177 # Per bank write bursts 75system.physmem.perBankRdBursts::9 9299 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9268 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9485 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9621 # Per bank write bursts 79system.physmem.perBankRdBursts::13 9970 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10158 # Per bank write bursts 81system.physmem.perBankRdBursts::15 10001 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8060 # Per bank write bursts 83system.physmem.perBankWrBursts::1 7801 # Per bank write bursts 84system.physmem.perBankWrBursts::2 7998 # Per bank write bursts 85system.physmem.perBankWrBursts::3 7765 # Per bank write bursts 86system.physmem.perBankWrBursts::4 8116 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7896 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7662 # Per bank write bursts 89system.physmem.perBankWrBursts::7 7717 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7519 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7838 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7675 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7654 # Per bank write bursts 94system.physmem.perBankWrBursts::12 8493 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8626 # Per bank write bursts 96system.physmem.perBankWrBursts::14 8402 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7944 # Per bank write bursts | 47system.physmem.bw_total::cpu.inst 159419 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 1738695 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5456 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 3465075 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 154566 # Number of read requests accepted 52system.physmem.writeReqs 173500 # Number of write requests accepted 53system.physmem.readBursts 154566 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 173500 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 9886080 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue 57system.physmem.bytesWritten 10951744 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 9892224 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 11104000 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 2352 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 1595 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 9833 # Per bank write bursts 64system.physmem.perBankRdBursts::1 9504 # Per bank write bursts 65system.physmem.perBankRdBursts::2 9844 # Per bank write bursts 66system.physmem.perBankRdBursts::3 9497 # Per bank write bursts 67system.physmem.perBankRdBursts::4 9570 # Per bank write bursts 68system.physmem.perBankRdBursts::5 9679 # Per bank write bursts 69system.physmem.perBankRdBursts::6 9540 # Per bank write bursts 70system.physmem.perBankRdBursts::7 9680 # Per bank write bursts 71system.physmem.perBankRdBursts::8 9214 # Per bank write bursts 72system.physmem.perBankRdBursts::9 9453 # Per bank write bursts 73system.physmem.perBankRdBursts::10 9241 # Per bank write bursts 74system.physmem.perBankRdBursts::11 9575 # Per bank write bursts 75system.physmem.perBankRdBursts::12 9600 # Per bank write bursts 76system.physmem.perBankRdBursts::13 10182 # Per bank write bursts 77system.physmem.perBankRdBursts::14 10246 # Per bank write bursts 78system.physmem.perBankRdBursts::15 9812 # Per bank write bursts 79system.physmem.perBankWrBursts::0 10679 # Per bank write bursts 80system.physmem.perBankWrBursts::1 10594 # Per bank write bursts 81system.physmem.perBankWrBursts::2 10884 # Per bank write bursts 82system.physmem.perBankWrBursts::3 10241 # Per bank write bursts 83system.physmem.perBankWrBursts::4 10237 # Per bank write bursts 84system.physmem.perBankWrBursts::5 10759 # Per bank write bursts 85system.physmem.perBankWrBursts::6 10579 # Per bank write bursts 86system.physmem.perBankWrBursts::7 10814 # Per bank write bursts 87system.physmem.perBankWrBursts::8 10762 # Per bank write bursts 88system.physmem.perBankWrBursts::9 11220 # Per bank write bursts 89system.physmem.perBankWrBursts::10 10499 # Per bank write bursts 90system.physmem.perBankWrBursts::11 10145 # Per bank write bursts 91system.physmem.perBankWrBursts::12 11054 # Per bank write bursts 92system.physmem.perBankWrBursts::13 11426 # Per bank write bursts 93system.physmem.perBankWrBursts::14 10852 # Per bank write bursts 94system.physmem.perBankWrBursts::15 10376 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 99system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 100system.physmem.totGap 5194410571500 # Total gap between requests | 96system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 97system.physmem.totGap 5196466283500 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 155585 # Read request sizes (log2) | 104system.physmem.readPktSize::6 154566 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 127186 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 151951 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 2969 # What read queue length does an incoming req see | 111system.physmem.writePktSize::6 173500 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 151257 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 2780 # What read queue length does an incoming req see |
| 117system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see | 114system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see |
| 118system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see | 115system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 35 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see |
| 121system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 118system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see --- 25 unchanged lines hidden (view full) --- 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 2364 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3127 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6124 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6381 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6410 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7424 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 8105 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8845 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 9948 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 9118 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8439 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7706 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7452 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6421 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6193 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6287 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6139 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 216 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 191 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 191 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 214 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 184 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 176 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 181 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 61 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 18 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 55971 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 323.047292 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 191.702498 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 334.763320 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 19466 34.78% 34.78% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 13850 24.74% 59.52% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5737 10.25% 69.77% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3527 6.30% 76.08% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2331 4.16% 80.24% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1635 2.92% 83.16% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1137 2.03% 85.19% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 981 1.75% 86.95% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7307 13.05% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 55971 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5932 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 26.188806 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 621.686791 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 5931 99.98% 99.98% # Reads before turning the bus around for writes | 159system.physmem.wrQLenPdf::15 2693 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 5142 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 8647 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 9871 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 10255 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 11236 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 11623 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 12575 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 12144 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 12750 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 11495 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 10962 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 9581 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 8954 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 7063 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 6898 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 506 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 348 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 261 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 153 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 13 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 58532 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 356.006287 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 207.370190 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 358.892439 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 19432 33.20% 33.20% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 13728 23.45% 56.65% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 5812 9.93% 66.58% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 3460 5.91% 72.49% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 2276 3.89% 76.38% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 1654 2.83% 79.21% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1160 1.98% 81.19% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1010 1.73% 82.92% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 10000 17.08% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 58532 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 6314 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 24.461831 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 602.615488 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 6313 99.98% 99.98% # Reads before turning the bus around for writes |
| 229system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes | 226system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 230system.physmem.rdPerTurnAround::total 5932 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 5932 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 21.437289 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 19.381245 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 13.855005 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 4878 82.23% 82.23% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 44 0.74% 82.97% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 36 0.61% 83.58% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 295 4.97% 88.55% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 297 5.01% 93.56% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 20 0.34% 93.90% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 18 0.30% 94.20% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 14 0.24% 94.44% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 21 0.35% 94.79% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 5 0.08% 94.88% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 1 0.02% 94.89% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 3 0.05% 94.94% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 234 3.94% 98.89% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 3 0.05% 98.94% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 4 0.07% 99.01% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 4 0.07% 99.07% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 9 0.15% 99.22% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 12 0.20% 99.43% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 2 0.03% 99.46% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 5 0.08% 99.54% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::108-111 2 0.03% 99.58% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 8 0.13% 99.71% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 2 0.03% 99.75% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::128-131 10 0.17% 99.93% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::140-143 3 0.05% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::total 5932 # Writes before turning the bus around for reads 263system.physmem.totQLat 1472209750 # Total ticks spent queuing 264system.physmem.totMemAccLat 4385116000 # Total ticks spent from burst creation until serviced by the DRAM 265system.physmem.totBusLat 776775000 # Total ticks spent in databus transfers 266system.physmem.avgQLat 9476.42 # Average queueing delay per DRAM burst | 227system.physmem.rdPerTurnAround::total 6314 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 6314 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 27.101837 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 21.618222 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 26.504313 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 4900 77.61% 77.61% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 45 0.71% 78.32% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 20 0.32% 78.63% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 269 4.26% 82.90% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 162 2.57% 85.46% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 59 0.93% 86.40% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 31 0.49% 86.89% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 30 0.48% 87.36% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 184 2.91% 90.28% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 10 0.16% 90.43% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 13 0.21% 90.64% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 9 0.14% 90.78% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 33 0.52% 91.31% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 21 0.33% 91.64% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 17 0.27% 91.91% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 41 0.65% 92.56% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 96 1.52% 94.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::84-87 7 0.11% 94.19% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::88-91 8 0.13% 94.31% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::92-95 18 0.29% 94.60% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 170 2.69% 97.29% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 5 0.08% 97.37% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 12 0.19% 97.56% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::108-111 4 0.06% 97.62% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 20 0.32% 97.94% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 4 0.06% 98.00% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::120-123 7 0.11% 98.12% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 6 0.10% 98.21% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 38 0.60% 98.81% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 9 0.14% 98.95% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 3 0.05% 99.00% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 7 0.11% 99.11% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 12 0.19% 99.30% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::148-151 3 0.05% 99.35% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::152-155 2 0.03% 99.38% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::156-159 3 0.05% 99.43% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::160-163 7 0.11% 99.54% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::164-167 3 0.05% 99.59% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::168-171 1 0.02% 99.60% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::172-175 2 0.03% 99.64% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::176-179 3 0.05% 99.68% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::180-183 4 0.06% 99.75% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::184-187 2 0.03% 99.78% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::188-191 1 0.02% 99.79% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::192-195 4 0.06% 99.86% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::200-203 3 0.05% 99.90% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::204-207 1 0.02% 99.92% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::216-219 1 0.02% 99.94% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::220-223 1 0.02% 99.95% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::228-231 2 0.03% 99.98% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::total 6314 # Writes before turning the bus around for reads 284system.physmem.totQLat 1460181000 # Total ticks spent queuing 285system.physmem.totMemAccLat 4356493500 # Total ticks spent from burst creation until serviced by the DRAM 286system.physmem.totBusLat 772350000 # Total ticks spent in databus transfers 287system.physmem.avgQLat 9452.85 # Average queueing delay per DRAM burst |
| 267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 288system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 268system.physmem.avgMemAccLat 28226.42 # Average memory access latency per DRAM burst 269system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s 270system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s 271system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s 272system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s | 289system.physmem.avgMemAccLat 28202.85 # Average memory access latency per DRAM burst 290system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s 291system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s 292system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s 293system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s |
| 273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 274system.physmem.busUtil 0.03 # Data bus utilization in percentage 275system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads | 294system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 295system.physmem.busUtil 0.03 # Data bus utilization in percentage 296system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads |
| 276system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes | 297system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes |
| 277system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 298system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 278system.physmem.avgWrQLen 21.88 # Average write queue length when enqueuing 279system.physmem.readRowHits 127796 # Number of row buffer hits during reads 280system.physmem.writeRowHits 98753 # Number of row buffer hits during writes | 299system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing 300system.physmem.readRowHits 127064 # Number of row buffer hits during reads 301system.physmem.writeRowHits 139994 # Number of row buffer hits during writes |
| 281system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads | 302system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads |
| 282system.physmem.writeRowHitRate 77.64 # Row buffer hit rate for writes 283system.physmem.avgGap 18369672.18 # Average gap between requests 284system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined 285system.physmem.memoryStateTime::IDLE 4972956663750 # Time in different power states 286system.physmem.memoryStateTime::REF 173452760000 # Time in different power states | 303system.physmem.writeRowHitRate 81.80 # Row buffer hit rate for writes 304system.physmem.avgGap 15839697.75 # Average gap between requests 305system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined 306system.physmem.memoryStateTime::IDLE 4974958806500 # Time in different power states 307system.physmem.memoryStateTime::REF 173521400000 # Time in different power states |
| 287system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 308system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 288system.physmem.memoryStateTime::ACT 48001096250 # Time in different power states | 309system.physmem.memoryStateTime::ACT 47986025500 # Time in different power states |
| 289system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 310system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 290system.physmem.actEnergy::0 211543920 # Energy for activate commands per rank (pJ) 291system.physmem.actEnergy::1 211596840 # Energy for activate commands per rank (pJ) 292system.physmem.preEnergy::0 115425750 # Energy for precharge commands per rank (pJ) 293system.physmem.preEnergy::1 115454625 # Energy for precharge commands per rank (pJ) 294system.physmem.readEnergy::0 611332800 # Energy for read commands per rank (pJ) 295system.physmem.readEnergy::1 600428400 # Energy for read commands per rank (pJ) 296system.physmem.writeEnergy::0 408337200 # Energy for write commands per rank (pJ) 297system.physmem.writeEnergy::1 415698480 # Energy for write commands per rank (pJ) 298system.physmem.refreshEnergy::0 339273598560 # Energy for refresh commands per rank (pJ) 299system.physmem.refreshEnergy::1 339273598560 # Energy for refresh commands per rank (pJ) 300system.physmem.actBackEnergy::0 134393532390 # Energy for active background per rank (pJ) 301system.physmem.actBackEnergy::1 134240531850 # Energy for active background per rank (pJ) 302system.physmem.preBackEnergy::0 2998756974750 # Energy for precharge background per rank (pJ) 303system.physmem.preBackEnergy::1 2998891185750 # Energy for precharge background per rank (pJ) 304system.physmem.totalEnergy::0 3473770745370 # Total energy per rank (pJ) 305system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ) 306system.physmem.averagePower::0 668.751736 # Core power per rank (mW) 307system.physmem.averagePower::1 668.747452 # Core power per rank (mW) | 311system.physmem.actEnergy::0 218272320 # Energy for activate commands per rank (pJ) 312system.physmem.actEnergy::1 224229600 # Energy for activate commands per rank (pJ) 313system.physmem.preEnergy::0 119097000 # Energy for precharge commands per rank (pJ) 314system.physmem.preEnergy::1 122347500 # Energy for precharge commands per rank (pJ) 315system.physmem.readEnergy::0 601746600 # Energy for read commands per rank (pJ) 316system.physmem.readEnergy::1 603111600 # Energy for read commands per rank (pJ) 317system.physmem.writeEnergy::0 549419760 # Energy for write commands per rank (pJ) 318system.physmem.writeEnergy::1 559444320 # Energy for write commands per rank (pJ) 319system.physmem.refreshEnergy::0 339407858400 # Energy for refresh commands per rank (pJ) 320system.physmem.refreshEnergy::1 339407858400 # Energy for refresh commands per rank (pJ) 321system.physmem.actBackEnergy::0 134224004700 # Energy for active background per rank (pJ) 322system.physmem.actBackEnergy::1 134453555955 # Energy for active background per rank (pJ) 323system.physmem.preBackEnergy::0 3000139025250 # Energy for precharge background per rank (pJ) 324system.physmem.preBackEnergy::1 2999937664500 # Energy for precharge background per rank (pJ) 325system.physmem.totalEnergy::0 3475259424030 # Total energy per rank (pJ) 326system.physmem.totalEnergy::1 3475308211875 # Total energy per rank (pJ) 327system.physmem.averagePower::0 668.773676 # Core power per rank (mW) 328system.physmem.averagePower::1 668.783065 # Core power per rank (mW) |
| 308system.cpu_clk_domain.clock 500 # Clock period in ticks 309system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 329system.cpu_clk_domain.clock 500 # Clock period in ticks 330system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 310system.cpu.numCycles 10388821270 # number of cpu cycles simulated | 331system.cpu.numCycles 10392932694 # number of cpu cycles simulated |
| 311system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 312system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 332system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 333system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 313system.cpu.committedInsts 128422722 # Number of instructions committed 314system.cpu.committedOps 247557000 # Number of ops (including micro ops) committed 315system.cpu.num_int_alu_accesses 232138334 # Number of integer alu accesses | 334system.cpu.committedInsts 128418244 # Number of instructions committed 335system.cpu.committedOps 247550593 # Number of ops (including micro ops) committed 336system.cpu.num_int_alu_accesses 232131886 # Number of integer alu accesses |
| 316system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses | 337system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses |
| 317system.cpu.num_func_calls 2301199 # number of times a function call or return occured 318system.cpu.num_conditional_control_insts 23183159 # number of instructions that are conditional controls 319system.cpu.num_int_insts 232138334 # number of integer instructions | 338system.cpu.num_func_calls 2300917 # number of times a function call or return occured 339system.cpu.num_conditional_control_insts 23183149 # number of instructions that are conditional controls 340system.cpu.num_int_insts 232131886 # number of integer instructions |
| 320system.cpu.num_fp_insts 0 # number of float instructions | 341system.cpu.num_fp_insts 0 # number of float instructions |
| 321system.cpu.num_int_register_reads 434808798 # number of times the integer registers were read 322system.cpu.num_int_register_writes 197991574 # number of times the integer registers were written | 342system.cpu.num_int_register_reads 434791523 # number of times the integer registers were read 343system.cpu.num_int_register_writes 197987761 # number of times the integer registers were written |
| 323system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 324system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 344system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 345system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 325system.cpu.num_cc_register_reads 132893231 # number of times the CC registers were read 326system.cpu.num_cc_register_writes 95600147 # number of times the CC registers were written 327system.cpu.num_mem_refs 22258678 # number of memory refs 328system.cpu.num_load_insts 13887993 # Number of load instructions 329system.cpu.num_store_insts 8370685 # Number of store instructions 330system.cpu.num_idle_cycles 9791802498.998116 # Number of idle cycles 331system.cpu.num_busy_cycles 597018771.001885 # Number of busy cycles 332system.cpu.not_idle_fraction 0.057467 # Percentage of non-idle cycles 333system.cpu.idle_fraction 0.942533 # Percentage of idle cycles 334system.cpu.Branches 26323220 # Number of branches fetched 335system.cpu.op_class::No_OpClass 174807 0.07% 0.07% # Class of executed instruction 336system.cpu.op_class::IntAlu 224862012 90.83% 90.90% # Class of executed instruction 337system.cpu.op_class::IntMult 139985 0.06% 90.96% # Class of executed instruction 338system.cpu.op_class::IntDiv 123095 0.05% 91.01% # Class of executed instruction | 346system.cpu.num_cc_register_reads 132892118 # number of times the CC registers were read 347system.cpu.num_cc_register_writes 95599960 # number of times the CC registers were written 348system.cpu.num_mem_refs 22255642 # number of memory refs 349system.cpu.num_load_insts 13887148 # Number of load instructions 350system.cpu.num_store_insts 8368494 # Number of store instructions 351system.cpu.num_idle_cycles 9795963958.998116 # Number of idle cycles 352system.cpu.num_busy_cycles 596968735.001885 # Number of busy cycles 353system.cpu.not_idle_fraction 0.057440 # Percentage of non-idle cycles 354system.cpu.idle_fraction 0.942560 # Percentage of idle cycles 355system.cpu.Branches 26322824 # Number of branches fetched 356system.cpu.op_class::No_OpClass 174818 0.07% 0.07% # Class of executed instruction 357system.cpu.op_class::IntAlu 224858584 90.83% 90.90% # Class of executed instruction 358system.cpu.op_class::IntMult 140018 0.06% 90.96% # Class of executed instruction 359system.cpu.op_class::IntDiv 123105 0.05% 91.01% # Class of executed instruction |
| 339system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction 340system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction 341system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction 342system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction 343system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction 344system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction 345system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction 346system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 357system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction 358system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction 359system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction 360system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction 361system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction 362system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction 363system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction 364system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction | 360system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction 361system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction 362system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction 363system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction 364system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction 365system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction 366system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction 367system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 378system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction 379system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction 380system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction 381system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction 382system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction 383system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction 384system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction 385system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction |
| 365system.cpu.op_class::MemRead 13887993 5.61% 96.62% # Class of executed instruction 366system.cpu.op_class::MemWrite 8370685 3.38% 100.00% # Class of executed instruction | 386system.cpu.op_class::MemRead 13887148 5.61% 96.62% # Class of executed instruction 387system.cpu.op_class::MemWrite 8368494 3.38% 100.00% # Class of executed instruction |
| 367system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 368system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 388system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 389system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 369system.cpu.op_class::total 247558577 # Class of executed instruction | 390system.cpu.op_class::total 247552167 # Class of executed instruction |
| 370system.cpu.kern.inst.arm 0 # number of arm instructions executed 371system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 391system.cpu.kern.inst.arm 0 # number of arm instructions executed 392system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 372system.cpu.dcache.tags.replacements 1622351 # number of replacements 373system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use 374system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks. 375system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks. 376system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks. | 393system.cpu.dcache.tags.replacements 1622836 # number of replacements 394system.cpu.dcache.tags.tagsinuse 511.996904 # Cycle average of tags in use 395system.cpu.dcache.tags.total_refs 20034858 # Total number of references to valid blocks. 396system.cpu.dcache.tags.sampled_refs 1623348 # Sample count of references to valid blocks. 397system.cpu.dcache.tags.avg_refs 12.341690 # Average number of references to valid blocks. |
| 377system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. | 398system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. |
| 378system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor | 399system.cpu.dcache.tags.occ_blocks::cpu.data 511.996904 # Average occupied blocks per requestor |
| 379system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 380system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 381system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 400system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 401system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 402system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 382system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 383system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 384system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id | 403system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id 404system.cpu.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id 405system.cpu.dcache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id |
| 385system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 386system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 406system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 407system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 387system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses 388system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses 389system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits 390system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits 391system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits 392system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits 393system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits 394system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits 395system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits 396system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits 397system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits 398system.cpu.dcache.overall_hits::total 20036172 # number of overall hits 399system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses 400system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses 401system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses 402system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses 403system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses 404system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses 405system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses 406system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses 407system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses 408system.cpu.dcache.overall_misses::total 1634692 # number of overall misses 409system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles 410system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles 411system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles 412system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles 413system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles 414system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles 415system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles 416system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles 417system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses) 418system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses) 419system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses) 420system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses) 421system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses) 422system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses) 423system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses 424system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses 425system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses 426system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses 427system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses 428system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses 429system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses 430system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses 431system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses 432system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses 433system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses 434system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses 435system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses 436system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses 437system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency 438system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency 439system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency 440system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency 441system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency 442system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency 443system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency 444system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency 445system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked | 408system.cpu.dcache.tags.tag_accesses 88294796 # Number of tag accesses 409system.cpu.dcache.tags.data_accesses 88294796 # Number of data accesses 410system.cpu.dcache.ReadReq_hits::cpu.data 11940626 # number of ReadReq hits 411system.cpu.dcache.ReadReq_hits::total 11940626 # number of ReadReq hits 412system.cpu.dcache.WriteReq_hits::cpu.data 8032822 # number of WriteReq hits 413system.cpu.dcache.WriteReq_hits::total 8032822 # number of WriteReq hits 414system.cpu.dcache.SoftPFReq_hits::cpu.data 59222 # number of SoftPFReq hits 415system.cpu.dcache.SoftPFReq_hits::total 59222 # number of SoftPFReq hits 416system.cpu.dcache.demand_hits::cpu.data 19973448 # number of demand (read+write) hits 417system.cpu.dcache.demand_hits::total 19973448 # number of demand (read+write) hits 418system.cpu.dcache.overall_hits::cpu.data 20032670 # number of overall hits 419system.cpu.dcache.overall_hits::total 20032670 # number of overall hits 420system.cpu.dcache.ReadReq_misses::cpu.data 907502 # number of ReadReq misses 421system.cpu.dcache.ReadReq_misses::total 907502 # number of ReadReq misses 422system.cpu.dcache.WriteReq_misses::cpu.data 325247 # number of WriteReq misses 423system.cpu.dcache.WriteReq_misses::total 325247 # number of WriteReq misses 424system.cpu.dcache.SoftPFReq_misses::cpu.data 402429 # number of SoftPFReq misses 425system.cpu.dcache.SoftPFReq_misses::total 402429 # number of SoftPFReq misses 426system.cpu.dcache.demand_misses::cpu.data 1232749 # number of demand (read+write) misses 427system.cpu.dcache.demand_misses::total 1232749 # number of demand (read+write) misses 428system.cpu.dcache.overall_misses::cpu.data 1635178 # number of overall misses 429system.cpu.dcache.overall_misses::total 1635178 # number of overall misses 430system.cpu.dcache.ReadReq_miss_latency::cpu.data 12738871000 # number of ReadReq miss cycles 431system.cpu.dcache.ReadReq_miss_latency::total 12738871000 # number of ReadReq miss cycles 432system.cpu.dcache.WriteReq_miss_latency::cpu.data 11339051069 # number of WriteReq miss cycles 433system.cpu.dcache.WriteReq_miss_latency::total 11339051069 # number of WriteReq miss cycles 434system.cpu.dcache.demand_miss_latency::cpu.data 24077922069 # number of demand (read+write) miss cycles 435system.cpu.dcache.demand_miss_latency::total 24077922069 # number of demand (read+write) miss cycles 436system.cpu.dcache.overall_miss_latency::cpu.data 24077922069 # number of overall miss cycles 437system.cpu.dcache.overall_miss_latency::total 24077922069 # number of overall miss cycles 438system.cpu.dcache.ReadReq_accesses::cpu.data 12848128 # number of ReadReq accesses(hits+misses) 439system.cpu.dcache.ReadReq_accesses::total 12848128 # number of ReadReq accesses(hits+misses) 440system.cpu.dcache.WriteReq_accesses::cpu.data 8358069 # number of WriteReq accesses(hits+misses) 441system.cpu.dcache.WriteReq_accesses::total 8358069 # number of WriteReq accesses(hits+misses) 442system.cpu.dcache.SoftPFReq_accesses::cpu.data 461651 # number of SoftPFReq accesses(hits+misses) 443system.cpu.dcache.SoftPFReq_accesses::total 461651 # number of SoftPFReq accesses(hits+misses) 444system.cpu.dcache.demand_accesses::cpu.data 21206197 # number of demand (read+write) accesses 445system.cpu.dcache.demand_accesses::total 21206197 # number of demand (read+write) accesses 446system.cpu.dcache.overall_accesses::cpu.data 21667848 # number of overall (read+write) accesses 447system.cpu.dcache.overall_accesses::total 21667848 # number of overall (read+write) accesses 448system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070633 # miss rate for ReadReq accesses 449system.cpu.dcache.ReadReq_miss_rate::total 0.070633 # miss rate for ReadReq accesses 450system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038914 # miss rate for WriteReq accesses 451system.cpu.dcache.WriteReq_miss_rate::total 0.038914 # miss rate for WriteReq accesses 452system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871717 # miss rate for SoftPFReq accesses 453system.cpu.dcache.SoftPFReq_miss_rate::total 0.871717 # miss rate for SoftPFReq accesses 454system.cpu.dcache.demand_miss_rate::cpu.data 0.058132 # miss rate for demand accesses 455system.cpu.dcache.demand_miss_rate::total 0.058132 # miss rate for demand accesses 456system.cpu.dcache.overall_miss_rate::cpu.data 0.075466 # miss rate for overall accesses 457system.cpu.dcache.overall_miss_rate::total 0.075466 # miss rate for overall accesses 458system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14037.292480 # average ReadReq miss latency 459system.cpu.dcache.ReadReq_avg_miss_latency::total 14037.292480 # average ReadReq miss latency 460system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34862.892107 # average WriteReq miss latency 461system.cpu.dcache.WriteReq_avg_miss_latency::total 34862.892107 # average WriteReq miss latency 462system.cpu.dcache.demand_avg_miss_latency::cpu.data 19531.893410 # average overall miss latency 463system.cpu.dcache.demand_avg_miss_latency::total 19531.893410 # average overall miss latency 464system.cpu.dcache.overall_avg_miss_latency::cpu.data 14724.954757 # average overall miss latency 465system.cpu.dcache.overall_avg_miss_latency::total 14724.954757 # average overall miss latency 466system.cpu.dcache.blocked_cycles::no_mshrs 6197 # number of cycles access was blocked |
| 446system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 467system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 447system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked | 468system.cpu.dcache.blocked::no_mshrs 83 # number of cycles access was blocked |
| 448system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 469system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 449system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked | 470system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.662651 # average number of cycles each access was blocked |
| 450system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 451system.cpu.dcache.fast_writes 0 # number of fast writes performed 452system.cpu.dcache.cache_copies 0 # number of cache copies performed | 471system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 472system.cpu.dcache.fast_writes 0 # number of fast writes performed 473system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 453system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks 454system.cpu.dcache.writebacks::total 1538923 # number of writebacks 455system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits 456system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits 457system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits 458system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits 459system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits 460system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits 461system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits 462system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits 463system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses 464system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses 465system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses 466system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses 467system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses 468system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses 469system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses 470system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses 471system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses 472system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses 473system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles 474system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles 475system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles 476system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles 477system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles 478system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles 479system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles 480system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles 481system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles 482system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles | 474system.cpu.dcache.writebacks::writebacks 1539435 # number of writebacks 475system.cpu.dcache.writebacks::total 1539435 # number of writebacks 476system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291 # number of ReadReq MSHR hits 477system.cpu.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits 478system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9259 # number of WriteReq MSHR hits 479system.cpu.dcache.WriteReq_mshr_hits::total 9259 # number of WriteReq MSHR hits 480system.cpu.dcache.demand_mshr_hits::cpu.data 9550 # number of demand (read+write) MSHR hits 481system.cpu.dcache.demand_mshr_hits::total 9550 # number of demand (read+write) MSHR hits 482system.cpu.dcache.overall_mshr_hits::cpu.data 9550 # number of overall MSHR hits 483system.cpu.dcache.overall_mshr_hits::total 9550 # number of overall MSHR hits 484system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907211 # number of ReadReq MSHR misses 485system.cpu.dcache.ReadReq_mshr_misses::total 907211 # number of ReadReq MSHR misses 486system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315988 # number of WriteReq MSHR misses 487system.cpu.dcache.WriteReq_mshr_misses::total 315988 # number of WriteReq MSHR misses 488system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402393 # number of SoftPFReq MSHR misses 489system.cpu.dcache.SoftPFReq_mshr_misses::total 402393 # number of SoftPFReq MSHR misses 490system.cpu.dcache.demand_mshr_misses::cpu.data 1223199 # number of demand (read+write) MSHR misses 491system.cpu.dcache.demand_mshr_misses::total 1223199 # number of demand (read+write) MSHR misses 492system.cpu.dcache.overall_mshr_misses::cpu.data 1625592 # number of overall MSHR misses 493system.cpu.dcache.overall_mshr_misses::total 1625592 # number of overall MSHR misses 494system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10916933250 # number of ReadReq MSHR miss cycles 495system.cpu.dcache.ReadReq_mshr_miss_latency::total 10916933250 # number of ReadReq MSHR miss cycles 496system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10204146879 # number of WriteReq MSHR miss cycles 497system.cpu.dcache.WriteReq_mshr_miss_latency::total 10204146879 # number of WriteReq MSHR miss cycles 498system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337559000 # number of SoftPFReq MSHR miss cycles 499system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337559000 # number of SoftPFReq MSHR miss cycles 500system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21121080129 # number of demand (read+write) MSHR miss cycles 501system.cpu.dcache.demand_mshr_miss_latency::total 21121080129 # number of demand (read+write) MSHR miss cycles 502system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26458639129 # number of overall MSHR miss cycles 503system.cpu.dcache.overall_mshr_miss_latency::total 26458639129 # number of overall MSHR miss cycles |
| 483system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles 484system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles | 504system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles 505system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles |
| 485system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles 486system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles 487system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles 488system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles 489system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses 490system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses 491system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses 492system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses 493system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses 494system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses 495system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses 496system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses 497system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses 498system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses 499system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency 500system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency 501system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency 502system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency 503system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency 504system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency 505system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency 506system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency 507system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency | 506system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561805000 # number of WriteReq MSHR uncacheable cycles 507system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561805000 # number of WriteReq MSHR uncacheable cycles 508system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802178000 # number of overall MSHR uncacheable cycles 509system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802178000 # number of overall MSHR uncacheable cycles 510system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070610 # mshr miss rate for ReadReq accesses 511system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070610 # mshr miss rate for ReadReq accesses 512system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037806 # mshr miss rate for WriteReq accesses 513system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037806 # mshr miss rate for WriteReq accesses 514system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871639 # mshr miss rate for SoftPFReq accesses 515system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871639 # mshr miss rate for SoftPFReq accesses 516system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057681 # mshr miss rate for demand accesses 517system.cpu.dcache.demand_mshr_miss_rate::total 0.057681 # mshr miss rate for demand accesses 518system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075023 # mshr miss rate for overall accesses 519system.cpu.dcache.overall_mshr_miss_rate::total 0.075023 # mshr miss rate for overall accesses 520system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12033.510672 # average ReadReq mshr miss latency 521system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12033.510672 # average ReadReq mshr miss latency 522system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32292.830357 # average WriteReq mshr miss latency 523system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32292.830357 # average WriteReq mshr miss latency 524system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13264.542375 # average SoftPFReq mshr miss latency 525system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13264.542375 # average SoftPFReq mshr miss latency 526system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17267.084202 # average overall mshr miss latency 527system.cpu.dcache.demand_avg_mshr_miss_latency::total 17267.084202 # average overall mshr miss latency 528system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16276.309879 # average overall mshr miss latency 529system.cpu.dcache.overall_avg_mshr_miss_latency::total 16276.309879 # average overall mshr miss latency |
| 509system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 510system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 511system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 512system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 513system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 514system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 515system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 530system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 531system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 532system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 533system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 534system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 535system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 536system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 516system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements 517system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use 518system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks. 519system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks. 520system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks. 521system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit. 522system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor 523system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy 524system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy | 537system.cpu.dtb_walker_cache.tags.replacements 7764 # number of replacements 538system.cpu.dtb_walker_cache.tags.tagsinuse 5.069200 # Cycle average of tags in use 539system.cpu.dtb_walker_cache.tags.total_refs 13087 # Total number of references to valid blocks. 540system.cpu.dtb_walker_cache.tags.sampled_refs 7779 # Sample count of references to valid blocks. 541system.cpu.dtb_walker_cache.tags.avg_refs 1.682350 # Average number of references to valid blocks. 542system.cpu.dtb_walker_cache.tags.warmup_cycle 5159703878000 # Cycle when the warmup percentage was hit. 543system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.069200 # Average occupied blocks per requestor 544system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316825 # Average percentage of cache occupancy 545system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316825 # Average percentage of cache occupancy |
| 525system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 526system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 527system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 528system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 529system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id | 546system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 547system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 548system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 549system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 550system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id |
| 530system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses 531system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses 532system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits 533system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits 534system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits 535system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits 536system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits 537system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits 538system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses 539system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses 540system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses 541system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses 542system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses 543system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses 544system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles 545system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles 546system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles 547system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles 548system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles 549system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles 550system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses) 551system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses) 552system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses 553system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses 554system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses 555system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses 556system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses 557system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses 558system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses 559system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses 560system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses 561system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses 562system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency 563system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency 564system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency 565system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency 566system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency 567system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency | 551system.cpu.dtb_walker_cache.tags.tag_accesses 53125 # Number of tag accesses 552system.cpu.dtb_walker_cache.tags.data_accesses 53125 # Number of data accesses 553system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13088 # number of ReadReq hits 554system.cpu.dtb_walker_cache.ReadReq_hits::total 13088 # number of ReadReq hits 555system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13088 # number of demand (read+write) hits 556system.cpu.dtb_walker_cache.demand_hits::total 13088 # number of demand (read+write) hits 557system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13088 # number of overall hits 558system.cpu.dtb_walker_cache.overall_hits::total 13088 # number of overall hits 559system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8983 # number of ReadReq misses 560system.cpu.dtb_walker_cache.ReadReq_misses::total 8983 # number of ReadReq misses 561system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8983 # number of demand (read+write) misses 562system.cpu.dtb_walker_cache.demand_misses::total 8983 # number of demand (read+write) misses 563system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8983 # number of overall misses 564system.cpu.dtb_walker_cache.overall_misses::total 8983 # number of overall misses 565system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95259000 # number of ReadReq miss cycles 566system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95259000 # number of ReadReq miss cycles 567system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95259000 # number of demand (read+write) miss cycles 568system.cpu.dtb_walker_cache.demand_miss_latency::total 95259000 # number of demand (read+write) miss cycles 569system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95259000 # number of overall miss cycles 570system.cpu.dtb_walker_cache.overall_miss_latency::total 95259000 # number of overall miss cycles 571system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22071 # number of ReadReq accesses(hits+misses) 572system.cpu.dtb_walker_cache.ReadReq_accesses::total 22071 # number of ReadReq accesses(hits+misses) 573system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22071 # number of demand (read+write) accesses 574system.cpu.dtb_walker_cache.demand_accesses::total 22071 # number of demand (read+write) accesses 575system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22071 # number of overall (read+write) accesses 576system.cpu.dtb_walker_cache.overall_accesses::total 22071 # number of overall (read+write) accesses 577system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407005 # miss rate for ReadReq accesses 578system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407005 # miss rate for ReadReq accesses 579system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407005 # miss rate for demand accesses 580system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407005 # miss rate for demand accesses 581system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407005 # miss rate for overall accesses 582system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407005 # miss rate for overall accesses 583system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10604.363798 # average ReadReq miss latency 584system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10604.363798 # average ReadReq miss latency 585system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency 586system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10604.363798 # average overall miss latency 587system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency 588system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10604.363798 # average overall miss latency |
| 568system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 569system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 570system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 571system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 572system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 573system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 574system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 575system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 589system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 590system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 591system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 592system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 593system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 594system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 595system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 596system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 576system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks 577system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks 578system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses 579system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses 580system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses 581system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses 582system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses 583system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses 584system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles 585system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles 586system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles 587system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles 588system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles 589system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles 590system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses 591system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses 592system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses 593system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses 594system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses 595system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses 596system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency 597system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency 598system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency 599system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency 600system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency 601system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency | 597system.cpu.dtb_walker_cache.writebacks::writebacks 3015 # number of writebacks 598system.cpu.dtb_walker_cache.writebacks::total 3015 # number of writebacks 599system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8983 # number of ReadReq MSHR misses 600system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8983 # number of ReadReq MSHR misses 601system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8983 # number of demand (read+write) MSHR misses 602system.cpu.dtb_walker_cache.demand_mshr_misses::total 8983 # number of demand (read+write) MSHR misses 603system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8983 # number of overall MSHR misses 604system.cpu.dtb_walker_cache.overall_mshr_misses::total 8983 # number of overall MSHR misses 605system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77292500 # number of ReadReq MSHR miss cycles 606system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77292500 # number of ReadReq MSHR miss cycles 607system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77292500 # number of demand (read+write) MSHR miss cycles 608system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77292500 # number of demand (read+write) MSHR miss cycles 609system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77292500 # number of overall MSHR miss cycles 610system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77292500 # number of overall MSHR miss cycles 611system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for ReadReq accesses 612system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407005 # mshr miss rate for ReadReq accesses 613system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for demand accesses 614system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407005 # mshr miss rate for demand accesses 615system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for overall accesses 616system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407005 # mshr miss rate for overall accesses 617system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average ReadReq mshr miss latency 618system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8604.308138 # average ReadReq mshr miss latency 619system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency 620system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency 621system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency 622system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency |
| 602system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 623system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 603system.cpu.icache.tags.replacements 791372 # number of replacements 604system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use 605system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks. 606system.cpu.icache.tags.sampled_refs 791884 # Sample count of references to valid blocks. 607system.cpu.icache.tags.avg_refs 182.702791 # Average number of references to valid blocks. | 624system.cpu.icache.tags.replacements 791291 # number of replacements 625system.cpu.icache.tags.tagsinuse 510.349956 # Cycle average of tags in use 626system.cpu.icache.tags.total_refs 144673577 # Total number of references to valid blocks. 627system.cpu.icache.tags.sampled_refs 791803 # Sample count of references to valid blocks. 628system.cpu.icache.tags.avg_refs 182.714106 # Average number of references to valid blocks. |
| 608system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit. | 629system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit. |
| 609system.cpu.icache.tags.occ_blocks::cpu.inst 510.348934 # Average occupied blocks per requestor 610system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy 611system.cpu.icache.tags.occ_percent::total 0.996775 # Average percentage of cache occupancy | 630system.cpu.icache.tags.occ_blocks::cpu.inst 510.349956 # Average occupied blocks per requestor 631system.cpu.icache.tags.occ_percent::cpu.inst 0.996777 # Average percentage of cache occupancy 632system.cpu.icache.tags.occ_percent::total 0.996777 # Average percentage of cache occupancy |
| 612system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 633system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 613system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 614system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id 615system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id 616system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id | 634system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 635system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id 636system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id 637system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id |
| 617system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 638system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 618system.cpu.icache.tags.tag_accesses 146263199 # Number of tag accesses 619system.cpu.icache.tags.data_accesses 146263199 # Number of data accesses 620system.cpu.icache.ReadReq_hits::cpu.inst 144679417 # number of ReadReq hits 621system.cpu.icache.ReadReq_hits::total 144679417 # number of ReadReq hits 622system.cpu.icache.demand_hits::cpu.inst 144679417 # number of demand (read+write) hits 623system.cpu.icache.demand_hits::total 144679417 # number of demand (read+write) hits 624system.cpu.icache.overall_hits::cpu.inst 144679417 # number of overall hits 625system.cpu.icache.overall_hits::total 144679417 # number of overall hits 626system.cpu.icache.ReadReq_misses::cpu.inst 791891 # number of ReadReq misses 627system.cpu.icache.ReadReq_misses::total 791891 # number of ReadReq misses 628system.cpu.icache.demand_misses::cpu.inst 791891 # number of demand (read+write) misses 629system.cpu.icache.demand_misses::total 791891 # number of demand (read+write) misses 630system.cpu.icache.overall_misses::cpu.inst 791891 # number of overall misses 631system.cpu.icache.overall_misses::total 791891 # number of overall misses 632system.cpu.icache.ReadReq_miss_latency::cpu.inst 11123124618 # number of ReadReq miss cycles 633system.cpu.icache.ReadReq_miss_latency::total 11123124618 # number of ReadReq miss cycles 634system.cpu.icache.demand_miss_latency::cpu.inst 11123124618 # number of demand (read+write) miss cycles 635system.cpu.icache.demand_miss_latency::total 11123124618 # number of demand (read+write) miss cycles 636system.cpu.icache.overall_miss_latency::cpu.inst 11123124618 # number of overall miss cycles 637system.cpu.icache.overall_miss_latency::total 11123124618 # number of overall miss cycles 638system.cpu.icache.ReadReq_accesses::cpu.inst 145471308 # number of ReadReq accesses(hits+misses) 639system.cpu.icache.ReadReq_accesses::total 145471308 # number of ReadReq accesses(hits+misses) 640system.cpu.icache.demand_accesses::cpu.inst 145471308 # number of demand (read+write) accesses 641system.cpu.icache.demand_accesses::total 145471308 # number of demand (read+write) accesses 642system.cpu.icache.overall_accesses::cpu.inst 145471308 # number of overall (read+write) accesses 643system.cpu.icache.overall_accesses::total 145471308 # number of overall (read+write) accesses 644system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005444 # miss rate for ReadReq accesses 645system.cpu.icache.ReadReq_miss_rate::total 0.005444 # miss rate for ReadReq accesses 646system.cpu.icache.demand_miss_rate::cpu.inst 0.005444 # miss rate for demand accesses 647system.cpu.icache.demand_miss_rate::total 0.005444 # miss rate for demand accesses 648system.cpu.icache.overall_miss_rate::cpu.inst 0.005444 # miss rate for overall accesses 649system.cpu.icache.overall_miss_rate::total 0.005444 # miss rate for overall accesses 650system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14046.282403 # average ReadReq miss latency 651system.cpu.icache.ReadReq_avg_miss_latency::total 14046.282403 # average ReadReq miss latency 652system.cpu.icache.demand_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency 653system.cpu.icache.demand_avg_miss_latency::total 14046.282403 # average overall miss latency 654system.cpu.icache.overall_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency 655system.cpu.icache.overall_avg_miss_latency::total 14046.282403 # average overall miss latency | 639system.cpu.icache.tags.tag_accesses 146257197 # Number of tag accesses 640system.cpu.icache.tags.data_accesses 146257197 # Number of data accesses 641system.cpu.icache.ReadReq_hits::cpu.inst 144673577 # number of ReadReq hits 642system.cpu.icache.ReadReq_hits::total 144673577 # number of ReadReq hits 643system.cpu.icache.demand_hits::cpu.inst 144673577 # number of demand (read+write) hits 644system.cpu.icache.demand_hits::total 144673577 # number of demand (read+write) hits 645system.cpu.icache.overall_hits::cpu.inst 144673577 # number of overall hits 646system.cpu.icache.overall_hits::total 144673577 # number of overall hits 647system.cpu.icache.ReadReq_misses::cpu.inst 791810 # number of ReadReq misses 648system.cpu.icache.ReadReq_misses::total 791810 # number of ReadReq misses 649system.cpu.icache.demand_misses::cpu.inst 791810 # number of demand (read+write) misses 650system.cpu.icache.demand_misses::total 791810 # number of demand (read+write) misses 651system.cpu.icache.overall_misses::cpu.inst 791810 # number of overall misses 652system.cpu.icache.overall_misses::total 791810 # number of overall misses 653system.cpu.icache.ReadReq_miss_latency::cpu.inst 11120002617 # number of ReadReq miss cycles 654system.cpu.icache.ReadReq_miss_latency::total 11120002617 # number of ReadReq miss cycles 655system.cpu.icache.demand_miss_latency::cpu.inst 11120002617 # number of demand (read+write) miss cycles 656system.cpu.icache.demand_miss_latency::total 11120002617 # number of demand (read+write) miss cycles 657system.cpu.icache.overall_miss_latency::cpu.inst 11120002617 # number of overall miss cycles 658system.cpu.icache.overall_miss_latency::total 11120002617 # number of overall miss cycles 659system.cpu.icache.ReadReq_accesses::cpu.inst 145465387 # number of ReadReq accesses(hits+misses) 660system.cpu.icache.ReadReq_accesses::total 145465387 # number of ReadReq accesses(hits+misses) 661system.cpu.icache.demand_accesses::cpu.inst 145465387 # number of demand (read+write) accesses 662system.cpu.icache.demand_accesses::total 145465387 # number of demand (read+write) accesses 663system.cpu.icache.overall_accesses::cpu.inst 145465387 # number of overall (read+write) accesses 664system.cpu.icache.overall_accesses::total 145465387 # number of overall (read+write) accesses 665system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005443 # miss rate for ReadReq accesses 666system.cpu.icache.ReadReq_miss_rate::total 0.005443 # miss rate for ReadReq accesses 667system.cpu.icache.demand_miss_rate::cpu.inst 0.005443 # miss rate for demand accesses 668system.cpu.icache.demand_miss_rate::total 0.005443 # miss rate for demand accesses 669system.cpu.icache.overall_miss_rate::cpu.inst 0.005443 # miss rate for overall accesses 670system.cpu.icache.overall_miss_rate::total 0.005443 # miss rate for overall accesses 671system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14043.776432 # average ReadReq miss latency 672system.cpu.icache.ReadReq_avg_miss_latency::total 14043.776432 # average ReadReq miss latency 673system.cpu.icache.demand_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency 674system.cpu.icache.demand_avg_miss_latency::total 14043.776432 # average overall miss latency 675system.cpu.icache.overall_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency 676system.cpu.icache.overall_avg_miss_latency::total 14043.776432 # average overall miss latency |
| 656system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 657system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 659system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 660system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 661system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 662system.cpu.icache.fast_writes 0 # number of fast writes performed 663system.cpu.icache.cache_copies 0 # number of cache copies performed | 677system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 678system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 679system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 680system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 681system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 682system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 683system.cpu.icache.fast_writes 0 # number of fast writes performed 684system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 664system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791891 # number of ReadReq MSHR misses 665system.cpu.icache.ReadReq_mshr_misses::total 791891 # number of ReadReq MSHR misses 666system.cpu.icache.demand_mshr_misses::cpu.inst 791891 # number of demand (read+write) MSHR misses 667system.cpu.icache.demand_mshr_misses::total 791891 # number of demand (read+write) MSHR misses 668system.cpu.icache.overall_mshr_misses::cpu.inst 791891 # number of overall MSHR misses 669system.cpu.icache.overall_mshr_misses::total 791891 # number of overall MSHR misses 670system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9534445382 # number of ReadReq MSHR miss cycles 671system.cpu.icache.ReadReq_mshr_miss_latency::total 9534445382 # number of ReadReq MSHR miss cycles 672system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9534445382 # number of demand (read+write) MSHR miss cycles 673system.cpu.icache.demand_mshr_miss_latency::total 9534445382 # number of demand (read+write) MSHR miss cycles 674system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9534445382 # number of overall MSHR miss cycles 675system.cpu.icache.overall_mshr_miss_latency::total 9534445382 # number of overall MSHR miss cycles 676system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for ReadReq accesses 677system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005444 # mshr miss rate for ReadReq accesses 678system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for demand accesses 679system.cpu.icache.demand_mshr_miss_rate::total 0.005444 # mshr miss rate for demand accesses 680system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for overall accesses 681system.cpu.icache.overall_mshr_miss_rate::total 0.005444 # mshr miss rate for overall accesses 682system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12040.098173 # average ReadReq mshr miss latency 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12040.098173 # average ReadReq mshr miss latency 684system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency 686system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency | 685system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791810 # number of ReadReq MSHR misses 686system.cpu.icache.ReadReq_mshr_misses::total 791810 # number of ReadReq MSHR misses 687system.cpu.icache.demand_mshr_misses::cpu.inst 791810 # number of demand (read+write) MSHR misses 688system.cpu.icache.demand_mshr_misses::total 791810 # number of demand (read+write) MSHR misses 689system.cpu.icache.overall_mshr_misses::cpu.inst 791810 # number of overall MSHR misses 690system.cpu.icache.overall_mshr_misses::total 791810 # number of overall MSHR misses 691system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9531495383 # number of ReadReq MSHR miss cycles 692system.cpu.icache.ReadReq_mshr_miss_latency::total 9531495383 # number of ReadReq MSHR miss cycles 693system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9531495383 # number of demand (read+write) MSHR miss cycles 694system.cpu.icache.demand_mshr_miss_latency::total 9531495383 # number of demand (read+write) MSHR miss cycles 695system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9531495383 # number of overall MSHR miss cycles 696system.cpu.icache.overall_mshr_miss_latency::total 9531495383 # number of overall MSHR miss cycles 697system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for ReadReq accesses 698system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005443 # mshr miss rate for ReadReq accesses 699system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for demand accesses 700system.cpu.icache.demand_mshr_miss_rate::total 0.005443 # mshr miss rate for demand accesses 701system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for overall accesses 702system.cpu.icache.overall_mshr_miss_rate::total 0.005443 # mshr miss rate for overall accesses 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12037.604202 # average ReadReq mshr miss latency 704system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12037.604202 # average ReadReq mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12037.604202 # average overall mshr miss latency 706system.cpu.icache.demand_avg_mshr_miss_latency::total 12037.604202 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12037.604202 # average overall mshr miss latency 708system.cpu.icache.overall_avg_mshr_miss_latency::total 12037.604202 # average overall mshr miss latency |
| 688system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 709system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 689system.cpu.itb_walker_cache.tags.replacements 3756 # number of replacements 690system.cpu.itb_walker_cache.tags.tagsinuse 3.071335 # Cycle average of tags in use 691system.cpu.itb_walker_cache.tags.total_refs 7599 # Total number of references to valid blocks. 692system.cpu.itb_walker_cache.tags.sampled_refs 3768 # Sample count of references to valid blocks. 693system.cpu.itb_walker_cache.tags.avg_refs 2.016720 # Average number of references to valid blocks. 694system.cpu.itb_walker_cache.tags.warmup_cycle 5167567118000 # Cycle when the warmup percentage was hit. 695system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071335 # Average occupied blocks per requestor 696system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191958 # Average percentage of cache occupancy 697system.cpu.itb_walker_cache.tags.occ_percent::total 0.191958 # Average percentage of cache occupancy | 710system.cpu.itb_walker_cache.tags.replacements 3671 # number of replacements 711system.cpu.itb_walker_cache.tags.tagsinuse 3.091001 # Cycle average of tags in use 712system.cpu.itb_walker_cache.tags.total_refs 7743 # Total number of references to valid blocks. 713system.cpu.itb_walker_cache.tags.sampled_refs 3683 # Sample count of references to valid blocks. 714system.cpu.itb_walker_cache.tags.avg_refs 2.102362 # Average number of references to valid blocks. 715system.cpu.itb_walker_cache.tags.warmup_cycle 5161228729000 # Cycle when the warmup percentage was hit. 716system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.091001 # Average occupied blocks per requestor 717system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.193188 # Average percentage of cache occupancy 718system.cpu.itb_walker_cache.tags.occ_percent::total 0.193188 # Average percentage of cache occupancy |
| 698system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 699system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 700system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 701system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 702system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 703system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id | 719system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 720system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 721system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 722system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 723system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 724system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id |
| 704system.cpu.itb_walker_cache.tags.tag_accesses 29071 # Number of tag accesses 705system.cpu.itb_walker_cache.tags.data_accesses 29071 # Number of data accesses 706system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7599 # number of ReadReq hits 707system.cpu.itb_walker_cache.ReadReq_hits::total 7599 # number of ReadReq hits | 725system.cpu.itb_walker_cache.tags.tag_accesses 29095 # Number of tag accesses 726system.cpu.itb_walker_cache.tags.data_accesses 29095 # Number of data accesses 727system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7743 # number of ReadReq hits 728system.cpu.itb_walker_cache.ReadReq_hits::total 7743 # number of ReadReq hits |
| 708system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 709system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 729system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 730system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 710system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7601 # number of demand (read+write) hits 711system.cpu.itb_walker_cache.demand_hits::total 7601 # number of demand (read+write) hits 712system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7601 # number of overall hits 713system.cpu.itb_walker_cache.overall_hits::total 7601 # number of overall hits 714system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4623 # number of ReadReq misses 715system.cpu.itb_walker_cache.ReadReq_misses::total 4623 # number of ReadReq misses 716system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4623 # number of demand (read+write) misses 717system.cpu.itb_walker_cache.demand_misses::total 4623 # number of demand (read+write) misses 718system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4623 # number of overall misses 719system.cpu.itb_walker_cache.overall_misses::total 4623 # number of overall misses 720system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 47504750 # number of ReadReq miss cycles 721system.cpu.itb_walker_cache.ReadReq_miss_latency::total 47504750 # number of ReadReq miss cycles 722system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 47504750 # number of demand (read+write) miss cycles 723system.cpu.itb_walker_cache.demand_miss_latency::total 47504750 # number of demand (read+write) miss cycles 724system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 47504750 # number of overall miss cycles 725system.cpu.itb_walker_cache.overall_miss_latency::total 47504750 # number of overall miss cycles 726system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12222 # number of ReadReq accesses(hits+misses) 727system.cpu.itb_walker_cache.ReadReq_accesses::total 12222 # number of ReadReq accesses(hits+misses) | 731system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7745 # number of demand (read+write) hits 732system.cpu.itb_walker_cache.demand_hits::total 7745 # number of demand (read+write) hits 733system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7745 # number of overall hits 734system.cpu.itb_walker_cache.overall_hits::total 7745 # number of overall hits 735system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4535 # number of ReadReq misses 736system.cpu.itb_walker_cache.ReadReq_misses::total 4535 # number of ReadReq misses 737system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4535 # number of demand (read+write) misses 738system.cpu.itb_walker_cache.demand_misses::total 4535 # number of demand (read+write) misses 739system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4535 # number of overall misses 740system.cpu.itb_walker_cache.overall_misses::total 4535 # number of overall misses 741system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45208750 # number of ReadReq miss cycles 742system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45208750 # number of ReadReq miss cycles 743system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45208750 # number of demand (read+write) miss cycles 744system.cpu.itb_walker_cache.demand_miss_latency::total 45208750 # number of demand (read+write) miss cycles 745system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45208750 # number of overall miss cycles 746system.cpu.itb_walker_cache.overall_miss_latency::total 45208750 # number of overall miss cycles 747system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12278 # number of ReadReq accesses(hits+misses) 748system.cpu.itb_walker_cache.ReadReq_accesses::total 12278 # number of ReadReq accesses(hits+misses) |
| 728system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 729system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 749system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 750system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 730system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12224 # number of demand (read+write) accesses 731system.cpu.itb_walker_cache.demand_accesses::total 12224 # number of demand (read+write) accesses 732system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12224 # number of overall (read+write) accesses 733system.cpu.itb_walker_cache.overall_accesses::total 12224 # number of overall (read+write) accesses 734system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.378252 # miss rate for ReadReq accesses 735system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.378252 # miss rate for ReadReq accesses 736system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.378190 # miss rate for demand accesses 737system.cpu.itb_walker_cache.demand_miss_rate::total 0.378190 # miss rate for demand accesses 738system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.378190 # miss rate for overall accesses 739system.cpu.itb_walker_cache.overall_miss_rate::total 0.378190 # miss rate for overall accesses 740system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10275.740861 # average ReadReq miss latency 741system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10275.740861 # average ReadReq miss latency 742system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency 743system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10275.740861 # average overall miss latency 744system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency 745system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10275.740861 # average overall miss latency | 751system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12280 # number of demand (read+write) accesses 752system.cpu.itb_walker_cache.demand_accesses::total 12280 # number of demand (read+write) accesses 753system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12280 # number of overall (read+write) accesses 754system.cpu.itb_walker_cache.overall_accesses::total 12280 # number of overall (read+write) accesses 755system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.369360 # miss rate for ReadReq accesses 756system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.369360 # miss rate for ReadReq accesses 757system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.369300 # miss rate for demand accesses 758system.cpu.itb_walker_cache.demand_miss_rate::total 0.369300 # miss rate for demand accesses 759system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.369300 # miss rate for overall accesses 760system.cpu.itb_walker_cache.overall_miss_rate::total 0.369300 # miss rate for overall accesses 761system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9968.853363 # average ReadReq miss latency 762system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9968.853363 # average ReadReq miss latency 763system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9968.853363 # average overall miss latency 764system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9968.853363 # average overall miss latency 765system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9968.853363 # average overall miss latency 766system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9968.853363 # average overall miss latency |
| 746system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 747system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 748system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 749system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 750system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 751system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 752system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 753system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 767system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 768system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 769system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 770system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 771system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 772system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 773system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 774system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 754system.cpu.itb_walker_cache.writebacks::writebacks 825 # number of writebacks 755system.cpu.itb_walker_cache.writebacks::total 825 # number of writebacks 756system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4623 # number of ReadReq MSHR misses 757system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4623 # number of ReadReq MSHR misses 758system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4623 # number of demand (read+write) MSHR misses 759system.cpu.itb_walker_cache.demand_mshr_misses::total 4623 # number of demand (read+write) MSHR misses 760system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4623 # number of overall MSHR misses 761system.cpu.itb_walker_cache.overall_mshr_misses::total 4623 # number of overall MSHR misses 762system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38257250 # number of ReadReq MSHR miss cycles 763system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38257250 # number of ReadReq MSHR miss cycles 764system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38257250 # number of demand (read+write) MSHR miss cycles 765system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38257250 # number of demand (read+write) MSHR miss cycles 766system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38257250 # number of overall MSHR miss cycles 767system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38257250 # number of overall MSHR miss cycles 768system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.378252 # mshr miss rate for ReadReq accesses 769system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.378252 # mshr miss rate for ReadReq accesses 770system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for demand accesses 771system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.378190 # mshr miss rate for demand accesses 772system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for overall accesses 773system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.378190 # mshr miss rate for overall accesses 774system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average ReadReq mshr miss latency 775system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8275.416396 # average ReadReq mshr miss latency 776system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency 777system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency 778system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency 779system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency | 775system.cpu.itb_walker_cache.writebacks::writebacks 782 # number of writebacks 776system.cpu.itb_walker_cache.writebacks::total 782 # number of writebacks 777system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4535 # number of ReadReq MSHR misses 778system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4535 # number of ReadReq MSHR misses 779system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4535 # number of demand (read+write) MSHR misses 780system.cpu.itb_walker_cache.demand_mshr_misses::total 4535 # number of demand (read+write) MSHR misses 781system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4535 # number of overall MSHR misses 782system.cpu.itb_walker_cache.overall_mshr_misses::total 4535 # number of overall MSHR misses 783system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 36137250 # number of ReadReq MSHR miss cycles 784system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 36137250 # number of ReadReq MSHR miss cycles 785system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 36137250 # number of demand (read+write) MSHR miss cycles 786system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 36137250 # number of demand (read+write) MSHR miss cycles 787system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 36137250 # number of overall MSHR miss cycles 788system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 36137250 # number of overall MSHR miss cycles 789system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.369360 # mshr miss rate for ReadReq accesses 790system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.369360 # mshr miss rate for ReadReq accesses 791system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.369300 # mshr miss rate for demand accesses 792system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.369300 # mshr miss rate for demand accesses 793system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.369300 # mshr miss rate for overall accesses 794system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.369300 # mshr miss rate for overall accesses 795system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average ReadReq mshr miss latency 796system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7968.522602 # average ReadReq mshr miss latency 797system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average overall mshr miss latency 798system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7968.522602 # average overall mshr miss latency 799system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average overall mshr miss latency 800system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7968.522602 # average overall mshr miss latency |
| 780system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 801system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 781system.cpu.l2cache.tags.replacements 87384 # number of replacements 782system.cpu.l2cache.tags.tagsinuse 64746.924059 # Cycle average of tags in use 783system.cpu.l2cache.tags.total_refs 3489247 # Total number of references to valid blocks. 784system.cpu.l2cache.tags.sampled_refs 152088 # Sample count of references to valid blocks. 785system.cpu.l2cache.tags.avg_refs 22.942290 # Average number of references to valid blocks. | 802system.cpu.l2cache.tags.replacements 87090 # number of replacements 803system.cpu.l2cache.tags.tagsinuse 64747.295038 # Cycle average of tags in use 804system.cpu.l2cache.tags.total_refs 3489215 # Total number of references to valid blocks. 805system.cpu.l2cache.tags.sampled_refs 151848 # Sample count of references to valid blocks. 806system.cpu.l2cache.tags.avg_refs 22.978340 # Average number of references to valid blocks. |
| 786system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 807system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 787system.cpu.l2cache.tags.occ_blocks::writebacks 50375.433193 # Average occupied blocks per requestor 788system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006760 # Average occupied blocks per requestor 789system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141629 # Average occupied blocks per requestor 790system.cpu.l2cache.tags.occ_blocks::cpu.inst 3244.771000 # Average occupied blocks per requestor 791system.cpu.l2cache.tags.occ_blocks::cpu.data 11126.571476 # Average occupied blocks per requestor 792system.cpu.l2cache.tags.occ_percent::writebacks 0.768668 # Average percentage of cache occupancy | 808system.cpu.l2cache.tags.occ_blocks::writebacks 50370.250728 # Average occupied blocks per requestor 809system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.007923 # Average occupied blocks per requestor 810system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141558 # Average occupied blocks per requestor 811system.cpu.l2cache.tags.occ_blocks::cpu.inst 3248.489299 # Average occupied blocks per requestor 812system.cpu.l2cache.tags.occ_blocks::cpu.data 11128.405530 # Average occupied blocks per requestor 813system.cpu.l2cache.tags.occ_percent::writebacks 0.768589 # Average percentage of cache occupancy |
| 793system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 794system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 814system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 815system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 795system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049511 # Average percentage of cache occupancy 796system.cpu.l2cache.tags.occ_percent::cpu.data 0.169778 # Average percentage of cache occupancy 797system.cpu.l2cache.tags.occ_percent::total 0.987960 # Average percentage of cache occupancy 798system.cpu.l2cache.tags.occ_task_id_blocks::1024 64704 # Occupied blocks per task id 799system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 800system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 801system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2830 # Occupied blocks per task id 802system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4041 # Occupied blocks per task id 803system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57717 # Occupied blocks per task id 804system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987305 # Percentage of cache occupancy per task id 805system.cpu.l2cache.tags.tag_accesses 32214708 # Number of tag accesses 806system.cpu.l2cache.tags.data_accesses 32214708 # Number of data accesses 807system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6577 # number of ReadReq hits 808system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3185 # number of ReadReq hits 809system.cpu.l2cache.ReadReq_hits::cpu.inst 778918 # number of ReadReq hits 810system.cpu.l2cache.ReadReq_hits::cpu.data 1279822 # number of ReadReq hits 811system.cpu.l2cache.ReadReq_hits::total 2068502 # number of ReadReq hits 812system.cpu.l2cache.Writeback_hits::writebacks 1542758 # number of Writeback hits 813system.cpu.l2cache.Writeback_hits::total 1542758 # number of Writeback hits 814system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits 815system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits 816system.cpu.l2cache.ReadExReq_hits::cpu.data 199803 # number of ReadExReq hits 817system.cpu.l2cache.ReadExReq_hits::total 199803 # number of ReadExReq hits 818system.cpu.l2cache.demand_hits::cpu.dtb.walker 6577 # number of demand (read+write) hits 819system.cpu.l2cache.demand_hits::cpu.itb.walker 3185 # number of demand (read+write) hits 820system.cpu.l2cache.demand_hits::cpu.inst 778918 # number of demand (read+write) hits 821system.cpu.l2cache.demand_hits::cpu.data 1479625 # number of demand (read+write) hits 822system.cpu.l2cache.demand_hits::total 2268305 # number of demand (read+write) hits 823system.cpu.l2cache.overall_hits::cpu.dtb.walker 6577 # number of overall hits 824system.cpu.l2cache.overall_hits::cpu.itb.walker 3185 # number of overall hits 825system.cpu.l2cache.overall_hits::cpu.inst 778918 # number of overall hits 826system.cpu.l2cache.overall_hits::cpu.data 1479625 # number of overall hits 827system.cpu.l2cache.overall_hits::total 2268305 # number of overall hits | 816system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049568 # Average percentage of cache occupancy 817system.cpu.l2cache.tags.occ_percent::cpu.data 0.169806 # Average percentage of cache occupancy 818system.cpu.l2cache.tags.occ_percent::total 0.987965 # Average percentage of cache occupancy 819system.cpu.l2cache.tags.occ_task_id_blocks::1024 64758 # Occupied blocks per task id 820system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 821system.cpu.l2cache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id 822system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2868 # Occupied blocks per task id 823system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4655 # Occupied blocks per task id 824system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57121 # Occupied blocks per task id 825system.cpu.l2cache.tags.occ_task_id_percent::1024 0.988129 # Percentage of cache occupancy per task id 826system.cpu.l2cache.tags.tag_accesses 32220029 # Number of tag accesses 827system.cpu.l2cache.tags.data_accesses 32220029 # Number of data accesses 828system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6582 # number of ReadReq hits 829system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2969 # number of ReadReq hits 830system.cpu.l2cache.ReadReq_hits::cpu.inst 778852 # number of ReadReq hits 831system.cpu.l2cache.ReadReq_hits::cpu.data 1280153 # number of ReadReq hits 832system.cpu.l2cache.ReadReq_hits::total 2068556 # number of ReadReq hits 833system.cpu.l2cache.Writeback_hits::writebacks 1543232 # number of Writeback hits 834system.cpu.l2cache.Writeback_hits::total 1543232 # number of Writeback hits 835system.cpu.l2cache.UpgradeReq_hits::cpu.data 331 # number of UpgradeReq hits 836system.cpu.l2cache.UpgradeReq_hits::total 331 # number of UpgradeReq hits 837system.cpu.l2cache.ReadExReq_hits::cpu.data 200337 # number of ReadExReq hits 838system.cpu.l2cache.ReadExReq_hits::total 200337 # number of ReadExReq hits 839system.cpu.l2cache.demand_hits::cpu.dtb.walker 6582 # number of demand (read+write) hits 840system.cpu.l2cache.demand_hits::cpu.itb.walker 2969 # number of demand (read+write) hits 841system.cpu.l2cache.demand_hits::cpu.inst 778852 # number of demand (read+write) hits 842system.cpu.l2cache.demand_hits::cpu.data 1480490 # number of demand (read+write) hits 843system.cpu.l2cache.demand_hits::total 2268893 # number of demand (read+write) hits 844system.cpu.l2cache.overall_hits::cpu.dtb.walker 6582 # number of overall hits 845system.cpu.l2cache.overall_hits::cpu.itb.walker 2969 # number of overall hits 846system.cpu.l2cache.overall_hits::cpu.inst 778852 # number of overall hits 847system.cpu.l2cache.overall_hits::cpu.data 1480490 # number of overall hits 848system.cpu.l2cache.overall_hits::total 2268893 # number of overall hits |
| 828system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 829system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses | 849system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 850system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses |
| 830system.cpu.l2cache.ReadReq_misses::cpu.inst 12960 # number of ReadReq misses 831system.cpu.l2cache.ReadReq_misses::cpu.data 28635 # number of ReadReq misses 832system.cpu.l2cache.ReadReq_misses::total 41601 # number of ReadReq misses 833system.cpu.l2cache.UpgradeReq_misses::cpu.data 1351 # number of UpgradeReq misses 834system.cpu.l2cache.UpgradeReq_misses::total 1351 # number of UpgradeReq misses 835system.cpu.l2cache.ReadExReq_misses::cpu.data 113819 # number of ReadExReq misses 836system.cpu.l2cache.ReadExReq_misses::total 113819 # number of ReadExReq misses | 851system.cpu.l2cache.ReadReq_misses::cpu.inst 12945 # number of ReadReq misses 852system.cpu.l2cache.ReadReq_misses::cpu.data 28645 # number of ReadReq misses 853system.cpu.l2cache.ReadReq_misses::total 41596 # number of ReadReq misses 854system.cpu.l2cache.UpgradeReq_misses::cpu.data 1332 # number of UpgradeReq misses 855system.cpu.l2cache.UpgradeReq_misses::total 1332 # number of UpgradeReq misses 856system.cpu.l2cache.ReadExReq_misses::cpu.data 113458 # number of ReadExReq misses 857system.cpu.l2cache.ReadExReq_misses::total 113458 # number of ReadExReq misses |
| 837system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 838system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses | 858system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 859system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses |
| 839system.cpu.l2cache.demand_misses::cpu.inst 12960 # number of demand (read+write) misses 840system.cpu.l2cache.demand_misses::cpu.data 142454 # number of demand (read+write) misses 841system.cpu.l2cache.demand_misses::total 155420 # number of demand (read+write) misses | 860system.cpu.l2cache.demand_misses::cpu.inst 12945 # number of demand (read+write) misses 861system.cpu.l2cache.demand_misses::cpu.data 142103 # number of demand (read+write) misses 862system.cpu.l2cache.demand_misses::total 155054 # number of demand (read+write) misses |
| 842system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 843system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses | 863system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 864system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses |
| 844system.cpu.l2cache.overall_misses::cpu.inst 12960 # number of overall misses 845system.cpu.l2cache.overall_misses::cpu.data 142454 # number of overall misses 846system.cpu.l2cache.overall_misses::total 155420 # number of overall misses | 865system.cpu.l2cache.overall_misses::cpu.inst 12945 # number of overall misses 866system.cpu.l2cache.overall_misses::cpu.data 142103 # number of overall misses 867system.cpu.l2cache.overall_misses::total 155054 # number of overall misses |
| 847system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles 848system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 350750 # number of ReadReq miss cycles | 868system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles 869system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 350750 # number of ReadReq miss cycles |
| 849system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 953249250 # number of ReadReq miss cycles 850system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2133765000 # number of ReadReq miss cycles 851system.cpu.l2cache.ReadReq_miss_latency::total 3087454250 # number of ReadReq miss cycles 852system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15012361 # number of UpgradeReq miss cycles 853system.cpu.l2cache.UpgradeReq_miss_latency::total 15012361 # number of UpgradeReq miss cycles 854system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7880712972 # number of ReadExReq miss cycles 855system.cpu.l2cache.ReadExReq_miss_latency::total 7880712972 # number of ReadExReq miss cycles | 870system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 951041750 # number of ReadReq miss cycles 871system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2142471500 # number of ReadReq miss cycles 872system.cpu.l2cache.ReadReq_miss_latency::total 3093953250 # number of ReadReq miss cycles 873system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16007872 # number of UpgradeReq miss cycles 874system.cpu.l2cache.UpgradeReq_miss_latency::total 16007872 # number of UpgradeReq miss cycles 875system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7848897720 # number of ReadExReq miss cycles 876system.cpu.l2cache.ReadExReq_miss_latency::total 7848897720 # number of ReadExReq miss cycles |
| 856system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles 857system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 350750 # number of demand (read+write) miss cycles | 877system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles 878system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 350750 # number of demand (read+write) miss cycles |
| 858system.cpu.l2cache.demand_miss_latency::cpu.inst 953249250 # number of demand (read+write) miss cycles 859system.cpu.l2cache.demand_miss_latency::cpu.data 10014477972 # number of demand (read+write) miss cycles 860system.cpu.l2cache.demand_miss_latency::total 10968167222 # number of demand (read+write) miss cycles | 879system.cpu.l2cache.demand_miss_latency::cpu.inst 951041750 # number of demand (read+write) miss cycles 880system.cpu.l2cache.demand_miss_latency::cpu.data 9991369220 # number of demand (read+write) miss cycles 881system.cpu.l2cache.demand_miss_latency::total 10942850970 # number of demand (read+write) miss cycles |
| 861system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles 862system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 350750 # number of overall miss cycles | 882system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles 883system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 350750 # number of overall miss cycles |
| 863system.cpu.l2cache.overall_miss_latency::cpu.inst 953249250 # number of overall miss cycles 864system.cpu.l2cache.overall_miss_latency::cpu.data 10014477972 # number of overall miss cycles 865system.cpu.l2cache.overall_miss_latency::total 10968167222 # number of overall miss cycles 866system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6578 # number of ReadReq accesses(hits+misses) 867system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3190 # number of ReadReq accesses(hits+misses) 868system.cpu.l2cache.ReadReq_accesses::cpu.inst 791878 # number of ReadReq accesses(hits+misses) 869system.cpu.l2cache.ReadReq_accesses::cpu.data 1308457 # number of ReadReq accesses(hits+misses) 870system.cpu.l2cache.ReadReq_accesses::total 2110103 # number of ReadReq accesses(hits+misses) 871system.cpu.l2cache.Writeback_accesses::writebacks 1542758 # number of Writeback accesses(hits+misses) 872system.cpu.l2cache.Writeback_accesses::total 1542758 # number of Writeback accesses(hits+misses) 873system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1672 # number of UpgradeReq accesses(hits+misses) 874system.cpu.l2cache.UpgradeReq_accesses::total 1672 # number of UpgradeReq accesses(hits+misses) 875system.cpu.l2cache.ReadExReq_accesses::cpu.data 313622 # number of ReadExReq accesses(hits+misses) 876system.cpu.l2cache.ReadExReq_accesses::total 313622 # number of ReadExReq accesses(hits+misses) 877system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6578 # number of demand (read+write) accesses 878system.cpu.l2cache.demand_accesses::cpu.itb.walker 3190 # number of demand (read+write) accesses 879system.cpu.l2cache.demand_accesses::cpu.inst 791878 # number of demand (read+write) accesses 880system.cpu.l2cache.demand_accesses::cpu.data 1622079 # number of demand (read+write) accesses 881system.cpu.l2cache.demand_accesses::total 2423725 # number of demand (read+write) accesses 882system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6578 # number of overall (read+write) accesses 883system.cpu.l2cache.overall_accesses::cpu.itb.walker 3190 # number of overall (read+write) accesses 884system.cpu.l2cache.overall_accesses::cpu.inst 791878 # number of overall (read+write) accesses 885system.cpu.l2cache.overall_accesses::cpu.data 1622079 # number of overall (read+write) accesses 886system.cpu.l2cache.overall_accesses::total 2423725 # number of overall (read+write) accesses | 884system.cpu.l2cache.overall_miss_latency::cpu.inst 951041750 # number of overall miss cycles 885system.cpu.l2cache.overall_miss_latency::cpu.data 9991369220 # number of overall miss cycles 886system.cpu.l2cache.overall_miss_latency::total 10942850970 # number of overall miss cycles 887system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6583 # number of ReadReq accesses(hits+misses) 888system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2974 # number of ReadReq accesses(hits+misses) 889system.cpu.l2cache.ReadReq_accesses::cpu.inst 791797 # number of ReadReq accesses(hits+misses) 890system.cpu.l2cache.ReadReq_accesses::cpu.data 1308798 # number of ReadReq accesses(hits+misses) 891system.cpu.l2cache.ReadReq_accesses::total 2110152 # number of ReadReq accesses(hits+misses) 892system.cpu.l2cache.Writeback_accesses::writebacks 1543232 # number of Writeback accesses(hits+misses) 893system.cpu.l2cache.Writeback_accesses::total 1543232 # number of Writeback accesses(hits+misses) 894system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1663 # number of UpgradeReq accesses(hits+misses) 895system.cpu.l2cache.UpgradeReq_accesses::total 1663 # number of UpgradeReq accesses(hits+misses) 896system.cpu.l2cache.ReadExReq_accesses::cpu.data 313795 # number of ReadExReq accesses(hits+misses) 897system.cpu.l2cache.ReadExReq_accesses::total 313795 # number of ReadExReq accesses(hits+misses) 898system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6583 # number of demand (read+write) accesses 899system.cpu.l2cache.demand_accesses::cpu.itb.walker 2974 # number of demand (read+write) accesses 900system.cpu.l2cache.demand_accesses::cpu.inst 791797 # number of demand (read+write) accesses 901system.cpu.l2cache.demand_accesses::cpu.data 1622593 # number of demand (read+write) accesses 902system.cpu.l2cache.demand_accesses::total 2423947 # number of demand (read+write) accesses 903system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6583 # number of overall (read+write) accesses 904system.cpu.l2cache.overall_accesses::cpu.itb.walker 2974 # number of overall (read+write) accesses 905system.cpu.l2cache.overall_accesses::cpu.inst 791797 # number of overall (read+write) accesses 906system.cpu.l2cache.overall_accesses::cpu.data 1622593 # number of overall (read+write) accesses 907system.cpu.l2cache.overall_accesses::total 2423947 # number of overall (read+write) accesses |
| 887system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000152 # miss rate for ReadReq accesses | 908system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000152 # miss rate for ReadReq accesses |
| 888system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001567 # miss rate for ReadReq accesses 889system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016366 # miss rate for ReadReq accesses 890system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021885 # miss rate for ReadReq accesses 891system.cpu.l2cache.ReadReq_miss_rate::total 0.019715 # miss rate for ReadReq accesses 892system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808014 # miss rate for UpgradeReq accesses 893system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808014 # miss rate for UpgradeReq accesses 894system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362918 # miss rate for ReadExReq accesses 895system.cpu.l2cache.ReadExReq_miss_rate::total 0.362918 # miss rate for ReadExReq accesses | 909system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001681 # miss rate for ReadReq accesses 910system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016349 # miss rate for ReadReq accesses 911system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021886 # miss rate for ReadReq accesses 912system.cpu.l2cache.ReadReq_miss_rate::total 0.019712 # miss rate for ReadReq accesses 913system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800962 # miss rate for UpgradeReq accesses 914system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800962 # miss rate for UpgradeReq accesses 915system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361567 # miss rate for ReadExReq accesses 916system.cpu.l2cache.ReadExReq_miss_rate::total 0.361567 # miss rate for ReadExReq accesses |
| 896system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000152 # miss rate for demand accesses | 917system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000152 # miss rate for demand accesses |
| 897system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001567 # miss rate for demand accesses 898system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016366 # miss rate for demand accesses 899system.cpu.l2cache.demand_miss_rate::cpu.data 0.087822 # miss rate for demand accesses 900system.cpu.l2cache.demand_miss_rate::total 0.064124 # miss rate for demand accesses | 918system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001681 # miss rate for demand accesses 919system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016349 # miss rate for demand accesses 920system.cpu.l2cache.demand_miss_rate::cpu.data 0.087578 # miss rate for demand accesses 921system.cpu.l2cache.demand_miss_rate::total 0.063968 # miss rate for demand accesses |
| 901system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000152 # miss rate for overall accesses | 922system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000152 # miss rate for overall accesses |
| 902system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001567 # miss rate for overall accesses 903system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016366 # miss rate for overall accesses 904system.cpu.l2cache.overall_miss_rate::cpu.data 0.087822 # miss rate for overall accesses 905system.cpu.l2cache.overall_miss_rate::total 0.064124 # miss rate for overall accesses | 923system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001681 # miss rate for overall accesses 924system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016349 # miss rate for overall accesses 925system.cpu.l2cache.overall_miss_rate::cpu.data 0.087578 # miss rate for overall accesses 926system.cpu.l2cache.overall_miss_rate::total 0.063968 # miss rate for overall accesses |
| 906system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency 907system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 70150 # average ReadReq miss latency | 927system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency 928system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 70150 # average ReadReq miss latency |
| 908system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73553.182870 # average ReadReq miss latency 909system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74515.976951 # average ReadReq miss latency 910system.cpu.l2cache.ReadReq_avg_miss_latency::total 74215.866205 # average ReadReq miss latency 911system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11112.036269 # average UpgradeReq miss latency 912system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11112.036269 # average UpgradeReq miss latency 913system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.993244 # average ReadExReq miss latency 914system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.993244 # average ReadExReq miss latency | 929system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73467.883353 # average ReadReq miss latency 930system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74793.908186 # average ReadReq miss latency 931system.cpu.l2cache.ReadReq_avg_miss_latency::total 74381.028224 # average ReadReq miss latency 932system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12017.921922 # average UpgradeReq miss latency 933system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12017.921922 # average UpgradeReq miss latency 934system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69178.883111 # average ReadExReq miss latency 935system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69178.883111 # average ReadExReq miss latency |
| 915system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 916system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency | 936system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 937system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency |
| 917system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73553.182870 # average overall miss latency 918system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70299.731647 # average overall miss latency 919system.cpu.l2cache.demand_avg_miss_latency::total 70571.144138 # average overall miss latency | 938system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73467.883353 # average overall miss latency 939system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70310.755016 # average overall miss latency 940system.cpu.l2cache.demand_avg_miss_latency::total 70574.451288 # average overall miss latency |
| 920system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 921system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency | 941system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 942system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency |
| 922system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73553.182870 # average overall miss latency 923system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70299.731647 # average overall miss latency 924system.cpu.l2cache.overall_avg_miss_latency::total 70571.144138 # average overall miss latency | 943system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73467.883353 # average overall miss latency 944system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70310.755016 # average overall miss latency 945system.cpu.l2cache.overall_avg_miss_latency::total 70574.451288 # average overall miss latency |
| 925system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 926system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 927system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 928system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 929system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 930system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 931system.cpu.l2cache.fast_writes 0 # number of fast writes performed 932system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 946system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 947system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 948system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 949system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 950system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 951system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 952system.cpu.l2cache.fast_writes 0 # number of fast writes performed 953system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 933system.cpu.l2cache.writebacks::writebacks 80466 # number of writebacks 934system.cpu.l2cache.writebacks::total 80466 # number of writebacks | 954system.cpu.l2cache.writebacks::writebacks 80112 # number of writebacks 955system.cpu.l2cache.writebacks::total 80112 # number of writebacks |
| 935system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses 936system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses | 956system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses 957system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses |
| 937system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12960 # number of ReadReq MSHR misses 938system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28635 # number of ReadReq MSHR misses 939system.cpu.l2cache.ReadReq_mshr_misses::total 41601 # number of ReadReq MSHR misses 940system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1351 # number of UpgradeReq MSHR misses 941system.cpu.l2cache.UpgradeReq_mshr_misses::total 1351 # number of UpgradeReq MSHR misses 942system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113819 # number of ReadExReq MSHR misses 943system.cpu.l2cache.ReadExReq_mshr_misses::total 113819 # number of ReadExReq MSHR misses | 958system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12945 # number of ReadReq MSHR misses 959system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28645 # number of ReadReq MSHR misses 960system.cpu.l2cache.ReadReq_mshr_misses::total 41596 # number of ReadReq MSHR misses 961system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1332 # number of UpgradeReq MSHR misses 962system.cpu.l2cache.UpgradeReq_mshr_misses::total 1332 # number of UpgradeReq MSHR misses 963system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113458 # number of ReadExReq MSHR misses 964system.cpu.l2cache.ReadExReq_mshr_misses::total 113458 # number of ReadExReq MSHR misses |
| 944system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses 945system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses | 965system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses 966system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses |
| 946system.cpu.l2cache.demand_mshr_misses::cpu.inst 12960 # number of demand (read+write) MSHR misses 947system.cpu.l2cache.demand_mshr_misses::cpu.data 142454 # number of demand (read+write) MSHR misses 948system.cpu.l2cache.demand_mshr_misses::total 155420 # number of demand (read+write) MSHR misses | 967system.cpu.l2cache.demand_mshr_misses::cpu.inst 12945 # number of demand (read+write) MSHR misses 968system.cpu.l2cache.demand_mshr_misses::cpu.data 142103 # number of demand (read+write) MSHR misses 969system.cpu.l2cache.demand_mshr_misses::total 155054 # number of demand (read+write) MSHR misses |
| 949system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses 950system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses | 970system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses 971system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses |
| 951system.cpu.l2cache.overall_mshr_misses::cpu.inst 12960 # number of overall MSHR misses 952system.cpu.l2cache.overall_mshr_misses::cpu.data 142454 # number of overall MSHR misses 953system.cpu.l2cache.overall_mshr_misses::total 155420 # number of overall MSHR misses | 972system.cpu.l2cache.overall_mshr_misses::cpu.inst 12945 # number of overall MSHR misses 973system.cpu.l2cache.overall_mshr_misses::cpu.data 142103 # number of overall MSHR misses 974system.cpu.l2cache.overall_mshr_misses::total 155054 # number of overall MSHR misses |
| 954system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles 955system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287750 # number of ReadReq MSHR miss cycles | 975system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles 976system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287750 # number of ReadReq MSHR miss cycles |
| 956system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 790892250 # number of ReadReq MSHR miss cycles 957system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1774999000 # number of ReadReq MSHR miss cycles 958system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2566255250 # number of ReadReq MSHR miss cycles 959system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13524351 # number of UpgradeReq MSHR miss cycles 960system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13524351 # number of UpgradeReq MSHR miss cycles 961system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6458128028 # number of ReadExReq MSHR miss cycles 962system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6458128028 # number of ReadExReq MSHR miss cycles | 977system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 788869250 # number of ReadReq MSHR miss cycles 978system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1783855500 # number of ReadReq MSHR miss cycles 979system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2573088750 # number of ReadReq MSHR miss cycles 980system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14201815 # number of UpgradeReq MSHR miss cycles 981system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14201815 # number of UpgradeReq MSHR miss cycles 982system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6430736280 # number of ReadExReq MSHR miss cycles 983system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6430736280 # number of ReadExReq MSHR miss cycles |
| 963system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles 964system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles | 984system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles 985system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles |
| 965system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 790892250 # number of demand (read+write) MSHR miss cycles 966system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8233127028 # number of demand (read+write) MSHR miss cycles 967system.cpu.l2cache.demand_mshr_miss_latency::total 9024383278 # number of demand (read+write) MSHR miss cycles | 986system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 788869250 # number of demand (read+write) MSHR miss cycles 987system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8214591780 # number of demand (read+write) MSHR miss cycles 988system.cpu.l2cache.demand_mshr_miss_latency::total 9003825030 # number of demand (read+write) MSHR miss cycles |
| 968system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles 969system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles | 989system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles 990system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles |
| 970system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 790892250 # number of overall MSHR miss cycles 971system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8233127028 # number of overall MSHR miss cycles 972system.cpu.l2cache.overall_mshr_miss_latency::total 9024383278 # number of overall MSHR miss cycles | 991system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 788869250 # number of overall MSHR miss cycles 992system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8214591780 # number of overall MSHR miss cycles 993system.cpu.l2cache.overall_mshr_miss_latency::total 9003825030 # number of overall MSHR miss cycles |
| 973system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86680074500 # number of ReadReq MSHR uncacheable cycles 974system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86680074500 # number of ReadReq MSHR uncacheable cycles | 994system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86680074500 # number of ReadReq MSHR uncacheable cycles 995system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86680074500 # number of ReadReq MSHR uncacheable cycles |
| 975system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2394893500 # number of WriteReq MSHR uncacheable cycles 976system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2394893500 # number of WriteReq MSHR uncacheable cycles 977system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89074968000 # number of overall MSHR uncacheable cycles 978system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89074968000 # number of overall MSHR uncacheable cycles | 996system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2395003500 # number of WriteReq MSHR uncacheable cycles 997system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2395003500 # number of WriteReq MSHR uncacheable cycles 998system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89075078000 # number of overall MSHR uncacheable cycles 999system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89075078000 # number of overall MSHR uncacheable cycles |
| 979system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for ReadReq accesses | 1000system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for ReadReq accesses |
| 980system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for ReadReq accesses 981system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for ReadReq accesses 982system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021885 # mshr miss rate for ReadReq accesses 983system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019715 # mshr miss rate for ReadReq accesses 984system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808014 # mshr miss rate for UpgradeReq accesses 985system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808014 # mshr miss rate for UpgradeReq accesses 986system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362918 # mshr miss rate for ReadExReq accesses 987system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362918 # mshr miss rate for ReadExReq accesses | 1001system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for ReadReq accesses 1002system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for ReadReq accesses 1003system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021886 # mshr miss rate for ReadReq accesses 1004system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019712 # mshr miss rate for ReadReq accesses 1005system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800962 # mshr miss rate for UpgradeReq accesses 1006system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800962 # mshr miss rate for UpgradeReq accesses 1007system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361567 # mshr miss rate for ReadExReq accesses 1008system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361567 # mshr miss rate for ReadExReq accesses |
| 988system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for demand accesses | 1009system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for demand accesses |
| 989system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for demand accesses 990system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for demand accesses 991system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087822 # mshr miss rate for demand accesses 992system.cpu.l2cache.demand_mshr_miss_rate::total 0.064124 # mshr miss rate for demand accesses | 1010system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for demand accesses 1011system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for demand accesses 1012system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087578 # mshr miss rate for demand accesses 1013system.cpu.l2cache.demand_mshr_miss_rate::total 0.063968 # mshr miss rate for demand accesses |
| 993system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for overall accesses | 1014system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for overall accesses |
| 994system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for overall accesses 995system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for overall accesses 996system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087822 # mshr miss rate for overall accesses 997system.cpu.l2cache.overall_mshr_miss_rate::total 0.064124 # mshr miss rate for overall accesses | 1015system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for overall accesses 1016system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for overall accesses 1017system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087578 # mshr miss rate for overall accesses 1018system.cpu.l2cache.overall_mshr_miss_rate::total 0.063968 # mshr miss rate for overall accesses |
| 998system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency 999system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency | 1019system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency 1020system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency |
| 1000system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61025.636574 # average ReadReq mshr miss latency 1001system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61987.043827 # average ReadReq mshr miss latency 1002system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.345256 # average ReadReq mshr miss latency 1003system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.622502 # average UpgradeReq mshr miss latency 1004system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.622502 # average UpgradeReq mshr miss latency 1005system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56740.333582 # average ReadExReq mshr miss latency 1006system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56740.333582 # average ReadExReq mshr miss latency | 1021system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60940.073387 # average ReadReq mshr miss latency 1022system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62274.585442 # average ReadReq mshr miss latency 1023system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61859.042937 # average ReadReq mshr miss latency 1024system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10662.023273 # average UpgradeReq mshr miss latency 1025system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10662.023273 # average UpgradeReq mshr miss latency 1026system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56679.443318 # average ReadExReq mshr miss latency 1027system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56679.443318 # average ReadExReq mshr miss latency |
| 1007system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1008system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency | 1028system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1029system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency |
| 1009system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency 1010system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency | 1030system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency 1031system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency 1032system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency |
| 1012system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1013system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency | 1033system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1034system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency |
| 1014system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency 1015system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency | 1035system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency 1036system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency 1037system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency |
| 1017system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1018system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1019system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1020system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1021system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1022system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1023system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1038system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1039system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1040system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1041system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1042system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1043system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1044system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1024system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution 1025system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution 1026system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution 1027system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution 1028system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution 1029system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution 1030system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution 1031system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution 1032system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution 1033system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution 1034system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes) 1035system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes) 1036system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes) 1037system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes) 1038system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes) 1039system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes) 1040system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes) 1041system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) 1042system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes) 1043system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes) 1044system.cpu.toL2Bus.snoops 52938 # Total snoops (count) 1045system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram 1046system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram 1047system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram | 1045system.cpu.toL2Bus.trans_dist::ReadReq 2697337 # Transaction distribution 1046system.cpu.toL2Bus.trans_dist::ReadResp 2696818 # Transaction distribution 1047system.cpu.toL2Bus.trans_dist::WriteReq 13890 # Transaction distribution 1048system.cpu.toL2Bus.trans_dist::WriteResp 13890 # Transaction distribution 1049system.cpu.toL2Bus.trans_dist::Writeback 1543232 # Transaction distribution 1050system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1051system.cpu.toL2Bus.trans_dist::UpgradeReq 2201 # Transaction distribution 1052system.cpu.toL2Bus.trans_dist::UpgradeResp 2201 # Transaction distribution 1053system.cpu.toL2Bus.trans_dist::ReadExReq 313800 # Transaction distribution 1054system.cpu.toL2Bus.trans_dist::ReadExResp 313800 # Transaction distribution 1055system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583607 # Packet count per connected master and slave (bytes) 1056system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5980523 # Packet count per connected master and slave (bytes) 1057system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8291 # Packet count per connected master and slave (bytes) 1058system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18581 # Packet count per connected master and slave (bytes) 1059system.cpu.toL2Bus.pkt_count::total 7591002 # Packet count per connected master and slave (bytes) 1060system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50675008 # Cumulative packet size per connected master and slave (bytes) 1061system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204057491 # Cumulative packet size per connected master and slave (bytes) 1062system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 240384 # Cumulative packet size per connected master and slave (bytes) 1063system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 614272 # Cumulative packet size per connected master and slave (bytes) 1064system.cpu.toL2Bus.pkt_size::total 255587155 # Cumulative packet size per connected master and slave (bytes) 1065system.cpu.toL2Bus.snoops 53212 # Total snoops (count) 1066system.cpu.toL2Bus.snoop_fanout::samples 4021729 # Request fanout histogram 1067system.cpu.toL2Bus.snoop_fanout::mean 3.011827 # Request fanout histogram 1068system.cpu.toL2Bus.snoop_fanout::stdev 0.108106 # Request fanout histogram |
| 1048system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1049system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1050system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1051system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1069system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1070system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1071system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1072system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1052system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram 1053system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram | 1073system.cpu.toL2Bus.snoop_fanout::3 3974165 98.82% 98.82% # Request fanout histogram 1074system.cpu.toL2Bus.snoop_fanout::4 47564 1.18% 100.00% # Request fanout histogram |
| 1054system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1055system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1056system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 1075system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1076system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1077system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 1057system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram 1058system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks) | 1078system.cpu.toL2Bus.snoop_fanout::total 4021729 # Request fanout histogram 1079system.cpu.toL2Bus.reqLayer0.occupancy 3834985000 # Layer occupancy (ticks) |
| 1059system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1060system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) 1061system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1080system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1081system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) 1082system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1062system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks) | 1083system.cpu.toL2Bus.respLayer0.occupancy 1190158617 # Layer occupancy (ticks) |
| 1063system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1084system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1064system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks) | 1085system.cpu.toL2Bus.respLayer1.occupancy 3054984845 # Layer occupancy (ticks) |
| 1065system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1086system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1066system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks) | 1087system.cpu.toL2Bus.respLayer2.occupancy 6803250 # Layer occupancy (ticks) |
| 1067system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1088system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1068system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks) | 1089system.cpu.toL2Bus.respLayer3.occupancy 13474750 # Layer occupancy (ticks) |
| 1069system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1090system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1070system.iobus.trans_dist::ReadReq 230267 # Transaction distribution 1071system.iobus.trans_dist::ReadResp 230267 # Transaction distribution 1072system.iobus.trans_dist::WriteReq 57693 # Transaction distribution 1073system.iobus.trans_dist::WriteResp 57694 # Transaction distribution 1074system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution | 1091system.iobus.trans_dist::ReadReq 230264 # Transaction distribution 1092system.iobus.trans_dist::ReadResp 230264 # Transaction distribution 1093system.iobus.trans_dist::WriteReq 57694 # Transaction distribution 1094system.iobus.trans_dist::WriteResp 10974 # Transaction distribution 1095system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 1075system.iobus.trans_dist::MessageReq 1655 # Transaction distribution 1076system.iobus.trans_dist::MessageResp 1655 # Transaction distribution 1077system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1078system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1079system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1080system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1081system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1082system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 1088system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1089system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) 1090system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1091system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1092system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1093system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1094system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 1095system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) | 1096system.iobus.trans_dist::MessageReq 1655 # Transaction distribution 1097system.iobus.trans_dist::MessageResp 1655 # Transaction distribution 1098system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1099system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1100system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1101system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1102system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1103system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 1109system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1110system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) 1111system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1112system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1113system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1114system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1115system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 1116system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) |
| 1096system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes) 1097system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes) | 1117system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes) 1118system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes) |
| 1098system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) 1099system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) | 1119system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) 1120system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) |
| 1100system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes) | 1121system.iobus.pkt_count::total 579226 # Packet count per connected master and slave (bytes) |
| 1101system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1102system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1103system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1104system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1105system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1106system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1107system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1108system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1109system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 1110system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1111system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1112system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1113system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) 1114system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1115system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1116system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1117system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1118system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 1119system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) | 1122system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1123system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1124system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1125system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1126system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1127system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1128system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1129system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1130system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 1131system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1132system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1133system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1134system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) 1135system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1136system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1137system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1138system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1139system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 1140system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) |
| 1120system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes) 1121system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes) | 1141system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes) 1142system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes) |
| 1122system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) 1123system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) | 1143system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) 1144system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) |
| 1124system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes) | 1145system.iobus.pkt_size::total 3280590 # Cumulative packet size per connected master and slave (bytes) |
| 1125system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) 1126system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1127system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1128system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1129system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1130system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1131system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 1132system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) --- 20 unchanged lines hidden (view full) --- 1153system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1154system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1155system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1156system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1157system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1158system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1159system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1160system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) | 1146system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) 1147system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1148system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1149system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1150system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1151system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1152system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 1153system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) --- 20 unchanged lines hidden (view full) --- 1174system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1175system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1176system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1177system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1178system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1179system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1180system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1181system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) |
| 1161system.iobus.reqLayer19.occupancy 421906845 # Layer occupancy (ticks) | 1182system.iobus.reqLayer19.occupancy 448397612 # Layer occupancy (ticks) |
| 1162system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1163system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1164system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1165system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) 1166system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 1183system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1184system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1185system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1186system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) 1187system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1167system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks) | 1188system.iobus.respLayer1.occupancy 52228501 # Layer occupancy (ticks) |
| 1168system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1169system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) 1170system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) | 1189system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1190system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) 1191system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1171system.iocache.tags.replacements 47512 # number of replacements 1172system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use | 1192system.iocache.tags.replacements 47510 # number of replacements 1193system.iocache.tags.tagsinuse 0.132770 # Cycle average of tags in use |
| 1173system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 1194system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 1174system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks. | 1195system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks. |
| 1175system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 1196system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 1176system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit. 1177system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor 1178system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy 1179system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy | 1197system.iocache.tags.warmup_cycle 5045851378000 # Cycle when the warmup percentage was hit. 1198system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.132770 # Average occupied blocks per requestor 1199system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008298 # Average percentage of cache occupancy 1200system.iocache.tags.occ_percent::total 0.008298 # Average percentage of cache occupancy |
| 1180system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1181system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1182system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 1201system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1202system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1203system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 1183system.iocache.tags.tag_accesses 428111 # Number of tag accesses 1184system.iocache.tags.data_accesses 428111 # Number of data accesses 1185system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 1186system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits 1187system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses 1188system.iocache.ReadReq_misses::total 847 # number of ReadReq misses 1189system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses 1190system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses 1191system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses 1192system.iocache.demand_misses::total 847 # number of demand (read+write) misses 1193system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses 1194system.iocache.overall_misses::total 847 # number of overall misses 1195system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles 1196system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles 1197system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles 1198system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles 1199system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles 1200system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles 1201system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses) 1202system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses) 1203system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses) 1204system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses) 1205system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses 1206system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses 1207system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses 1208system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses | 1204system.iocache.tags.tag_accesses 428076 # Number of tag accesses 1205system.iocache.tags.data_accesses 428076 # Number of data accesses 1206system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses 1207system.iocache.ReadReq_misses::total 844 # number of ReadReq misses 1208system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 1209system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses 1210system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses 1211system.iocache.demand_misses::total 844 # number of demand (read+write) misses 1212system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses 1213system.iocache.overall_misses::total 844 # number of overall misses 1214system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143496186 # number of ReadReq miss cycles 1215system.iocache.ReadReq_miss_latency::total 143496186 # number of ReadReq miss cycles 1216system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12353940925 # number of WriteInvalidateReq miss cycles 1217system.iocache.WriteInvalidateReq_miss_latency::total 12353940925 # number of WriteInvalidateReq miss cycles 1218system.iocache.demand_miss_latency::pc.south_bridge.ide 143496186 # number of demand (read+write) miss cycles 1219system.iocache.demand_miss_latency::total 143496186 # number of demand (read+write) miss cycles 1220system.iocache.overall_miss_latency::pc.south_bridge.ide 143496186 # number of overall miss cycles 1221system.iocache.overall_miss_latency::total 143496186 # number of overall miss cycles 1222system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) 1223system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) 1224system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1225system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 1226system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses 1227system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses 1228system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses 1229system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses |
| 1209system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1210system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 1230system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1231system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 1211system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses 1212system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses | 1232system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 1233system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses |
| 1213system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1214system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1215system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1216system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 1234system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1235system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1236system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1237system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 1217system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency 1218system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency 1219system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency 1220system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency 1221system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency 1222system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency 1223system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked | 1238system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average ReadReq miss latency 1239system.iocache.ReadReq_avg_miss_latency::total 170019.177725 # average ReadReq miss latency 1240system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264425.105415 # average WriteInvalidateReq miss latency 1241system.iocache.WriteInvalidateReq_avg_miss_latency::total 264425.105415 # average WriteInvalidateReq miss latency 1242system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency 1243system.iocache.demand_avg_miss_latency::total 170019.177725 # average overall miss latency 1244system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency 1245system.iocache.overall_avg_miss_latency::total 170019.177725 # average overall miss latency 1246system.iocache.blocked_cycles::no_mshrs 70456 # number of cycles access was blocked |
| 1224system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1247system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1225system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked | 1248system.iocache.blocked::no_mshrs 9155 # number of cycles access was blocked |
| 1226system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 1249system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 1227system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked | 1250system.iocache.avg_blocked_cycles::no_mshrs 7.695904 # average number of cycles each access was blocked |
| 1228system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1251system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1229system.iocache.fast_writes 46720 # number of fast writes performed | 1252system.iocache.fast_writes 0 # number of fast writes performed |
| 1230system.iocache.cache_copies 0 # number of cache copies performed | 1253system.iocache.cache_copies 0 # number of cache copies performed |
| 1231system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses 1232system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses 1233system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses 1234system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses 1235system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses 1236system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses 1237system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles 1238system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles 1239system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles 1240system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles 1241system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles 1242system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles 1243system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles 1244system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles | 1254system.iocache.writebacks::writebacks 46668 # number of writebacks 1255system.iocache.writebacks::total 46668 # number of writebacks 1256system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses 1257system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses 1258system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 1259system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses 1260system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses 1261system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses 1262system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses 1263system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses 1264system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of ReadReq MSHR miss cycles 1265system.iocache.ReadReq_mshr_miss_latency::total 99583186 # number of ReadReq MSHR miss cycles 1266system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9924498927 # number of WriteInvalidateReq MSHR miss cycles 1267system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9924498927 # number of WriteInvalidateReq MSHR miss cycles 1268system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of demand (read+write) MSHR miss cycles 1269system.iocache.demand_mshr_miss_latency::total 99583186 # number of demand (read+write) MSHR miss cycles 1270system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of overall MSHR miss cycles 1271system.iocache.overall_mshr_miss_latency::total 99583186 # number of overall MSHR miss cycles |
| 1245system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1246system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 1272system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1273system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 1274system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1275system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses |
|
| 1247system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1248system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1249system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1250system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 1276system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1277system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1278system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1279system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 1251system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency 1252system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency 1253system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency 1254system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1255system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 1256system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency 1257system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 1258system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency | 1280system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average ReadReq mshr miss latency 1281system.iocache.ReadReq_avg_mshr_miss_latency::total 117989.556872 # average ReadReq mshr miss latency 1282system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212425.062650 # average WriteInvalidateReq mshr miss latency 1283system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212425.062650 # average WriteInvalidateReq mshr miss latency 1284system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency 1285system.iocache.demand_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency 1286system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency 1287system.iocache.overall_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency |
| 1259system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | 1288system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1260system.membus.trans_dist::ReadReq 624009 # Transaction distribution 1261system.membus.trans_dist::ReadResp 624009 # Transaction distribution 1262system.membus.trans_dist::WriteReq 13889 # Transaction distribution 1263system.membus.trans_dist::WriteResp 13889 # Transaction distribution 1264system.membus.trans_dist::Writeback 80466 # Transaction distribution | 1289system.membus.trans_dist::ReadReq 624001 # Transaction distribution 1290system.membus.trans_dist::ReadResp 624001 # Transaction distribution 1291system.membus.trans_dist::WriteReq 13890 # Transaction distribution 1292system.membus.trans_dist::WriteResp 13890 # Transaction distribution 1293system.membus.trans_dist::Writeback 126780 # Transaction distribution |
| 1265system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1266system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution | 1294system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1295system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 1267system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution 1268system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution 1269system.membus.trans_dist::ReadExReq 113541 # Transaction distribution 1270system.membus.trans_dist::ReadExResp 113541 # Transaction distribution | 1296system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution 1297system.membus.trans_dist::UpgradeResp 1612 # Transaction distribution 1298system.membus.trans_dist::ReadExReq 113178 # Transaction distribution 1299system.membus.trans_dist::ReadExResp 113178 # Transaction distribution |
| 1271system.membus.trans_dist::MessageReq 1655 # Transaction distribution 1272system.membus.trans_dist::MessageResp 1655 # Transaction distribution 1273system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) 1274system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) 1275system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) | 1300system.membus.trans_dist::MessageReq 1655 # Transaction distribution 1301system.membus.trans_dist::MessageResp 1655 # Transaction distribution 1302system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) 1303system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) 1304system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) |
| 1276system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes) 1277system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes) 1278system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes) 1279system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes) 1280system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes) 1281system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes) | 1305system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) 1306system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392754 # Packet count per connected master and slave (bytes) 1307system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1583656 # Packet count per connected master and slave (bytes) 1308system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141395 # Packet count per connected master and slave (bytes) 1309system.membus.pkt_count_system.iocache.mem_side::total 141395 # Packet count per connected master and slave (bytes) 1310system.membus.pkt_count::total 1728361 # Packet count per connected master and slave (bytes) |
| 1282system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) 1283system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) 1284system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) | 1311system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) 1312system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) 1313system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) |
| 1285system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes) 1286system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes) 1287system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes) 1288system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 1289system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 1290system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes) 1291system.membus.snoops 943 # Total snoops (count) 1292system.membus.snoop_fanout::samples 285344 # Request fanout histogram | 1314system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) 1315system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14991040 # Cumulative packet size per connected master and slave (bytes) 1316system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16657939 # Cumulative packet size per connected master and slave (bytes) 1317system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes) 1318system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes) 1319system.membus.pkt_size::total 22669743 # Cumulative packet size per connected master and slave (bytes) 1320system.membus.snoops 1607 # Total snoops (count) 1321system.membus.snoop_fanout::samples 331268 # Request fanout histogram |
| 1293system.membus.snoop_fanout::mean 1 # Request fanout histogram 1294system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1295system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1296system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 1322system.membus.snoop_fanout::mean 1 # Request fanout histogram 1323system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1324system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1325system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 1297system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram | 1326system.membus.snoop_fanout::1 331268 100.00% 100.00% # Request fanout histogram |
| 1298system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1299system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1300system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1301system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 1327system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1328system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1329system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1330system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1302system.membus.snoop_fanout::total 285344 # Request fanout histogram | 1331system.membus.snoop_fanout::total 331268 # Request fanout histogram |
| 1303system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) 1304system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 1332system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) 1333system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 1305system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks) | 1334system.membus.reqLayer1.occupancy 358100000 # Layer occupancy (ticks) |
| 1306system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1307system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) 1308system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 1335system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1336system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) 1337system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 1309system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks) | 1338system.membus.reqLayer3.occupancy 1728081500 # Layer occupancy (ticks) |
| 1310system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1311system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) 1312system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 1339system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1340system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) 1341system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1313system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks) | 1342system.membus.respLayer2.occupancy 2618580655 # Layer occupancy (ticks) |
| 1314system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 1343system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 1315system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks) | 1344system.membus.respLayer4.occupancy 54329499 # Layer occupancy (ticks) |
| 1316system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1317system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1318system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1319system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1320system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1321system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1322system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1323system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1324system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1325system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1326system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1327system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1328system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1329 1330---------- End Simulation Statistics ---------- | 1345system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1346system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1347system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1348system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1349system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1350system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1351system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1352system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1353system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1354system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1355system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1356system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1357system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1358 1359---------- End Simulation Statistics ---------- |