| stats.txt (10513:ca4438b6e39a) | stats.txt (10540:45204db420c0) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.194411 # Number of seconds simulated 4sim_ticks 5194410635000 # Number of ticks simulated 5final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.194411 # Number of seconds simulated 4sim_ticks 5194410635000 # Number of ticks simulated 5final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1079720 # Simulator instruction rate (inst/s) 8host_op_rate 2081347 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43672253601 # Simulator tick rate (ticks/s) 10host_mem_usage 589096 # Number of bytes of host memory used 11host_seconds 118.94 # Real time elapsed on the host | 7host_inst_rate 1282120 # Simulator instruction rate (inst/s) 8host_op_rate 2471507 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 51858853246 # Simulator tick rate (ticks/s) 10host_mem_usage 594916 # Number of bytes of host memory used 11host_seconds 100.16 # Real time elapsed on the host |
| 12sim_insts 128422722 # Number of instructions simulated 13sim_ops 247557000 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 128422722 # Number of instructions simulated 13sim_ops 247557000 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | |
| 17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
|
| 21system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory 26system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory | 21system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory 26system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory |
| 27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | |
| 28system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory | 27system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
|
| 32system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory | 32system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory |
| 36system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) | |
| 37system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s) |
| 40system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) |
|
| 41system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 991416 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s) | 41system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 991416 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s) |
| 48system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s) | |
| 49system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s) | 48system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s) |
| 52system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s) |
|
| 53system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 155585 # Number of read requests accepted 55system.physmem.writeReqs 127186 # Number of write requests accepted 56system.physmem.readBursts 155585 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 127186 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 9942720 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 14720 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8138624 # Total number of bytes written to DRAM --- 239 unchanged lines hidden (view full) --- 300system.physmem.actBackEnergy::0 134393532390 # Energy for active background per rank (pJ) 301system.physmem.actBackEnergy::1 134240531850 # Energy for active background per rank (pJ) 302system.physmem.preBackEnergy::0 2998756974750 # Energy for precharge background per rank (pJ) 303system.physmem.preBackEnergy::1 2998891185750 # Energy for precharge background per rank (pJ) 304system.physmem.totalEnergy::0 3473770745370 # Total energy per rank (pJ) 305system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ) 306system.physmem.averagePower::0 668.751736 # Core power per rank (mW) 307system.physmem.averagePower::1 668.747452 # Core power per rank (mW) | 53system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 155585 # Number of read requests accepted 55system.physmem.writeReqs 127186 # Number of write requests accepted 56system.physmem.readBursts 155585 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 127186 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 9942720 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 14720 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8138624 # Total number of bytes written to DRAM --- 239 unchanged lines hidden (view full) --- 300system.physmem.actBackEnergy::0 134393532390 # Energy for active background per rank (pJ) 301system.physmem.actBackEnergy::1 134240531850 # Energy for active background per rank (pJ) 302system.physmem.preBackEnergy::0 2998756974750 # Energy for precharge background per rank (pJ) 303system.physmem.preBackEnergy::1 2998891185750 # Energy for precharge background per rank (pJ) 304system.physmem.totalEnergy::0 3473770745370 # Total energy per rank (pJ) 305system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ) 306system.physmem.averagePower::0 668.751736 # Core power per rank (mW) 307system.physmem.averagePower::1 668.747452 # Core power per rank (mW) |
| 308system.membus.trans_dist::ReadReq 624009 # Transaction distribution 309system.membus.trans_dist::ReadResp 624009 # Transaction distribution 310system.membus.trans_dist::WriteReq 13889 # Transaction distribution 311system.membus.trans_dist::WriteResp 13889 # Transaction distribution 312system.membus.trans_dist::Writeback 80466 # Transaction distribution 313system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 314system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 315system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution 316system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution 317system.membus.trans_dist::ReadExReq 113541 # Transaction distribution 318system.membus.trans_dist::ReadExResp 113541 # Transaction distribution 319system.membus.trans_dist::MessageReq 1655 # Transaction distribution 320system.membus.trans_dist::MessageResp 1655 # Transaction distribution 321system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) 322system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) 323system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) 324system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes) 325system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes) 326system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes) 330system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) 331system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) 332system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) 333system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes) 334system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes) 335system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes) 336system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 337system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 338system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes) 339system.membus.snoops 943 # Total snoops (count) 340system.membus.snoop_fanout::samples 285344 # Request fanout histogram 341system.membus.snoop_fanout::mean 1 # Request fanout histogram 342system.membus.snoop_fanout::stdev 0 # Request fanout histogram 343system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 344system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 345system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram 346system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 347system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 348system.membus.snoop_fanout::min_value 1 # Request fanout histogram 349system.membus.snoop_fanout::max_value 1 # Request fanout histogram 350system.membus.snoop_fanout::total 285344 # Request fanout histogram 351system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) 352system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 353system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks) 354system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 355system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) 356system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 357system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks) 358system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 359system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) 360system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 361system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks) 362system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 363system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks) 364system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 365system.iocache.tags.replacements 47512 # number of replacements 366system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use 367system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 368system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks. 369system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 370system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit. 371system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor 372system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy 373system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy 374system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 375system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 376system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 377system.iocache.tags.tag_accesses 428111 # Number of tag accesses 378system.iocache.tags.data_accesses 428111 # Number of data accesses 379system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 380system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits 381system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses 382system.iocache.ReadReq_misses::total 847 # number of ReadReq misses 383system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses 384system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses 385system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses 386system.iocache.demand_misses::total 847 # number of demand (read+write) misses 387system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses 388system.iocache.overall_misses::total 847 # number of overall misses 389system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles 390system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles 391system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles 392system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles 393system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles 394system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles 395system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses) 396system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses) 397system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses) 398system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses) 399system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses 400system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses 401system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses 402system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses 403system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 404system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 405system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses 406system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses 407system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 408system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 409system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 410system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 411system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency 412system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency 413system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency 414system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency 415system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency 416system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency 417system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked 418system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 419system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked 420system.iocache.blocked::no_targets 0 # number of cycles access was blocked 421system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked 422system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 423system.iocache.fast_writes 46720 # number of fast writes performed 424system.iocache.cache_copies 0 # number of cache copies performed 425system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses 426system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses 427system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses 428system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses 429system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses 430system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses 431system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles 432system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles 433system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles 434system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles 435system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles 436system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles 437system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles 438system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles 439system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 440system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 441system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 442system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 443system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 444system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 445system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency 446system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency 447system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency 448system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 449system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 450system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency 451system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 452system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency 453system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 454system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 455system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 456system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 457system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 458system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 459system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 460system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 461system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 462system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 463system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 464system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 465system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 466system.iobus.trans_dist::ReadReq 230267 # Transaction distribution 467system.iobus.trans_dist::ReadResp 230267 # Transaction distribution 468system.iobus.trans_dist::WriteReq 57693 # Transaction distribution 469system.iobus.trans_dist::WriteResp 57694 # Transaction distribution 470system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution 471system.iobus.trans_dist::MessageReq 1655 # Transaction distribution 472system.iobus.trans_dist::MessageResp 1655 # Transaction distribution 473system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 474system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 475system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 476system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 477system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 478system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 479system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 480system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 481system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) 482system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 483system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 484system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 485system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) 486system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 487system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 488system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 489system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 490system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 491system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) 492system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes) 493system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes) 494system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) 495system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) 496system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes) 497system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 498system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 499system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 500system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 501system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 503system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 504system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 505system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 506system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 507system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 508system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 509system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) 510system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 511system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 512system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 513system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 514system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 515system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) 516system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes) 517system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes) 518system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) 519system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) 520system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes) 521system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) 522system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 523system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 524system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 525system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 526system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 527system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 528system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 529system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 530system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 531system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 532system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 533system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) 534system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 535system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 536system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 537system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 538system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 539system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) 540system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 541system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 542system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 543system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 544system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 545system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 546system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 547system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) 548system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 549system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 550system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 551system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 552system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 553system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 554system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 555system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 556system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 557system.iobus.reqLayer18.occupancy 421906845 # Layer occupancy (ticks) 558system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 559system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 560system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 561system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) 562system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 563system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks) 564system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 565system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) 566system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) | |
| 567system.cpu_clk_domain.clock 500 # Clock period in ticks 568system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 569system.cpu.numCycles 10388821270 # number of cpu cycles simulated 570system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 571system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 572system.cpu.committedInsts 128422722 # Number of instructions committed 573system.cpu.committedOps 247557000 # Number of ops (including micro ops) committed 574system.cpu.num_int_alu_accesses 232138334 # Number of integer alu accesses --- 48 unchanged lines hidden (view full) --- 623system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction 624system.cpu.op_class::MemRead 13887993 5.61% 96.62% # Class of executed instruction 625system.cpu.op_class::MemWrite 8370685 3.38% 100.00% # Class of executed instruction 626system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 627system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 628system.cpu.op_class::total 247558577 # Class of executed instruction 629system.cpu.kern.inst.arm 0 # number of arm instructions executed 630system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 308system.cpu_clk_domain.clock 500 # Clock period in ticks 309system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 310system.cpu.numCycles 10388821270 # number of cpu cycles simulated 311system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 312system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 313system.cpu.committedInsts 128422722 # Number of instructions committed 314system.cpu.committedOps 247557000 # Number of ops (including micro ops) committed 315system.cpu.num_int_alu_accesses 232138334 # Number of integer alu accesses --- 48 unchanged lines hidden (view full) --- 364system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction 365system.cpu.op_class::MemRead 13887993 5.61% 96.62% # Class of executed instruction 366system.cpu.op_class::MemWrite 8370685 3.38% 100.00% # Class of executed instruction 367system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 368system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 369system.cpu.op_class::total 247558577 # Class of executed instruction 370system.cpu.kern.inst.arm 0 # number of arm instructions executed 371system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 372system.cpu.dcache.tags.replacements 1622351 # number of replacements 373system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use 374system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks. 375system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks. 376system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks. 377system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. 378system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor 379system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 380system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 381system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 382system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 383system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 384system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 385system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 386system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 387system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses 388system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses 389system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits 390system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits 391system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits 392system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits 393system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits 394system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits 395system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits 396system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits 397system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits 398system.cpu.dcache.overall_hits::total 20036172 # number of overall hits 399system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses 400system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses 401system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses 402system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses 403system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses 404system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses 405system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses 406system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses 407system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses 408system.cpu.dcache.overall_misses::total 1634692 # number of overall misses 409system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles 410system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles 411system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles 412system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles 413system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles 414system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles 415system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles 416system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles 417system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses) 418system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses) 419system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses) 420system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses) 421system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses) 422system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses) 423system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses 424system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses 425system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses 426system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses 427system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses 428system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses 429system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses 430system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses 431system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses 432system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses 433system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses 434system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses 435system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses 436system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses 437system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency 438system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency 439system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency 440system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency 441system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency 442system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency 443system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency 444system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency 445system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked 446system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 447system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked 448system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 449system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked 450system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 451system.cpu.dcache.fast_writes 0 # number of fast writes performed 452system.cpu.dcache.cache_copies 0 # number of cache copies performed 453system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks 454system.cpu.dcache.writebacks::total 1538923 # number of writebacks 455system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits 456system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits 457system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits 458system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits 459system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits 460system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits 461system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits 462system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits 463system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses 464system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses 465system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses 466system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses 467system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses 468system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses 469system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses 470system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses 471system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses 472system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses 473system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles 474system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles 475system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles 476system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles 477system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles 478system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles 479system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles 480system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles 481system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles 482system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles 483system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles 484system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles 485system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles 486system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles 487system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles 488system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles 489system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses 490system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses 491system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses 492system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses 493system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses 494system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses 495system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses 496system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses 497system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses 498system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses 499system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency 500system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency 501system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency 502system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency 503system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency 504system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency 505system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency 506system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency 507system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency 509system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 510system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 511system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 512system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 513system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 514system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 515system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 516system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements 517system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use 518system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks. 519system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks. 520system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks. 521system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit. 522system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor 523system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy 524system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy 525system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 526system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 527system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 528system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 529system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 530system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses 531system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses 532system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits 533system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits 534system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits 535system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits 536system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits 537system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits 538system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses 539system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses 540system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses 541system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses 542system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses 543system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses 544system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles 545system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles 546system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles 547system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles 548system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles 549system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles 550system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses) 551system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses) 552system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses 553system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses 554system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses 555system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses 556system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses 557system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses 558system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses 559system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses 560system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses 561system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses 562system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency 563system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency 564system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency 565system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency 566system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency 567system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency 568system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 569system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 570system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 571system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 572system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 573system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 574system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 575system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 576system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks 577system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks 578system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses 579system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses 580system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses 581system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses 582system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses 583system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses 584system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles 585system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles 586system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles 587system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles 588system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles 589system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles 590system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses 591system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses 592system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses 593system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses 594system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses 595system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses 596system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency 597system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency 598system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency 599system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency 600system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency 601system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency 602system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 631system.cpu.icache.tags.replacements 791372 # number of replacements 632system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use 633system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks. 634system.cpu.icache.tags.sampled_refs 791884 # Sample count of references to valid blocks. 635system.cpu.icache.tags.avg_refs 182.702791 # Average number of references to valid blocks. 636system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit. 637system.cpu.icache.tags.occ_blocks::cpu.inst 510.348934 # Average occupied blocks per requestor 638system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy --- 162 unchanged lines hidden (view full) --- 801system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.378190 # mshr miss rate for overall accesses 802system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average ReadReq mshr miss latency 803system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8275.416396 # average ReadReq mshr miss latency 804system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency 805system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency 806system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency 807system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency 808system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 603system.cpu.icache.tags.replacements 791372 # number of replacements 604system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use 605system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks. 606system.cpu.icache.tags.sampled_refs 791884 # Sample count of references to valid blocks. 607system.cpu.icache.tags.avg_refs 182.702791 # Average number of references to valid blocks. 608system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit. 609system.cpu.icache.tags.occ_blocks::cpu.inst 510.348934 # Average occupied blocks per requestor 610system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy --- 162 unchanged lines hidden (view full) --- 773system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.378190 # mshr miss rate for overall accesses 774system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average ReadReq mshr miss latency 775system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8275.416396 # average ReadReq mshr miss latency 776system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency 777system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency 778system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency 779system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency 780system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 809system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements 810system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use 811system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks. 812system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks. 813system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks. 814system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit. 815system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor 816system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy 817system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy 818system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 819system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 820system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 821system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 822system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 823system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses 824system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses 825system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits 826system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits 827system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits 828system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits 829system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits 830system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits 831system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses 832system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses 833system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses 834system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses 835system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses 836system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses 837system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles 838system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles 839system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles 840system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles 841system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles 842system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles 843system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses) 844system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses) 845system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses 846system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses 847system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses 848system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses 849system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses 850system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses 851system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses 852system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses 853system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses 854system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses 855system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency 856system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency 857system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency 858system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency 859system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency 860system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency 861system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 862system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 863system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 864system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 865system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 866system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 867system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 868system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 869system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks 870system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks 871system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses 872system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses 873system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses 874system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses 875system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses 876system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses 877system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles 878system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles 879system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles 880system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles 881system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles 882system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles 883system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses 884system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses 885system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses 886system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses 887system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses 888system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses 889system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency 890system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency 891system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency 892system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency 893system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency 894system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency 895system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 896system.cpu.dcache.tags.replacements 1622351 # number of replacements 897system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use 898system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks. 899system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks. 900system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks. 901system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. 902system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor 903system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 904system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 905system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 906system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 907system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 908system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 909system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 910system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 911system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses 912system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses 913system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits 914system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits 915system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits 916system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits 917system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits 918system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits 919system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits 920system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits 921system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits 922system.cpu.dcache.overall_hits::total 20036172 # number of overall hits 923system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses 924system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses 925system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses 926system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses 927system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses 928system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses 929system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses 930system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses 931system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses 932system.cpu.dcache.overall_misses::total 1634692 # number of overall misses 933system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles 934system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles 935system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles 936system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles 937system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles 938system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles 939system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles 940system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles 941system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses) 942system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses) 943system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses) 944system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses) 945system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses) 946system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses) 947system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses 948system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses 949system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses 950system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses 951system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses 952system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses 953system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses 954system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses 955system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses 956system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses 957system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses 958system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses 959system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses 960system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses 961system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency 962system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency 963system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency 964system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency 965system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency 966system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency 967system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency 968system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency 969system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked 970system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 971system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked 972system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 973system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked 974system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 975system.cpu.dcache.fast_writes 0 # number of fast writes performed 976system.cpu.dcache.cache_copies 0 # number of cache copies performed 977system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks 978system.cpu.dcache.writebacks::total 1538923 # number of writebacks 979system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits 980system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits 981system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits 982system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits 983system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits 984system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits 985system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits 986system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits 987system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses 988system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses 989system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses 990system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses 991system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses 992system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses 993system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses 994system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses 995system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses 996system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses 997system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles 998system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles 999system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles 1000system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles 1001system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles 1002system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles 1003system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles 1004system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles 1005system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles 1006system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles 1007system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles 1008system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles 1009system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles 1010system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles 1011system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles 1012system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles 1013system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses 1014system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses 1015system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses 1016system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses 1017system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses 1018system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses 1019system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses 1020system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses 1021system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses 1022system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses 1023system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency 1024system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency 1025system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency 1026system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency 1027system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency 1028system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency 1029system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency 1030system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency 1031system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency 1032system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency 1033system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1034system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1035system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1036system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1037system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1038system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1039system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1040system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution 1041system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution 1042system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution 1043system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution 1044system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution 1045system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution 1046system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution 1047system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution 1048system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution 1049system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution 1050system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes) 1051system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes) 1052system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes) 1053system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes) 1054system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes) 1055system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes) 1056system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes) 1057system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) 1058system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes) 1059system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes) 1060system.cpu.toL2Bus.snoops 52938 # Total snoops (count) 1061system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram 1062system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram 1063system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram 1064system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1065system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1066system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1067system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1068system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram 1069system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram 1070system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1071system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1072system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1073system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram 1074system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks) 1075system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1076system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) 1077system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1078system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks) 1079system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1080system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks) 1081system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1082system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks) 1083system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1084system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks) 1085system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | |
| 1086system.cpu.l2cache.tags.replacements 87384 # number of replacements 1087system.cpu.l2cache.tags.tagsinuse 64746.924059 # Cycle average of tags in use 1088system.cpu.l2cache.tags.total_refs 3489247 # Total number of references to valid blocks. 1089system.cpu.l2cache.tags.sampled_refs 152088 # Sample count of references to valid blocks. 1090system.cpu.l2cache.tags.avg_refs 22.942290 # Average number of references to valid blocks. 1091system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1092system.cpu.l2cache.tags.occ_blocks::writebacks 50375.433193 # Average occupied blocks per requestor 1093system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006760 # Average occupied blocks per requestor --- 227 unchanged lines hidden (view full) --- 1321system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency 1322system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1323system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1324system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1325system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1326system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1327system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1328system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 781system.cpu.l2cache.tags.replacements 87384 # number of replacements 782system.cpu.l2cache.tags.tagsinuse 64746.924059 # Cycle average of tags in use 783system.cpu.l2cache.tags.total_refs 3489247 # Total number of references to valid blocks. 784system.cpu.l2cache.tags.sampled_refs 152088 # Sample count of references to valid blocks. 785system.cpu.l2cache.tags.avg_refs 22.942290 # Average number of references to valid blocks. 786system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 787system.cpu.l2cache.tags.occ_blocks::writebacks 50375.433193 # Average occupied blocks per requestor 788system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006760 # Average occupied blocks per requestor --- 227 unchanged lines hidden (view full) --- 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency 1017system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1018system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1019system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1020system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1021system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1022system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1023system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1024system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution 1025system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution 1026system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution 1027system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution 1028system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution 1029system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution 1030system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution 1031system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution 1032system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution 1033system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution 1034system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes) 1035system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes) 1036system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes) 1037system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes) 1038system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes) 1039system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes) 1040system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes) 1041system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) 1042system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes) 1043system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes) 1044system.cpu.toL2Bus.snoops 52938 # Total snoops (count) 1045system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram 1046system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram 1047system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram 1048system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1049system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1050system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1051system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1052system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram 1053system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram 1054system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1055system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1056system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1057system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram 1058system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks) 1059system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1060system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) 1061system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1062system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks) 1063system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1064system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks) 1065system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1066system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks) 1067system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1068system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks) 1069system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1070system.iobus.trans_dist::ReadReq 230267 # Transaction distribution 1071system.iobus.trans_dist::ReadResp 230267 # Transaction distribution 1072system.iobus.trans_dist::WriteReq 57693 # Transaction distribution 1073system.iobus.trans_dist::WriteResp 57694 # Transaction distribution 1074system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution 1075system.iobus.trans_dist::MessageReq 1655 # Transaction distribution 1076system.iobus.trans_dist::MessageResp 1655 # Transaction distribution 1077system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1078system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1079system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1080system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1081system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1082system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 1083system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1084system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1085system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) 1086system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1087system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 1088system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1089system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) 1090system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1091system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1092system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1093system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1094system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 1095system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) 1096system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes) 1097system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes) 1098system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) 1099system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) 1100system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes) 1101system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1102system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1103system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1104system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1105system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1106system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1107system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1108system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1109system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 1110system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1111system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 1112system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1113system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) 1114system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1115system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1116system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1117system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1118system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 1119system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) 1120system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes) 1121system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes) 1122system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) 1123system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) 1124system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes) 1125system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) 1126system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1127system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1128system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1129system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1130system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1131system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 1132system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1133system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1134system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1135system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1136system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1137system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) 1138system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1139system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1140system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1141system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1142system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1143system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) 1144system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1145system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1146system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1147system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1148system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1149system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 1150system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 1151system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) 1152system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1153system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 1154system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1155system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1156system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1157system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1158system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1159system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1160system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1161system.iobus.reqLayer18.occupancy 421906845 # Layer occupancy (ticks) 1162system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1163system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 1164system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1165system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) 1166system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1167system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks) 1168system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1169system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) 1170system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 1171system.iocache.tags.replacements 47512 # number of replacements 1172system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use 1173system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1174system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks. 1175system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1176system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit. 1177system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor 1178system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy 1179system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy 1180system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1181system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1182system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1183system.iocache.tags.tag_accesses 428111 # Number of tag accesses 1184system.iocache.tags.data_accesses 428111 # Number of data accesses 1185system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 1186system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits 1187system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses 1188system.iocache.ReadReq_misses::total 847 # number of ReadReq misses 1189system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses 1190system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses 1191system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses 1192system.iocache.demand_misses::total 847 # number of demand (read+write) misses 1193system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses 1194system.iocache.overall_misses::total 847 # number of overall misses 1195system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles 1196system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles 1197system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles 1198system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles 1199system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles 1200system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles 1201system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses) 1202system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses) 1203system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses) 1204system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses) 1205system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses 1206system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses 1207system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses 1208system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses 1209system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1210system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1211system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses 1212system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses 1213system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1214system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1215system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1216system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1217system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency 1218system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency 1219system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency 1220system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency 1221system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency 1222system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency 1223system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked 1224system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1225system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked 1226system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1227system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked 1228system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1229system.iocache.fast_writes 46720 # number of fast writes performed 1230system.iocache.cache_copies 0 # number of cache copies performed 1231system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses 1232system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses 1233system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses 1234system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses 1235system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses 1236system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses 1237system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles 1238system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles 1239system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles 1240system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles 1241system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles 1242system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles 1243system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles 1244system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles 1245system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1246system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1247system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1248system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1249system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1250system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1251system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency 1252system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency 1253system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency 1254system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1255system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 1256system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency 1257system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 1258system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency 1259system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1260system.membus.trans_dist::ReadReq 624009 # Transaction distribution 1261system.membus.trans_dist::ReadResp 624009 # Transaction distribution 1262system.membus.trans_dist::WriteReq 13889 # Transaction distribution 1263system.membus.trans_dist::WriteResp 13889 # Transaction distribution 1264system.membus.trans_dist::Writeback 80466 # Transaction distribution 1265system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1266system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 1267system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution 1268system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution 1269system.membus.trans_dist::ReadExReq 113541 # Transaction distribution 1270system.membus.trans_dist::ReadExResp 113541 # Transaction distribution 1271system.membus.trans_dist::MessageReq 1655 # Transaction distribution 1272system.membus.trans_dist::MessageResp 1655 # Transaction distribution 1273system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) 1274system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) 1275system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) 1276system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes) 1277system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes) 1278system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes) 1279system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes) 1280system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes) 1281system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes) 1282system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) 1283system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) 1284system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) 1285system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes) 1286system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes) 1287system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes) 1288system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 1289system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 1290system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes) 1291system.membus.snoops 943 # Total snoops (count) 1292system.membus.snoop_fanout::samples 285344 # Request fanout histogram 1293system.membus.snoop_fanout::mean 1 # Request fanout histogram 1294system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1295system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1296system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1297system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram 1298system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1299system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1300system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1301system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1302system.membus.snoop_fanout::total 285344 # Request fanout histogram 1303system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) 1304system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1305system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks) 1306system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1307system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) 1308system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1309system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks) 1310system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1311system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) 1312system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 1313system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks) 1314system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1315system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks) 1316system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1317system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1318system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1319system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1320system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1321system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1322system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1323system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1324system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1325system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1326system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1327system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1328system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
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| 1329 1330---------- End Simulation Statistics ---------- | 1329 1330---------- End Simulation Statistics ---------- |