| stats.txt (10451:3a87241adfb8) | stats.txt (10513:ca4438b6e39a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.194411 # Number of seconds simulated 4sim_ticks 5194410635000 # Number of ticks simulated 5final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.194411 # Number of seconds simulated 4sim_ticks 5194410635000 # Number of ticks simulated 5final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 693425 # Simulator instruction rate (inst/s) 8host_op_rate 1336696 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 28047460404 # Simulator tick rate (ticks/s) 10host_mem_usage 637768 # Number of bytes of host memory used 11host_seconds 185.20 # Real time elapsed on the host | 7host_inst_rate 1079720 # Simulator instruction rate (inst/s) 8host_op_rate 2081347 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 43672253601 # Simulator tick rate (ticks/s) 10host_mem_usage 589096 # Number of bytes of host memory used 11host_seconds 118.94 # Real time elapsed on the host |
| 12sim_insts 128422722 # Number of instructions simulated 13sim_ops 247557000 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory --- 399 unchanged lines hidden (view full) --- 419system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked 420system.iocache.blocked::no_targets 0 # number of cycles access was blocked 421system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked 422system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 423system.iocache.fast_writes 46720 # number of fast writes performed 424system.iocache.cache_copies 0 # number of cache copies performed 425system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses 426system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses | 12sim_insts 128422722 # Number of instructions simulated 13sim_ops 247557000 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory --- 399 unchanged lines hidden (view full) --- 419system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked 420system.iocache.blocked::no_targets 0 # number of cycles access was blocked 421system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked 422system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 423system.iocache.fast_writes 46720 # number of fast writes performed 424system.iocache.cache_copies 0 # number of cache copies performed 425system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses 426system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses |
| 427system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 428system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses | |
| 429system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses 430system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses 431system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses 432system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses 433system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles 434system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles 435system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles 436system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles 437system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles 438system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles 439system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles 440system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles 441system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 442system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 427system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses 428system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses 429system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses 430system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses 431system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles 432system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles 433system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles 434system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles 435system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles 436system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles 437system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles 438system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles 439system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 440system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 443system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.999979 # mshr miss rate for WriteInvalidateReq accesses 444system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999979 # mshr miss rate for WriteInvalidateReq accesses | |
| 445system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 446system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 447system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 448system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 449system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency 450system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency | 441system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 442system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 443system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 444system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 445system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency 446system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency |
| 451system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60522.456336 # average WriteInvalidateReq mshr miss latency 452system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60522.456336 # average WriteInvalidateReq mshr miss latency | 447system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency 448system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency |
| 453system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 454system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency 455system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 456system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency 457system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 458system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 459system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 460system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). --- 874 unchanged lines hidden --- | 449system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 450system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency 451system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 452system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency 453system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 454system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 455system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 456system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). --- 874 unchanged lines hidden --- |