| stats.txt (10433:821cbe4a183b) | stats.txt (10451:3a87241adfb8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.192511 # Number of seconds simulated 4sim_ticks 5192511044000 # Number of ticks simulated 5final_tick 5192511044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.194411 # Number of seconds simulated 4sim_ticks 5194410635000 # Number of ticks simulated 5final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1399863 # Simulator instruction rate (inst/s) 8host_op_rate 2698503 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56649883486 # Simulator tick rate (ticks/s) 10host_mem_usage 595716 # Number of bytes of host memory used 11host_seconds 91.66 # Real time elapsed on the host 12sim_insts 128310974 # Number of instructions simulated 13sim_ops 247343919 # Number of ops (including micro ops) simulated | 7host_inst_rate 693425 # Simulator instruction rate (inst/s) 8host_op_rate 1336696 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 28047460404 # Simulator tick rate (ticks/s) 10host_mem_usage 637768 # Number of bytes of host memory used 11host_seconds 185.20 # Real time elapsed on the host 12sim_insts 128422722 # Number of instructions simulated 13sim_ops 247557000 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9076288 # Number of bytes read from this memory 21system.physmem.bytes_read::total 9932544 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5141952 # Number of bytes written to this memory | 19system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory 21system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory | 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 8132032 # Number of bytes written to this memory | 26system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory |
| 27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | 27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 29system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 141817 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 155196 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 80343 # Number of write requests responded to by this memory | 30system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory | 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 127063 # Number of write requests responded to by this memory 36system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory 36system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) | 38system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::cpu.inst 159356 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1747957 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1912859 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 159356 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 159356 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 990263 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 575845 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1566108 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 990263 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::pc.south_bridge.ide 581305 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 991416 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) |
| 50system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) | 50system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::cpu.inst 159356 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1747957 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3478967 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 155196 # Number of read requests accepted 55system.physmem.writeReqs 127063 # Number of write requests accepted 56system.physmem.readBursts 155196 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 127063 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 9914944 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 17600 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8130496 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 9932544 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 8132032 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 275 # Number of DRAM read bursts serviced by the write queue | 51system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 155585 # Number of read requests accepted 55system.physmem.writeReqs 127186 # Number of write requests accepted 56system.physmem.readBursts 155585 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 127186 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 9942720 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 14720 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8138624 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 9957440 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 8139904 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 230 # Number of DRAM read bursts serviced by the write queue |
| 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 65system.physmem.neitherReadNorWriteReqs 1594 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10479 # Per bank write bursts 67system.physmem.perBankRdBursts::1 9637 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10137 # Per bank write bursts 69system.physmem.perBankRdBursts::3 9789 # Per bank write bursts 70system.physmem.perBankRdBursts::4 9555 # Per bank write bursts 71system.physmem.perBankRdBursts::5 9513 # Per bank write bursts 72system.physmem.perBankRdBursts::6 9351 # Per bank write bursts 73system.physmem.perBankRdBursts::7 9512 # Per bank write bursts 74system.physmem.perBankRdBursts::8 9073 # Per bank write bursts 75system.physmem.perBankRdBursts::9 8991 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9630 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9438 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9550 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10095 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10146 # Per bank write bursts 81system.physmem.perBankRdBursts::15 10025 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8301 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8002 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8301 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8212 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7990 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7535 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7392 # Per bank write bursts 89system.physmem.perBankWrBursts::7 7734 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7444 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7612 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7970 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7896 # Per bank write bursts 94system.physmem.perBankWrBursts::12 8102 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8416 # Per bank write bursts 96system.physmem.perBankWrBursts::14 8297 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7835 # Per bank write bursts | 65system.physmem.neitherReadNorWriteReqs 1629 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10087 # Per bank write bursts 67system.physmem.perBankRdBursts::1 9924 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10111 # Per bank write bursts 69system.physmem.perBankRdBursts::3 9612 # Per bank write bursts 70system.physmem.perBankRdBursts::4 10046 # Per bank write bursts 71system.physmem.perBankRdBursts::5 9507 # Per bank write bursts 72system.physmem.perBankRdBursts::6 9544 # Per bank write bursts 73system.physmem.perBankRdBursts::7 9545 # Per bank write bursts 74system.physmem.perBankRdBursts::8 9177 # Per bank write bursts 75system.physmem.perBankRdBursts::9 9299 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9268 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9485 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9621 # Per bank write bursts 79system.physmem.perBankRdBursts::13 9970 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10158 # Per bank write bursts 81system.physmem.perBankRdBursts::15 10001 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8060 # Per bank write bursts 83system.physmem.perBankWrBursts::1 7801 # Per bank write bursts 84system.physmem.perBankWrBursts::2 7998 # Per bank write bursts 85system.physmem.perBankWrBursts::3 7765 # Per bank write bursts 86system.physmem.perBankWrBursts::4 8116 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7896 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7662 # Per bank write bursts 89system.physmem.perBankWrBursts::7 7717 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7519 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7838 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7675 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7654 # Per bank write bursts 94system.physmem.perBankWrBursts::12 8493 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8626 # Per bank write bursts 96system.physmem.perBankWrBursts::14 8402 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7944 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 1 # Number of times write queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 1 # Number of times write queue was full causing retry |
| 100system.physmem.totGap 5192510980500 # Total gap between requests | 100system.physmem.totGap 5194410571500 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 155196 # Read request sizes (log2) | 107system.physmem.readPktSize::6 155585 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 127063 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 151525 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 2962 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 127186 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 151951 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 2969 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see |
| 119system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 119system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 2384 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3176 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6154 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6388 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6392 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7445 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 8129 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8789 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 9861 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 9041 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7645 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7364 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6417 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6189 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6244 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6141 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 237 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 221 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 254 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 206 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 203 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 199 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 182 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 177 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 179 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 41 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 37 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 57292 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 314.972003 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 184.928814 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 333.427002 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 21127 36.88% 36.88% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 13732 23.97% 60.84% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5729 10.00% 70.84% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3461 6.04% 76.89% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2250 3.93% 80.81% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1575 2.75% 83.56% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1105 1.93% 85.49% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1008 1.76% 87.25% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7305 12.75% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 57292 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 26.232854 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 621.882480 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 5904 99.98% 99.98% # Reads before turning the bus around for writes | 162system.physmem.wrQLenPdf::15 2364 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3127 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6124 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6381 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6410 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7424 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 8105 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8845 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 9948 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 9118 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8439 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7706 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7452 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6421 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6193 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6287 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6139 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 216 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 191 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 191 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 214 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 184 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 176 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 181 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 61 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 18 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 55971 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 323.047292 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 191.702498 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 334.763320 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 19466 34.78% 34.78% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 13850 24.74% 59.52% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5737 10.25% 69.77% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3527 6.30% 76.08% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2331 4.16% 80.24% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1635 2.92% 83.16% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1137 2.03% 85.19% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 981 1.75% 86.95% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7307 13.05% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 55971 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5932 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 26.188806 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 621.686791 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 5931 99.98% 99.98% # Reads before turning the bus around for writes |
| 229system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes | 229system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 230system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 21.513802 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 19.393687 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 14.130484 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 4886 82.74% 82.74% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 42 0.71% 83.45% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 41 0.69% 84.15% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 275 4.66% 88.81% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 267 4.52% 93.33% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 20 0.34% 93.67% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 10 0.17% 93.84% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 19 0.32% 94.16% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 22 0.37% 94.53% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 8 0.14% 94.67% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 6 0.10% 94.77% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 2 0.03% 94.80% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 226 3.83% 98.63% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 6 0.10% 98.73% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 4 0.07% 98.80% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 3 0.05% 98.85% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 15 0.25% 99.10% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::88-91 1 0.02% 99.12% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::92-95 1 0.02% 99.14% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::96-99 13 0.22% 99.36% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::100-103 1 0.02% 99.37% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::104-107 6 0.10% 99.48% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 3 0.05% 99.53% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 8 0.14% 99.66% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::116-119 2 0.03% 99.70% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::120-123 3 0.05% 99.75% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::128-131 12 0.20% 99.95% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads 265system.physmem.totQLat 1558594500 # Total ticks spent queuing 266system.physmem.totMemAccLat 4463363250 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 774605000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 10060.58 # Average queueing delay per DRAM burst | 230system.physmem.rdPerTurnAround::total 5932 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 5932 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 21.437289 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 19.381245 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 13.855005 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 4878 82.23% 82.23% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 44 0.74% 82.97% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 36 0.61% 83.58% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 295 4.97% 88.55% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 297 5.01% 93.56% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 20 0.34% 93.90% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 18 0.30% 94.20% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 14 0.24% 94.44% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 21 0.35% 94.79% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 5 0.08% 94.88% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 1 0.02% 94.89% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 3 0.05% 94.94% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 234 3.94% 98.89% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 3 0.05% 98.94% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 4 0.07% 99.01% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::76-79 4 0.07% 99.07% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::80-83 9 0.15% 99.22% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::96-99 12 0.20% 99.43% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::100-103 2 0.03% 99.46% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::104-107 5 0.08% 99.54% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::108-111 2 0.03% 99.58% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::112-115 8 0.13% 99.71% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::116-119 2 0.03% 99.75% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::128-131 10 0.17% 99.93% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::140-143 3 0.05% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::total 5932 # Writes before turning the bus around for reads 263system.physmem.totQLat 1472209750 # Total ticks spent queuing 264system.physmem.totMemAccLat 4385116000 # Total ticks spent from burst creation until serviced by the DRAM 265system.physmem.totBusLat 776775000 # Total ticks spent in databus transfers 266system.physmem.avgQLat 9476.42 # Average queueing delay per DRAM burst |
| 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 267system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 270system.physmem.avgMemAccLat 28810.58 # Average memory access latency per DRAM burst | 268system.physmem.avgMemAccLat 28226.42 # Average memory access latency per DRAM burst |
| 271system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s | 269system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s 270system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s |
| 273system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s | 271system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s |
| 274system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.03 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 272system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s 273system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 274system.physmem.busUtil 0.03 # Data bus utilization in percentage 275system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 276system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 277system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 280system.physmem.avgWrQLen 22.05 # Average write queue length when enqueuing 281system.physmem.readRowHits 125976 # Number of row buffer hits during reads 282system.physmem.writeRowHits 98691 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 77.67 # Row buffer hit rate for writes 285system.physmem.avgGap 18396263.65 # Average gap between requests 286system.physmem.pageHitRate 79.67 # Row buffer hit rate, read and write combined 287system.physmem.memoryStateTime::IDLE 4970934831000 # Time in different power states 288system.physmem.memoryStateTime::REF 173389320000 # Time in different power states | 278system.physmem.avgWrQLen 21.88 # Average write queue length when enqueuing 279system.physmem.readRowHits 127796 # Number of row buffer hits during reads 280system.physmem.writeRowHits 98753 # Number of row buffer hits during writes 281system.physmem.readRowHitRate 82.26 # Row buffer hit rate for reads 282system.physmem.writeRowHitRate 77.64 # Row buffer hit rate for writes 283system.physmem.avgGap 18369672.18 # Average gap between requests 284system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined 285system.physmem.memoryStateTime::IDLE 4972956663750 # Time in different power states 286system.physmem.memoryStateTime::REF 173452760000 # Time in different power states |
| 289system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 287system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 290system.physmem.memoryStateTime::ACT 48186778000 # Time in different power states | 288system.physmem.memoryStateTime::ACT 48001096250 # Time in different power states |
| 291system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 289system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 292system.physmem.actEnergy::0 214242840 # Energy for activate commands per rank (pJ) 293system.physmem.actEnergy::1 218884680 # Energy for activate commands per rank (pJ) 294system.physmem.preEnergy::0 116898375 # Energy for precharge commands per rank (pJ) 295system.physmem.preEnergy::1 119431125 # Energy for precharge commands per rank (pJ) 296system.physmem.readEnergy::0 608189400 # Energy for read commands per rank (pJ) 297system.physmem.readEnergy::1 600186600 # Energy for read commands per rank (pJ) 298system.physmem.writeEnergy::0 411266160 # Energy for write commands per rank (pJ) 299system.physmem.writeEnergy::1 411946560 # Energy for write commands per rank (pJ) 300system.physmem.refreshEnergy::0 339149509920 # Energy for refresh commands per rank (pJ) 301system.physmem.refreshEnergy::1 339149509920 # Energy for refresh commands per rank (pJ) 302system.physmem.actBackEnergy::0 134171647065 # Energy for active background per rank (pJ) 303system.physmem.actBackEnergy::1 134426407995 # Energy for active background per rank (pJ) 304system.physmem.preBackEnergy::0 2997811704000 # Energy for precharge background per rank (pJ) 305system.physmem.preBackEnergy::1 2997588229500 # Energy for precharge background per rank (pJ) 306system.physmem.totalEnergy::0 3472483457760 # Total energy per rank (pJ) 307system.physmem.totalEnergy::1 3472514596380 # Total energy per rank (pJ) 308system.physmem.averagePower::0 668.748507 # Core power per rank (mW) 309system.physmem.averagePower::1 668.754504 # Core power per rank (mW) 310system.membus.trans_dist::ReadReq 623858 # Transaction distribution 311system.membus.trans_dist::ReadResp 623858 # Transaction distribution 312system.membus.trans_dist::WriteReq 13773 # Transaction distribution 313system.membus.trans_dist::WriteResp 13773 # Transaction distribution 314system.membus.trans_dist::Writeback 80343 # Transaction distribution | 290system.physmem.actEnergy::0 211543920 # Energy for activate commands per rank (pJ) 291system.physmem.actEnergy::1 211596840 # Energy for activate commands per rank (pJ) 292system.physmem.preEnergy::0 115425750 # Energy for precharge commands per rank (pJ) 293system.physmem.preEnergy::1 115454625 # Energy for precharge commands per rank (pJ) 294system.physmem.readEnergy::0 611332800 # Energy for read commands per rank (pJ) 295system.physmem.readEnergy::1 600428400 # Energy for read commands per rank (pJ) 296system.physmem.writeEnergy::0 408337200 # Energy for write commands per rank (pJ) 297system.physmem.writeEnergy::1 415698480 # Energy for write commands per rank (pJ) 298system.physmem.refreshEnergy::0 339273598560 # Energy for refresh commands per rank (pJ) 299system.physmem.refreshEnergy::1 339273598560 # Energy for refresh commands per rank (pJ) 300system.physmem.actBackEnergy::0 134393532390 # Energy for active background per rank (pJ) 301system.physmem.actBackEnergy::1 134240531850 # Energy for active background per rank (pJ) 302system.physmem.preBackEnergy::0 2998756974750 # Energy for precharge background per rank (pJ) 303system.physmem.preBackEnergy::1 2998891185750 # Energy for precharge background per rank (pJ) 304system.physmem.totalEnergy::0 3473770745370 # Total energy per rank (pJ) 305system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ) 306system.physmem.averagePower::0 668.751736 # Core power per rank (mW) 307system.physmem.averagePower::1 668.747452 # Core power per rank (mW) 308system.membus.trans_dist::ReadReq 624009 # Transaction distribution 309system.membus.trans_dist::ReadResp 624009 # Transaction distribution 310system.membus.trans_dist::WriteReq 13889 # Transaction distribution 311system.membus.trans_dist::WriteResp 13889 # Transaction distribution 312system.membus.trans_dist::Writeback 80466 # Transaction distribution |
| 315system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 316system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution | 313system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 314system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution |
| 317system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution 318system.membus.trans_dist::UpgradeResp 1594 # Transaction distribution 319system.membus.trans_dist::ReadExReq 113180 # Transaction distribution 320system.membus.trans_dist::ReadExResp 113180 # Transaction distribution 321system.membus.trans_dist::MessageReq 1654 # Transaction distribution 322system.membus.trans_dist::MessageResp 1654 # Transaction distribution 323system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) 324system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) 325system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) 326system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393589 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584027 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94722 # Packet count per connected master and slave (bytes) 330system.membus.pkt_count_system.iocache.mem_side::total 94722 # Packet count per connected master and slave (bytes) 331system.membus.pkt_count::total 1682057 # Packet count per connected master and slave (bytes) 332system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) 333system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) 334system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) 335system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) 336system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15046144 # Cumulative packet size per connected master and slave (bytes) 337system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16712805 # Cumulative packet size per connected master and slave (bytes) | 315system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution 316system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution 317system.membus.trans_dist::ReadExReq 113541 # Transaction distribution 318system.membus.trans_dist::ReadExResp 113541 # Transaction distribution 319system.membus.trans_dist::MessageReq 1655 # Transaction distribution 320system.membus.trans_dist::MessageResp 1655 # Transaction distribution 321system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) 322system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) 323system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480788 # Packet count per connected master and slave (bytes) 324system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes) 325system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes) 326system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes) 327system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes) 328system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes) 329system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes) 330system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) 331system.membus.pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) 332system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246674 # Cumulative packet size per connected master and slave (bytes) 333system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes) 334system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes) 335system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes) |
| 338system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 339system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) | 336system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 337system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) |
| 340system.membus.pkt_size::total 19737853 # Cumulative packet size per connected master and slave (bytes) 341system.membus.snoops 948 # Total snoops (count) 342system.membus.snoop_fanout::samples 284802 # Request fanout histogram | 338system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes) 339system.membus.snoops 943 # Total snoops (count) 340system.membus.snoop_fanout::samples 285344 # Request fanout histogram |
| 343system.membus.snoop_fanout::mean 1 # Request fanout histogram 344system.membus.snoop_fanout::stdev 0 # Request fanout histogram 345system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 346system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 341system.membus.snoop_fanout::mean 1 # Request fanout histogram 342system.membus.snoop_fanout::stdev 0 # Request fanout histogram 343system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 344system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 347system.membus.snoop_fanout::1 284802 100.00% 100.00% # Request fanout histogram | 345system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram |
| 348system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 349system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 350system.membus.snoop_fanout::min_value 1 # Request fanout histogram 351system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 346system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 347system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 348system.membus.snoop_fanout::min_value 1 # Request fanout histogram 349system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 352system.membus.snoop_fanout::total 284802 # Request fanout histogram 353system.membus.reqLayer0.occupancy 256795500 # Layer occupancy (ticks) | 350system.membus.snoop_fanout::total 285344 # Request fanout histogram 351system.membus.reqLayer0.occupancy 257196000 # Layer occupancy (ticks) |
| 354system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 352system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 355system.membus.reqLayer1.occupancy 358101500 # Layer occupancy (ticks) | 353system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks) |
| 356system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 354system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 357system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) | 355system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) |
| 358system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 356system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 359system.membus.reqLayer3.occupancy 1310597750 # Layer occupancy (ticks) | 357system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks) |
| 360system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) | 358system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) |
| 361system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) | 359system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) |
| 362system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 360system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 363system.membus.respLayer2.occupancy 2618526656 # Layer occupancy (ticks) | 361system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks) |
| 364system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 362system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 365system.membus.respLayer4.occupancy 54286498 # Layer occupancy (ticks) | 363system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks) |
| 366system.membus.respLayer4.utilization 0.0 # Layer utilization (%) | 364system.membus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 367system.iocache.tags.replacements 47504 # number of replacements 368system.iocache.tags.tagsinuse 0.112573 # Cycle average of tags in use | 365system.iocache.tags.replacements 47512 # number of replacements 366system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use |
| 369system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 367system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 370system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks. | 368system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks. |
| 371system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 369system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 372system.iocache.tags.warmup_cycle 5045778761000 # Cycle when the warmup percentage was hit. 373system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112573 # Average occupied blocks per requestor 374system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007036 # Average percentage of cache occupancy 375system.iocache.tags.occ_percent::total 0.007036 # Average percentage of cache occupancy | 370system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit. 371system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor 372system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy 373system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy |
| 376system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 377system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 378system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 374system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 375system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 376system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 379system.iocache.tags.tag_accesses 428031 # Number of tag accesses 380system.iocache.tags.data_accesses 428031 # Number of data accesses | 377system.iocache.tags.tag_accesses 428111 # Number of tag accesses 378system.iocache.tags.data_accesses 428111 # Number of data accesses |
| 381system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 382system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits | 379system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 380system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits |
| 383system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses 384system.iocache.ReadReq_misses::total 839 # number of ReadReq misses 385system.iocache.demand_misses::pc.south_bridge.ide 839 # number of demand (read+write) misses 386system.iocache.demand_misses::total 839 # number of demand (read+write) misses 387system.iocache.overall_misses::pc.south_bridge.ide 839 # number of overall misses 388system.iocache.overall_misses::total 839 # number of overall misses 389system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140842436 # number of ReadReq miss cycles 390system.iocache.ReadReq_miss_latency::total 140842436 # number of ReadReq miss cycles 391system.iocache.demand_miss_latency::pc.south_bridge.ide 140842436 # number of demand (read+write) miss cycles 392system.iocache.demand_miss_latency::total 140842436 # number of demand (read+write) miss cycles 393system.iocache.overall_miss_latency::pc.south_bridge.ide 140842436 # number of overall miss cycles 394system.iocache.overall_miss_latency::total 140842436 # number of overall miss cycles 395system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses) 396system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses) 397system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 398system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 399system.iocache.demand_accesses::pc.south_bridge.ide 839 # number of demand (read+write) accesses 400system.iocache.demand_accesses::total 839 # number of demand (read+write) accesses 401system.iocache.overall_accesses::pc.south_bridge.ide 839 # number of overall (read+write) accesses 402system.iocache.overall_accesses::total 839 # number of overall (read+write) accesses | 381system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses 382system.iocache.ReadReq_misses::total 847 # number of ReadReq misses 383system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses 384system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses 385system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses 386system.iocache.demand_misses::total 847 # number of demand (read+write) misses 387system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses 388system.iocache.overall_misses::total 847 # number of overall misses 389system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles 390system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles 391system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles 392system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles 393system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles 394system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles 395system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses) 396system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses) 397system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses) 398system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses) 399system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses 400system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses 401system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses 402system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses |
| 403system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 404system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 403system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 404system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 405system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses 406system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses |
|
| 405system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 406system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 407system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 408system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 407system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 408system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 409system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 410system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 409system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average ReadReq miss latency 410system.iocache.ReadReq_avg_miss_latency::total 167869.411204 # average ReadReq miss latency 411system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency 412system.iocache.demand_avg_miss_latency::total 167869.411204 # average overall miss latency 413system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency 414system.iocache.overall_avg_miss_latency::total 167869.411204 # average overall miss latency | 411system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency 412system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency 413system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency 414system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency 415system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency 416system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency |
| 415system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked 416system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 417system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked 418system.iocache.blocked::no_targets 0 # number of cycles access was blocked 419system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked 420system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 421system.iocache.fast_writes 46720 # number of fast writes performed 422system.iocache.cache_copies 0 # number of cache copies performed | 417system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked 418system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 419system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked 420system.iocache.blocked::no_targets 0 # number of cycles access was blocked 421system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked 422system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 423system.iocache.fast_writes 46720 # number of fast writes performed 424system.iocache.cache_copies 0 # number of cache copies performed |
| 423system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses 424system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses | 425system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses 426system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses |
| 425system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 426system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses | 427system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 428system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses |
| 427system.iocache.demand_mshr_misses::pc.south_bridge.ide 839 # number of demand (read+write) MSHR misses 428system.iocache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses 429system.iocache.overall_mshr_misses::pc.south_bridge.ide 839 # number of overall MSHR misses 430system.iocache.overall_mshr_misses::total 839 # number of overall MSHR misses 431system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of ReadReq MSHR miss cycles 432system.iocache.ReadReq_mshr_miss_latency::total 97188936 # number of ReadReq MSHR miss cycles 433system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2836981412 # number of WriteInvalidateReq MSHR miss cycles 434system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2836981412 # number of WriteInvalidateReq MSHR miss cycles 435system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of demand (read+write) MSHR miss cycles 436system.iocache.demand_mshr_miss_latency::total 97188936 # number of demand (read+write) MSHR miss cycles 437system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of overall MSHR miss cycles 438system.iocache.overall_mshr_miss_latency::total 97188936 # number of overall MSHR miss cycles | 429system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses 430system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses 431system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses 432system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses 433system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles 434system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles 435system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles 436system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles 437system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles 438system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles 439system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles 440system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles |
| 439system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 440system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses | 441system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 442system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses |
| 441system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 442system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses | 443system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.999979 # mshr miss rate for WriteInvalidateReq accesses 444system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999979 # mshr miss rate for WriteInvalidateReq accesses |
| 443system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 444system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 445system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 446system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 445system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 446system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 447system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 448system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 447system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average ReadReq mshr miss latency 448system.iocache.ReadReq_avg_mshr_miss_latency::total 115839.017878 # average ReadReq mshr miss latency 449system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60723.061045 # average WriteInvalidateReq mshr miss latency 450system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60723.061045 # average WriteInvalidateReq mshr miss latency 451system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency 452system.iocache.demand_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency 453system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency 454system.iocache.overall_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency | 449system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency 450system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency 451system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60522.456336 # average WriteInvalidateReq mshr miss latency 452system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60522.456336 # average WriteInvalidateReq mshr miss latency 453system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 454system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency 455system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency 456system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency |
| 455system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 456system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 457system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 458system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 459system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 460system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 461system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 462system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 463system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 464system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 465system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 466system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 467system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 457system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 458system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 459system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 460system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 461system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 462system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 463system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 464system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 465system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 466system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 467system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 468system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 469system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 468system.iobus.trans_dist::ReadReq 230144 # Transaction distribution 469system.iobus.trans_dist::ReadResp 230144 # Transaction distribution 470system.iobus.trans_dist::WriteReq 57579 # Transaction distribution 471system.iobus.trans_dist::WriteResp 57579 # Transaction distribution 472system.iobus.trans_dist::MessageReq 1654 # Transaction distribution 473system.iobus.trans_dist::MessageResp 1654 # Transaction distribution | 470system.iobus.trans_dist::ReadReq 230267 # Transaction distribution 471system.iobus.trans_dist::ReadResp 230267 # Transaction distribution 472system.iobus.trans_dist::WriteReq 57693 # Transaction distribution 473system.iobus.trans_dist::WriteResp 57694 # Transaction distribution 474system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution 475system.iobus.trans_dist::MessageReq 1655 # Transaction distribution 476system.iobus.trans_dist::MessageResp 1655 # Transaction distribution |
| 474system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 475system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 476system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 477system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 478system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 479system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 480system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 481system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 482system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) 483system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 484system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 485system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) | 477system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 478system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 479system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 480system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 481system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 482system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 483system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 484system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 485system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) 486system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 487system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 488system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) |
| 486system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) | 489system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) |
| 487system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 488system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 489system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 490system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 491system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) | 490system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 491system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 492system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 493system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 494system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) |
| 492system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) 493system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) 494system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes) 495system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) 496system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) 497system.iobus.pkt_count::total 578754 # Packet count per connected master and slave (bytes) | 495system.iobus.pkt_count_system.bridge.master::total 480788 # Packet count per connected master and slave (bytes) 496system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes) 497system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes) 498system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) 499system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) 500system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes) |
| 498system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 499system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 500system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 501system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 503system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 504system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 505system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 506system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 507system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 508system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 509system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) | 501system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 503system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 504system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 505system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 506system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 507system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 508system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 509system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 510system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 511system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 512system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) |
| 510system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) | 513system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) |
| 511system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 512system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 513system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 514system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 515system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) | 514system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 515system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 516system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 517system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 518system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) |
| 516system.iobus.pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) 517system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) 518system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes) 519system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) 520system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) 521system.iobus.pkt_size::total 3280316 # Cumulative packet size per connected master and slave (bytes) 522system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) | 519system.iobus.pkt_size_system.bridge.master::total 246674 # Cumulative packet size per connected master and slave (bytes) 520system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes) 521system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes) 522system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) 523system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) 524system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes) 525system.iobus.reqLayer0.occupancy 3947664 # Layer occupancy (ticks) |
| 523system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 524system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 525system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 526system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 527system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 528system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 529system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 530system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) --- 9 unchanged lines hidden (view full) --- 540system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) 541system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 542system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 543system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 544system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 545system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 546system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 547system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) | 526system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 527system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 528system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 529system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 530system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 531system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 532system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 533system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) --- 9 unchanged lines hidden (view full) --- 543system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) 544system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 545system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 546system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 547system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 548system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 549system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 550system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) |
| 548system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks) | 551system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) |
| 549system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 550system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 551system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 552system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 553system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 554system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 555system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 556system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 557system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 552system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 553system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 554system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 555system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 556system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 557system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 558system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 559system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 560system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 558system.iobus.reqLayer18.occupancy 421888846 # Layer occupancy (ticks) | 561system.iobus.reqLayer18.occupancy 421906845 # Layer occupancy (ticks) |
| 559system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 560system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 561system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) | 562system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 563system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 564system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) |
| 562system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) | 565system.iobus.respLayer0.occupancy 469814000 # Layer occupancy (ticks) |
| 563system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 566system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 564system.iobus.respLayer1.occupancy 52218502 # Layer occupancy (ticks) | 567system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks) |
| 565system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) | 568system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 566system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) | 569system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) |
| 567system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 568system.cpu_clk_domain.clock 500 # Clock period in ticks 569system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 570system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 571system.cpu_clk_domain.clock 500 # Clock period in ticks 572system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 570system.cpu.numCycles 10385022088 # number of cpu cycles simulated | 573system.cpu.numCycles 10388821270 # number of cpu cycles simulated |
| 571system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 572system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 574system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 575system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 573system.cpu.committedInsts 128310974 # Number of instructions committed 574system.cpu.committedOps 247343919 # Number of ops (including micro ops) committed 575system.cpu.num_int_alu_accesses 231936467 # Number of integer alu accesses | 576system.cpu.committedInsts 128422722 # Number of instructions committed 577system.cpu.committedOps 247557000 # Number of ops (including micro ops) committed 578system.cpu.num_int_alu_accesses 232138334 # Number of integer alu accesses |
| 576system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses | 579system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses |
| 577system.cpu.num_func_calls 2299885 # number of times a function call or return occured 578system.cpu.num_conditional_control_insts 23161985 # number of instructions that are conditional controls 579system.cpu.num_int_insts 231936467 # number of integer instructions | 580system.cpu.num_func_calls 2301199 # number of times a function call or return occured 581system.cpu.num_conditional_control_insts 23183159 # number of instructions that are conditional controls 582system.cpu.num_int_insts 232138334 # number of integer instructions |
| 580system.cpu.num_fp_insts 0 # number of float instructions | 583system.cpu.num_fp_insts 0 # number of float instructions |
| 581system.cpu.num_int_register_reads 434450917 # number of times the integer registers were read 582system.cpu.num_int_register_writes 197819265 # number of times the integer registers were written | 584system.cpu.num_int_register_reads 434808798 # number of times the integer registers were read 585system.cpu.num_int_register_writes 197991574 # number of times the integer registers were written |
| 583system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 584system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 586system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 587system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 585system.cpu.num_cc_register_reads 132769519 # number of times the CC registers were read 586system.cpu.num_cc_register_writes 95505601 # number of times the CC registers were written 587system.cpu.num_mem_refs 22243286 # number of memory refs 588system.cpu.num_load_insts 13879256 # Number of load instructions 589system.cpu.num_store_insts 8364030 # Number of store instructions 590system.cpu.num_idle_cycles 9788400874.998116 # Number of idle cycles 591system.cpu.num_busy_cycles 596621213.001885 # Number of busy cycles 592system.cpu.not_idle_fraction 0.057450 # Percentage of non-idle cycles 593system.cpu.idle_fraction 0.942550 # Percentage of idle cycles 594system.cpu.Branches 26299942 # Number of branches fetched 595system.cpu.op_class::No_OpClass 174748 0.07% 0.07% # Class of executed instruction 596system.cpu.op_class::IntAlu 224664535 90.83% 90.90% # Class of executed instruction 597system.cpu.op_class::IntMult 139903 0.06% 90.96% # Class of executed instruction 598system.cpu.op_class::IntDiv 122942 0.05% 91.01% # Class of executed instruction | 588system.cpu.num_cc_register_reads 132893231 # number of times the CC registers were read 589system.cpu.num_cc_register_writes 95600147 # number of times the CC registers were written 590system.cpu.num_mem_refs 22258678 # number of memory refs 591system.cpu.num_load_insts 13887993 # Number of load instructions 592system.cpu.num_store_insts 8370685 # Number of store instructions 593system.cpu.num_idle_cycles 9791802498.998116 # Number of idle cycles 594system.cpu.num_busy_cycles 597018771.001885 # Number of busy cycles 595system.cpu.not_idle_fraction 0.057467 # Percentage of non-idle cycles 596system.cpu.idle_fraction 0.942533 # Percentage of idle cycles 597system.cpu.Branches 26323220 # Number of branches fetched 598system.cpu.op_class::No_OpClass 174807 0.07% 0.07% # Class of executed instruction 599system.cpu.op_class::IntAlu 224862012 90.83% 90.90% # Class of executed instruction 600system.cpu.op_class::IntMult 139985 0.06% 90.96% # Class of executed instruction 601system.cpu.op_class::IntDiv 123095 0.05% 91.01% # Class of executed instruction |
| 599system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction 600system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction 601system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction 602system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction 603system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction 604system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction 605system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction 606system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 617system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction 618system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction 619system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction 620system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction 621system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction 622system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction 623system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction 624system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction | 602system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction 603system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction 604system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction 605system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction 606system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction 607system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction 608system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction 609system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 620system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction 621system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction 622system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction 623system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction 624system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction 625system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction 626system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction 627system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction |
| 625system.cpu.op_class::MemRead 13879256 5.61% 96.62% # Class of executed instruction 626system.cpu.op_class::MemWrite 8364030 3.38% 100.00% # Class of executed instruction | 628system.cpu.op_class::MemRead 13887993 5.61% 96.62% # Class of executed instruction 629system.cpu.op_class::MemWrite 8370685 3.38% 100.00% # Class of executed instruction |
| 627system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 628system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 630system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 631system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 629system.cpu.op_class::total 247345414 # Class of executed instruction | 632system.cpu.op_class::total 247558577 # Class of executed instruction |
| 630system.cpu.kern.inst.arm 0 # number of arm instructions executed 631system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 633system.cpu.kern.inst.arm 0 # number of arm instructions executed 634system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 632system.cpu.icache.tags.replacements 790109 # number of replacements 633system.cpu.icache.tags.tagsinuse 510.353605 # Cycle average of tags in use 634system.cpu.icache.tags.total_refs 144545821 # Total number of references to valid blocks. 635system.cpu.icache.tags.sampled_refs 790621 # Sample count of references to valid blocks. 636system.cpu.icache.tags.avg_refs 182.825679 # Average number of references to valid blocks. 637system.cpu.icache.tags.warmup_cycle 161037022250 # Cycle when the warmup percentage was hit. 638system.cpu.icache.tags.occ_blocks::cpu.inst 510.353605 # Average occupied blocks per requestor 639system.cpu.icache.tags.occ_percent::cpu.inst 0.996784 # Average percentage of cache occupancy 640system.cpu.icache.tags.occ_percent::total 0.996784 # Average percentage of cache occupancy | 635system.cpu.icache.tags.replacements 791372 # number of replacements 636system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use 637system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks. 638system.cpu.icache.tags.sampled_refs 791884 # Sample count of references to valid blocks. 639system.cpu.icache.tags.avg_refs 182.702791 # Average number of references to valid blocks. 640system.cpu.icache.tags.warmup_cycle 161114367250 # Cycle when the warmup percentage was hit. 641system.cpu.icache.tags.occ_blocks::cpu.inst 510.348934 # Average occupied blocks per requestor 642system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy 643system.cpu.icache.tags.occ_percent::total 0.996775 # Average percentage of cache occupancy |
| 641system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 644system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 642system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 643system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id 644system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id 645system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id | 645system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 646system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id 647system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id 648system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id |
| 646system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 649system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 647system.cpu.icache.tags.tag_accesses 146127077 # Number of tag accesses 648system.cpu.icache.tags.data_accesses 146127077 # Number of data accesses 649system.cpu.icache.ReadReq_hits::cpu.inst 144545821 # number of ReadReq hits 650system.cpu.icache.ReadReq_hits::total 144545821 # number of ReadReq hits 651system.cpu.icache.demand_hits::cpu.inst 144545821 # number of demand (read+write) hits 652system.cpu.icache.demand_hits::total 144545821 # number of demand (read+write) hits 653system.cpu.icache.overall_hits::cpu.inst 144545821 # number of overall hits 654system.cpu.icache.overall_hits::total 144545821 # number of overall hits 655system.cpu.icache.ReadReq_misses::cpu.inst 790628 # number of ReadReq misses 656system.cpu.icache.ReadReq_misses::total 790628 # number of ReadReq misses 657system.cpu.icache.demand_misses::cpu.inst 790628 # number of demand (read+write) misses 658system.cpu.icache.demand_misses::total 790628 # number of demand (read+write) misses 659system.cpu.icache.overall_misses::cpu.inst 790628 # number of overall misses 660system.cpu.icache.overall_misses::total 790628 # number of overall misses 661system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108318120 # number of ReadReq miss cycles 662system.cpu.icache.ReadReq_miss_latency::total 11108318120 # number of ReadReq miss cycles 663system.cpu.icache.demand_miss_latency::cpu.inst 11108318120 # number of demand (read+write) miss cycles 664system.cpu.icache.demand_miss_latency::total 11108318120 # number of demand (read+write) miss cycles 665system.cpu.icache.overall_miss_latency::cpu.inst 11108318120 # number of overall miss cycles 666system.cpu.icache.overall_miss_latency::total 11108318120 # number of overall miss cycles 667system.cpu.icache.ReadReq_accesses::cpu.inst 145336449 # number of ReadReq accesses(hits+misses) 668system.cpu.icache.ReadReq_accesses::total 145336449 # number of ReadReq accesses(hits+misses) 669system.cpu.icache.demand_accesses::cpu.inst 145336449 # number of demand (read+write) accesses 670system.cpu.icache.demand_accesses::total 145336449 # number of demand (read+write) accesses 671system.cpu.icache.overall_accesses::cpu.inst 145336449 # number of overall (read+write) accesses 672system.cpu.icache.overall_accesses::total 145336449 # number of overall (read+write) accesses 673system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses 674system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses 675system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses 676system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses 677system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses 678system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses 679system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14049.993322 # average ReadReq miss latency 680system.cpu.icache.ReadReq_avg_miss_latency::total 14049.993322 # average ReadReq miss latency 681system.cpu.icache.demand_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency 682system.cpu.icache.demand_avg_miss_latency::total 14049.993322 # average overall miss latency 683system.cpu.icache.overall_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency 684system.cpu.icache.overall_avg_miss_latency::total 14049.993322 # average overall miss latency | 650system.cpu.icache.tags.tag_accesses 146263199 # Number of tag accesses 651system.cpu.icache.tags.data_accesses 146263199 # Number of data accesses 652system.cpu.icache.ReadReq_hits::cpu.inst 144679417 # number of ReadReq hits 653system.cpu.icache.ReadReq_hits::total 144679417 # number of ReadReq hits 654system.cpu.icache.demand_hits::cpu.inst 144679417 # number of demand (read+write) hits 655system.cpu.icache.demand_hits::total 144679417 # number of demand (read+write) hits 656system.cpu.icache.overall_hits::cpu.inst 144679417 # number of overall hits 657system.cpu.icache.overall_hits::total 144679417 # number of overall hits 658system.cpu.icache.ReadReq_misses::cpu.inst 791891 # number of ReadReq misses 659system.cpu.icache.ReadReq_misses::total 791891 # number of ReadReq misses 660system.cpu.icache.demand_misses::cpu.inst 791891 # number of demand (read+write) misses 661system.cpu.icache.demand_misses::total 791891 # number of demand (read+write) misses 662system.cpu.icache.overall_misses::cpu.inst 791891 # number of overall misses 663system.cpu.icache.overall_misses::total 791891 # number of overall misses 664system.cpu.icache.ReadReq_miss_latency::cpu.inst 11123124618 # number of ReadReq miss cycles 665system.cpu.icache.ReadReq_miss_latency::total 11123124618 # number of ReadReq miss cycles 666system.cpu.icache.demand_miss_latency::cpu.inst 11123124618 # number of demand (read+write) miss cycles 667system.cpu.icache.demand_miss_latency::total 11123124618 # number of demand (read+write) miss cycles 668system.cpu.icache.overall_miss_latency::cpu.inst 11123124618 # number of overall miss cycles 669system.cpu.icache.overall_miss_latency::total 11123124618 # number of overall miss cycles 670system.cpu.icache.ReadReq_accesses::cpu.inst 145471308 # number of ReadReq accesses(hits+misses) 671system.cpu.icache.ReadReq_accesses::total 145471308 # number of ReadReq accesses(hits+misses) 672system.cpu.icache.demand_accesses::cpu.inst 145471308 # number of demand (read+write) accesses 673system.cpu.icache.demand_accesses::total 145471308 # number of demand (read+write) accesses 674system.cpu.icache.overall_accesses::cpu.inst 145471308 # number of overall (read+write) accesses 675system.cpu.icache.overall_accesses::total 145471308 # number of overall (read+write) accesses 676system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005444 # miss rate for ReadReq accesses 677system.cpu.icache.ReadReq_miss_rate::total 0.005444 # miss rate for ReadReq accesses 678system.cpu.icache.demand_miss_rate::cpu.inst 0.005444 # miss rate for demand accesses 679system.cpu.icache.demand_miss_rate::total 0.005444 # miss rate for demand accesses 680system.cpu.icache.overall_miss_rate::cpu.inst 0.005444 # miss rate for overall accesses 681system.cpu.icache.overall_miss_rate::total 0.005444 # miss rate for overall accesses 682system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14046.282403 # average ReadReq miss latency 683system.cpu.icache.ReadReq_avg_miss_latency::total 14046.282403 # average ReadReq miss latency 684system.cpu.icache.demand_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency 685system.cpu.icache.demand_avg_miss_latency::total 14046.282403 # average overall miss latency 686system.cpu.icache.overall_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency 687system.cpu.icache.overall_avg_miss_latency::total 14046.282403 # average overall miss latency |
| 685system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 686system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 687system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 688system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 689system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 690system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 691system.cpu.icache.fast_writes 0 # number of fast writes performed 692system.cpu.icache.cache_copies 0 # number of cache copies performed | 688system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 689system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 690system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 691system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 692system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 693system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 694system.cpu.icache.fast_writes 0 # number of fast writes performed 695system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 693system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790628 # number of ReadReq MSHR misses 694system.cpu.icache.ReadReq_mshr_misses::total 790628 # number of ReadReq MSHR misses 695system.cpu.icache.demand_mshr_misses::cpu.inst 790628 # number of demand (read+write) MSHR misses 696system.cpu.icache.demand_mshr_misses::total 790628 # number of demand (read+write) MSHR misses 697system.cpu.icache.overall_mshr_misses::cpu.inst 790628 # number of overall MSHR misses 698system.cpu.icache.overall_mshr_misses::total 790628 # number of overall MSHR misses 699system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9522182380 # number of ReadReq MSHR miss cycles 700system.cpu.icache.ReadReq_mshr_miss_latency::total 9522182380 # number of ReadReq MSHR miss cycles 701system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9522182380 # number of demand (read+write) MSHR miss cycles 702system.cpu.icache.demand_mshr_miss_latency::total 9522182380 # number of demand (read+write) MSHR miss cycles 703system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9522182380 # number of overall MSHR miss cycles 704system.cpu.icache.overall_mshr_miss_latency::total 9522182380 # number of overall MSHR miss cycles 705system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses 706system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses 707system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses 708system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses 709system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses 710system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses 711system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12043.821342 # average ReadReq mshr miss latency 712system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12043.821342 # average ReadReq mshr miss latency 713system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency 714system.cpu.icache.demand_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency 715system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency 716system.cpu.icache.overall_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency | 696system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791891 # number of ReadReq MSHR misses 697system.cpu.icache.ReadReq_mshr_misses::total 791891 # number of ReadReq MSHR misses 698system.cpu.icache.demand_mshr_misses::cpu.inst 791891 # number of demand (read+write) MSHR misses 699system.cpu.icache.demand_mshr_misses::total 791891 # number of demand (read+write) MSHR misses 700system.cpu.icache.overall_mshr_misses::cpu.inst 791891 # number of overall MSHR misses 701system.cpu.icache.overall_mshr_misses::total 791891 # number of overall MSHR misses 702system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9534445382 # number of ReadReq MSHR miss cycles 703system.cpu.icache.ReadReq_mshr_miss_latency::total 9534445382 # number of ReadReq MSHR miss cycles 704system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9534445382 # number of demand (read+write) MSHR miss cycles 705system.cpu.icache.demand_mshr_miss_latency::total 9534445382 # number of demand (read+write) MSHR miss cycles 706system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9534445382 # number of overall MSHR miss cycles 707system.cpu.icache.overall_mshr_miss_latency::total 9534445382 # number of overall MSHR miss cycles 708system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for ReadReq accesses 709system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005444 # mshr miss rate for ReadReq accesses 710system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for demand accesses 711system.cpu.icache.demand_mshr_miss_rate::total 0.005444 # mshr miss rate for demand accesses 712system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for overall accesses 713system.cpu.icache.overall_mshr_miss_rate::total 0.005444 # mshr miss rate for overall accesses 714system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12040.098173 # average ReadReq mshr miss latency 715system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12040.098173 # average ReadReq mshr miss latency 716system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency 717system.cpu.icache.demand_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency 718system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency 719system.cpu.icache.overall_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency |
| 717system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 720system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 718system.cpu.itb_walker_cache.tags.replacements 3485 # number of replacements 719system.cpu.itb_walker_cache.tags.tagsinuse 3.066895 # Cycle average of tags in use 720system.cpu.itb_walker_cache.tags.total_refs 7845 # Total number of references to valid blocks. 721system.cpu.itb_walker_cache.tags.sampled_refs 3494 # Sample count of references to valid blocks. 722system.cpu.itb_walker_cache.tags.avg_refs 2.245278 # Average number of references to valid blocks. 723system.cpu.itb_walker_cache.tags.warmup_cycle 5167508806000 # Cycle when the warmup percentage was hit. 724system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.066895 # Average occupied blocks per requestor 725system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191681 # Average percentage of cache occupancy 726system.cpu.itb_walker_cache.tags.occ_percent::total 0.191681 # Average percentage of cache occupancy 727system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 9 # Occupied blocks per task id | 721system.cpu.itb_walker_cache.tags.replacements 3756 # number of replacements 722system.cpu.itb_walker_cache.tags.tagsinuse 3.071335 # Cycle average of tags in use 723system.cpu.itb_walker_cache.tags.total_refs 7599 # Total number of references to valid blocks. 724system.cpu.itb_walker_cache.tags.sampled_refs 3768 # Sample count of references to valid blocks. 725system.cpu.itb_walker_cache.tags.avg_refs 2.016720 # Average number of references to valid blocks. 726system.cpu.itb_walker_cache.tags.warmup_cycle 5167567118000 # Cycle when the warmup percentage was hit. 727system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071335 # Average occupied blocks per requestor 728system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191958 # Average percentage of cache occupancy 729system.cpu.itb_walker_cache.tags.occ_percent::total 0.191958 # Average percentage of cache occupancy 730system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id |
| 728system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id | 731system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id |
| 729system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 730system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 731system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.562500 # Percentage of cache occupancy per task id 732system.cpu.itb_walker_cache.tags.tag_accesses 28811 # Number of tag accesses 733system.cpu.itb_walker_cache.tags.data_accesses 28811 # Number of data accesses 734system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7868 # number of ReadReq hits 735system.cpu.itb_walker_cache.ReadReq_hits::total 7868 # number of ReadReq hits | 732system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 733system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id 734system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 735system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id 736system.cpu.itb_walker_cache.tags.tag_accesses 29071 # Number of tag accesses 737system.cpu.itb_walker_cache.tags.data_accesses 29071 # Number of data accesses 738system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7599 # number of ReadReq hits 739system.cpu.itb_walker_cache.ReadReq_hits::total 7599 # number of ReadReq hits |
| 736system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 737system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 740system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 741system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 738system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7870 # number of demand (read+write) hits 739system.cpu.itb_walker_cache.demand_hits::total 7870 # number of demand (read+write) hits 740system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7870 # number of overall hits 741system.cpu.itb_walker_cache.overall_hits::total 7870 # number of overall hits 742system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4357 # number of ReadReq misses 743system.cpu.itb_walker_cache.ReadReq_misses::total 4357 # number of ReadReq misses 744system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4357 # number of demand (read+write) misses 745system.cpu.itb_walker_cache.demand_misses::total 4357 # number of demand (read+write) misses 746system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4357 # number of overall misses 747system.cpu.itb_walker_cache.overall_misses::total 4357 # number of overall misses 748system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43584500 # number of ReadReq miss cycles 749system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43584500 # number of ReadReq miss cycles 750system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43584500 # number of demand (read+write) miss cycles 751system.cpu.itb_walker_cache.demand_miss_latency::total 43584500 # number of demand (read+write) miss cycles 752system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43584500 # number of overall miss cycles 753system.cpu.itb_walker_cache.overall_miss_latency::total 43584500 # number of overall miss cycles 754system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) 755system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) | 742system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7601 # number of demand (read+write) hits 743system.cpu.itb_walker_cache.demand_hits::total 7601 # number of demand (read+write) hits 744system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7601 # number of overall hits 745system.cpu.itb_walker_cache.overall_hits::total 7601 # number of overall hits 746system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4623 # number of ReadReq misses 747system.cpu.itb_walker_cache.ReadReq_misses::total 4623 # number of ReadReq misses 748system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4623 # number of demand (read+write) misses 749system.cpu.itb_walker_cache.demand_misses::total 4623 # number of demand (read+write) misses 750system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4623 # number of overall misses 751system.cpu.itb_walker_cache.overall_misses::total 4623 # number of overall misses 752system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 47504750 # number of ReadReq miss cycles 753system.cpu.itb_walker_cache.ReadReq_miss_latency::total 47504750 # number of ReadReq miss cycles 754system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 47504750 # number of demand (read+write) miss cycles 755system.cpu.itb_walker_cache.demand_miss_latency::total 47504750 # number of demand (read+write) miss cycles 756system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 47504750 # number of overall miss cycles 757system.cpu.itb_walker_cache.overall_miss_latency::total 47504750 # number of overall miss cycles 758system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12222 # number of ReadReq accesses(hits+misses) 759system.cpu.itb_walker_cache.ReadReq_accesses::total 12222 # number of ReadReq accesses(hits+misses) |
| 756system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 757system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 760system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 761system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 758system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses 759system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 760system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses 761system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 762system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356401 # miss rate for ReadReq accesses 763system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356401 # miss rate for ReadReq accesses 764system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356343 # miss rate for demand accesses 765system.cpu.itb_walker_cache.demand_miss_rate::total 0.356343 # miss rate for demand accesses 766system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356343 # miss rate for overall accesses 767system.cpu.itb_walker_cache.overall_miss_rate::total 0.356343 # miss rate for overall accesses 768system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10003.327978 # average ReadReq miss latency 769system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10003.327978 # average ReadReq miss latency 770system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency 771system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10003.327978 # average overall miss latency 772system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency 773system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10003.327978 # average overall miss latency | 762system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12224 # number of demand (read+write) accesses 763system.cpu.itb_walker_cache.demand_accesses::total 12224 # number of demand (read+write) accesses 764system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12224 # number of overall (read+write) accesses 765system.cpu.itb_walker_cache.overall_accesses::total 12224 # number of overall (read+write) accesses 766system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.378252 # miss rate for ReadReq accesses 767system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.378252 # miss rate for ReadReq accesses 768system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.378190 # miss rate for demand accesses 769system.cpu.itb_walker_cache.demand_miss_rate::total 0.378190 # miss rate for demand accesses 770system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.378190 # miss rate for overall accesses 771system.cpu.itb_walker_cache.overall_miss_rate::total 0.378190 # miss rate for overall accesses 772system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10275.740861 # average ReadReq miss latency 773system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10275.740861 # average ReadReq miss latency 774system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency 775system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10275.740861 # average overall miss latency 776system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency 777system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10275.740861 # average overall miss latency |
| 774system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 775system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 776system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 777system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 778system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 779system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 780system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 781system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 778system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 779system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 780system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 781system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 782system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 783system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 784system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 785system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 782system.cpu.itb_walker_cache.writebacks::writebacks 747 # number of writebacks 783system.cpu.itb_walker_cache.writebacks::total 747 # number of writebacks 784system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4357 # number of ReadReq MSHR misses 785system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4357 # number of ReadReq MSHR misses 786system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4357 # number of demand (read+write) MSHR misses 787system.cpu.itb_walker_cache.demand_mshr_misses::total 4357 # number of demand (read+write) MSHR misses 788system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4357 # number of overall MSHR misses 789system.cpu.itb_walker_cache.overall_mshr_misses::total 4357 # number of overall MSHR misses 790system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34868500 # number of ReadReq MSHR miss cycles 791system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34868500 # number of ReadReq MSHR miss cycles 792system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34868500 # number of demand (read+write) MSHR miss cycles 793system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34868500 # number of demand (read+write) MSHR miss cycles 794system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34868500 # number of overall MSHR miss cycles 795system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34868500 # number of overall MSHR miss cycles 796system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356401 # mshr miss rate for ReadReq accesses 797system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356401 # mshr miss rate for ReadReq accesses 798system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for demand accesses 799system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356343 # mshr miss rate for demand accesses 800system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for overall accesses 801system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356343 # mshr miss rate for overall accesses 802system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average ReadReq mshr miss latency 803system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8002.868947 # average ReadReq mshr miss latency 804system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency 805system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency 806system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency 807system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency | 786system.cpu.itb_walker_cache.writebacks::writebacks 825 # number of writebacks 787system.cpu.itb_walker_cache.writebacks::total 825 # number of writebacks 788system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4623 # number of ReadReq MSHR misses 789system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4623 # number of ReadReq MSHR misses 790system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4623 # number of demand (read+write) MSHR misses 791system.cpu.itb_walker_cache.demand_mshr_misses::total 4623 # number of demand (read+write) MSHR misses 792system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4623 # number of overall MSHR misses 793system.cpu.itb_walker_cache.overall_mshr_misses::total 4623 # number of overall MSHR misses 794system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38257250 # number of ReadReq MSHR miss cycles 795system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38257250 # number of ReadReq MSHR miss cycles 796system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38257250 # number of demand (read+write) MSHR miss cycles 797system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38257250 # number of demand (read+write) MSHR miss cycles 798system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38257250 # number of overall MSHR miss cycles 799system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38257250 # number of overall MSHR miss cycles 800system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.378252 # mshr miss rate for ReadReq accesses 801system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.378252 # mshr miss rate for ReadReq accesses 802system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for demand accesses 803system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.378190 # mshr miss rate for demand accesses 804system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for overall accesses 805system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.378190 # mshr miss rate for overall accesses 806system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average ReadReq mshr miss latency 807system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8275.416396 # average ReadReq mshr miss latency 808system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency 809system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency 810system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency 811system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency |
| 808system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 812system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 809system.cpu.dtb_walker_cache.tags.replacements 7826 # number of replacements 810system.cpu.dtb_walker_cache.tags.tagsinuse 5.051872 # Cycle average of tags in use 811system.cpu.dtb_walker_cache.tags.total_refs 12792 # Total number of references to valid blocks. 812system.cpu.dtb_walker_cache.tags.sampled_refs 7842 # Sample count of references to valid blocks. 813system.cpu.dtb_walker_cache.tags.avg_refs 1.631217 # Average number of references to valid blocks. 814system.cpu.dtb_walker_cache.tags.warmup_cycle 5165211267000 # Cycle when the warmup percentage was hit. 815system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051872 # Average occupied blocks per requestor 816system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315742 # Average percentage of cache occupancy 817system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315742 # Average percentage of cache occupancy 818system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id | 813system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements 814system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use 815system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks. 816system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks. 817system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks. 818system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit. 819system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor 820system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy 821system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy 822system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id |
| 819system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id | 823system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id |
| 820system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id | 824system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id |
| 821system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id | 825system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id |
| 822system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 823system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 824system.cpu.dtb_walker_cache.tags.tag_accesses 52641 # Number of tag accesses 825system.cpu.dtb_walker_cache.tags.data_accesses 52641 # Number of data accesses 826system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12792 # number of ReadReq hits 827system.cpu.dtb_walker_cache.ReadReq_hits::total 12792 # number of ReadReq hits 828system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12792 # number of demand (read+write) hits 829system.cpu.dtb_walker_cache.demand_hits::total 12792 # number of demand (read+write) hits 830system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12792 # number of overall hits 831system.cpu.dtb_walker_cache.overall_hits::total 12792 # number of overall hits 832system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9019 # number of ReadReq misses 833system.cpu.dtb_walker_cache.ReadReq_misses::total 9019 # number of ReadReq misses 834system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9019 # number of demand (read+write) misses 835system.cpu.dtb_walker_cache.demand_misses::total 9019 # number of demand (read+write) misses 836system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9019 # number of overall misses 837system.cpu.dtb_walker_cache.overall_misses::total 9019 # number of overall misses 838system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95783000 # number of ReadReq miss cycles 839system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95783000 # number of ReadReq miss cycles 840system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95783000 # number of demand (read+write) miss cycles 841system.cpu.dtb_walker_cache.demand_miss_latency::total 95783000 # number of demand (read+write) miss cycles 842system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95783000 # number of overall miss cycles 843system.cpu.dtb_walker_cache.overall_miss_latency::total 95783000 # number of overall miss cycles 844system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21811 # number of ReadReq accesses(hits+misses) 845system.cpu.dtb_walker_cache.ReadReq_accesses::total 21811 # number of ReadReq accesses(hits+misses) 846system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21811 # number of demand (read+write) accesses 847system.cpu.dtb_walker_cache.demand_accesses::total 21811 # number of demand (read+write) accesses 848system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21811 # number of overall (read+write) accesses 849system.cpu.dtb_walker_cache.overall_accesses::total 21811 # number of overall (read+write) accesses 850system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.413507 # miss rate for ReadReq accesses 851system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.413507 # miss rate for ReadReq accesses 852system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.413507 # miss rate for demand accesses 853system.cpu.dtb_walker_cache.demand_miss_rate::total 0.413507 # miss rate for demand accesses 854system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.413507 # miss rate for overall accesses 855system.cpu.dtb_walker_cache.overall_miss_rate::total 0.413507 # miss rate for overall accesses 856system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10620.135270 # average ReadReq miss latency 857system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10620.135270 # average ReadReq miss latency 858system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency 859system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10620.135270 # average overall miss latency 860system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency 861system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10620.135270 # average overall miss latency | 826system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 827system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses 828system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses 829system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits 830system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits 831system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits 832system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits 833system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits 834system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits 835system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses 836system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses 837system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses 838system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses 839system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses 840system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses 841system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles 842system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles 843system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles 844system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles 845system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles 846system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles 847system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses) 848system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses) 849system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses 850system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses 851system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses 852system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses 853system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses 854system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses 855system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses 856system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses 857system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses 858system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses 859system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency 860system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency 861system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency 862system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency 863system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency 864system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency |
| 862system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 863system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 864system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 865system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 866system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 867system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 868system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 869system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 865system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 866system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 867system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 868system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 869system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 870system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 871system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 872system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 870system.cpu.dtb_walker_cache.writebacks::writebacks 2842 # number of writebacks 871system.cpu.dtb_walker_cache.writebacks::total 2842 # number of writebacks 872system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9019 # number of ReadReq MSHR misses 873system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9019 # number of ReadReq MSHR misses 874system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9019 # number of demand (read+write) MSHR misses 875system.cpu.dtb_walker_cache.demand_mshr_misses::total 9019 # number of demand (read+write) MSHR misses 876system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9019 # number of overall MSHR misses 877system.cpu.dtb_walker_cache.overall_mshr_misses::total 9019 # number of overall MSHR misses 878system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77744500 # number of ReadReq MSHR miss cycles 879system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77744500 # number of ReadReq MSHR miss cycles 880system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77744500 # number of demand (read+write) MSHR miss cycles 881system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77744500 # number of demand (read+write) MSHR miss cycles 882system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77744500 # number of overall MSHR miss cycles 883system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77744500 # number of overall MSHR miss cycles 884system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for ReadReq accesses 885system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.413507 # mshr miss rate for ReadReq accesses 886system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for demand accesses 887system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.413507 # mshr miss rate for demand accesses 888system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for overall accesses 889system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.413507 # mshr miss rate for overall accesses 890system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average ReadReq mshr miss latency 891system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8620.079831 # average ReadReq mshr miss latency 892system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency 893system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency 894system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency 895system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency | 873system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks 874system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks 875system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses 876system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses 877system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses 878system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses 879system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses 880system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses 881system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles 882system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles 883system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles 884system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles 885system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles 886system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles 887system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses 888system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses 889system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses 890system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses 891system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses 892system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses 893system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency 894system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency 895system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency 896system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency 897system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency 898system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency |
| 896system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 899system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 897system.cpu.dcache.tags.replacements 1621218 # number of replacements 898system.cpu.dcache.tags.tagsinuse 511.996934 # Cycle average of tags in use 899system.cpu.dcache.tags.total_refs 20024389 # Total number of references to valid blocks. 900system.cpu.dcache.tags.sampled_refs 1621730 # Sample count of references to valid blocks. 901system.cpu.dcache.tags.avg_refs 12.347548 # Average number of references to valid blocks. | 900system.cpu.dcache.tags.replacements 1622351 # number of replacements 901system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use 902system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks. 903system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks. 904system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks. |
| 902system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. | 905system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. |
| 903system.cpu.dcache.tags.occ_blocks::cpu.data 511.996934 # Average occupied blocks per requestor | 906system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor |
| 904system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 905system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 906system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 907system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 908system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 909system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 907system.cpu.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 908system.cpu.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id 909system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id | 910system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 911system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id 912system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id 913system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id |
| 910system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 914system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 911system.cpu.dcache.tags.tag_accesses 88244906 # Number of tag accesses 912system.cpu.dcache.tags.data_accesses 88244906 # Number of data accesses 913system.cpu.dcache.ReadReq_hits::cpu.data 11933720 # number of ReadReq hits 914system.cpu.dcache.ReadReq_hits::total 11933720 # number of ReadReq hits 915system.cpu.dcache.WriteReq_hits::cpu.data 8029176 # number of WriteReq hits 916system.cpu.dcache.WriteReq_hits::total 8029176 # number of WriteReq hits 917system.cpu.dcache.SoftPFReq_hits::cpu.data 59323 # number of SoftPFReq hits 918system.cpu.dcache.SoftPFReq_hits::total 59323 # number of SoftPFReq hits 919system.cpu.dcache.demand_hits::cpu.data 19962896 # number of demand (read+write) hits 920system.cpu.dcache.demand_hits::total 19962896 # number of demand (read+write) hits 921system.cpu.dcache.overall_hits::cpu.data 20022219 # number of overall hits 922system.cpu.dcache.overall_hits::total 20022219 # number of overall hits 923system.cpu.dcache.ReadReq_misses::cpu.data 906567 # number of ReadReq misses 924system.cpu.dcache.ReadReq_misses::total 906567 # number of ReadReq misses 925system.cpu.dcache.WriteReq_misses::cpu.data 324536 # number of WriteReq misses 926system.cpu.dcache.WriteReq_misses::total 324536 # number of WriteReq misses 927system.cpu.dcache.SoftPFReq_misses::cpu.data 402460 # number of SoftPFReq misses 928system.cpu.dcache.SoftPFReq_misses::total 402460 # number of SoftPFReq misses 929system.cpu.dcache.demand_misses::cpu.data 1231103 # number of demand (read+write) misses 930system.cpu.dcache.demand_misses::total 1231103 # number of demand (read+write) misses 931system.cpu.dcache.overall_misses::cpu.data 1633563 # number of overall misses 932system.cpu.dcache.overall_misses::total 1633563 # number of overall misses 933system.cpu.dcache.ReadReq_miss_latency::cpu.data 12726532750 # number of ReadReq miss cycles 934system.cpu.dcache.ReadReq_miss_latency::total 12726532750 # number of ReadReq miss cycles 935system.cpu.dcache.WriteReq_miss_latency::cpu.data 11379509067 # number of WriteReq miss cycles 936system.cpu.dcache.WriteReq_miss_latency::total 11379509067 # number of WriteReq miss cycles 937system.cpu.dcache.demand_miss_latency::cpu.data 24106041817 # number of demand (read+write) miss cycles 938system.cpu.dcache.demand_miss_latency::total 24106041817 # number of demand (read+write) miss cycles 939system.cpu.dcache.overall_miss_latency::cpu.data 24106041817 # number of overall miss cycles 940system.cpu.dcache.overall_miss_latency::total 24106041817 # number of overall miss cycles 941system.cpu.dcache.ReadReq_accesses::cpu.data 12840287 # number of ReadReq accesses(hits+misses) 942system.cpu.dcache.ReadReq_accesses::total 12840287 # number of ReadReq accesses(hits+misses) 943system.cpu.dcache.WriteReq_accesses::cpu.data 8353712 # number of WriteReq accesses(hits+misses) 944system.cpu.dcache.WriteReq_accesses::total 8353712 # number of WriteReq accesses(hits+misses) 945system.cpu.dcache.SoftPFReq_accesses::cpu.data 461783 # number of SoftPFReq accesses(hits+misses) 946system.cpu.dcache.SoftPFReq_accesses::total 461783 # number of SoftPFReq accesses(hits+misses) 947system.cpu.dcache.demand_accesses::cpu.data 21193999 # number of demand (read+write) accesses 948system.cpu.dcache.demand_accesses::total 21193999 # number of demand (read+write) accesses 949system.cpu.dcache.overall_accesses::cpu.data 21655782 # number of overall (read+write) accesses 950system.cpu.dcache.overall_accesses::total 21655782 # number of overall (read+write) accesses 951system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070603 # miss rate for ReadReq accesses 952system.cpu.dcache.ReadReq_miss_rate::total 0.070603 # miss rate for ReadReq accesses 953system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038849 # miss rate for WriteReq accesses 954system.cpu.dcache.WriteReq_miss_rate::total 0.038849 # miss rate for WriteReq accesses 955system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871535 # miss rate for SoftPFReq accesses 956system.cpu.dcache.SoftPFReq_miss_rate::total 0.871535 # miss rate for SoftPFReq accesses 957system.cpu.dcache.demand_miss_rate::cpu.data 0.058087 # miss rate for demand accesses 958system.cpu.dcache.demand_miss_rate::total 0.058087 # miss rate for demand accesses | 915system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses 916system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses 917system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits 918system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits 919system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits 920system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits 921system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits 922system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits 923system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits 924system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits 925system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits 926system.cpu.dcache.overall_hits::total 20036172 # number of overall hits 927system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses 928system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses 929system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses 930system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses 931system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses 932system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses 933system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses 934system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses 935system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses 936system.cpu.dcache.overall_misses::total 1634692 # number of overall misses 937system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles 938system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles 939system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles 940system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles 941system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles 942system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles 943system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles 944system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles 945system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses) 946system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses) 947system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses) 948system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses) 949system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses) 950system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses) 951system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses 952system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses 953system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses 954system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses 955system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses 956system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses 957system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses 958system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses 959system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses 960system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses 961system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses 962system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses |
| 959system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses 960system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses | 963system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses 964system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses |
| 961system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.160169 # average ReadReq miss latency 962system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.160169 # average ReadReq miss latency 963system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35063.934562 # average WriteReq miss latency 964system.cpu.dcache.WriteReq_avg_miss_latency::total 35063.934562 # average WriteReq miss latency 965system.cpu.dcache.demand_avg_miss_latency::cpu.data 19580.848895 # average overall miss latency 966system.cpu.dcache.demand_avg_miss_latency::total 19580.848895 # average overall miss latency 967system.cpu.dcache.overall_avg_miss_latency::cpu.data 14756.726136 # average overall miss latency 968system.cpu.dcache.overall_avg_miss_latency::total 14756.726136 # average overall miss latency 969system.cpu.dcache.blocked_cycles::no_mshrs 8324 # number of cycles access was blocked | 965system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency 966system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency 967system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency 968system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency 969system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency 970system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency 971system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency 972system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency 973system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked |
| 970system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 974system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 971system.cpu.dcache.blocked::no_mshrs 80 # number of cycles access was blocked | 975system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked |
| 972system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 976system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 973system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.050000 # average number of cycles each access was blocked | 977system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked |
| 974system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 975system.cpu.dcache.fast_writes 0 # number of fast writes performed 976system.cpu.dcache.cache_copies 0 # number of cache copies performed | 978system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 979system.cpu.dcache.fast_writes 0 # number of fast writes performed 980system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 977system.cpu.dcache.writebacks::writebacks 1537872 # number of writebacks 978system.cpu.dcache.writebacks::total 1537872 # number of writebacks 979system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits 980system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits 981system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9293 # number of WriteReq MSHR hits 982system.cpu.dcache.WriteReq_mshr_hits::total 9293 # number of WriteReq MSHR hits 983system.cpu.dcache.demand_mshr_hits::cpu.data 9580 # number of demand (read+write) MSHR hits 984system.cpu.dcache.demand_mshr_hits::total 9580 # number of demand (read+write) MSHR hits 985system.cpu.dcache.overall_mshr_hits::cpu.data 9580 # number of overall MSHR hits 986system.cpu.dcache.overall_mshr_hits::total 9580 # number of overall MSHR hits 987system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906280 # number of ReadReq MSHR misses 988system.cpu.dcache.ReadReq_mshr_misses::total 906280 # number of ReadReq MSHR misses 989system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315243 # number of WriteReq MSHR misses 990system.cpu.dcache.WriteReq_mshr_misses::total 315243 # number of WriteReq MSHR misses 991system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402425 # number of SoftPFReq MSHR misses 992system.cpu.dcache.SoftPFReq_mshr_misses::total 402425 # number of SoftPFReq MSHR misses 993system.cpu.dcache.demand_mshr_misses::cpu.data 1221523 # number of demand (read+write) MSHR misses 994system.cpu.dcache.demand_mshr_misses::total 1221523 # number of demand (read+write) MSHR misses 995system.cpu.dcache.overall_mshr_misses::cpu.data 1623948 # number of overall MSHR misses 996system.cpu.dcache.overall_mshr_misses::total 1623948 # number of overall MSHR misses 997system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10906302000 # number of ReadReq MSHR miss cycles 998system.cpu.dcache.ReadReq_mshr_miss_latency::total 10906302000 # number of ReadReq MSHR miss cycles 999system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245705379 # number of WriteReq MSHR miss cycles 1000system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245705379 # number of WriteReq MSHR miss cycles 1001system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5368514000 # number of SoftPFReq MSHR miss cycles 1002system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5368514000 # number of SoftPFReq MSHR miss cycles 1003system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21152007379 # number of demand (read+write) MSHR miss cycles 1004system.cpu.dcache.demand_mshr_miss_latency::total 21152007379 # number of demand (read+write) MSHR miss cycles 1005system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26520521379 # number of overall MSHR miss cycles 1006system.cpu.dcache.overall_mshr_miss_latency::total 26520521379 # number of overall MSHR miss cycles 1007system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672000 # number of ReadReq MSHR uncacheable cycles 1008system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672000 # number of ReadReq MSHR uncacheable cycles 1009system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536037000 # number of WriteReq MSHR uncacheable cycles 1010system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536037000 # number of WriteReq MSHR uncacheable cycles 1011system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96750709000 # number of overall MSHR uncacheable cycles 1012system.cpu.dcache.overall_mshr_uncacheable_latency::total 96750709000 # number of overall MSHR uncacheable cycles 1013system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070581 # mshr miss rate for ReadReq accesses 1014system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070581 # mshr miss rate for ReadReq accesses 1015system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037737 # mshr miss rate for WriteReq accesses 1016system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037737 # mshr miss rate for WriteReq accesses 1017system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871459 # mshr miss rate for SoftPFReq accesses 1018system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871459 # mshr miss rate for SoftPFReq accesses 1019system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057635 # mshr miss rate for demand accesses 1020system.cpu.dcache.demand_mshr_miss_rate::total 0.057635 # mshr miss rate for demand accesses 1021system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074989 # mshr miss rate for overall accesses 1022system.cpu.dcache.overall_mshr_miss_rate::total 0.074989 # mshr miss rate for overall accesses 1023system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12034.141766 # average ReadReq mshr miss latency 1024system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12034.141766 # average ReadReq mshr miss latency 1025system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32500.976640 # average WriteReq mshr miss latency 1026system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32500.976640 # average WriteReq mshr miss latency 1027system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13340.408772 # average SoftPFReq mshr miss latency 1028system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13340.408772 # average SoftPFReq mshr miss latency 1029system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17316.094236 # average overall mshr miss latency 1030system.cpu.dcache.demand_avg_mshr_miss_latency::total 17316.094236 # average overall mshr miss latency 1031system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16330.893218 # average overall mshr miss latency 1032system.cpu.dcache.overall_avg_mshr_miss_latency::total 16330.893218 # average overall mshr miss latency | 981system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks 982system.cpu.dcache.writebacks::total 1538923 # number of writebacks 983system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits 984system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits 985system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits 986system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits 987system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits 988system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits 989system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits 990system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits 991system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses 992system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses 993system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses 994system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses 995system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses 996system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses 997system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses 998system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses 999system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses 1000system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses 1001system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles 1002system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles 1003system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles 1004system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles 1005system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles 1006system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles 1007system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles 1008system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles 1009system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles 1010system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles 1011system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94240373000 # number of ReadReq MSHR uncacheable cycles 1012system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94240373000 # number of ReadReq MSHR uncacheable cycles 1013system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles 1014system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles 1015system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles 1016system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles 1017system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses 1018system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses 1019system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses 1020system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses 1021system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses 1022system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses 1023system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses 1024system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses 1025system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses 1026system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses 1027system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency 1028system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency 1029system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency 1030system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency 1031system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency 1032system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency 1033system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency 1034system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency 1035system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency 1036system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency |
| 1033system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1034system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1035system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1036system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1037system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1038system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1039system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1037system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1038system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1039system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1040system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1041system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1042system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1043system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1040system.cpu.toL2Bus.trans_dist::ReadReq 2694994 # Transaction distribution 1041system.cpu.toL2Bus.trans_dist::ReadResp 2694474 # Transaction distribution 1042system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution 1043system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution 1044system.cpu.toL2Bus.trans_dist::Writeback 1541461 # Transaction distribution | 1044system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution 1045system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution 1046system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution 1047system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution 1048system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution |
| 1045system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution | 1049system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution |
| 1046system.cpu.toL2Bus.trans_dist::UpgradeReq 2183 # Transaction distribution 1047system.cpu.toL2Bus.trans_dist::UpgradeResp 2183 # Transaction distribution 1048system.cpu.toL2Bus.trans_dist::ReadExReq 313073 # Transaction distribution 1049system.cpu.toL2Bus.trans_dist::ReadExResp 313073 # Transaction distribution 1050system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581243 # Packet count per connected master and slave (bytes) 1051system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5975195 # Packet count per connected master and slave (bytes) 1052system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7975 # Packet count per connected master and slave (bytes) 1053system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18479 # Packet count per connected master and slave (bytes) 1054system.cpu.toL2Bus.pkt_count::total 7582892 # Packet count per connected master and slave (bytes) 1055system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50599360 # Cumulative packet size per connected master and slave (bytes) 1056system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203853221 # Cumulative packet size per connected master and slave (bytes) 1057system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 231552 # Cumulative packet size per connected master and slave (bytes) 1058system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605440 # Cumulative packet size per connected master and slave (bytes) 1059system.cpu.toL2Bus.pkt_size::total 255289573 # Cumulative packet size per connected master and slave (bytes) 1060system.cpu.toL2Bus.snoops 53135 # Total snoops (count) 1061system.cpu.toL2Bus.snoop_fanout::samples 4016986 # Request fanout histogram 1062system.cpu.toL2Bus.snoop_fanout::mean 3.011840 # Request fanout histogram 1063system.cpu.toL2Bus.snoop_fanout::stdev 0.108164 # Request fanout histogram | 1050system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution 1051system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution 1052system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution 1053system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution 1054system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes) 1055system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes) 1056system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes) 1057system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes) 1058system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes) 1059system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes) 1060system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes) 1061system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes) 1062system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes) 1063system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes) 1064system.cpu.toL2Bus.snoops 52938 # Total snoops (count) 1065system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram 1066system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram 1067system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram |
| 1064system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1065system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1066system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1067system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1068system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1069system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1070system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1071system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1068system.cpu.toL2Bus.snoop_fanout::3 3969426 98.82% 98.82% # Request fanout histogram 1069system.cpu.toL2Bus.snoop_fanout::4 47560 1.18% 100.00% # Request fanout histogram | 1072system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram 1073system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram |
| 1070system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1071system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1072system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 1074system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1075system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1076system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 1073system.cpu.toL2Bus.snoop_fanout::total 4016986 # Request fanout histogram 1074system.cpu.toL2Bus.reqLayer0.occupancy 3830670000 # Layer occupancy (ticks) | 1077system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram 1078system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks) |
| 1075system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1079system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1076system.cpu.toL2Bus.snoopLayer0.occupancy 478500 # Layer occupancy (ticks) | 1080system.cpu.toL2Bus.snoopLayer0.occupancy 487500 # Layer occupancy (ticks) |
| 1077system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1081system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1078system.cpu.toL2Bus.respLayer0.occupancy 1188381870 # Layer occupancy (ticks) | 1082system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks) |
| 1079system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1083system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1080system.cpu.toL2Bus.respLayer1.occupancy 3052447844 # Layer occupancy (ticks) | 1084system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks) |
| 1081system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1085system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1082system.cpu.toL2Bus.respLayer2.occupancy 6536500 # Layer occupancy (ticks) | 1086system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks) |
| 1083system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1087system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1084system.cpu.toL2Bus.respLayer3.occupancy 13528750 # Layer occupancy (ticks) | 1088system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks) |
| 1085system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1089system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1086system.cpu.l2cache.tags.replacements 87289 # number of replacements 1087system.cpu.l2cache.tags.tagsinuse 64708.241819 # Cycle average of tags in use 1088system.cpu.l2cache.tags.total_refs 3488268 # Total number of references to valid blocks. 1089system.cpu.l2cache.tags.sampled_refs 151942 # Sample count of references to valid blocks. 1090system.cpu.l2cache.tags.avg_refs 22.957892 # Average number of references to valid blocks. | 1090system.cpu.l2cache.tags.replacements 87384 # number of replacements 1091system.cpu.l2cache.tags.tagsinuse 64746.924059 # Cycle average of tags in use 1092system.cpu.l2cache.tags.total_refs 3489247 # Total number of references to valid blocks. 1093system.cpu.l2cache.tags.sampled_refs 152088 # Sample count of references to valid blocks. 1094system.cpu.l2cache.tags.avg_refs 22.942290 # Average number of references to valid blocks. |
| 1091system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1095system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1092system.cpu.l2cache.tags.occ_blocks::writebacks 50201.970335 # Average occupied blocks per requestor 1093system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.012829 # Average occupied blocks per requestor 1094system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor 1095system.cpu.l2cache.tags.occ_blocks::cpu.inst 3236.502324 # Average occupied blocks per requestor 1096system.cpu.l2cache.tags.occ_blocks::cpu.data 11269.615072 # Average occupied blocks per requestor 1097system.cpu.l2cache.tags.occ_percent::writebacks 0.766021 # Average percentage of cache occupancy | 1096system.cpu.l2cache.tags.occ_blocks::writebacks 50375.433193 # Average occupied blocks per requestor 1097system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006760 # Average occupied blocks per requestor 1098system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141629 # Average occupied blocks per requestor 1099system.cpu.l2cache.tags.occ_blocks::cpu.inst 3244.771000 # Average occupied blocks per requestor 1100system.cpu.l2cache.tags.occ_blocks::cpu.data 11126.571476 # Average occupied blocks per requestor 1101system.cpu.l2cache.tags.occ_percent::writebacks 0.768668 # Average percentage of cache occupancy |
| 1098system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 1099system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 1102system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 1103system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 1100system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049385 # Average percentage of cache occupancy 1101system.cpu.l2cache.tags.occ_percent::cpu.data 0.171961 # Average percentage of cache occupancy 1102system.cpu.l2cache.tags.occ_percent::total 0.987369 # Average percentage of cache occupancy 1103system.cpu.l2cache.tags.occ_task_id_blocks::1024 64653 # Occupied blocks per task id 1104system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 1105system.cpu.l2cache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id 1106system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id 1107system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4737 # Occupied blocks per task id 1108system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56942 # Occupied blocks per task id 1109system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986526 # Percentage of cache occupancy per task id 1110system.cpu.l2cache.tags.tag_accesses 32181921 # Number of tag accesses 1111system.cpu.l2cache.tags.data_accesses 32181921 # Number of data accesses 1112system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6616 # number of ReadReq hits 1113system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2866 # number of ReadReq hits 1114system.cpu.l2cache.ReadReq_hits::cpu.inst 777686 # number of ReadReq hits 1115system.cpu.l2cache.ReadReq_hits::cpu.data 1279269 # number of ReadReq hits 1116system.cpu.l2cache.ReadReq_hits::total 2066437 # number of ReadReq hits 1117system.cpu.l2cache.Writeback_hits::writebacks 1541461 # number of Writeback hits 1118system.cpu.l2cache.Writeback_hits::total 1541461 # number of Writeback hits 1119system.cpu.l2cache.UpgradeReq_hits::cpu.data 312 # number of UpgradeReq hits 1120system.cpu.l2cache.UpgradeReq_hits::total 312 # number of UpgradeReq hits 1121system.cpu.l2cache.ReadExReq_hits::cpu.data 199613 # number of ReadExReq hits 1122system.cpu.l2cache.ReadExReq_hits::total 199613 # number of ReadExReq hits 1123system.cpu.l2cache.demand_hits::cpu.dtb.walker 6616 # number of demand (read+write) hits 1124system.cpu.l2cache.demand_hits::cpu.itb.walker 2866 # number of demand (read+write) hits 1125system.cpu.l2cache.demand_hits::cpu.inst 777686 # number of demand (read+write) hits 1126system.cpu.l2cache.demand_hits::cpu.data 1478882 # number of demand (read+write) hits 1127system.cpu.l2cache.demand_hits::total 2266050 # number of demand (read+write) hits 1128system.cpu.l2cache.overall_hits::cpu.dtb.walker 6616 # number of overall hits 1129system.cpu.l2cache.overall_hits::cpu.itb.walker 2866 # number of overall hits 1130system.cpu.l2cache.overall_hits::cpu.inst 777686 # number of overall hits 1131system.cpu.l2cache.overall_hits::cpu.data 1478882 # number of overall hits 1132system.cpu.l2cache.overall_hits::total 2266050 # number of overall hits 1133system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses | 1104system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049511 # Average percentage of cache occupancy 1105system.cpu.l2cache.tags.occ_percent::cpu.data 0.169778 # Average percentage of cache occupancy 1106system.cpu.l2cache.tags.occ_percent::total 0.987960 # Average percentage of cache occupancy 1107system.cpu.l2cache.tags.occ_task_id_blocks::1024 64704 # Occupied blocks per task id 1108system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 1109system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 1110system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2830 # Occupied blocks per task id 1111system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4041 # Occupied blocks per task id 1112system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57717 # Occupied blocks per task id 1113system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987305 # Percentage of cache occupancy per task id 1114system.cpu.l2cache.tags.tag_accesses 32214708 # Number of tag accesses 1115system.cpu.l2cache.tags.data_accesses 32214708 # Number of data accesses 1116system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6577 # number of ReadReq hits 1117system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3185 # number of ReadReq hits 1118system.cpu.l2cache.ReadReq_hits::cpu.inst 778918 # number of ReadReq hits 1119system.cpu.l2cache.ReadReq_hits::cpu.data 1279822 # number of ReadReq hits 1120system.cpu.l2cache.ReadReq_hits::total 2068502 # number of ReadReq hits 1121system.cpu.l2cache.Writeback_hits::writebacks 1542758 # number of Writeback hits 1122system.cpu.l2cache.Writeback_hits::total 1542758 # number of Writeback hits 1123system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits 1124system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits 1125system.cpu.l2cache.ReadExReq_hits::cpu.data 199803 # number of ReadExReq hits 1126system.cpu.l2cache.ReadExReq_hits::total 199803 # number of ReadExReq hits 1127system.cpu.l2cache.demand_hits::cpu.dtb.walker 6577 # number of demand (read+write) hits 1128system.cpu.l2cache.demand_hits::cpu.itb.walker 3185 # number of demand (read+write) hits 1129system.cpu.l2cache.demand_hits::cpu.inst 778918 # number of demand (read+write) hits 1130system.cpu.l2cache.demand_hits::cpu.data 1479625 # number of demand (read+write) hits 1131system.cpu.l2cache.demand_hits::total 2268305 # number of demand (read+write) hits 1132system.cpu.l2cache.overall_hits::cpu.dtb.walker 6577 # number of overall hits 1133system.cpu.l2cache.overall_hits::cpu.itb.walker 3185 # number of overall hits 1134system.cpu.l2cache.overall_hits::cpu.inst 778918 # number of overall hits 1135system.cpu.l2cache.overall_hits::cpu.data 1479625 # number of overall hits 1136system.cpu.l2cache.overall_hits::total 2268305 # number of overall hits 1137system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses |
| 1134system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses | 1138system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses |
| 1135system.cpu.l2cache.ReadReq_misses::cpu.inst 12929 # number of ReadReq misses 1136system.cpu.l2cache.ReadReq_misses::cpu.data 28637 # number of ReadReq misses 1137system.cpu.l2cache.ReadReq_misses::total 41573 # number of ReadReq misses 1138system.cpu.l2cache.UpgradeReq_misses::cpu.data 1319 # number of UpgradeReq misses 1139system.cpu.l2cache.UpgradeReq_misses::total 1319 # number of UpgradeReq misses 1140system.cpu.l2cache.ReadExReq_misses::cpu.data 113455 # number of ReadExReq misses 1141system.cpu.l2cache.ReadExReq_misses::total 113455 # number of ReadExReq misses 1142system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses | 1139system.cpu.l2cache.ReadReq_misses::cpu.inst 12960 # number of ReadReq misses 1140system.cpu.l2cache.ReadReq_misses::cpu.data 28635 # number of ReadReq misses 1141system.cpu.l2cache.ReadReq_misses::total 41601 # number of ReadReq misses 1142system.cpu.l2cache.UpgradeReq_misses::cpu.data 1351 # number of UpgradeReq misses 1143system.cpu.l2cache.UpgradeReq_misses::total 1351 # number of UpgradeReq misses 1144system.cpu.l2cache.ReadExReq_misses::cpu.data 113819 # number of ReadExReq misses 1145system.cpu.l2cache.ReadExReq_misses::total 113819 # number of ReadExReq misses 1146system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses |
| 1143system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses | 1147system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses |
| 1144system.cpu.l2cache.demand_misses::cpu.inst 12929 # number of demand (read+write) misses 1145system.cpu.l2cache.demand_misses::cpu.data 142092 # number of demand (read+write) misses 1146system.cpu.l2cache.demand_misses::total 155028 # number of demand (read+write) misses 1147system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses | 1148system.cpu.l2cache.demand_misses::cpu.inst 12960 # number of demand (read+write) misses 1149system.cpu.l2cache.demand_misses::cpu.data 142454 # number of demand (read+write) misses 1150system.cpu.l2cache.demand_misses::total 155420 # number of demand (read+write) misses 1151system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses |
| 1148system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses | 1152system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses |
| 1149system.cpu.l2cache.overall_misses::cpu.inst 12929 # number of overall misses 1150system.cpu.l2cache.overall_misses::cpu.data 142092 # number of overall misses 1151system.cpu.l2cache.overall_misses::total 155028 # number of overall misses 1152system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 164250 # number of ReadReq miss cycles 1153system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 365000 # number of ReadReq miss cycles 1154system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 954586500 # number of ReadReq miss cycles 1155system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2172547250 # number of ReadReq miss cycles 1156system.cpu.l2cache.ReadReq_miss_latency::total 3127663000 # number of ReadReq miss cycles 1157system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15242851 # number of UpgradeReq miss cycles 1158system.cpu.l2cache.UpgradeReq_miss_latency::total 15242851 # number of UpgradeReq miss cycles 1159system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7899568975 # number of ReadExReq miss cycles 1160system.cpu.l2cache.ReadExReq_miss_latency::total 7899568975 # number of ReadExReq miss cycles 1161system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 164250 # number of demand (read+write) miss cycles 1162system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 365000 # number of demand (read+write) miss cycles 1163system.cpu.l2cache.demand_miss_latency::cpu.inst 954586500 # number of demand (read+write) miss cycles 1164system.cpu.l2cache.demand_miss_latency::cpu.data 10072116225 # number of demand (read+write) miss cycles 1165system.cpu.l2cache.demand_miss_latency::total 11027231975 # number of demand (read+write) miss cycles 1166system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 164250 # number of overall miss cycles 1167system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 365000 # number of overall miss cycles 1168system.cpu.l2cache.overall_miss_latency::cpu.inst 954586500 # number of overall miss cycles 1169system.cpu.l2cache.overall_miss_latency::cpu.data 10072116225 # number of overall miss cycles 1170system.cpu.l2cache.overall_miss_latency::total 11027231975 # number of overall miss cycles 1171system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6618 # number of ReadReq accesses(hits+misses) 1172system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2871 # number of ReadReq accesses(hits+misses) 1173system.cpu.l2cache.ReadReq_accesses::cpu.inst 790615 # number of ReadReq accesses(hits+misses) 1174system.cpu.l2cache.ReadReq_accesses::cpu.data 1307906 # number of ReadReq accesses(hits+misses) 1175system.cpu.l2cache.ReadReq_accesses::total 2108010 # number of ReadReq accesses(hits+misses) 1176system.cpu.l2cache.Writeback_accesses::writebacks 1541461 # number of Writeback accesses(hits+misses) 1177system.cpu.l2cache.Writeback_accesses::total 1541461 # number of Writeback accesses(hits+misses) 1178system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1631 # number of UpgradeReq accesses(hits+misses) 1179system.cpu.l2cache.UpgradeReq_accesses::total 1631 # number of UpgradeReq accesses(hits+misses) 1180system.cpu.l2cache.ReadExReq_accesses::cpu.data 313068 # number of ReadExReq accesses(hits+misses) 1181system.cpu.l2cache.ReadExReq_accesses::total 313068 # number of ReadExReq accesses(hits+misses) 1182system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6618 # number of demand (read+write) accesses 1183system.cpu.l2cache.demand_accesses::cpu.itb.walker 2871 # number of demand (read+write) accesses 1184system.cpu.l2cache.demand_accesses::cpu.inst 790615 # number of demand (read+write) accesses 1185system.cpu.l2cache.demand_accesses::cpu.data 1620974 # number of demand (read+write) accesses 1186system.cpu.l2cache.demand_accesses::total 2421078 # number of demand (read+write) accesses 1187system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6618 # number of overall (read+write) accesses 1188system.cpu.l2cache.overall_accesses::cpu.itb.walker 2871 # number of overall (read+write) accesses 1189system.cpu.l2cache.overall_accesses::cpu.inst 790615 # number of overall (read+write) accesses 1190system.cpu.l2cache.overall_accesses::cpu.data 1620974 # number of overall (read+write) accesses 1191system.cpu.l2cache.overall_accesses::total 2421078 # number of overall (read+write) accesses 1192system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000302 # miss rate for ReadReq accesses 1193system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001742 # miss rate for ReadReq accesses 1194system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016353 # miss rate for ReadReq accesses 1195system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021895 # miss rate for ReadReq accesses 1196system.cpu.l2cache.ReadReq_miss_rate::total 0.019721 # miss rate for ReadReq accesses 1197system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808706 # miss rate for UpgradeReq accesses 1198system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808706 # miss rate for UpgradeReq accesses 1199system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362397 # miss rate for ReadExReq accesses 1200system.cpu.l2cache.ReadExReq_miss_rate::total 0.362397 # miss rate for ReadExReq accesses 1201system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000302 # miss rate for demand accesses 1202system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001742 # miss rate for demand accesses 1203system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016353 # miss rate for demand accesses 1204system.cpu.l2cache.demand_miss_rate::cpu.data 0.087658 # miss rate for demand accesses 1205system.cpu.l2cache.demand_miss_rate::total 0.064033 # miss rate for demand accesses 1206system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000302 # miss rate for overall accesses 1207system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001742 # miss rate for overall accesses 1208system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016353 # miss rate for overall accesses 1209system.cpu.l2cache.overall_miss_rate::cpu.data 0.087658 # miss rate for overall accesses 1210system.cpu.l2cache.overall_miss_rate::total 0.064033 # miss rate for overall accesses 1211system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82125 # average ReadReq miss latency 1212system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 73000 # average ReadReq miss latency 1213system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73832.972388 # average ReadReq miss latency 1214system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75865.043475 # average ReadReq miss latency 1215system.cpu.l2cache.ReadReq_avg_miss_latency::total 75233.035865 # average ReadReq miss latency 1216system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11556.369219 # average UpgradeReq miss latency 1217system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11556.369219 # average UpgradeReq miss latency 1218system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69627.332202 # average ReadExReq miss latency 1219system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69627.332202 # average ReadExReq miss latency 1220system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82125 # average overall miss latency 1221system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency 1222system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73832.972388 # average overall miss latency 1223system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70884.470801 # average overall miss latency 1224system.cpu.l2cache.demand_avg_miss_latency::total 71130.582701 # average overall miss latency 1225system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82125 # average overall miss latency 1226system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency 1227system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73832.972388 # average overall miss latency 1228system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70884.470801 # average overall miss latency 1229system.cpu.l2cache.overall_avg_miss_latency::total 71130.582701 # average overall miss latency | 1153system.cpu.l2cache.overall_misses::cpu.inst 12960 # number of overall misses 1154system.cpu.l2cache.overall_misses::cpu.data 142454 # number of overall misses 1155system.cpu.l2cache.overall_misses::total 155420 # number of overall misses 1156system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles 1157system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 350750 # number of ReadReq miss cycles 1158system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 953249250 # number of ReadReq miss cycles 1159system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2133765000 # number of ReadReq miss cycles 1160system.cpu.l2cache.ReadReq_miss_latency::total 3087454250 # number of ReadReq miss cycles 1161system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15012361 # number of UpgradeReq miss cycles 1162system.cpu.l2cache.UpgradeReq_miss_latency::total 15012361 # number of UpgradeReq miss cycles 1163system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7880712972 # number of ReadExReq miss cycles 1164system.cpu.l2cache.ReadExReq_miss_latency::total 7880712972 # number of ReadExReq miss cycles 1165system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles 1166system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 350750 # number of demand (read+write) miss cycles 1167system.cpu.l2cache.demand_miss_latency::cpu.inst 953249250 # number of demand (read+write) miss cycles 1168system.cpu.l2cache.demand_miss_latency::cpu.data 10014477972 # number of demand (read+write) miss cycles 1169system.cpu.l2cache.demand_miss_latency::total 10968167222 # number of demand (read+write) miss cycles 1170system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles 1171system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 350750 # number of overall miss cycles 1172system.cpu.l2cache.overall_miss_latency::cpu.inst 953249250 # number of overall miss cycles 1173system.cpu.l2cache.overall_miss_latency::cpu.data 10014477972 # number of overall miss cycles 1174system.cpu.l2cache.overall_miss_latency::total 10968167222 # number of overall miss cycles 1175system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6578 # number of ReadReq accesses(hits+misses) 1176system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3190 # number of ReadReq accesses(hits+misses) 1177system.cpu.l2cache.ReadReq_accesses::cpu.inst 791878 # number of ReadReq accesses(hits+misses) 1178system.cpu.l2cache.ReadReq_accesses::cpu.data 1308457 # number of ReadReq accesses(hits+misses) 1179system.cpu.l2cache.ReadReq_accesses::total 2110103 # number of ReadReq accesses(hits+misses) 1180system.cpu.l2cache.Writeback_accesses::writebacks 1542758 # number of Writeback accesses(hits+misses) 1181system.cpu.l2cache.Writeback_accesses::total 1542758 # number of Writeback accesses(hits+misses) 1182system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1672 # number of UpgradeReq accesses(hits+misses) 1183system.cpu.l2cache.UpgradeReq_accesses::total 1672 # number of UpgradeReq accesses(hits+misses) 1184system.cpu.l2cache.ReadExReq_accesses::cpu.data 313622 # number of ReadExReq accesses(hits+misses) 1185system.cpu.l2cache.ReadExReq_accesses::total 313622 # number of ReadExReq accesses(hits+misses) 1186system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6578 # number of demand (read+write) accesses 1187system.cpu.l2cache.demand_accesses::cpu.itb.walker 3190 # number of demand (read+write) accesses 1188system.cpu.l2cache.demand_accesses::cpu.inst 791878 # number of demand (read+write) accesses 1189system.cpu.l2cache.demand_accesses::cpu.data 1622079 # number of demand (read+write) accesses 1190system.cpu.l2cache.demand_accesses::total 2423725 # number of demand (read+write) accesses 1191system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6578 # number of overall (read+write) accesses 1192system.cpu.l2cache.overall_accesses::cpu.itb.walker 3190 # number of overall (read+write) accesses 1193system.cpu.l2cache.overall_accesses::cpu.inst 791878 # number of overall (read+write) accesses 1194system.cpu.l2cache.overall_accesses::cpu.data 1622079 # number of overall (read+write) accesses 1195system.cpu.l2cache.overall_accesses::total 2423725 # number of overall (read+write) accesses 1196system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000152 # miss rate for ReadReq accesses 1197system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001567 # miss rate for ReadReq accesses 1198system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016366 # miss rate for ReadReq accesses 1199system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021885 # miss rate for ReadReq accesses 1200system.cpu.l2cache.ReadReq_miss_rate::total 0.019715 # miss rate for ReadReq accesses 1201system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808014 # miss rate for UpgradeReq accesses 1202system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808014 # miss rate for UpgradeReq accesses 1203system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362918 # miss rate for ReadExReq accesses 1204system.cpu.l2cache.ReadExReq_miss_rate::total 0.362918 # miss rate for ReadExReq accesses 1205system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000152 # miss rate for demand accesses 1206system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001567 # miss rate for demand accesses 1207system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016366 # miss rate for demand accesses 1208system.cpu.l2cache.demand_miss_rate::cpu.data 0.087822 # miss rate for demand accesses 1209system.cpu.l2cache.demand_miss_rate::total 0.064124 # miss rate for demand accesses 1210system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000152 # miss rate for overall accesses 1211system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001567 # miss rate for overall accesses 1212system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016366 # miss rate for overall accesses 1213system.cpu.l2cache.overall_miss_rate::cpu.data 0.087822 # miss rate for overall accesses 1214system.cpu.l2cache.overall_miss_rate::total 0.064124 # miss rate for overall accesses 1215system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency 1216system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 70150 # average ReadReq miss latency 1217system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73553.182870 # average ReadReq miss latency 1218system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74515.976951 # average ReadReq miss latency 1219system.cpu.l2cache.ReadReq_avg_miss_latency::total 74215.866205 # average ReadReq miss latency 1220system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11112.036269 # average UpgradeReq miss latency 1221system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11112.036269 # average UpgradeReq miss latency 1222system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.993244 # average ReadExReq miss latency 1223system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.993244 # average ReadExReq miss latency 1224system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 1225system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency 1226system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73553.182870 # average overall miss latency 1227system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70299.731647 # average overall miss latency 1228system.cpu.l2cache.demand_avg_miss_latency::total 70571.144138 # average overall miss latency 1229system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency 1230system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency 1231system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73553.182870 # average overall miss latency 1232system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70299.731647 # average overall miss latency 1233system.cpu.l2cache.overall_avg_miss_latency::total 70571.144138 # average overall miss latency |
| 1230system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1231system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1232system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1233system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1234system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1235system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1236system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1237system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1234system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1235system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1236system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1237system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1238system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1239system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1240system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1241system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1238system.cpu.l2cache.writebacks::writebacks 80343 # number of writebacks 1239system.cpu.l2cache.writebacks::total 80343 # number of writebacks 1240system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2 # number of ReadReq MSHR misses | 1242system.cpu.l2cache.writebacks::writebacks 80466 # number of writebacks 1243system.cpu.l2cache.writebacks::total 80466 # number of writebacks 1244system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses |
| 1241system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses | 1245system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses |
| 1242system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12929 # number of ReadReq MSHR misses 1243system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28637 # number of ReadReq MSHR misses 1244system.cpu.l2cache.ReadReq_mshr_misses::total 41573 # number of ReadReq MSHR misses 1245system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1319 # number of UpgradeReq MSHR misses 1246system.cpu.l2cache.UpgradeReq_mshr_misses::total 1319 # number of UpgradeReq MSHR misses 1247system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113455 # number of ReadExReq MSHR misses 1248system.cpu.l2cache.ReadExReq_mshr_misses::total 113455 # number of ReadExReq MSHR misses 1249system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2 # number of demand (read+write) MSHR misses | 1246system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12960 # number of ReadReq MSHR misses 1247system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28635 # number of ReadReq MSHR misses 1248system.cpu.l2cache.ReadReq_mshr_misses::total 41601 # number of ReadReq MSHR misses 1249system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1351 # number of UpgradeReq MSHR misses 1250system.cpu.l2cache.UpgradeReq_mshr_misses::total 1351 # number of UpgradeReq MSHR misses 1251system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113819 # number of ReadExReq MSHR misses 1252system.cpu.l2cache.ReadExReq_mshr_misses::total 113819 # number of ReadExReq MSHR misses 1253system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses |
| 1250system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses | 1254system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses |
| 1251system.cpu.l2cache.demand_mshr_misses::cpu.inst 12929 # number of demand (read+write) MSHR misses 1252system.cpu.l2cache.demand_mshr_misses::cpu.data 142092 # number of demand (read+write) MSHR misses 1253system.cpu.l2cache.demand_mshr_misses::total 155028 # number of demand (read+write) MSHR misses 1254system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2 # number of overall MSHR misses | 1255system.cpu.l2cache.demand_mshr_misses::cpu.inst 12960 # number of demand (read+write) MSHR misses 1256system.cpu.l2cache.demand_mshr_misses::cpu.data 142454 # number of demand (read+write) MSHR misses 1257system.cpu.l2cache.demand_mshr_misses::total 155420 # number of demand (read+write) MSHR misses 1258system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses |
| 1255system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses | 1259system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses |
| 1256system.cpu.l2cache.overall_mshr_misses::cpu.inst 12929 # number of overall MSHR misses 1257system.cpu.l2cache.overall_mshr_misses::cpu.data 142092 # number of overall MSHR misses 1258system.cpu.l2cache.overall_mshr_misses::total 155028 # number of overall MSHR misses 1259system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 138750 # number of ReadReq MSHR miss cycles 1260system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301500 # number of ReadReq MSHR miss cycles 1261system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 792612500 # number of ReadReq MSHR miss cycles 1262system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1813424750 # number of ReadReq MSHR miss cycles 1263system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2606477500 # number of ReadReq MSHR miss cycles 1264system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13194319 # number of UpgradeReq MSHR miss cycles 1265system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13194319 # number of UpgradeReq MSHR miss cycles 1266system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6481465525 # number of ReadExReq MSHR miss cycles 1267system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6481465525 # number of ReadExReq MSHR miss cycles 1268system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 138750 # number of demand (read+write) MSHR miss cycles 1269system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301500 # number of demand (read+write) MSHR miss cycles 1270system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 792612500 # number of demand (read+write) MSHR miss cycles 1271system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8294890275 # number of demand (read+write) MSHR miss cycles 1272system.cpu.l2cache.demand_mshr_miss_latency::total 9087943025 # number of demand (read+write) MSHR miss cycles 1273system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 138750 # number of overall MSHR miss cycles 1274system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles 1275system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 792612500 # number of overall MSHR miss cycles 1276system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8294890275 # number of overall MSHR miss cycles 1277system.cpu.l2cache.overall_mshr_miss_latency::total 9087943025 # number of overall MSHR miss cycles 1278system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655868500 # number of ReadReq MSHR uncacheable cycles 1279system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655868500 # number of ReadReq MSHR uncacheable cycles 1280system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370634000 # number of WriteReq MSHR uncacheable cycles 1281system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370634000 # number of WriteReq MSHR uncacheable cycles 1282system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026502500 # number of overall MSHR uncacheable cycles 1283system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026502500 # number of overall MSHR uncacheable cycles 1284system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for ReadReq accesses 1285system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for ReadReq accesses 1286system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for ReadReq accesses 1287system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021895 # mshr miss rate for ReadReq accesses 1288system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019721 # mshr miss rate for ReadReq accesses 1289system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808706 # mshr miss rate for UpgradeReq accesses 1290system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808706 # mshr miss rate for UpgradeReq accesses 1291system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362397 # mshr miss rate for ReadExReq accesses 1292system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362397 # mshr miss rate for ReadExReq accesses 1293system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for demand accesses 1294system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for demand accesses 1295system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for demand accesses 1296system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for demand accesses 1297system.cpu.l2cache.demand_mshr_miss_rate::total 0.064033 # mshr miss rate for demand accesses 1298system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for overall accesses 1299system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for overall accesses 1300system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for overall accesses 1301system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for overall accesses 1302system.cpu.l2cache.overall_mshr_miss_rate::total 0.064033 # mshr miss rate for overall accesses 1303system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average ReadReq mshr miss latency 1304system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency 1305system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61305.011989 # average ReadReq mshr miss latency 1306system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63324.536439 # average ReadReq mshr miss latency 1307system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62696.401511 # average ReadReq mshr miss latency 1308system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.274450 # average UpgradeReq mshr miss latency 1309system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.274450 # average UpgradeReq mshr miss latency 1310system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57128.073025 # average ReadExReq mshr miss latency 1311system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57128.073025 # average ReadExReq mshr miss latency 1312system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency 1313system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency 1314system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency 1315system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency 1316system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency 1317system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency 1318system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency 1319system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency 1320system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency 1321system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency | 1260system.cpu.l2cache.overall_mshr_misses::cpu.inst 12960 # number of overall MSHR misses 1261system.cpu.l2cache.overall_mshr_misses::cpu.data 142454 # number of overall MSHR misses 1262system.cpu.l2cache.overall_mshr_misses::total 155420 # number of overall MSHR misses 1263system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles 1264system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287750 # number of ReadReq MSHR miss cycles 1265system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 790892250 # number of ReadReq MSHR miss cycles 1266system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1774999000 # number of ReadReq MSHR miss cycles 1267system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2566255250 # number of ReadReq MSHR miss cycles 1268system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13524351 # number of UpgradeReq MSHR miss cycles 1269system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13524351 # number of UpgradeReq MSHR miss cycles 1270system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6458128028 # number of ReadExReq MSHR miss cycles 1271system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6458128028 # number of ReadExReq MSHR miss cycles 1272system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles 1273system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles 1274system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 790892250 # number of demand (read+write) MSHR miss cycles 1275system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8233127028 # number of demand (read+write) MSHR miss cycles 1276system.cpu.l2cache.demand_mshr_miss_latency::total 9024383278 # number of demand (read+write) MSHR miss cycles 1277system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles 1278system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles 1279system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 790892250 # number of overall MSHR miss cycles 1280system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8233127028 # number of overall MSHR miss cycles 1281system.cpu.l2cache.overall_mshr_miss_latency::total 9024383278 # number of overall MSHR miss cycles 1282system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86680074500 # number of ReadReq MSHR uncacheable cycles 1283system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86680074500 # number of ReadReq MSHR uncacheable cycles 1284system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2394893500 # number of WriteReq MSHR uncacheable cycles 1285system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2394893500 # number of WriteReq MSHR uncacheable cycles 1286system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89074968000 # number of overall MSHR uncacheable cycles 1287system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89074968000 # number of overall MSHR uncacheable cycles 1288system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for ReadReq accesses 1289system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for ReadReq accesses 1290system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for ReadReq accesses 1291system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021885 # mshr miss rate for ReadReq accesses 1292system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019715 # mshr miss rate for ReadReq accesses 1293system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808014 # mshr miss rate for UpgradeReq accesses 1294system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808014 # mshr miss rate for UpgradeReq accesses 1295system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362918 # mshr miss rate for ReadExReq accesses 1296system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362918 # mshr miss rate for ReadExReq accesses 1297system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for demand accesses 1298system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for demand accesses 1299system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for demand accesses 1300system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087822 # mshr miss rate for demand accesses 1301system.cpu.l2cache.demand_mshr_miss_rate::total 0.064124 # mshr miss rate for demand accesses 1302system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000152 # mshr miss rate for overall accesses 1303system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for overall accesses 1304system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for overall accesses 1305system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087822 # mshr miss rate for overall accesses 1306system.cpu.l2cache.overall_mshr_miss_rate::total 0.064124 # mshr miss rate for overall accesses 1307system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency 1308system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency 1309system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61025.636574 # average ReadReq mshr miss latency 1310system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61987.043827 # average ReadReq mshr miss latency 1311system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.345256 # average ReadReq mshr miss latency 1312system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.622502 # average UpgradeReq mshr miss latency 1313system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.622502 # average UpgradeReq mshr miss latency 1314system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56740.333582 # average ReadExReq mshr miss latency 1315system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56740.333582 # average ReadExReq mshr miss latency 1316system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1317system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency 1318system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency 1319system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency 1320system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency 1321system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency 1322system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency 1323system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency 1324system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency 1325system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency |
| 1322system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1323system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1324system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1325system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1326system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1327system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1328system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1329 1330---------- End Simulation Statistics ---------- | 1326system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1327system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1328system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1329system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1330system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1331system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1332system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1333 1334---------- End Simulation Statistics ---------- |