| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.192526 # Number of seconds simulated 4sim_ticks 5192526233000 # Number of ticks simulated 5final_tick 5192526233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.192511 # Number of seconds simulated 4sim_ticks 5192511044000 # Number of ticks simulated 5final_tick 5192511044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1492668 # Simulator instruction rate (inst/s) 8host_op_rate 2877328 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 60393582039 # Simulator tick rate (ticks/s) 10host_mem_usage 592376 # Number of bytes of host memory used 11host_seconds 85.98 # Real time elapsed on the host 12sim_insts 128336778 # Number of instructions simulated 13sim_ops 247387190 # Number of ops (including micro ops) simulated | 7host_inst_rate 1018343 # Simulator instruction rate (inst/s) 8host_op_rate 1963050 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41210458750 # Simulator tick rate (ticks/s) 10host_mem_usage 646888 # Number of bytes of host memory used 11host_seconds 126.00 # Real time elapsed on the host 12sim_insts 128310974 # Number of instructions simulated 13sim_ops 247343919 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 829632 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9090688 # Number of bytes read from this memory 21system.physmem.bytes_read::total 9949056 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 829632 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 829632 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5138240 # Number of bytes written to this memory | 19system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 9076288 # Number of bytes read from this memory 21system.physmem.bytes_read::total 9932544 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5141952 # Number of bytes written to this memory |
| 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory | 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory |
| 26system.physmem.bytes_written::total 8128320 # Number of bytes written to this memory | 26system.physmem.bytes_written::total 8132032 # Number of bytes written to this memory |
| 27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | 27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 29system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::cpu.inst 12963 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 142042 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 155454 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 80285 # Number of write requests responded to by this memory | 30system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 141817 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 155196 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 80343 # Number of write requests responded to by this memory |
| 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory | 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory |
| 35system.physmem.num_writes::total 127005 # Number of write requests responded to by this memory | 35system.physmem.num_writes::total 127063 # Number of write requests responded to by this memory |
| 36system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) | 37system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) | 38system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) |
| 39system.physmem.bw_read::cpu.inst 159774 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1750725 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1916034 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 159774 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 159774 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 989545 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 575843 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1565388 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 989545 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::pc.south_bridge.ide 581303 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::cpu.inst 159356 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1747957 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1912859 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 159356 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 159356 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 990263 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 575845 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1566108 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 990263 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::pc.south_bridge.ide 581305 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) |
| 50system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) | 50system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) |
| 51system.physmem.bw_total::cpu.inst 159774 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1750725 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3481422 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 155454 # Number of read requests accepted 55system.physmem.writeReqs 127005 # Number of write requests accepted 56system.physmem.readBursts 155454 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 127005 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 9932928 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 16128 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8126720 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 9949056 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 8128320 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 252 # Number of DRAM read bursts serviced by the write queue | 51system.physmem.bw_total::cpu.inst 159356 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1747957 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3478967 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 155196 # Number of read requests accepted 55system.physmem.writeReqs 127063 # Number of write requests accepted 56system.physmem.readBursts 155196 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 127063 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 9914944 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 17600 # Total number of bytes read from write queue 60system.physmem.bytesWritten 8130496 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 9932544 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 8132032 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 275 # Number of DRAM read bursts serviced by the write queue |
| 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one | 64system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| 65system.physmem.neitherReadNorWriteReqs 1602 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10234 # Per bank write bursts 67system.physmem.perBankRdBursts::1 9830 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10412 # Per bank write bursts 69system.physmem.perBankRdBursts::3 9937 # Per bank write bursts 70system.physmem.perBankRdBursts::4 9788 # Per bank write bursts 71system.physmem.perBankRdBursts::5 9348 # Per bank write bursts 72system.physmem.perBankRdBursts::6 9238 # Per bank write bursts 73system.physmem.perBankRdBursts::7 9473 # Per bank write bursts 74system.physmem.perBankRdBursts::8 9270 # Per bank write bursts 75system.physmem.perBankRdBursts::9 9085 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9528 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9619 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9707 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10058 # Per bank write bursts 80system.physmem.perBankRdBursts::14 9877 # Per bank write bursts 81system.physmem.perBankRdBursts::15 9798 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8316 # Per bank write bursts 83system.physmem.perBankWrBursts::1 7729 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8212 # Per bank write bursts 85system.physmem.perBankWrBursts::3 7860 # Per bank write bursts 86system.physmem.perBankWrBursts::4 8063 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7657 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7184 # Per bank write bursts 89system.physmem.perBankWrBursts::7 7824 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7616 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7570 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7824 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7928 # Per bank write bursts 94system.physmem.perBankWrBursts::12 8040 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8642 # Per bank write bursts 96system.physmem.perBankWrBursts::14 8420 # Per bank write bursts 97system.physmem.perBankWrBursts::15 8095 # Per bank write bursts | 65system.physmem.neitherReadNorWriteReqs 1594 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 10479 # Per bank write bursts 67system.physmem.perBankRdBursts::1 9637 # Per bank write bursts 68system.physmem.perBankRdBursts::2 10137 # Per bank write bursts 69system.physmem.perBankRdBursts::3 9789 # Per bank write bursts 70system.physmem.perBankRdBursts::4 9555 # Per bank write bursts 71system.physmem.perBankRdBursts::5 9513 # Per bank write bursts 72system.physmem.perBankRdBursts::6 9351 # Per bank write bursts 73system.physmem.perBankRdBursts::7 9512 # Per bank write bursts 74system.physmem.perBankRdBursts::8 9073 # Per bank write bursts 75system.physmem.perBankRdBursts::9 8991 # Per bank write bursts 76system.physmem.perBankRdBursts::10 9630 # Per bank write bursts 77system.physmem.perBankRdBursts::11 9438 # Per bank write bursts 78system.physmem.perBankRdBursts::12 9550 # Per bank write bursts 79system.physmem.perBankRdBursts::13 10095 # Per bank write bursts 80system.physmem.perBankRdBursts::14 10146 # Per bank write bursts 81system.physmem.perBankRdBursts::15 10025 # Per bank write bursts 82system.physmem.perBankWrBursts::0 8301 # Per bank write bursts 83system.physmem.perBankWrBursts::1 8002 # Per bank write bursts 84system.physmem.perBankWrBursts::2 8301 # Per bank write bursts 85system.physmem.perBankWrBursts::3 8212 # Per bank write bursts 86system.physmem.perBankWrBursts::4 7990 # Per bank write bursts 87system.physmem.perBankWrBursts::5 7535 # Per bank write bursts 88system.physmem.perBankWrBursts::6 7392 # Per bank write bursts 89system.physmem.perBankWrBursts::7 7734 # Per bank write bursts 90system.physmem.perBankWrBursts::8 7444 # Per bank write bursts 91system.physmem.perBankWrBursts::9 7612 # Per bank write bursts 92system.physmem.perBankWrBursts::10 7970 # Per bank write bursts 93system.physmem.perBankWrBursts::11 7896 # Per bank write bursts 94system.physmem.perBankWrBursts::12 8102 # Per bank write bursts 95system.physmem.perBankWrBursts::13 8416 # Per bank write bursts 96system.physmem.perBankWrBursts::14 8297 # Per bank write bursts 97system.physmem.perBankWrBursts::15 7835 # Per bank write bursts |
| 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 99system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 100system.physmem.totGap 5192526169500 # Total gap between requests | 99system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 100system.physmem.totGap 5192510980500 # Total gap between requests |
| 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) | 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 0 # Read request sizes (log2) 105system.physmem.readPktSize::4 0 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 107system.physmem.readPktSize::6 155454 # Read request sizes (log2) | 107system.physmem.readPktSize::6 155196 # Read request sizes (log2) |
| 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) | 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 0 # Write request sizes (log2) 111system.physmem.writePktSize::3 0 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 114system.physmem.writePktSize::6 127005 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 151750 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 3023 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see | 114system.physmem.writePktSize::6 127063 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 151525 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 2962 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see |
| 119system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 119system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see --- 27 unchanged lines hidden (view full) --- 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::15 2439 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3242 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6145 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6383 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6406 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 7175 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7465 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 8169 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8822 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 9909 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 9129 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8509 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7675 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7337 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6397 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6159 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6188 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6092 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 164 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 191 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 179 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 171 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 146 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 28 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 56259 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 321.007910 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 189.347718 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 335.337897 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 20082 35.70% 35.70% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 13652 24.27% 59.96% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5681 10.10% 70.06% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3443 6.12% 76.18% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2317 4.12% 80.30% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1632 2.90% 83.20% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1101 1.96% 85.16% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1008 1.79% 86.95% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7343 13.05% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 56259 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5896 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 26.315638 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 622.349689 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 5895 99.98% 99.98% # Reads before turning the bus around for writes | 162system.physmem.wrQLenPdf::15 2384 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 3176 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 6154 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 6388 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 6392 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 7445 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 8129 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 8789 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 9861 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 9041 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 7645 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 7364 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 6417 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 6189 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 6244 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 6141 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 237 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 221 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 254 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 206 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 203 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 199 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 182 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 177 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 179 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 41 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 37 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 57292 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 314.972003 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 184.928814 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 333.427002 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 21127 36.88% 36.88% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 13732 23.97% 60.84% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 5729 10.00% 70.84% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 3461 6.04% 76.89% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 2250 3.93% 80.81% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 1575 2.75% 83.56% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 1105 1.93% 85.49% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 1008 1.76% 87.25% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 7305 12.75% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 57292 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 26.232854 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 621.882480 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 5904 99.98% 99.98% # Reads before turning the bus around for writes |
| 229system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes | 229system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 230system.physmem.rdPerTurnAround::total 5896 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 5896 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 21.536635 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 19.431893 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 14.049302 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 4860 82.43% 82.43% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 44 0.75% 83.18% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 38 0.64% 83.82% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 287 4.87% 88.69% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 272 4.61% 93.30% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 20 0.34% 93.64% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 25 0.42% 94.06% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 11 0.19% 94.25% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 27 0.46% 94.71% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 4 0.07% 94.78% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 3 0.05% 94.83% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 1 0.02% 94.84% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 223 3.78% 98.63% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 4 0.07% 98.69% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 6 0.10% 98.80% # Writes before turning the bus around for reads | 230system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes 231system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::mean 21.513802 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::gmean 19.393687 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::stdev 14.130484 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::16-19 4886 82.74% 82.74% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::20-23 42 0.71% 83.45% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::24-27 41 0.69% 84.15% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::28-31 275 4.66% 88.81% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::32-35 267 4.52% 93.33% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::36-39 20 0.34% 93.67% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::40-43 10 0.17% 93.84% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::44-47 19 0.32% 94.16% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::48-51 22 0.37% 94.53% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::52-55 8 0.14% 94.67% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::56-59 6 0.10% 94.77% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::60-63 2 0.03% 94.80% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-67 226 3.83% 98.63% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::68-71 6 0.10% 98.73% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::72-75 4 0.07% 98.80% # Writes before turning the bus around for reads |
| 250system.physmem.wrPerTurnAround::76-79 3 0.05% 98.85% # Writes before turning the bus around for reads | 250system.physmem.wrPerTurnAround::76-79 3 0.05% 98.85% # Writes before turning the bus around for reads |
| 251system.physmem.wrPerTurnAround::80-83 20 0.34% 99.19% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::84-87 1 0.02% 99.20% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::92-95 1 0.02% 99.22% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::96-99 10 0.17% 99.39% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::100-103 2 0.03% 99.42% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::104-107 2 0.03% 99.46% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 2 0.03% 99.49% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 8 0.14% 99.63% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::116-119 2 0.03% 99.66% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::120-123 4 0.07% 99.73% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::128-131 13 0.22% 99.95% # Writes before turning the bus around for reads | 251system.physmem.wrPerTurnAround::80-83 15 0.25% 99.10% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::88-91 1 0.02% 99.12% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::92-95 1 0.02% 99.14% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::96-99 13 0.22% 99.36% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::100-103 1 0.02% 99.37% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::104-107 6 0.10% 99.48% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::108-111 3 0.05% 99.53% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 8 0.14% 99.66% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::116-119 2 0.03% 99.70% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::120-123 3 0.05% 99.75% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::128-131 12 0.20% 99.95% # Writes before turning the bus around for reads |
| 262system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads | 262system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads |
| 264system.physmem.wrPerTurnAround::total 5896 # Writes before turning the bus around for reads 265system.physmem.totQLat 1473683250 # Total ticks spent queuing 266system.physmem.totMemAccLat 4383720750 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 776010000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 9495.26 # Average queueing delay per DRAM burst | 264system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads 265system.physmem.totQLat 1558594500 # Total ticks spent queuing 266system.physmem.totMemAccLat 4463363250 # Total ticks spent from burst creation until serviced by the DRAM 267system.physmem.totBusLat 774605000 # Total ticks spent in databus transfers 268system.physmem.avgQLat 10060.58 # Average queueing delay per DRAM burst |
| 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 269system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 270system.physmem.avgMemAccLat 28245.26 # Average memory access latency per DRAM burst | 270system.physmem.avgMemAccLat 28810.58 # Average memory access latency per DRAM burst |
| 271system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s | 271system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s 272system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s |
| 273system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s | 273system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s |
| 274system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.03 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing | 274system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s 275system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 276system.physmem.busUtil 0.03 # Data bus utilization in percentage 277system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 278system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 279system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 280system.physmem.avgWrQLen 22.52 # Average write queue length when enqueuing 281system.physmem.readRowHits 127189 # Number of row buffer hits during reads 282system.physmem.writeRowHits 98733 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes 285system.physmem.avgGap 18383291.63 # Average gap between requests 286system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined 287system.physmem.memoryStateTime::IDLE 4971157882750 # Time in different power states 288system.physmem.memoryStateTime::REF 173389840000 # Time in different power states | 280system.physmem.avgWrQLen 22.05 # Average write queue length when enqueuing 281system.physmem.readRowHits 125976 # Number of row buffer hits during reads 282system.physmem.writeRowHits 98691 # Number of row buffer hits during writes 283system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads 284system.physmem.writeRowHitRate 77.67 # Row buffer hit rate for writes 285system.physmem.avgGap 18396263.65 # Average gap between requests 286system.physmem.pageHitRate 79.67 # Row buffer hit rate, read and write combined 287system.physmem.memoryStateTime::IDLE 4970934831000 # Time in different power states 288system.physmem.memoryStateTime::REF 173389320000 # Time in different power states |
| 289system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 289system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 290system.physmem.memoryStateTime::ACT 47978395250 # Time in different power states | 290system.physmem.memoryStateTime::ACT 48186778000 # Time in different power states |
| 291system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 291system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 292system.membus.throughput 3808612 # Throughput (bytes/s) 293system.membus.trans_dist::ReadReq 623901 # Transaction distribution 294system.membus.trans_dist::ReadResp 623901 # Transaction distribution | 292system.membus.trans_dist::ReadReq 623858 # Transaction distribution 293system.membus.trans_dist::ReadResp 623858 # Transaction distribution |
| 295system.membus.trans_dist::WriteReq 13773 # Transaction distribution 296system.membus.trans_dist::WriteResp 13773 # Transaction distribution | 294system.membus.trans_dist::WriteReq 13773 # Transaction distribution 295system.membus.trans_dist::WriteResp 13773 # Transaction distribution |
| 297system.membus.trans_dist::Writeback 80285 # Transaction distribution | 296system.membus.trans_dist::Writeback 80343 # Transaction distribution |
| 298system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 299system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 300system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution | 297system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 298system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 299system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution |
| 301system.membus.trans_dist::UpgradeResp 1602 # Transaction distribution 302system.membus.trans_dist::ReadExReq 113400 # Transaction distribution 303system.membus.trans_dist::ReadExResp 113400 # Transaction distribution | 300system.membus.trans_dist::UpgradeResp 1594 # Transaction distribution 301system.membus.trans_dist::ReadExReq 113180 # Transaction distribution 302system.membus.trans_dist::ReadExResp 113180 # Transaction distribution |
| 304system.membus.trans_dist::MessageReq 1654 # Transaction distribution 305system.membus.trans_dist::MessageResp 1654 # Transaction distribution 306system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) 308system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) 309system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) | 303system.membus.trans_dist::MessageReq 1654 # Transaction distribution 304system.membus.trans_dist::MessageResp 1654 # Transaction distribution 305system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) 306system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) 307system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) 308system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes) |
| 310system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394055 # Packet count per connected master and slave (bytes) 311system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584493 # Packet count per connected master and slave (bytes) 312system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94727 # Packet count per connected master and slave (bytes) 313system.membus.pkt_count_system.iocache.mem_side::total 94727 # Packet count per connected master and slave (bytes) 314system.membus.pkt_count::total 1682528 # Packet count per connected master and slave (bytes) 315system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) 316system.membus.tot_pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) 317system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) 318system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) 319system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15058944 # Cumulative packet size per connected master and slave (bytes) 320system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16725605 # Cumulative packet size per connected master and slave (bytes) 321system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size::total 19750653 # Cumulative packet size per connected master and slave (bytes) 324system.membus.data_through_bus 19750653 # Total data (bytes) 325system.membus.snoop_data_through_bus 25664 # Total snoop data (bytes) | 309system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393589 # Packet count per connected master and slave (bytes) 310system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584027 # Packet count per connected master and slave (bytes) 311system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94722 # Packet count per connected master and slave (bytes) 312system.membus.pkt_count_system.iocache.mem_side::total 94722 # Packet count per connected master and slave (bytes) 313system.membus.pkt_count::total 1682057 # Packet count per connected master and slave (bytes) 314system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) 315system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) 316system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) 317system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes) 318system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15046144 # Cumulative packet size per connected master and slave (bytes) 319system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16712805 # Cumulative packet size per connected master and slave (bytes) 320system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) 321system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) 322system.membus.pkt_size::total 19737853 # Cumulative packet size per connected master and slave (bytes) 323system.membus.snoops 948 # Total snoops (count) 324system.membus.snoop_fanout::samples 284802 # Request fanout histogram 325system.membus.snoop_fanout::mean 1 # Request fanout histogram 326system.membus.snoop_fanout::stdev 0 # Request fanout histogram 327system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 328system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 329system.membus.snoop_fanout::1 284802 100.00% 100.00% # Request fanout histogram 330system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 331system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 332system.membus.snoop_fanout::min_value 1 # Request fanout histogram 333system.membus.snoop_fanout::max_value 1 # Request fanout histogram 334system.membus.snoop_fanout::total 284802 # Request fanout histogram |
| 326system.membus.reqLayer0.occupancy 256795500 # Layer occupancy (ticks) 327system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) | 335system.membus.reqLayer0.occupancy 256795500 # Layer occupancy (ticks) 336system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) |
| 328system.membus.reqLayer1.occupancy 359321500 # Layer occupancy (ticks) | 337system.membus.reqLayer1.occupancy 358101500 # Layer occupancy (ticks) |
| 329system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 330system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) 331system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) | 338system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 339system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks) 340system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) |
| 332system.membus.reqLayer3.occupancy 1309717000 # Layer occupancy (ticks) | 341system.membus.reqLayer3.occupancy 1310597750 # Layer occupancy (ticks) |
| 333system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 334system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) 335system.membus.respLayer0.utilization 0.0 # Layer utilization (%) | 342system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 343system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks) 344system.membus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 336system.membus.respLayer2.occupancy 2621518398 # Layer occupancy (ticks) | 345system.membus.respLayer2.occupancy 2618526656 # Layer occupancy (ticks) |
| 337system.membus.respLayer2.utilization 0.1 # Layer utilization (%) | 346system.membus.respLayer2.utilization 0.1 # Layer utilization (%) |
| 338system.membus.respLayer4.occupancy 54330498 # Layer occupancy (ticks) | 347system.membus.respLayer4.occupancy 54286498 # Layer occupancy (ticks) |
| 339system.membus.respLayer4.utilization 0.0 # Layer utilization (%) | 348system.membus.respLayer4.utilization 0.0 # Layer utilization (%) |
| 340system.iocache.tags.replacements 47509 # number of replacements 341system.iocache.tags.tagsinuse 0.112613 # Cycle average of tags in use | 349system.iocache.tags.replacements 47504 # number of replacements 350system.iocache.tags.tagsinuse 0.112573 # Cycle average of tags in use |
| 342system.iocache.tags.total_refs 0 # Total number of references to valid blocks. | 351system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
| 343system.iocache.tags.sampled_refs 47525 # Sample count of references to valid blocks. | 352system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks. |
| 344system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. | 353system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
| 345system.iocache.tags.warmup_cycle 5045777659000 # Cycle when the warmup percentage was hit. 346system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112613 # Average occupied blocks per requestor 347system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007038 # Average percentage of cache occupancy 348system.iocache.tags.occ_percent::total 0.007038 # Average percentage of cache occupancy | 354system.iocache.tags.warmup_cycle 5045778761000 # Cycle when the warmup percentage was hit. 355system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112573 # Average occupied blocks per requestor 356system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007036 # Average percentage of cache occupancy 357system.iocache.tags.occ_percent::total 0.007036 # Average percentage of cache occupancy |
| 349system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 350system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 351system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id | 358system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 359system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 360system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
| 352system.iocache.tags.tag_accesses 428076 # Number of tag accesses 353system.iocache.tags.data_accesses 428076 # Number of data accesses | 361system.iocache.tags.tag_accesses 428031 # Number of tag accesses 362system.iocache.tags.data_accesses 428031 # Number of data accesses |
| 354system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 355system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits | 363system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 364system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits |
| 356system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses 357system.iocache.ReadReq_misses::total 844 # number of ReadReq misses 358system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses 359system.iocache.demand_misses::total 844 # number of demand (read+write) misses 360system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses 361system.iocache.overall_misses::total 844 # number of overall misses 362system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141199186 # number of ReadReq miss cycles 363system.iocache.ReadReq_miss_latency::total 141199186 # number of ReadReq miss cycles 364system.iocache.demand_miss_latency::pc.south_bridge.ide 141199186 # number of demand (read+write) miss cycles 365system.iocache.demand_miss_latency::total 141199186 # number of demand (read+write) miss cycles 366system.iocache.overall_miss_latency::pc.south_bridge.ide 141199186 # number of overall miss cycles 367system.iocache.overall_miss_latency::total 141199186 # number of overall miss cycles 368system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) 369system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) | 365system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses 366system.iocache.ReadReq_misses::total 839 # number of ReadReq misses 367system.iocache.demand_misses::pc.south_bridge.ide 839 # number of demand (read+write) misses 368system.iocache.demand_misses::total 839 # number of demand (read+write) misses 369system.iocache.overall_misses::pc.south_bridge.ide 839 # number of overall misses 370system.iocache.overall_misses::total 839 # number of overall misses 371system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140842436 # number of ReadReq miss cycles 372system.iocache.ReadReq_miss_latency::total 140842436 # number of ReadReq miss cycles 373system.iocache.demand_miss_latency::pc.south_bridge.ide 140842436 # number of demand (read+write) miss cycles 374system.iocache.demand_miss_latency::total 140842436 # number of demand (read+write) miss cycles 375system.iocache.overall_miss_latency::pc.south_bridge.ide 140842436 # number of overall miss cycles 376system.iocache.overall_miss_latency::total 140842436 # number of overall miss cycles 377system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses) 378system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses) |
| 370system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 371system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) | 379system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 380system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) |
| 372system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses 373system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses 374system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses 375system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses | 381system.iocache.demand_accesses::pc.south_bridge.ide 839 # number of demand (read+write) accesses 382system.iocache.demand_accesses::total 839 # number of demand (read+write) accesses 383system.iocache.overall_accesses::pc.south_bridge.ide 839 # number of overall (read+write) accesses 384system.iocache.overall_accesses::total 839 # number of overall (read+write) accesses |
| 376system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 377system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 378system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 379system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 380system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 381system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses | 385system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 386system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 387system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 388system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 389system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 390system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
| 382system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average ReadReq miss latency 383system.iocache.ReadReq_avg_miss_latency::total 167297.613744 # average ReadReq miss latency 384system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency 385system.iocache.demand_avg_miss_latency::total 167297.613744 # average overall miss latency 386system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency 387system.iocache.overall_avg_miss_latency::total 167297.613744 # average overall miss latency | 391system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average ReadReq miss latency 392system.iocache.ReadReq_avg_miss_latency::total 167869.411204 # average ReadReq miss latency 393system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency 394system.iocache.demand_avg_miss_latency::total 167869.411204 # average overall miss latency 395system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency 396system.iocache.overall_avg_miss_latency::total 167869.411204 # average overall miss latency |
| 388system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked 389system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 390system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked 391system.iocache.blocked::no_targets 0 # number of cycles access was blocked 392system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked 393system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 394system.iocache.fast_writes 46720 # number of fast writes performed 395system.iocache.cache_copies 0 # number of cache copies performed | 397system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked 398system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 399system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked 400system.iocache.blocked::no_targets 0 # number of cycles access was blocked 401system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked 402system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 403system.iocache.fast_writes 46720 # number of fast writes performed 404system.iocache.cache_copies 0 # number of cache copies performed |
| 396system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses 397system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses | 405system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses 406system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses |
| 398system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 399system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses | 407system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 408system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses |
| 400system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses 401system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses 402system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses 403system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses 404system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of ReadReq MSHR miss cycles 405system.iocache.ReadReq_mshr_miss_latency::total 97286186 # number of ReadReq MSHR miss cycles 406system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2834928162 # number of WriteInvalidateReq MSHR miss cycles 407system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2834928162 # number of WriteInvalidateReq MSHR miss cycles 408system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of demand (read+write) MSHR miss cycles 409system.iocache.demand_mshr_miss_latency::total 97286186 # number of demand (read+write) MSHR miss cycles 410system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of overall MSHR miss cycles 411system.iocache.overall_mshr_miss_latency::total 97286186 # number of overall MSHR miss cycles | 409system.iocache.demand_mshr_misses::pc.south_bridge.ide 839 # number of demand (read+write) MSHR misses 410system.iocache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses 411system.iocache.overall_mshr_misses::pc.south_bridge.ide 839 # number of overall MSHR misses 412system.iocache.overall_mshr_misses::total 839 # number of overall MSHR misses 413system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of ReadReq MSHR miss cycles 414system.iocache.ReadReq_mshr_miss_latency::total 97188936 # number of ReadReq MSHR miss cycles 415system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2836981412 # number of WriteInvalidateReq MSHR miss cycles 416system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2836981412 # number of WriteInvalidateReq MSHR miss cycles 417system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of demand (read+write) MSHR miss cycles 418system.iocache.demand_mshr_miss_latency::total 97188936 # number of demand (read+write) MSHR miss cycles 419system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of overall MSHR miss cycles 420system.iocache.overall_mshr_miss_latency::total 97188936 # number of overall MSHR miss cycles |
| 412system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 413system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 414system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 415system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 416system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 417system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 418system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 419system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses | 421system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 422system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 423system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 424system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 425system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 426system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 427system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 428system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses |
| 420system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average ReadReq mshr miss latency 421system.iocache.ReadReq_avg_mshr_miss_latency::total 115267.992891 # average ReadReq mshr miss latency 422system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60679.113057 # average WriteInvalidateReq mshr miss latency 423system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60679.113057 # average WriteInvalidateReq mshr miss latency 424system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency 425system.iocache.demand_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency 426system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency 427system.iocache.overall_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency | 429system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average ReadReq mshr miss latency 430system.iocache.ReadReq_avg_mshr_miss_latency::total 115839.017878 # average ReadReq mshr miss latency 431system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60723.061045 # average WriteInvalidateReq mshr miss latency 432system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60723.061045 # average WriteInvalidateReq mshr miss latency 433system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency 434system.iocache.demand_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency 435system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency 436system.iocache.overall_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency |
| 428system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 429system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 430system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 431system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 432system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 433system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 434system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 435system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 436system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 437system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 438system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 439system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 440system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 437system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 438system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 439system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 440system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 441system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 442system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 443system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 444system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 445system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 446system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 447system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 448system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 449system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 441system.iobus.throughput 631746 # Throughput (bytes/s) 442system.iobus.trans_dist::ReadReq 230149 # Transaction distribution 443system.iobus.trans_dist::ReadResp 230149 # Transaction distribution | 450system.iobus.trans_dist::ReadReq 230144 # Transaction distribution 451system.iobus.trans_dist::ReadResp 230144 # Transaction distribution |
| 444system.iobus.trans_dist::WriteReq 57579 # Transaction distribution 445system.iobus.trans_dist::WriteResp 57579 # Transaction distribution 446system.iobus.trans_dist::MessageReq 1654 # Transaction distribution 447system.iobus.trans_dist::MessageResp 1654 # Transaction distribution 448system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 449system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 450system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 451system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) --- 7 unchanged lines hidden (view full) --- 459system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 460system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 461system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 462system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 463system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 464system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 465system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 466system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) | 452system.iobus.trans_dist::WriteReq 57579 # Transaction distribution 453system.iobus.trans_dist::WriteResp 57579 # Transaction distribution 454system.iobus.trans_dist::MessageReq 1654 # Transaction distribution 455system.iobus.trans_dist::MessageResp 1654 # Transaction distribution 456system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 457system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 458system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 459system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) --- 7 unchanged lines hidden (view full) --- 467system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 468system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 469system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 470system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 471system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 472system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 473system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 474system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) |
| 467system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes) 468system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes) | 475system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes) 476system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes) |
| 469system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) 470system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) | 477system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) 478system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) |
| 471system.iobus.pkt_count::total 578764 # Packet count per connected master and slave (bytes) 472system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 473system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 474system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 475system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 476system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 477system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 478system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 479system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 480system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 481system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 482system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 483system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 484system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 485system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 486system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 487system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 488system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 489system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 490system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) 491system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes) 492system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes) 493system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) 494system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) 495system.iobus.tot_pkt_size::total 3280356 # Cumulative packet size per connected master and slave (bytes) 496system.iobus.data_through_bus 3280356 # Total data (bytes) | 479system.iobus.pkt_count::total 578754 # Packet count per connected master and slave (bytes) 480system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 481system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 482system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 483system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 484system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 485system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 486system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 487system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 488system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 489system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 490system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 491system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 492system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 493system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 494system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 495system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 496system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 497system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 498system.iobus.pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) 499system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes) 500system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes) 501system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) 503system.iobus.pkt_size::total 3280316 # Cumulative packet size per connected master and slave (bytes) |
| 497system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) 498system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 499system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 500system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 501system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 502system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 503system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 504system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) --- 20 unchanged lines hidden (view full) --- 525system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 526system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 527system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 528system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 529system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 530system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 531system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 532system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) | 504system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks) 505system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 506system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 507system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 508system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 509system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 510system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 511system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) --- 20 unchanged lines hidden (view full) --- 532system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 533system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 534system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 535system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 536system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 537system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 538system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 539system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) |
| 533system.iobus.reqLayer18.occupancy 421898846 # Layer occupancy (ticks) | 540system.iobus.reqLayer18.occupancy 421888846 # Layer occupancy (ticks) |
| 534system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 535system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 536system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 537system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) 538system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) | 541system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 542system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 543system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 544system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) 545system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 539system.iobus.respLayer1.occupancy 52228502 # Layer occupancy (ticks) | 546system.iobus.respLayer1.occupancy 52218502 # Layer occupancy (ticks) |
| 540system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 541system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) 542system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 543system.cpu_clk_domain.clock 500 # Clock period in ticks 544system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 547system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 548system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) 549system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 550system.cpu_clk_domain.clock 500 # Clock period in ticks 551system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 545system.cpu.numCycles 10385052466 # number of cpu cycles simulated | 552system.cpu.numCycles 10385022088 # number of cpu cycles simulated |
| 546system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 547system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 553system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 554system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 548system.cpu.committedInsts 128336778 # Number of instructions committed 549system.cpu.committedOps 247387190 # Number of ops (including micro ops) committed 550system.cpu.num_int_alu_accesses 231979854 # Number of integer alu accesses | 555system.cpu.committedInsts 128310974 # Number of instructions committed 556system.cpu.committedOps 247343919 # Number of ops (including micro ops) committed 557system.cpu.num_int_alu_accesses 231936467 # Number of integer alu accesses |
| 551system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses | 558system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses |
| 552system.cpu.num_func_calls 2299861 # number of times a function call or return occured 553system.cpu.num_conditional_control_insts 23168822 # number of instructions that are conditional controls 554system.cpu.num_int_insts 231979854 # number of integer instructions | 559system.cpu.num_func_calls 2299885 # number of times a function call or return occured 560system.cpu.num_conditional_control_insts 23161985 # number of instructions that are conditional controls 561system.cpu.num_int_insts 231936467 # number of integer instructions |
| 555system.cpu.num_fp_insts 0 # number of float instructions | 562system.cpu.num_fp_insts 0 # number of float instructions |
| 556system.cpu.num_int_register_reads 434516750 # number of times the integer registers were read 557system.cpu.num_int_register_writes 197854064 # number of times the integer registers were written | 563system.cpu.num_int_register_reads 434450917 # number of times the integer registers were read 564system.cpu.num_int_register_writes 197819265 # number of times the integer registers were written |
| 558system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 559system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 565system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 566system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 560system.cpu.num_cc_register_reads 132811657 # number of times the CC registers were read 561system.cpu.num_cc_register_writes 95534544 # number of times the CC registers were written 562system.cpu.num_mem_refs 22246380 # number of memory refs 563system.cpu.num_load_insts 13880618 # Number of load instructions 564system.cpu.num_store_insts 8365762 # Number of store instructions 565system.cpu.num_idle_cycles 9788359567.998116 # Number of idle cycles 566system.cpu.num_busy_cycles 596692898.001885 # Number of busy cycles 567system.cpu.not_idle_fraction 0.057457 # Percentage of non-idle cycles 568system.cpu.idle_fraction 0.942543 # Percentage of idle cycles 569system.cpu.Branches 26306776 # Number of branches fetched 570system.cpu.op_class::No_OpClass 174693 0.07% 0.07% # Class of executed instruction 571system.cpu.op_class::IntAlu 224704760 90.83% 90.90% # Class of executed instruction 572system.cpu.op_class::IntMult 139946 0.06% 90.96% # Class of executed instruction 573system.cpu.op_class::IntDiv 122983 0.05% 91.01% # Class of executed instruction | 567system.cpu.num_cc_register_reads 132769519 # number of times the CC registers were read 568system.cpu.num_cc_register_writes 95505601 # number of times the CC registers were written 569system.cpu.num_mem_refs 22243286 # number of memory refs 570system.cpu.num_load_insts 13879256 # Number of load instructions 571system.cpu.num_store_insts 8364030 # Number of store instructions 572system.cpu.num_idle_cycles 9788400874.998116 # Number of idle cycles 573system.cpu.num_busy_cycles 596621213.001885 # Number of busy cycles 574system.cpu.not_idle_fraction 0.057450 # Percentage of non-idle cycles 575system.cpu.idle_fraction 0.942550 # Percentage of idle cycles 576system.cpu.Branches 26299942 # Number of branches fetched 577system.cpu.op_class::No_OpClass 174748 0.07% 0.07% # Class of executed instruction 578system.cpu.op_class::IntAlu 224664535 90.83% 90.90% # Class of executed instruction 579system.cpu.op_class::IntMult 139903 0.06% 90.96% # Class of executed instruction 580system.cpu.op_class::IntDiv 122942 0.05% 91.01% # Class of executed instruction |
| 574system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction 575system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction 576system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction 577system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction 578system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction 579system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction 580system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction 581system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 592system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction 593system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction 594system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction 595system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction 596system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction 597system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction 598system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction 599system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction | 581system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction 582system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction 583system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction 584system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction 585system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction 586system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction 587system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction 588system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 599system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction 600system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction 601system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction 602system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction 603system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction 604system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction 605system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction 606system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction |
| 600system.cpu.op_class::MemRead 13880618 5.61% 96.62% # Class of executed instruction 601system.cpu.op_class::MemWrite 8365762 3.38% 100.00% # Class of executed instruction | 607system.cpu.op_class::MemRead 13879256 5.61% 96.62% # Class of executed instruction 608system.cpu.op_class::MemWrite 8364030 3.38% 100.00% # Class of executed instruction |
| 602system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 603system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 609system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 610system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 604system.cpu.op_class::total 247388762 # Class of executed instruction | 611system.cpu.op_class::total 247345414 # Class of executed instruction |
| 605system.cpu.kern.inst.arm 0 # number of arm instructions executed 606system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 612system.cpu.kern.inst.arm 0 # number of arm instructions executed 613system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 607system.cpu.icache.tags.replacements 794564 # number of replacements 608system.cpu.icache.tags.tagsinuse 510.353610 # Cycle average of tags in use 609system.cpu.icache.tags.total_refs 144580687 # Total number of references to valid blocks. 610system.cpu.icache.tags.sampled_refs 795076 # Sample count of references to valid blocks. 611system.cpu.icache.tags.avg_refs 181.845115 # Average number of references to valid blocks. 612system.cpu.icache.tags.warmup_cycle 161037642250 # Cycle when the warmup percentage was hit. 613system.cpu.icache.tags.occ_blocks::cpu.inst 510.353610 # Average occupied blocks per requestor | 614system.cpu.icache.tags.replacements 790109 # number of replacements 615system.cpu.icache.tags.tagsinuse 510.353605 # Cycle average of tags in use 616system.cpu.icache.tags.total_refs 144545821 # Total number of references to valid blocks. 617system.cpu.icache.tags.sampled_refs 790621 # Sample count of references to valid blocks. 618system.cpu.icache.tags.avg_refs 182.825679 # Average number of references to valid blocks. 619system.cpu.icache.tags.warmup_cycle 161037022250 # Cycle when the warmup percentage was hit. 620system.cpu.icache.tags.occ_blocks::cpu.inst 510.353605 # Average occupied blocks per requestor |
| 614system.cpu.icache.tags.occ_percent::cpu.inst 0.996784 # Average percentage of cache occupancy 615system.cpu.icache.tags.occ_percent::total 0.996784 # Average percentage of cache occupancy 616system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 621system.cpu.icache.tags.occ_percent::cpu.inst 0.996784 # Average percentage of cache occupancy 622system.cpu.icache.tags.occ_percent::total 0.996784 # Average percentage of cache occupancy 623system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 617system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 618system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id 619system.cpu.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id | 624system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 625system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id 626system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id |
| 620system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 621system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 627system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 628system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 622system.cpu.icache.tags.tag_accesses 146170853 # Number of tag accesses 623system.cpu.icache.tags.data_accesses 146170853 # Number of data accesses 624system.cpu.icache.ReadReq_hits::cpu.inst 144580687 # number of ReadReq hits 625system.cpu.icache.ReadReq_hits::total 144580687 # number of ReadReq hits 626system.cpu.icache.demand_hits::cpu.inst 144580687 # number of demand (read+write) hits 627system.cpu.icache.demand_hits::total 144580687 # number of demand (read+write) hits 628system.cpu.icache.overall_hits::cpu.inst 144580687 # number of overall hits 629system.cpu.icache.overall_hits::total 144580687 # number of overall hits 630system.cpu.icache.ReadReq_misses::cpu.inst 795083 # number of ReadReq misses 631system.cpu.icache.ReadReq_misses::total 795083 # number of ReadReq misses 632system.cpu.icache.demand_misses::cpu.inst 795083 # number of demand (read+write) misses 633system.cpu.icache.demand_misses::total 795083 # number of demand (read+write) misses 634system.cpu.icache.overall_misses::cpu.inst 795083 # number of overall misses 635system.cpu.icache.overall_misses::total 795083 # number of overall misses 636system.cpu.icache.ReadReq_miss_latency::cpu.inst 11158319369 # number of ReadReq miss cycles 637system.cpu.icache.ReadReq_miss_latency::total 11158319369 # number of ReadReq miss cycles 638system.cpu.icache.demand_miss_latency::cpu.inst 11158319369 # number of demand (read+write) miss cycles 639system.cpu.icache.demand_miss_latency::total 11158319369 # number of demand (read+write) miss cycles 640system.cpu.icache.overall_miss_latency::cpu.inst 11158319369 # number of overall miss cycles 641system.cpu.icache.overall_miss_latency::total 11158319369 # number of overall miss cycles 642system.cpu.icache.ReadReq_accesses::cpu.inst 145375770 # number of ReadReq accesses(hits+misses) 643system.cpu.icache.ReadReq_accesses::total 145375770 # number of ReadReq accesses(hits+misses) 644system.cpu.icache.demand_accesses::cpu.inst 145375770 # number of demand (read+write) accesses 645system.cpu.icache.demand_accesses::total 145375770 # number of demand (read+write) accesses 646system.cpu.icache.overall_accesses::cpu.inst 145375770 # number of overall (read+write) accesses 647system.cpu.icache.overall_accesses::total 145375770 # number of overall (read+write) accesses 648system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005469 # miss rate for ReadReq accesses 649system.cpu.icache.ReadReq_miss_rate::total 0.005469 # miss rate for ReadReq accesses 650system.cpu.icache.demand_miss_rate::cpu.inst 0.005469 # miss rate for demand accesses 651system.cpu.icache.demand_miss_rate::total 0.005469 # miss rate for demand accesses 652system.cpu.icache.overall_miss_rate::cpu.inst 0.005469 # miss rate for overall accesses 653system.cpu.icache.overall_miss_rate::total 0.005469 # miss rate for overall accesses 654system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14034.156647 # average ReadReq miss latency 655system.cpu.icache.ReadReq_avg_miss_latency::total 14034.156647 # average ReadReq miss latency 656system.cpu.icache.demand_avg_miss_latency::cpu.inst 14034.156647 # average overall miss latency 657system.cpu.icache.demand_avg_miss_latency::total 14034.156647 # average overall miss latency 658system.cpu.icache.overall_avg_miss_latency::cpu.inst 14034.156647 # average overall miss latency 659system.cpu.icache.overall_avg_miss_latency::total 14034.156647 # average overall miss latency | 629system.cpu.icache.tags.tag_accesses 146127077 # Number of tag accesses 630system.cpu.icache.tags.data_accesses 146127077 # Number of data accesses 631system.cpu.icache.ReadReq_hits::cpu.inst 144545821 # number of ReadReq hits 632system.cpu.icache.ReadReq_hits::total 144545821 # number of ReadReq hits 633system.cpu.icache.demand_hits::cpu.inst 144545821 # number of demand (read+write) hits 634system.cpu.icache.demand_hits::total 144545821 # number of demand (read+write) hits 635system.cpu.icache.overall_hits::cpu.inst 144545821 # number of overall hits 636system.cpu.icache.overall_hits::total 144545821 # number of overall hits 637system.cpu.icache.ReadReq_misses::cpu.inst 790628 # number of ReadReq misses 638system.cpu.icache.ReadReq_misses::total 790628 # number of ReadReq misses 639system.cpu.icache.demand_misses::cpu.inst 790628 # number of demand (read+write) misses 640system.cpu.icache.demand_misses::total 790628 # number of demand (read+write) misses 641system.cpu.icache.overall_misses::cpu.inst 790628 # number of overall misses 642system.cpu.icache.overall_misses::total 790628 # number of overall misses 643system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108318120 # number of ReadReq miss cycles 644system.cpu.icache.ReadReq_miss_latency::total 11108318120 # number of ReadReq miss cycles 645system.cpu.icache.demand_miss_latency::cpu.inst 11108318120 # number of demand (read+write) miss cycles 646system.cpu.icache.demand_miss_latency::total 11108318120 # number of demand (read+write) miss cycles 647system.cpu.icache.overall_miss_latency::cpu.inst 11108318120 # number of overall miss cycles 648system.cpu.icache.overall_miss_latency::total 11108318120 # number of overall miss cycles 649system.cpu.icache.ReadReq_accesses::cpu.inst 145336449 # number of ReadReq accesses(hits+misses) 650system.cpu.icache.ReadReq_accesses::total 145336449 # number of ReadReq accesses(hits+misses) 651system.cpu.icache.demand_accesses::cpu.inst 145336449 # number of demand (read+write) accesses 652system.cpu.icache.demand_accesses::total 145336449 # number of demand (read+write) accesses 653system.cpu.icache.overall_accesses::cpu.inst 145336449 # number of overall (read+write) accesses 654system.cpu.icache.overall_accesses::total 145336449 # number of overall (read+write) accesses 655system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses 656system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses 657system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses 658system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses 659system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses 660system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses 661system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14049.993322 # average ReadReq miss latency 662system.cpu.icache.ReadReq_avg_miss_latency::total 14049.993322 # average ReadReq miss latency 663system.cpu.icache.demand_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency 664system.cpu.icache.demand_avg_miss_latency::total 14049.993322 # average overall miss latency 665system.cpu.icache.overall_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency 666system.cpu.icache.overall_avg_miss_latency::total 14049.993322 # average overall miss latency |
| 660system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 661system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 662system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 663system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 664system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 665system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 666system.cpu.icache.fast_writes 0 # number of fast writes performed 667system.cpu.icache.cache_copies 0 # number of cache copies performed | 667system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 668system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 669system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 670system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 671system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 672system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 673system.cpu.icache.fast_writes 0 # number of fast writes performed 674system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 668system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795083 # number of ReadReq MSHR misses 669system.cpu.icache.ReadReq_mshr_misses::total 795083 # number of ReadReq MSHR misses 670system.cpu.icache.demand_mshr_misses::cpu.inst 795083 # number of demand (read+write) MSHR misses 671system.cpu.icache.demand_mshr_misses::total 795083 # number of demand (read+write) MSHR misses 672system.cpu.icache.overall_mshr_misses::cpu.inst 795083 # number of overall MSHR misses 673system.cpu.icache.overall_mshr_misses::total 795083 # number of overall MSHR misses 674system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9563233631 # number of ReadReq MSHR miss cycles 675system.cpu.icache.ReadReq_mshr_miss_latency::total 9563233631 # number of ReadReq MSHR miss cycles 676system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9563233631 # number of demand (read+write) MSHR miss cycles 677system.cpu.icache.demand_mshr_miss_latency::total 9563233631 # number of demand (read+write) MSHR miss cycles 678system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9563233631 # number of overall MSHR miss cycles 679system.cpu.icache.overall_mshr_miss_latency::total 9563233631 # number of overall MSHR miss cycles 680system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for ReadReq accesses 681system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005469 # mshr miss rate for ReadReq accesses 682system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for demand accesses 683system.cpu.icache.demand_mshr_miss_rate::total 0.005469 # mshr miss rate for demand accesses 684system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for overall accesses 685system.cpu.icache.overall_mshr_miss_rate::total 0.005469 # mshr miss rate for overall accesses 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.968943 # average ReadReq mshr miss latency 687system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.968943 # average ReadReq mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.968943 # average overall mshr miss latency 689system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.968943 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.968943 # average overall mshr miss latency 691system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.968943 # average overall mshr miss latency | 675system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790628 # number of ReadReq MSHR misses 676system.cpu.icache.ReadReq_mshr_misses::total 790628 # number of ReadReq MSHR misses 677system.cpu.icache.demand_mshr_misses::cpu.inst 790628 # number of demand (read+write) MSHR misses 678system.cpu.icache.demand_mshr_misses::total 790628 # number of demand (read+write) MSHR misses 679system.cpu.icache.overall_mshr_misses::cpu.inst 790628 # number of overall MSHR misses 680system.cpu.icache.overall_mshr_misses::total 790628 # number of overall MSHR misses 681system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9522182380 # number of ReadReq MSHR miss cycles 682system.cpu.icache.ReadReq_mshr_miss_latency::total 9522182380 # number of ReadReq MSHR miss cycles 683system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9522182380 # number of demand (read+write) MSHR miss cycles 684system.cpu.icache.demand_mshr_miss_latency::total 9522182380 # number of demand (read+write) MSHR miss cycles 685system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9522182380 # number of overall MSHR miss cycles 686system.cpu.icache.overall_mshr_miss_latency::total 9522182380 # number of overall MSHR miss cycles 687system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses 688system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses 689system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses 690system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses 691system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses 692system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses 693system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12043.821342 # average ReadReq mshr miss latency 694system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12043.821342 # average ReadReq mshr miss latency 695system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency 696system.cpu.icache.demand_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency 697system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency 698system.cpu.icache.overall_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency |
| 692system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 699system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 693system.cpu.itb_walker_cache.tags.replacements 3511 # number of replacements 694system.cpu.itb_walker_cache.tags.tagsinuse 3.067889 # Cycle average of tags in use 695system.cpu.itb_walker_cache.tags.total_refs 7844 # Total number of references to valid blocks. 696system.cpu.itb_walker_cache.tags.sampled_refs 3523 # Sample count of references to valid blocks. 697system.cpu.itb_walker_cache.tags.avg_refs 2.226511 # Average number of references to valid blocks. 698system.cpu.itb_walker_cache.tags.warmup_cycle 5164932679000 # Cycle when the warmup percentage was hit. 699system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.067889 # Average occupied blocks per requestor 700system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191743 # Average percentage of cache occupancy 701system.cpu.itb_walker_cache.tags.occ_percent::total 0.191743 # Average percentage of cache occupancy 702system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 703system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id 704system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id 705system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 706system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id 707system.cpu.itb_walker_cache.tags.tag_accesses 28837 # Number of tag accesses 708system.cpu.itb_walker_cache.tags.data_accesses 28837 # Number of data accesses 709system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7845 # number of ReadReq hits 710system.cpu.itb_walker_cache.ReadReq_hits::total 7845 # number of ReadReq hits | 700system.cpu.itb_walker_cache.tags.replacements 3485 # number of replacements 701system.cpu.itb_walker_cache.tags.tagsinuse 3.066895 # Cycle average of tags in use 702system.cpu.itb_walker_cache.tags.total_refs 7845 # Total number of references to valid blocks. 703system.cpu.itb_walker_cache.tags.sampled_refs 3494 # Sample count of references to valid blocks. 704system.cpu.itb_walker_cache.tags.avg_refs 2.245278 # Average number of references to valid blocks. 705system.cpu.itb_walker_cache.tags.warmup_cycle 5167508806000 # Cycle when the warmup percentage was hit. 706system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.066895 # Average occupied blocks per requestor 707system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191681 # Average percentage of cache occupancy 708system.cpu.itb_walker_cache.tags.occ_percent::total 0.191681 # Average percentage of cache occupancy 709system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 9 # Occupied blocks per task id 710system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 711system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 712system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 713system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.562500 # Percentage of cache occupancy per task id 714system.cpu.itb_walker_cache.tags.tag_accesses 28811 # Number of tag accesses 715system.cpu.itb_walker_cache.tags.data_accesses 28811 # Number of data accesses 716system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7868 # number of ReadReq hits 717system.cpu.itb_walker_cache.ReadReq_hits::total 7868 # number of ReadReq hits |
| 711system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 712system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 718system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 719system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 713system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7847 # number of demand (read+write) hits 714system.cpu.itb_walker_cache.demand_hits::total 7847 # number of demand (read+write) hits 715system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7847 # number of overall hits 716system.cpu.itb_walker_cache.overall_hits::total 7847 # number of overall hits 717system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4381 # number of ReadReq misses 718system.cpu.itb_walker_cache.ReadReq_misses::total 4381 # number of ReadReq misses 719system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4381 # number of demand (read+write) misses 720system.cpu.itb_walker_cache.demand_misses::total 4381 # number of demand (read+write) misses 721system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4381 # number of overall misses 722system.cpu.itb_walker_cache.overall_misses::total 4381 # number of overall misses 723system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43773750 # number of ReadReq miss cycles 724system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43773750 # number of ReadReq miss cycles 725system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43773750 # number of demand (read+write) miss cycles 726system.cpu.itb_walker_cache.demand_miss_latency::total 43773750 # number of demand (read+write) miss cycles 727system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43773750 # number of overall miss cycles 728system.cpu.itb_walker_cache.overall_miss_latency::total 43773750 # number of overall miss cycles 729system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12226 # number of ReadReq accesses(hits+misses) 730system.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses) | 720system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7870 # number of demand (read+write) hits 721system.cpu.itb_walker_cache.demand_hits::total 7870 # number of demand (read+write) hits 722system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7870 # number of overall hits 723system.cpu.itb_walker_cache.overall_hits::total 7870 # number of overall hits 724system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4357 # number of ReadReq misses 725system.cpu.itb_walker_cache.ReadReq_misses::total 4357 # number of ReadReq misses 726system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4357 # number of demand (read+write) misses 727system.cpu.itb_walker_cache.demand_misses::total 4357 # number of demand (read+write) misses 728system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4357 # number of overall misses 729system.cpu.itb_walker_cache.overall_misses::total 4357 # number of overall misses 730system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43584500 # number of ReadReq miss cycles 731system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43584500 # number of ReadReq miss cycles 732system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43584500 # number of demand (read+write) miss cycles 733system.cpu.itb_walker_cache.demand_miss_latency::total 43584500 # number of demand (read+write) miss cycles 734system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43584500 # number of overall miss cycles 735system.cpu.itb_walker_cache.overall_miss_latency::total 43584500 # number of overall miss cycles 736system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) 737system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) |
| 731system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 732system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 738system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 739system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 733system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12228 # number of demand (read+write) accesses 734system.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses 735system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12228 # number of overall (read+write) accesses 736system.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses 737system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358335 # miss rate for ReadReq accesses 738system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358335 # miss rate for ReadReq accesses 739system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358276 # miss rate for demand accesses 740system.cpu.itb_walker_cache.demand_miss_rate::total 0.358276 # miss rate for demand accesses 741system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358276 # miss rate for overall accesses 742system.cpu.itb_walker_cache.overall_miss_rate::total 0.358276 # miss rate for overall accesses 743system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9991.725633 # average ReadReq miss latency 744system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9991.725633 # average ReadReq miss latency 745system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency 746system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9991.725633 # average overall miss latency 747system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency 748system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9991.725633 # average overall miss latency | 740system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses 741system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 742system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses 743system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 744system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356401 # miss rate for ReadReq accesses 745system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356401 # miss rate for ReadReq accesses 746system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356343 # miss rate for demand accesses 747system.cpu.itb_walker_cache.demand_miss_rate::total 0.356343 # miss rate for demand accesses 748system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356343 # miss rate for overall accesses 749system.cpu.itb_walker_cache.overall_miss_rate::total 0.356343 # miss rate for overall accesses 750system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10003.327978 # average ReadReq miss latency 751system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10003.327978 # average ReadReq miss latency 752system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency 753system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10003.327978 # average overall miss latency 754system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency 755system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10003.327978 # average overall miss latency |
| 749system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 750system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 751system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 752system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 753system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 754system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 755system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 756system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 756system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 757system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 758system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 759system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 760system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 761system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 762system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 763system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 757system.cpu.itb_walker_cache.writebacks::writebacks 771 # number of writebacks 758system.cpu.itb_walker_cache.writebacks::total 771 # number of writebacks 759system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4381 # number of ReadReq MSHR misses 760system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4381 # number of ReadReq MSHR misses 761system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4381 # number of demand (read+write) MSHR misses 762system.cpu.itb_walker_cache.demand_mshr_misses::total 4381 # number of demand (read+write) MSHR misses 763system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4381 # number of overall MSHR misses 764system.cpu.itb_walker_cache.overall_mshr_misses::total 4381 # number of overall MSHR misses 765system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35010250 # number of ReadReq MSHR miss cycles 766system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35010250 # number of ReadReq MSHR miss cycles 767system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35010250 # number of demand (read+write) MSHR miss cycles 768system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35010250 # number of demand (read+write) MSHR miss cycles 769system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35010250 # number of overall MSHR miss cycles 770system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35010250 # number of overall MSHR miss cycles 771system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358335 # mshr miss rate for ReadReq accesses 772system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358335 # mshr miss rate for ReadReq accesses 773system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for demand accesses 774system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358276 # mshr miss rate for demand accesses 775system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for overall accesses 776system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358276 # mshr miss rate for overall accesses 777system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average ReadReq mshr miss latency 778system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7991.383246 # average ReadReq mshr miss latency 779system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency 780system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency 781system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency 782system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency | 764system.cpu.itb_walker_cache.writebacks::writebacks 747 # number of writebacks 765system.cpu.itb_walker_cache.writebacks::total 747 # number of writebacks 766system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4357 # number of ReadReq MSHR misses 767system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4357 # number of ReadReq MSHR misses 768system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4357 # number of demand (read+write) MSHR misses 769system.cpu.itb_walker_cache.demand_mshr_misses::total 4357 # number of demand (read+write) MSHR misses 770system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4357 # number of overall MSHR misses 771system.cpu.itb_walker_cache.overall_mshr_misses::total 4357 # number of overall MSHR misses 772system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34868500 # number of ReadReq MSHR miss cycles 773system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34868500 # number of ReadReq MSHR miss cycles 774system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34868500 # number of demand (read+write) MSHR miss cycles 775system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34868500 # number of demand (read+write) MSHR miss cycles 776system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34868500 # number of overall MSHR miss cycles 777system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34868500 # number of overall MSHR miss cycles 778system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356401 # mshr miss rate for ReadReq accesses 779system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356401 # mshr miss rate for ReadReq accesses 780system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for demand accesses 781system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356343 # mshr miss rate for demand accesses 782system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for overall accesses 783system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356343 # mshr miss rate for overall accesses 784system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average ReadReq mshr miss latency 785system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8002.868947 # average ReadReq mshr miss latency 786system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency 787system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency 788system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency 789system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency |
| 783system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 790system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 784system.cpu.dtb_walker_cache.tags.replacements 7447 # number of replacements 785system.cpu.dtb_walker_cache.tags.tagsinuse 5.051866 # Cycle average of tags in use 786system.cpu.dtb_walker_cache.tags.total_refs 13273 # Total number of references to valid blocks. 787system.cpu.dtb_walker_cache.tags.sampled_refs 7461 # Sample count of references to valid blocks. 788system.cpu.dtb_walker_cache.tags.avg_refs 1.778984 # Average number of references to valid blocks. 789system.cpu.dtb_walker_cache.tags.warmup_cycle 5163481853000 # Cycle when the warmup percentage was hit. 790system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051866 # Average occupied blocks per requestor | 791system.cpu.dtb_walker_cache.tags.replacements 7826 # number of replacements 792system.cpu.dtb_walker_cache.tags.tagsinuse 5.051872 # Cycle average of tags in use 793system.cpu.dtb_walker_cache.tags.total_refs 12792 # Total number of references to valid blocks. 794system.cpu.dtb_walker_cache.tags.sampled_refs 7842 # Sample count of references to valid blocks. 795system.cpu.dtb_walker_cache.tags.avg_refs 1.631217 # Average number of references to valid blocks. 796system.cpu.dtb_walker_cache.tags.warmup_cycle 5165211267000 # Cycle when the warmup percentage was hit. 797system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051872 # Average occupied blocks per requestor |
| 791system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315742 # Average percentage of cache occupancy 792system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315742 # Average percentage of cache occupancy | 798system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315742 # Average percentage of cache occupancy 799system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315742 # Average percentage of cache occupancy |
| 793system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id | 800system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id |
| 794system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id | 801system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id |
| 795system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 796system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 797system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 798system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id 799system.cpu.dtb_walker_cache.tags.tag_accesses 52546 # Number of tag accesses 800system.cpu.dtb_walker_cache.tags.data_accesses 52546 # Number of data accesses 801system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13289 # number of ReadReq hits 802system.cpu.dtb_walker_cache.ReadReq_hits::total 13289 # number of ReadReq hits 803system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13289 # number of demand (read+write) hits 804system.cpu.dtb_walker_cache.demand_hits::total 13289 # number of demand (read+write) hits 805system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13289 # number of overall hits 806system.cpu.dtb_walker_cache.overall_hits::total 13289 # number of overall hits 807system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8656 # number of ReadReq misses 808system.cpu.dtb_walker_cache.ReadReq_misses::total 8656 # number of ReadReq misses 809system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8656 # number of demand (read+write) misses 810system.cpu.dtb_walker_cache.demand_misses::total 8656 # number of demand (read+write) misses 811system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8656 # number of overall misses 812system.cpu.dtb_walker_cache.overall_misses::total 8656 # number of overall misses 813system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91979000 # number of ReadReq miss cycles 814system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91979000 # number of ReadReq miss cycles 815system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91979000 # number of demand (read+write) miss cycles 816system.cpu.dtb_walker_cache.demand_miss_latency::total 91979000 # number of demand (read+write) miss cycles 817system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91979000 # number of overall miss cycles 818system.cpu.dtb_walker_cache.overall_miss_latency::total 91979000 # number of overall miss cycles 819system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21945 # number of ReadReq accesses(hits+misses) 820system.cpu.dtb_walker_cache.ReadReq_accesses::total 21945 # number of ReadReq accesses(hits+misses) 821system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21945 # number of demand (read+write) accesses 822system.cpu.dtb_walker_cache.demand_accesses::total 21945 # number of demand (read+write) accesses 823system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21945 # number of overall (read+write) accesses 824system.cpu.dtb_walker_cache.overall_accesses::total 21945 # number of overall (read+write) accesses 825system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.394441 # miss rate for ReadReq accesses 826system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.394441 # miss rate for ReadReq accesses 827system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.394441 # miss rate for demand accesses 828system.cpu.dtb_walker_cache.demand_miss_rate::total 0.394441 # miss rate for demand accesses 829system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.394441 # miss rate for overall accesses 830system.cpu.dtb_walker_cache.overall_miss_rate::total 0.394441 # miss rate for overall accesses 831system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10626.039741 # average ReadReq miss latency 832system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10626.039741 # average ReadReq miss latency 833system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency 834system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10626.039741 # average overall miss latency 835system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency 836system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10626.039741 # average overall miss latency | 802system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 803system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 804system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 805system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 806system.cpu.dtb_walker_cache.tags.tag_accesses 52641 # Number of tag accesses 807system.cpu.dtb_walker_cache.tags.data_accesses 52641 # Number of data accesses 808system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12792 # number of ReadReq hits 809system.cpu.dtb_walker_cache.ReadReq_hits::total 12792 # number of ReadReq hits 810system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12792 # number of demand (read+write) hits 811system.cpu.dtb_walker_cache.demand_hits::total 12792 # number of demand (read+write) hits 812system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12792 # number of overall hits 813system.cpu.dtb_walker_cache.overall_hits::total 12792 # number of overall hits 814system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9019 # number of ReadReq misses 815system.cpu.dtb_walker_cache.ReadReq_misses::total 9019 # number of ReadReq misses 816system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9019 # number of demand (read+write) misses 817system.cpu.dtb_walker_cache.demand_misses::total 9019 # number of demand (read+write) misses 818system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9019 # number of overall misses 819system.cpu.dtb_walker_cache.overall_misses::total 9019 # number of overall misses 820system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95783000 # number of ReadReq miss cycles 821system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95783000 # number of ReadReq miss cycles 822system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95783000 # number of demand (read+write) miss cycles 823system.cpu.dtb_walker_cache.demand_miss_latency::total 95783000 # number of demand (read+write) miss cycles 824system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95783000 # number of overall miss cycles 825system.cpu.dtb_walker_cache.overall_miss_latency::total 95783000 # number of overall miss cycles 826system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21811 # number of ReadReq accesses(hits+misses) 827system.cpu.dtb_walker_cache.ReadReq_accesses::total 21811 # number of ReadReq accesses(hits+misses) 828system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21811 # number of demand (read+write) accesses 829system.cpu.dtb_walker_cache.demand_accesses::total 21811 # number of demand (read+write) accesses 830system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21811 # number of overall (read+write) accesses 831system.cpu.dtb_walker_cache.overall_accesses::total 21811 # number of overall (read+write) accesses 832system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.413507 # miss rate for ReadReq accesses 833system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.413507 # miss rate for ReadReq accesses 834system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.413507 # miss rate for demand accesses 835system.cpu.dtb_walker_cache.demand_miss_rate::total 0.413507 # miss rate for demand accesses 836system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.413507 # miss rate for overall accesses 837system.cpu.dtb_walker_cache.overall_miss_rate::total 0.413507 # miss rate for overall accesses 838system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10620.135270 # average ReadReq miss latency 839system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10620.135270 # average ReadReq miss latency 840system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency 841system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10620.135270 # average overall miss latency 842system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency 843system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10620.135270 # average overall miss latency |
| 837system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 838system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 839system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 840system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 841system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 842system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 843system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 844system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 844system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 845system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 846system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 847system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 848system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 849system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 850system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 851system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 845system.cpu.dtb_walker_cache.writebacks::writebacks 2980 # number of writebacks 846system.cpu.dtb_walker_cache.writebacks::total 2980 # number of writebacks 847system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8656 # number of ReadReq MSHR misses 848system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8656 # number of ReadReq MSHR misses 849system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8656 # number of demand (read+write) MSHR misses 850system.cpu.dtb_walker_cache.demand_mshr_misses::total 8656 # number of demand (read+write) MSHR misses 851system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8656 # number of overall MSHR misses 852system.cpu.dtb_walker_cache.overall_mshr_misses::total 8656 # number of overall MSHR misses 853system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74666500 # number of ReadReq MSHR miss cycles 854system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74666500 # number of ReadReq MSHR miss cycles 855system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74666500 # number of demand (read+write) MSHR miss cycles 856system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74666500 # number of demand (read+write) MSHR miss cycles 857system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74666500 # number of overall MSHR miss cycles 858system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74666500 # number of overall MSHR miss cycles 859system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for ReadReq accesses 860system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.394441 # mshr miss rate for ReadReq accesses 861system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for demand accesses 862system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.394441 # mshr miss rate for demand accesses 863system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for overall accesses 864system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.394441 # mshr miss rate for overall accesses 865system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average ReadReq mshr miss latency 866system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8625.981978 # average ReadReq mshr miss latency 867system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency 868system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency 869system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency 870system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency | 852system.cpu.dtb_walker_cache.writebacks::writebacks 2842 # number of writebacks 853system.cpu.dtb_walker_cache.writebacks::total 2842 # number of writebacks 854system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9019 # number of ReadReq MSHR misses 855system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9019 # number of ReadReq MSHR misses 856system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9019 # number of demand (read+write) MSHR misses 857system.cpu.dtb_walker_cache.demand_mshr_misses::total 9019 # number of demand (read+write) MSHR misses 858system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9019 # number of overall MSHR misses 859system.cpu.dtb_walker_cache.overall_mshr_misses::total 9019 # number of overall MSHR misses 860system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77744500 # number of ReadReq MSHR miss cycles 861system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77744500 # number of ReadReq MSHR miss cycles 862system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77744500 # number of demand (read+write) MSHR miss cycles 863system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77744500 # number of demand (read+write) MSHR miss cycles 864system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77744500 # number of overall MSHR miss cycles 865system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77744500 # number of overall MSHR miss cycles 866system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for ReadReq accesses 867system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.413507 # mshr miss rate for ReadReq accesses 868system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for demand accesses 869system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.413507 # mshr miss rate for demand accesses 870system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for overall accesses 871system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.413507 # mshr miss rate for overall accesses 872system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average ReadReq mshr miss latency 873system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8620.079831 # average ReadReq mshr miss latency 874system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency 875system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency 876system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency 877system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency |
| 871system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 878system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 872system.cpu.dcache.tags.replacements 1620883 # number of replacements 873system.cpu.dcache.tags.tagsinuse 511.997130 # Cycle average of tags in use 874system.cpu.dcache.tags.total_refs 20027756 # Total number of references to valid blocks. 875system.cpu.dcache.tags.sampled_refs 1621395 # Sample count of references to valid blocks. 876system.cpu.dcache.tags.avg_refs 12.352176 # Average number of references to valid blocks. | 879system.cpu.dcache.tags.replacements 1621218 # number of replacements 880system.cpu.dcache.tags.tagsinuse 511.996934 # Cycle average of tags in use 881system.cpu.dcache.tags.total_refs 20024389 # Total number of references to valid blocks. 882system.cpu.dcache.tags.sampled_refs 1621730 # Sample count of references to valid blocks. 883system.cpu.dcache.tags.avg_refs 12.347548 # Average number of references to valid blocks. |
| 877system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. | 884system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. |
| 878system.cpu.dcache.tags.occ_blocks::cpu.data 511.997130 # Average occupied blocks per requestor | 885system.cpu.dcache.tags.occ_blocks::cpu.data 511.996934 # Average occupied blocks per requestor |
| 879system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 880system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 881system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 886system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 887system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 888system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 882system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 883system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id 884system.cpu.dcache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id 885system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id | 889system.cpu.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 890system.cpu.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id 891system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id |
| 886system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 892system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 887system.cpu.dcache.tags.tag_accesses 88256675 # Number of tag accesses 888system.cpu.dcache.tags.data_accesses 88256675 # Number of data accesses 889system.cpu.dcache.ReadReq_hits::cpu.data 11935486 # number of ReadReq hits 890system.cpu.dcache.ReadReq_hits::total 11935486 # number of ReadReq hits 891system.cpu.dcache.WriteReq_hits::cpu.data 8030839 # number of WriteReq hits 892system.cpu.dcache.WriteReq_hits::total 8030839 # number of WriteReq hits 893system.cpu.dcache.SoftPFReq_hits::cpu.data 59261 # number of SoftPFReq hits 894system.cpu.dcache.SoftPFReq_hits::total 59261 # number of SoftPFReq hits 895system.cpu.dcache.demand_hits::cpu.data 19966325 # number of demand (read+write) hits 896system.cpu.dcache.demand_hits::total 19966325 # number of demand (read+write) hits 897system.cpu.dcache.overall_hits::cpu.data 20025586 # number of overall hits 898system.cpu.dcache.overall_hits::total 20025586 # number of overall hits 899system.cpu.dcache.ReadReq_misses::cpu.data 906294 # number of ReadReq misses 900system.cpu.dcache.ReadReq_misses::total 906294 # number of ReadReq misses 901system.cpu.dcache.WriteReq_misses::cpu.data 324617 # number of WriteReq misses 902system.cpu.dcache.WriteReq_misses::total 324617 # number of WriteReq misses 903system.cpu.dcache.SoftPFReq_misses::cpu.data 402313 # number of SoftPFReq misses 904system.cpu.dcache.SoftPFReq_misses::total 402313 # number of SoftPFReq misses 905system.cpu.dcache.demand_misses::cpu.data 1230911 # number of demand (read+write) misses 906system.cpu.dcache.demand_misses::total 1230911 # number of demand (read+write) misses 907system.cpu.dcache.overall_misses::cpu.data 1633224 # number of overall misses 908system.cpu.dcache.overall_misses::total 1633224 # number of overall misses 909system.cpu.dcache.ReadReq_miss_latency::cpu.data 12712957750 # number of ReadReq miss cycles 910system.cpu.dcache.ReadReq_miss_latency::total 12712957750 # number of ReadReq miss cycles 911system.cpu.dcache.WriteReq_miss_latency::cpu.data 11341720828 # number of WriteReq miss cycles 912system.cpu.dcache.WriteReq_miss_latency::total 11341720828 # number of WriteReq miss cycles 913system.cpu.dcache.demand_miss_latency::cpu.data 24054678578 # number of demand (read+write) miss cycles 914system.cpu.dcache.demand_miss_latency::total 24054678578 # number of demand (read+write) miss cycles 915system.cpu.dcache.overall_miss_latency::cpu.data 24054678578 # number of overall miss cycles 916system.cpu.dcache.overall_miss_latency::total 24054678578 # number of overall miss cycles 917system.cpu.dcache.ReadReq_accesses::cpu.data 12841780 # number of ReadReq accesses(hits+misses) 918system.cpu.dcache.ReadReq_accesses::total 12841780 # number of ReadReq accesses(hits+misses) 919system.cpu.dcache.WriteReq_accesses::cpu.data 8355456 # number of WriteReq accesses(hits+misses) 920system.cpu.dcache.WriteReq_accesses::total 8355456 # number of WriteReq accesses(hits+misses) 921system.cpu.dcache.SoftPFReq_accesses::cpu.data 461574 # number of SoftPFReq accesses(hits+misses) 922system.cpu.dcache.SoftPFReq_accesses::total 461574 # number of SoftPFReq accesses(hits+misses) 923system.cpu.dcache.demand_accesses::cpu.data 21197236 # number of demand (read+write) accesses 924system.cpu.dcache.demand_accesses::total 21197236 # number of demand (read+write) accesses 925system.cpu.dcache.overall_accesses::cpu.data 21658810 # number of overall (read+write) accesses 926system.cpu.dcache.overall_accesses::total 21658810 # number of overall (read+write) accesses 927system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070574 # miss rate for ReadReq accesses 928system.cpu.dcache.ReadReq_miss_rate::total 0.070574 # miss rate for ReadReq accesses 929system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038851 # miss rate for WriteReq accesses 930system.cpu.dcache.WriteReq_miss_rate::total 0.038851 # miss rate for WriteReq accesses 931system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871611 # miss rate for SoftPFReq accesses 932system.cpu.dcache.SoftPFReq_miss_rate::total 0.871611 # miss rate for SoftPFReq accesses 933system.cpu.dcache.demand_miss_rate::cpu.data 0.058069 # miss rate for demand accesses 934system.cpu.dcache.demand_miss_rate::total 0.058069 # miss rate for demand accesses 935system.cpu.dcache.overall_miss_rate::cpu.data 0.075407 # miss rate for overall accesses 936system.cpu.dcache.overall_miss_rate::total 0.075407 # miss rate for overall accesses 937system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14027.410255 # average ReadReq miss latency 938system.cpu.dcache.ReadReq_avg_miss_latency::total 14027.410255 # average ReadReq miss latency 939system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34938.776552 # average WriteReq miss latency 940system.cpu.dcache.WriteReq_avg_miss_latency::total 34938.776552 # average WriteReq miss latency 941system.cpu.dcache.demand_avg_miss_latency::cpu.data 19542.175330 # average overall miss latency 942system.cpu.dcache.demand_avg_miss_latency::total 19542.175330 # average overall miss latency 943system.cpu.dcache.overall_avg_miss_latency::cpu.data 14728.340128 # average overall miss latency 944system.cpu.dcache.overall_avg_miss_latency::total 14728.340128 # average overall miss latency 945system.cpu.dcache.blocked_cycles::no_mshrs 7655 # number of cycles access was blocked | 893system.cpu.dcache.tags.tag_accesses 88244906 # Number of tag accesses 894system.cpu.dcache.tags.data_accesses 88244906 # Number of data accesses 895system.cpu.dcache.ReadReq_hits::cpu.data 11933720 # number of ReadReq hits 896system.cpu.dcache.ReadReq_hits::total 11933720 # number of ReadReq hits 897system.cpu.dcache.WriteReq_hits::cpu.data 8029176 # number of WriteReq hits 898system.cpu.dcache.WriteReq_hits::total 8029176 # number of WriteReq hits 899system.cpu.dcache.SoftPFReq_hits::cpu.data 59323 # number of SoftPFReq hits 900system.cpu.dcache.SoftPFReq_hits::total 59323 # number of SoftPFReq hits 901system.cpu.dcache.demand_hits::cpu.data 19962896 # number of demand (read+write) hits 902system.cpu.dcache.demand_hits::total 19962896 # number of demand (read+write) hits 903system.cpu.dcache.overall_hits::cpu.data 20022219 # number of overall hits 904system.cpu.dcache.overall_hits::total 20022219 # number of overall hits 905system.cpu.dcache.ReadReq_misses::cpu.data 906567 # number of ReadReq misses 906system.cpu.dcache.ReadReq_misses::total 906567 # number of ReadReq misses 907system.cpu.dcache.WriteReq_misses::cpu.data 324536 # number of WriteReq misses 908system.cpu.dcache.WriteReq_misses::total 324536 # number of WriteReq misses 909system.cpu.dcache.SoftPFReq_misses::cpu.data 402460 # number of SoftPFReq misses 910system.cpu.dcache.SoftPFReq_misses::total 402460 # number of SoftPFReq misses 911system.cpu.dcache.demand_misses::cpu.data 1231103 # number of demand (read+write) misses 912system.cpu.dcache.demand_misses::total 1231103 # number of demand (read+write) misses 913system.cpu.dcache.overall_misses::cpu.data 1633563 # number of overall misses 914system.cpu.dcache.overall_misses::total 1633563 # number of overall misses 915system.cpu.dcache.ReadReq_miss_latency::cpu.data 12726532750 # number of ReadReq miss cycles 916system.cpu.dcache.ReadReq_miss_latency::total 12726532750 # number of ReadReq miss cycles 917system.cpu.dcache.WriteReq_miss_latency::cpu.data 11379509067 # number of WriteReq miss cycles 918system.cpu.dcache.WriteReq_miss_latency::total 11379509067 # number of WriteReq miss cycles 919system.cpu.dcache.demand_miss_latency::cpu.data 24106041817 # number of demand (read+write) miss cycles 920system.cpu.dcache.demand_miss_latency::total 24106041817 # number of demand (read+write) miss cycles 921system.cpu.dcache.overall_miss_latency::cpu.data 24106041817 # number of overall miss cycles 922system.cpu.dcache.overall_miss_latency::total 24106041817 # number of overall miss cycles 923system.cpu.dcache.ReadReq_accesses::cpu.data 12840287 # number of ReadReq accesses(hits+misses) 924system.cpu.dcache.ReadReq_accesses::total 12840287 # number of ReadReq accesses(hits+misses) 925system.cpu.dcache.WriteReq_accesses::cpu.data 8353712 # number of WriteReq accesses(hits+misses) 926system.cpu.dcache.WriteReq_accesses::total 8353712 # number of WriteReq accesses(hits+misses) 927system.cpu.dcache.SoftPFReq_accesses::cpu.data 461783 # number of SoftPFReq accesses(hits+misses) 928system.cpu.dcache.SoftPFReq_accesses::total 461783 # number of SoftPFReq accesses(hits+misses) 929system.cpu.dcache.demand_accesses::cpu.data 21193999 # number of demand (read+write) accesses 930system.cpu.dcache.demand_accesses::total 21193999 # number of demand (read+write) accesses 931system.cpu.dcache.overall_accesses::cpu.data 21655782 # number of overall (read+write) accesses 932system.cpu.dcache.overall_accesses::total 21655782 # number of overall (read+write) accesses 933system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070603 # miss rate for ReadReq accesses 934system.cpu.dcache.ReadReq_miss_rate::total 0.070603 # miss rate for ReadReq accesses 935system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038849 # miss rate for WriteReq accesses 936system.cpu.dcache.WriteReq_miss_rate::total 0.038849 # miss rate for WriteReq accesses 937system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871535 # miss rate for SoftPFReq accesses 938system.cpu.dcache.SoftPFReq_miss_rate::total 0.871535 # miss rate for SoftPFReq accesses 939system.cpu.dcache.demand_miss_rate::cpu.data 0.058087 # miss rate for demand accesses 940system.cpu.dcache.demand_miss_rate::total 0.058087 # miss rate for demand accesses 941system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses 942system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses 943system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.160169 # average ReadReq miss latency 944system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.160169 # average ReadReq miss latency 945system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35063.934562 # average WriteReq miss latency 946system.cpu.dcache.WriteReq_avg_miss_latency::total 35063.934562 # average WriteReq miss latency 947system.cpu.dcache.demand_avg_miss_latency::cpu.data 19580.848895 # average overall miss latency 948system.cpu.dcache.demand_avg_miss_latency::total 19580.848895 # average overall miss latency 949system.cpu.dcache.overall_avg_miss_latency::cpu.data 14756.726136 # average overall miss latency 950system.cpu.dcache.overall_avg_miss_latency::total 14756.726136 # average overall miss latency 951system.cpu.dcache.blocked_cycles::no_mshrs 8324 # number of cycles access was blocked |
| 946system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 952system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 947system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked | 953system.cpu.dcache.blocked::no_mshrs 80 # number of cycles access was blocked |
| 948system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 954system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 949system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.863014 # average number of cycles each access was blocked | 955system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.050000 # average number of cycles each access was blocked |
| 950system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 951system.cpu.dcache.fast_writes 0 # number of fast writes performed 952system.cpu.dcache.cache_copies 0 # number of cache copies performed | 956system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 957system.cpu.dcache.fast_writes 0 # number of fast writes performed 958system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 953system.cpu.dcache.writebacks::writebacks 1537682 # number of writebacks 954system.cpu.dcache.writebacks::total 1537682 # number of writebacks | 959system.cpu.dcache.writebacks::writebacks 1537872 # number of writebacks 960system.cpu.dcache.writebacks::total 1537872 # number of writebacks |
| 955system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits 956system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits | 961system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits 962system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits |
| 957system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9297 # number of WriteReq MSHR hits 958system.cpu.dcache.WriteReq_mshr_hits::total 9297 # number of WriteReq MSHR hits 959system.cpu.dcache.demand_mshr_hits::cpu.data 9584 # number of demand (read+write) MSHR hits 960system.cpu.dcache.demand_mshr_hits::total 9584 # number of demand (read+write) MSHR hits 961system.cpu.dcache.overall_mshr_hits::cpu.data 9584 # number of overall MSHR hits 962system.cpu.dcache.overall_mshr_hits::total 9584 # number of overall MSHR hits 963system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906007 # number of ReadReq MSHR misses 964system.cpu.dcache.ReadReq_mshr_misses::total 906007 # number of ReadReq MSHR misses 965system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315320 # number of WriteReq MSHR misses 966system.cpu.dcache.WriteReq_mshr_misses::total 315320 # number of WriteReq MSHR misses 967system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402278 # number of SoftPFReq MSHR misses 968system.cpu.dcache.SoftPFReq_mshr_misses::total 402278 # number of SoftPFReq MSHR misses 969system.cpu.dcache.demand_mshr_misses::cpu.data 1221327 # number of demand (read+write) MSHR misses 970system.cpu.dcache.demand_mshr_misses::total 1221327 # number of demand (read+write) MSHR misses 971system.cpu.dcache.overall_mshr_misses::cpu.data 1623605 # number of overall MSHR misses 972system.cpu.dcache.overall_mshr_misses::total 1623605 # number of overall MSHR misses 973system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10893569500 # number of ReadReq MSHR miss cycles 974system.cpu.dcache.ReadReq_mshr_miss_latency::total 10893569500 # number of ReadReq MSHR miss cycles 975system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10209797624 # number of WriteReq MSHR miss cycles 976system.cpu.dcache.WriteReq_mshr_miss_latency::total 10209797624 # number of WriteReq MSHR miss cycles 977system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5351981750 # number of SoftPFReq MSHR miss cycles 978system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5351981750 # number of SoftPFReq MSHR miss cycles 979system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21103367124 # number of demand (read+write) MSHR miss cycles 980system.cpu.dcache.demand_mshr_miss_latency::total 21103367124 # number of demand (read+write) MSHR miss cycles 981system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26455348874 # number of overall MSHR miss cycles 982system.cpu.dcache.overall_mshr_miss_latency::total 26455348874 # number of overall MSHR miss cycles | 963system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9293 # number of WriteReq MSHR hits 964system.cpu.dcache.WriteReq_mshr_hits::total 9293 # number of WriteReq MSHR hits 965system.cpu.dcache.demand_mshr_hits::cpu.data 9580 # number of demand (read+write) MSHR hits 966system.cpu.dcache.demand_mshr_hits::total 9580 # number of demand (read+write) MSHR hits 967system.cpu.dcache.overall_mshr_hits::cpu.data 9580 # number of overall MSHR hits 968system.cpu.dcache.overall_mshr_hits::total 9580 # number of overall MSHR hits 969system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906280 # number of ReadReq MSHR misses 970system.cpu.dcache.ReadReq_mshr_misses::total 906280 # number of ReadReq MSHR misses 971system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315243 # number of WriteReq MSHR misses 972system.cpu.dcache.WriteReq_mshr_misses::total 315243 # number of WriteReq MSHR misses 973system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402425 # number of SoftPFReq MSHR misses 974system.cpu.dcache.SoftPFReq_mshr_misses::total 402425 # number of SoftPFReq MSHR misses 975system.cpu.dcache.demand_mshr_misses::cpu.data 1221523 # number of demand (read+write) MSHR misses 976system.cpu.dcache.demand_mshr_misses::total 1221523 # number of demand (read+write) MSHR misses 977system.cpu.dcache.overall_mshr_misses::cpu.data 1623948 # number of overall MSHR misses 978system.cpu.dcache.overall_mshr_misses::total 1623948 # number of overall MSHR misses 979system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10906302000 # number of ReadReq MSHR miss cycles 980system.cpu.dcache.ReadReq_mshr_miss_latency::total 10906302000 # number of ReadReq MSHR miss cycles 981system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245705379 # number of WriteReq MSHR miss cycles 982system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245705379 # number of WriteReq MSHR miss cycles 983system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5368514000 # number of SoftPFReq MSHR miss cycles 984system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5368514000 # number of SoftPFReq MSHR miss cycles 985system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21152007379 # number of demand (read+write) MSHR miss cycles 986system.cpu.dcache.demand_mshr_miss_latency::total 21152007379 # number of demand (read+write) MSHR miss cycles 987system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26520521379 # number of overall MSHR miss cycles 988system.cpu.dcache.overall_mshr_miss_latency::total 26520521379 # number of overall MSHR miss cycles |
| 983system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672000 # number of ReadReq MSHR uncacheable cycles 984system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672000 # number of ReadReq MSHR uncacheable cycles | 989system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672000 # number of ReadReq MSHR uncacheable cycles 990system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672000 # number of ReadReq MSHR uncacheable cycles |
| 985system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537257000 # number of WriteReq MSHR uncacheable cycles 986system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537257000 # number of WriteReq MSHR uncacheable cycles 987system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96751929000 # number of overall MSHR uncacheable cycles 988system.cpu.dcache.overall_mshr_uncacheable_latency::total 96751929000 # number of overall MSHR uncacheable cycles 989system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070552 # mshr miss rate for ReadReq accesses 990system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070552 # mshr miss rate for ReadReq accesses 991system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037738 # mshr miss rate for WriteReq accesses 992system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037738 # mshr miss rate for WriteReq accesses 993system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871535 # mshr miss rate for SoftPFReq accesses 994system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871535 # mshr miss rate for SoftPFReq accesses 995system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057617 # mshr miss rate for demand accesses 996system.cpu.dcache.demand_mshr_miss_rate::total 0.057617 # mshr miss rate for demand accesses 997system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074963 # mshr miss rate for overall accesses 998system.cpu.dcache.overall_mshr_miss_rate::total 0.074963 # mshr miss rate for overall accesses 999system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.714497 # average ReadReq mshr miss latency 1000system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.714497 # average ReadReq mshr miss latency 1001system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32379.162831 # average WriteReq mshr miss latency 1002system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32379.162831 # average WriteReq mshr miss latency 1003system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13304.187030 # average SoftPFReq mshr miss latency 1004system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13304.187030 # average SoftPFReq mshr miss latency 1005system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17279.047400 # average overall mshr miss latency 1006system.cpu.dcache.demand_avg_mshr_miss_latency::total 17279.047400 # average overall mshr miss latency 1007system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16294.202638 # average overall mshr miss latency 1008system.cpu.dcache.overall_avg_mshr_miss_latency::total 16294.202638 # average overall mshr miss latency | 991system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536037000 # number of WriteReq MSHR uncacheable cycles 992system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536037000 # number of WriteReq MSHR uncacheable cycles 993system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96750709000 # number of overall MSHR uncacheable cycles 994system.cpu.dcache.overall_mshr_uncacheable_latency::total 96750709000 # number of overall MSHR uncacheable cycles 995system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070581 # mshr miss rate for ReadReq accesses 996system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070581 # mshr miss rate for ReadReq accesses 997system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037737 # mshr miss rate for WriteReq accesses 998system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037737 # mshr miss rate for WriteReq accesses 999system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871459 # mshr miss rate for SoftPFReq accesses 1000system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871459 # mshr miss rate for SoftPFReq accesses 1001system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057635 # mshr miss rate for demand accesses 1002system.cpu.dcache.demand_mshr_miss_rate::total 0.057635 # mshr miss rate for demand accesses 1003system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074989 # mshr miss rate for overall accesses 1004system.cpu.dcache.overall_mshr_miss_rate::total 0.074989 # mshr miss rate for overall accesses 1005system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12034.141766 # average ReadReq mshr miss latency 1006system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12034.141766 # average ReadReq mshr miss latency 1007system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32500.976640 # average WriteReq mshr miss latency 1008system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32500.976640 # average WriteReq mshr miss latency 1009system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13340.408772 # average SoftPFReq mshr miss latency 1010system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13340.408772 # average SoftPFReq mshr miss latency 1011system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17316.094236 # average overall mshr miss latency 1012system.cpu.dcache.demand_avg_mshr_miss_latency::total 17316.094236 # average overall mshr miss latency 1013system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16330.893218 # average overall mshr miss latency 1014system.cpu.dcache.overall_avg_mshr_miss_latency::total 16330.893218 # average overall mshr miss latency |
| 1009system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1010system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1011system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1012system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1013system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1014system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1015system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1015system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1016system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1017system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1018system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1019system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1020system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1021system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1016system.cpu.toL2Bus.throughput 49844829 # Throughput (bytes/s) 1017system.cpu.toL2Bus.trans_dist::ReadReq 2698695 # Transaction distribution 1018system.cpu.toL2Bus.trans_dist::ReadResp 2698173 # Transaction distribution | 1022system.cpu.toL2Bus.trans_dist::ReadReq 2694994 # Transaction distribution 1023system.cpu.toL2Bus.trans_dist::ReadResp 2694474 # Transaction distribution |
| 1019system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution 1020system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution | 1024system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution 1025system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution |
| 1021system.cpu.toL2Bus.trans_dist::Writeback 1541433 # Transaction distribution 1022system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution | 1026system.cpu.toL2Bus.trans_dist::Writeback 1541461 # Transaction distribution 1027system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution |
| 1023system.cpu.toL2Bus.trans_dist::UpgradeReq 2183 # Transaction distribution 1024system.cpu.toL2Bus.trans_dist::UpgradeResp 2183 # Transaction distribution | 1028system.cpu.toL2Bus.trans_dist::UpgradeReq 2183 # Transaction distribution 1029system.cpu.toL2Bus.trans_dist::UpgradeResp 2183 # Transaction distribution |
| 1025system.cpu.toL2Bus.trans_dist::ReadExReq 313150 # Transaction distribution 1026system.cpu.toL2Bus.trans_dist::ReadExResp 313150 # Transaction distribution 1027system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1590153 # Packet count per connected master and slave (bytes) 1028system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5974271 # Packet count per connected master and slave (bytes) 1029system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8035 # Packet count per connected master and slave (bytes) 1030system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18003 # Packet count per connected master and slave (bytes) 1031system.cpu.toL2Bus.pkt_count::total 7590462 # Packet count per connected master and slave (bytes) 1032system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50884480 # Cumulative packet size per connected master and slave (bytes) 1033system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203815525 # Cumulative packet size per connected master and slave (bytes) 1034system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 233856 # Cumulative packet size per connected master and slave (bytes) 1035system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 598208 # Cumulative packet size per connected master and slave (bytes) 1036system.cpu.toL2Bus.tot_pkt_size::total 255532069 # Cumulative packet size per connected master and slave (bytes) 1037system.cpu.toL2Bus.data_through_bus 255511461 # Total data (bytes) 1038system.cpu.toL2Bus.snoop_data_through_bus 3309120 # Total snoop data (bytes) 1039system.cpu.toL2Bus.reqLayer0.occupancy 3832514500 # Layer occupancy (ticks) | 1030system.cpu.toL2Bus.trans_dist::ReadExReq 313073 # Transaction distribution 1031system.cpu.toL2Bus.trans_dist::ReadExResp 313073 # Transaction distribution 1032system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581243 # Packet count per connected master and slave (bytes) 1033system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5975195 # Packet count per connected master and slave (bytes) 1034system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7975 # Packet count per connected master and slave (bytes) 1035system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18479 # Packet count per connected master and slave (bytes) 1036system.cpu.toL2Bus.pkt_count::total 7582892 # Packet count per connected master and slave (bytes) 1037system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50599360 # Cumulative packet size per connected master and slave (bytes) 1038system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203853221 # Cumulative packet size per connected master and slave (bytes) 1039system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 231552 # Cumulative packet size per connected master and slave (bytes) 1040system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605440 # Cumulative packet size per connected master and slave (bytes) 1041system.cpu.toL2Bus.pkt_size::total 255289573 # Cumulative packet size per connected master and slave (bytes) 1042system.cpu.toL2Bus.snoops 53135 # Total snoops (count) 1043system.cpu.toL2Bus.snoop_fanout::samples 4016986 # Request fanout histogram 1044system.cpu.toL2Bus.snoop_fanout::mean 3.011840 # Request fanout histogram 1045system.cpu.toL2Bus.snoop_fanout::stdev 0.108164 # Request fanout histogram 1046system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1047system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1048system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1049system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1050system.cpu.toL2Bus.snoop_fanout::3 3969426 98.82% 98.82% # Request fanout histogram 1051system.cpu.toL2Bus.snoop_fanout::4 47560 1.18% 100.00% # Request fanout histogram 1052system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1053system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1054system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1055system.cpu.toL2Bus.snoop_fanout::total 4016986 # Request fanout histogram 1056system.cpu.toL2Bus.reqLayer0.occupancy 3830670000 # Layer occupancy (ticks) |
| 1040system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1057system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1041system.cpu.toL2Bus.snoopLayer0.occupancy 483000 # Layer occupancy (ticks) | 1058system.cpu.toL2Bus.snoopLayer0.occupancy 478500 # Layer occupancy (ticks) |
| 1042system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1059system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1043system.cpu.toL2Bus.respLayer0.occupancy 1195084369 # Layer occupancy (ticks) | 1060system.cpu.toL2Bus.respLayer0.occupancy 1188381870 # Layer occupancy (ticks) |
| 1044system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1061system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1045system.cpu.toL2Bus.respLayer1.occupancy 3051993102 # Layer occupancy (ticks) | 1062system.cpu.toL2Bus.respLayer1.occupancy 3052447844 # Layer occupancy (ticks) |
| 1046system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) | 1063system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) |
| 1047system.cpu.toL2Bus.respLayer2.occupancy 6572250 # Layer occupancy (ticks) | 1064system.cpu.toL2Bus.respLayer2.occupancy 6536500 # Layer occupancy (ticks) |
| 1048system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) | 1065system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) |
| 1049system.cpu.toL2Bus.respLayer3.occupancy 12984250 # Layer occupancy (ticks) | 1066system.cpu.toL2Bus.respLayer3.occupancy 13528750 # Layer occupancy (ticks) |
| 1050system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1067system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1051system.cpu.l2cache.tags.replacements 87211 # number of replacements 1052system.cpu.l2cache.tags.tagsinuse 64746.136544 # Cycle average of tags in use 1053system.cpu.l2cache.tags.total_refs 3491181 # Total number of references to valid blocks. 1054system.cpu.l2cache.tags.sampled_refs 151954 # Sample count of references to valid blocks. 1055system.cpu.l2cache.tags.avg_refs 22.975249 # Average number of references to valid blocks. | 1068system.cpu.l2cache.tags.replacements 87289 # number of replacements 1069system.cpu.l2cache.tags.tagsinuse 64708.241819 # Cycle average of tags in use 1070system.cpu.l2cache.tags.total_refs 3488268 # Total number of references to valid blocks. 1071system.cpu.l2cache.tags.sampled_refs 151942 # Sample count of references to valid blocks. 1072system.cpu.l2cache.tags.avg_refs 22.957892 # Average number of references to valid blocks. |
| 1056system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1073system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1057system.cpu.l2cache.tags.occ_blocks::writebacks 50332.685507 # Average occupied blocks per requestor 1058system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006414 # Average occupied blocks per requestor 1059system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141265 # Average occupied blocks per requestor 1060system.cpu.l2cache.tags.occ_blocks::cpu.inst 3220.709839 # Average occupied blocks per requestor 1061system.cpu.l2cache.tags.occ_blocks::cpu.data 11192.593518 # Average occupied blocks per requestor 1062system.cpu.l2cache.tags.occ_percent::writebacks 0.768016 # Average percentage of cache occupancy | 1074system.cpu.l2cache.tags.occ_blocks::writebacks 50201.970335 # Average occupied blocks per requestor 1075system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.012829 # Average occupied blocks per requestor 1076system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor 1077system.cpu.l2cache.tags.occ_blocks::cpu.inst 3236.502324 # Average occupied blocks per requestor 1078system.cpu.l2cache.tags.occ_blocks::cpu.data 11269.615072 # Average occupied blocks per requestor 1079system.cpu.l2cache.tags.occ_percent::writebacks 0.766021 # Average percentage of cache occupancy |
| 1063system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 1064system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 1080system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 1081system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 1065system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049144 # Average percentage of cache occupancy 1066system.cpu.l2cache.tags.occ_percent::cpu.data 0.170785 # Average percentage of cache occupancy 1067system.cpu.l2cache.tags.occ_percent::total 0.987948 # Average percentage of cache occupancy 1068system.cpu.l2cache.tags.occ_task_id_blocks::1024 64743 # Occupied blocks per task id 1069system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 1070system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id 1071system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2897 # Occupied blocks per task id 1072system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4651 # Occupied blocks per task id 1073system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57056 # Occupied blocks per task id 1074system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987900 # Percentage of cache occupancy per task id 1075system.cpu.l2cache.tags.tag_accesses 32212608 # Number of tag accesses 1076system.cpu.l2cache.tags.data_accesses 32212608 # Number of data accesses 1077system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6366 # number of ReadReq hits 1078system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2878 # number of ReadReq hits 1079system.cpu.l2cache.ReadReq_hits::cpu.inst 782107 # number of ReadReq hits 1080system.cpu.l2cache.ReadReq_hits::cpu.data 1278785 # number of ReadReq hits 1081system.cpu.l2cache.ReadReq_hits::total 2070136 # number of ReadReq hits 1082system.cpu.l2cache.Writeback_hits::writebacks 1541433 # number of Writeback hits 1083system.cpu.l2cache.Writeback_hits::total 1541433 # number of Writeback hits 1084system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits 1085system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits 1086system.cpu.l2cache.ReadExReq_hits::cpu.data 199468 # number of ReadExReq hits 1087system.cpu.l2cache.ReadExReq_hits::total 199468 # number of ReadExReq hits 1088system.cpu.l2cache.demand_hits::cpu.dtb.walker 6366 # number of demand (read+write) hits 1089system.cpu.l2cache.demand_hits::cpu.itb.walker 2878 # number of demand (read+write) hits 1090system.cpu.l2cache.demand_hits::cpu.inst 782107 # number of demand (read+write) hits 1091system.cpu.l2cache.demand_hits::cpu.data 1478253 # number of demand (read+write) hits 1092system.cpu.l2cache.demand_hits::total 2269604 # number of demand (read+write) hits 1093system.cpu.l2cache.overall_hits::cpu.dtb.walker 6366 # number of overall hits 1094system.cpu.l2cache.overall_hits::cpu.itb.walker 2878 # number of overall hits 1095system.cpu.l2cache.overall_hits::cpu.inst 782107 # number of overall hits 1096system.cpu.l2cache.overall_hits::cpu.data 1478253 # number of overall hits 1097system.cpu.l2cache.overall_hits::total 2269604 # number of overall hits 1098system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses | 1082system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049385 # Average percentage of cache occupancy 1083system.cpu.l2cache.tags.occ_percent::cpu.data 0.171961 # Average percentage of cache occupancy 1084system.cpu.l2cache.tags.occ_percent::total 0.987369 # Average percentage of cache occupancy 1085system.cpu.l2cache.tags.occ_task_id_blocks::1024 64653 # Occupied blocks per task id 1086system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 1087system.cpu.l2cache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id 1088system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id 1089system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4737 # Occupied blocks per task id 1090system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56942 # Occupied blocks per task id 1091system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986526 # Percentage of cache occupancy per task id 1092system.cpu.l2cache.tags.tag_accesses 32181921 # Number of tag accesses 1093system.cpu.l2cache.tags.data_accesses 32181921 # Number of data accesses 1094system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6616 # number of ReadReq hits 1095system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2866 # number of ReadReq hits 1096system.cpu.l2cache.ReadReq_hits::cpu.inst 777686 # number of ReadReq hits 1097system.cpu.l2cache.ReadReq_hits::cpu.data 1279269 # number of ReadReq hits 1098system.cpu.l2cache.ReadReq_hits::total 2066437 # number of ReadReq hits 1099system.cpu.l2cache.Writeback_hits::writebacks 1541461 # number of Writeback hits 1100system.cpu.l2cache.Writeback_hits::total 1541461 # number of Writeback hits 1101system.cpu.l2cache.UpgradeReq_hits::cpu.data 312 # number of UpgradeReq hits 1102system.cpu.l2cache.UpgradeReq_hits::total 312 # number of UpgradeReq hits 1103system.cpu.l2cache.ReadExReq_hits::cpu.data 199613 # number of ReadExReq hits 1104system.cpu.l2cache.ReadExReq_hits::total 199613 # number of ReadExReq hits 1105system.cpu.l2cache.demand_hits::cpu.dtb.walker 6616 # number of demand (read+write) hits 1106system.cpu.l2cache.demand_hits::cpu.itb.walker 2866 # number of demand (read+write) hits 1107system.cpu.l2cache.demand_hits::cpu.inst 777686 # number of demand (read+write) hits 1108system.cpu.l2cache.demand_hits::cpu.data 1478882 # number of demand (read+write) hits 1109system.cpu.l2cache.demand_hits::total 2266050 # number of demand (read+write) hits 1110system.cpu.l2cache.overall_hits::cpu.dtb.walker 6616 # number of overall hits 1111system.cpu.l2cache.overall_hits::cpu.itb.walker 2866 # number of overall hits 1112system.cpu.l2cache.overall_hits::cpu.inst 777686 # number of overall hits 1113system.cpu.l2cache.overall_hits::cpu.data 1478882 # number of overall hits 1114system.cpu.l2cache.overall_hits::total 2266050 # number of overall hits 1115system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses |
| 1099system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses | 1116system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses |
| 1100system.cpu.l2cache.ReadReq_misses::cpu.inst 12963 # number of ReadReq misses 1101system.cpu.l2cache.ReadReq_misses::cpu.data 28642 # number of ReadReq misses 1102system.cpu.l2cache.ReadReq_misses::total 41611 # number of ReadReq misses 1103system.cpu.l2cache.UpgradeReq_misses::cpu.data 1325 # number of UpgradeReq misses 1104system.cpu.l2cache.UpgradeReq_misses::total 1325 # number of UpgradeReq misses 1105system.cpu.l2cache.ReadExReq_misses::cpu.data 113677 # number of ReadExReq misses 1106system.cpu.l2cache.ReadExReq_misses::total 113677 # number of ReadExReq misses 1107system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses | 1117system.cpu.l2cache.ReadReq_misses::cpu.inst 12929 # number of ReadReq misses 1118system.cpu.l2cache.ReadReq_misses::cpu.data 28637 # number of ReadReq misses 1119system.cpu.l2cache.ReadReq_misses::total 41573 # number of ReadReq misses 1120system.cpu.l2cache.UpgradeReq_misses::cpu.data 1319 # number of UpgradeReq misses 1121system.cpu.l2cache.UpgradeReq_misses::total 1319 # number of UpgradeReq misses 1122system.cpu.l2cache.ReadExReq_misses::cpu.data 113455 # number of ReadExReq misses 1123system.cpu.l2cache.ReadExReq_misses::total 113455 # number of ReadExReq misses 1124system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses |
| 1108system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses | 1125system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses |
| 1109system.cpu.l2cache.demand_misses::cpu.inst 12963 # number of demand (read+write) misses 1110system.cpu.l2cache.demand_misses::cpu.data 142319 # number of demand (read+write) misses 1111system.cpu.l2cache.demand_misses::total 155288 # number of demand (read+write) misses 1112system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses | 1126system.cpu.l2cache.demand_misses::cpu.inst 12929 # number of demand (read+write) misses 1127system.cpu.l2cache.demand_misses::cpu.data 142092 # number of demand (read+write) misses 1128system.cpu.l2cache.demand_misses::total 155028 # number of demand (read+write) misses 1129system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses |
| 1113system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses | 1130system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses |
| 1114system.cpu.l2cache.overall_misses::cpu.inst 12963 # number of overall misses 1115system.cpu.l2cache.overall_misses::cpu.data 142319 # number of overall misses 1116system.cpu.l2cache.overall_misses::total 155288 # number of overall misses 1117system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 61250 # number of ReadReq miss cycles 1118system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 350750 # number of ReadReq miss cycles 1119system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 946969000 # number of ReadReq miss cycles 1120system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2148496250 # number of ReadReq miss cycles 1121system.cpu.l2cache.ReadReq_miss_latency::total 3095877250 # number of ReadReq miss cycles 1122system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 14947864 # number of UpgradeReq miss cycles 1123system.cpu.l2cache.UpgradeReq_miss_latency::total 14947864 # number of UpgradeReq miss cycles 1124system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7865192973 # number of ReadExReq miss cycles 1125system.cpu.l2cache.ReadExReq_miss_latency::total 7865192973 # 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number of overall miss cycles 1136system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6367 # number of ReadReq accesses(hits+misses) 1137system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2883 # number of ReadReq accesses(hits+misses) 1138system.cpu.l2cache.ReadReq_accesses::cpu.inst 795070 # number of ReadReq accesses(hits+misses) 1139system.cpu.l2cache.ReadReq_accesses::cpu.data 1307427 # number of ReadReq accesses(hits+misses) 1140system.cpu.l2cache.ReadReq_accesses::total 2111747 # number of ReadReq accesses(hits+misses) 1141system.cpu.l2cache.Writeback_accesses::writebacks 1541433 # number of Writeback accesses(hits+misses) 1142system.cpu.l2cache.Writeback_accesses::total 1541433 # number of Writeback accesses(hits+misses) 1143system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1639 # number of UpgradeReq accesses(hits+misses) 1144system.cpu.l2cache.UpgradeReq_accesses::total 1639 # number of UpgradeReq accesses(hits+misses) 1145system.cpu.l2cache.ReadExReq_accesses::cpu.data 313145 # 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average overall miss latency 1209system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73832.972388 # average overall miss latency 1210system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70884.470801 # average overall miss latency 1211system.cpu.l2cache.overall_avg_miss_latency::total 71130.582701 # average overall miss latency |
| 1195system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1196system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1197system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1198system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1199system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1200system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1201system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1202system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 1212system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1213system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1214system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1215system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1216system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1217system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1218system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1219system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 1203system.cpu.l2cache.writebacks::writebacks 80285 # number of writebacks 1204system.cpu.l2cache.writebacks::total 80285 # number of writebacks 1205system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses | 1220system.cpu.l2cache.writebacks::writebacks 80343 # number of writebacks 1221system.cpu.l2cache.writebacks::total 80343 # number of writebacks 1222system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2 # number of ReadReq MSHR misses |
| 1206system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses | 1223system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses |
| 1207system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12963 # number of ReadReq MSHR misses 1208system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28642 # number of ReadReq MSHR misses 1209system.cpu.l2cache.ReadReq_mshr_misses::total 41611 # number of ReadReq MSHR misses 1210system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1325 # number of UpgradeReq MSHR misses 1211system.cpu.l2cache.UpgradeReq_mshr_misses::total 1325 # number of UpgradeReq MSHR misses 1212system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113677 # number of ReadExReq MSHR misses 1213system.cpu.l2cache.ReadExReq_mshr_misses::total 113677 # number of ReadExReq MSHR misses 1214system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses | 1224system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12929 # number of ReadReq MSHR misses 1225system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28637 # number of ReadReq MSHR misses 1226system.cpu.l2cache.ReadReq_mshr_misses::total 41573 # number of ReadReq MSHR misses 1227system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1319 # number of UpgradeReq MSHR misses 1228system.cpu.l2cache.UpgradeReq_mshr_misses::total 1319 # number of UpgradeReq MSHR misses 1229system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113455 # number of ReadExReq MSHR misses 1230system.cpu.l2cache.ReadExReq_mshr_misses::total 113455 # number of ReadExReq MSHR misses 1231system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2 # number of demand (read+write) MSHR misses |
| 1215system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses | 1232system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses |
| 1216system.cpu.l2cache.demand_mshr_misses::cpu.inst 12963 # number of demand (read+write) MSHR misses 1217system.cpu.l2cache.demand_mshr_misses::cpu.data 142319 # number of demand (read+write) MSHR misses 1218system.cpu.l2cache.demand_mshr_misses::total 155288 # number of demand (read+write) MSHR misses 1219system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses | 1233system.cpu.l2cache.demand_mshr_misses::cpu.inst 12929 # number of demand (read+write) MSHR misses 1234system.cpu.l2cache.demand_mshr_misses::cpu.data 142092 # number of demand (read+write) MSHR misses 1235system.cpu.l2cache.demand_mshr_misses::total 155028 # number of demand (read+write) MSHR misses 1236system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2 # number of overall MSHR misses |
| 1220system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses | 1237system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses |
| 1221system.cpu.l2cache.overall_mshr_misses::cpu.inst 12963 # number of overall MSHR misses 1222system.cpu.l2cache.overall_mshr_misses::cpu.data 142319 # number of overall MSHR misses 1223system.cpu.l2cache.overall_mshr_misses::total 155288 # number of overall MSHR misses 1224system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 48750 # number of ReadReq MSHR miss cycles 1225system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287750 # number of ReadReq MSHR miss cycles 1226system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 784590000 # number of ReadReq MSHR miss cycles 1227system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1789530750 # number of ReadReq MSHR miss cycles 1228system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2574457250 # number of ReadReq MSHR miss cycles 1229system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13262825 # number of UpgradeReq MSHR miss cycles 1230system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13262825 # number of UpgradeReq MSHR miss cycles 1231system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6444689027 # number of ReadExReq MSHR miss cycles 1232system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6444689027 # number of ReadExReq MSHR miss cycles 1233system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 48750 # number of demand (read+write) MSHR miss cycles 1234system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles 1235system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 784590000 # number of demand (read+write) MSHR miss cycles 1236system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8234219777 # number of demand (read+write) MSHR miss cycles 1237system.cpu.l2cache.demand_mshr_miss_latency::total 9019146277 # number of demand (read+write) MSHR miss cycles 1238system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 48750 # number of overall MSHR miss cycles 1239system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles 1240system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 784590000 # number of overall MSHR miss cycles 1241system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8234219777 # number of overall MSHR miss cycles 1242system.cpu.l2cache.overall_mshr_miss_latency::total 9019146277 # number of overall MSHR miss cycles | 1238system.cpu.l2cache.overall_mshr_misses::cpu.inst 12929 # number of overall MSHR misses 1239system.cpu.l2cache.overall_mshr_misses::cpu.data 142092 # number of overall MSHR misses 1240system.cpu.l2cache.overall_mshr_misses::total 155028 # number of overall MSHR misses 1241system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 138750 # number of ReadReq MSHR miss cycles 1242system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301500 # number of ReadReq MSHR miss cycles 1243system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 792612500 # number of ReadReq MSHR miss cycles 1244system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1813424750 # number of ReadReq MSHR miss cycles 1245system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2606477500 # number of ReadReq MSHR miss cycles 1246system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13194319 # number of UpgradeReq MSHR miss cycles 1247system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13194319 # number of UpgradeReq MSHR miss cycles 1248system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6481465525 # number of ReadExReq MSHR miss cycles 1249system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6481465525 # number of ReadExReq MSHR miss cycles 1250system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 138750 # number of demand (read+write) MSHR miss cycles 1251system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301500 # number of demand (read+write) MSHR miss cycles 1252system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 792612500 # number of demand (read+write) MSHR miss cycles 1253system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8294890275 # number of demand (read+write) MSHR miss cycles 1254system.cpu.l2cache.demand_mshr_miss_latency::total 9087943025 # number of demand (read+write) MSHR miss cycles 1255system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 138750 # number of overall MSHR miss cycles 1256system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles 1257system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 792612500 # number of overall MSHR miss cycles 1258system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8294890275 # number of overall MSHR miss cycles 1259system.cpu.l2cache.overall_mshr_miss_latency::total 9087943025 # number of overall MSHR miss cycles |
| 1243system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655868500 # number of ReadReq MSHR uncacheable cycles 1244system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655868500 # number of ReadReq MSHR uncacheable cycles 1245system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370634000 # number of WriteReq MSHR uncacheable cycles 1246system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370634000 # number of WriteReq MSHR uncacheable cycles 1247system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026502500 # number of overall MSHR uncacheable cycles 1248system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026502500 # number of overall MSHR uncacheable cycles | 1260system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655868500 # number of ReadReq MSHR uncacheable cycles 1261system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655868500 # number of ReadReq MSHR uncacheable cycles 1262system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370634000 # number of WriteReq MSHR uncacheable cycles 1263system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370634000 # number of WriteReq MSHR uncacheable cycles 1264system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026502500 # number of overall MSHR uncacheable cycles 1265system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026502500 # number of overall MSHR uncacheable cycles |
| 1249system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses 1250system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for ReadReq accesses 1251system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for ReadReq accesses 1252system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021907 # mshr miss rate for ReadReq accesses 1253system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019705 # mshr miss rate for ReadReq accesses 1254system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808420 # mshr miss rate for UpgradeReq accesses 1255system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808420 # mshr miss rate for UpgradeReq accesses 1256system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.363017 # mshr miss rate for ReadExReq accesses 1257system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.363017 # mshr miss rate for ReadExReq accesses 1258system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses 1259system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for demand accesses 1260system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for demand accesses 1261system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for demand accesses 1262system.cpu.l2cache.demand_mshr_miss_rate::total 0.064039 # mshr miss rate for demand accesses 1263system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses 1264system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for overall accesses 1265system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for overall accesses 1266system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for overall accesses 1267system.cpu.l2cache.overall_mshr_miss_rate::total 0.064039 # mshr miss rate for overall accesses 1268system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average ReadReq mshr miss latency 1269system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency 1270system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60525.341356 # average ReadReq mshr miss latency 1271system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.252496 # average ReadReq mshr miss latency 1272system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61869.631828 # average ReadReq mshr miss latency 1273system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.679245 # average UpgradeReq mshr miss latency 1274system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.679245 # average UpgradeReq mshr miss latency 1275system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56692.990024 # average ReadExReq mshr miss latency 1276system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56692.990024 # average ReadExReq mshr miss latency 1277system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency 1278system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency 1279system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency 1280system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency 1281system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency 1282system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency 1283system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency 1284system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency 1285system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency 1286system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency | 1266system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for ReadReq accesses 1267system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for ReadReq accesses 1268system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for ReadReq accesses 1269system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021895 # mshr miss rate for ReadReq accesses 1270system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019721 # mshr miss rate for ReadReq accesses 1271system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808706 # mshr miss rate for UpgradeReq accesses 1272system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808706 # mshr miss rate for UpgradeReq accesses 1273system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362397 # mshr miss rate for ReadExReq accesses 1274system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362397 # mshr miss rate for ReadExReq accesses 1275system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for demand accesses 1276system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for demand accesses 1277system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for demand accesses 1278system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for demand accesses 1279system.cpu.l2cache.demand_mshr_miss_rate::total 0.064033 # mshr miss rate for demand accesses 1280system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for overall accesses 1281system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for overall accesses 1282system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for overall accesses 1283system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for overall accesses 1284system.cpu.l2cache.overall_mshr_miss_rate::total 0.064033 # mshr miss rate for overall accesses 1285system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average ReadReq mshr miss latency 1286system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency 1287system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61305.011989 # average ReadReq mshr miss latency 1288system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63324.536439 # average ReadReq mshr miss latency 1289system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62696.401511 # average ReadReq mshr miss latency 1290system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.274450 # average UpgradeReq mshr miss latency 1291system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.274450 # average UpgradeReq mshr miss latency 1292system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57128.073025 # average ReadExReq mshr miss latency 1293system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57128.073025 # average ReadExReq mshr miss latency 1294system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency 1295system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency 1296system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency 1297system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency 1298system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency 1299system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency 1300system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency 1301system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency 1302system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency 1303system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency |
| 1287system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1288system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1289system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1290system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1291system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1292system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1293system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1294 1295---------- End Simulation Statistics ---------- | 1304system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1305system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1306system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1307system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1308system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1309system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1310system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1311 1312---------- End Simulation Statistics ---------- |