1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.191766 # Number of seconds simulated 4sim_ticks 5191766314000 # Number of ticks simulated 5final_tick 5191766314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 672863 # Simulator instruction rate (inst/s) 8host_op_rate 1291533 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25283717995 # Simulator tick rate (ticks/s) 10host_mem_usage 405876 # Number of bytes of host memory used 11host_seconds 205.34 # Real time elapsed on the host 12sim_insts 138165780 # Number of instructions simulated 13sim_ops 265203824 # Number of ops (including micro ops) simulated |
14system.physmem.bytes_read::pc.south_bridge.ide 2891072 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.inst 821248 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8939328 # Number of bytes read from this memory 18system.physmem.bytes_read::total 12651968 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 821248 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 821248 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 8080768 # Number of bytes written to this memory --- 16 unchanged lines hidden (view full) --- 38system.physmem.bw_write::total 1556458 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 1556458 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::pc.south_bridge.ide 556857 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.inst 158183 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::cpu.data 1721828 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::total 3993388 # Total bandwidth to/from this memory (bytes/s) 45system.l2c.replacements 86221 # number of replacements |
46system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use 47system.l2c.total_refs 3491043 # Total number of references to valid blocks. |
48system.l2c.sampled_refs 150947 # Sample count of references to valid blocks. |
49system.l2c.avg_refs 23.127608 # Average number of references to valid blocks. |
50system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
51system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor |
52system.l2c.occ_blocks::cpu.itb.walker 0.141198 # Average occupied blocks per requestor |
53system.l2c.occ_blocks::cpu.inst 3484.481205 # Average occupied blocks per requestor 54system.l2c.occ_blocks::cpu.data 11111.678558 # Average occupied blocks per requestor |
55system.l2c.occ_percent::writebacks 0.765539 # Average percentage of cache occupancy 56system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 57system.l2c.occ_percent::cpu.inst 0.053169 # Average percentage of cache occupancy 58system.l2c.occ_percent::cpu.data 0.169551 # Average percentage of cache occupancy 59system.l2c.occ_percent::total 0.988261 # Average percentage of cache occupancy 60system.l2c.ReadReq_hits::cpu.dtb.walker 6306 # number of ReadReq hits 61system.l2c.ReadReq_hits::cpu.itb.walker 2757 # number of ReadReq hits 62system.l2c.ReadReq_hits::cpu.inst 777565 # number of ReadReq hits |
63system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits 64system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits 65system.l2c.Writeback_hits::writebacks 1542135 # number of Writeback hits 66system.l2c.Writeback_hits::total 1542135 # number of Writeback hits |
67system.l2c.UpgradeReq_hits::cpu.data 319 # number of UpgradeReq hits 68system.l2c.UpgradeReq_hits::total 319 # number of UpgradeReq hits 69system.l2c.ReadExReq_hits::cpu.data 200451 # number of ReadExReq hits 70system.l2c.ReadExReq_hits::total 200451 # number of ReadExReq hits 71system.l2c.demand_hits::cpu.dtb.walker 6306 # number of demand (read+write) hits 72system.l2c.demand_hits::cpu.itb.walker 2757 # number of demand (read+write) hits 73system.l2c.demand_hits::cpu.inst 777565 # number of demand (read+write) hits |
74system.l2c.demand_hits::cpu.data 1479802 # number of demand (read+write) hits 75system.l2c.demand_hits::total 2266430 # number of demand (read+write) hits |
76system.l2c.overall_hits::cpu.dtb.walker 6306 # number of overall hits 77system.l2c.overall_hits::cpu.itb.walker 2757 # number of overall hits 78system.l2c.overall_hits::cpu.inst 777565 # number of overall hits |
79system.l2c.overall_hits::cpu.data 1479802 # number of overall hits 80system.l2c.overall_hits::total 2266430 # number of overall hits |
81system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 82system.l2c.ReadReq_misses::cpu.inst 12833 # number of ReadReq misses 83system.l2c.ReadReq_misses::cpu.data 28373 # number of ReadReq misses 84system.l2c.ReadReq_misses::total 41211 # number of ReadReq misses 85system.l2c.UpgradeReq_misses::cpu.data 1346 # number of UpgradeReq misses 86system.l2c.UpgradeReq_misses::total 1346 # number of UpgradeReq misses 87system.l2c.ReadExReq_misses::cpu.data 112235 # number of ReadExReq misses 88system.l2c.ReadExReq_misses::total 112235 # number of ReadExReq misses --- 19 unchanged lines hidden (view full) --- 108system.l2c.demand_miss_latency::total 7997111500 # number of demand (read+write) miss cycles 109system.l2c.overall_miss_latency::cpu.itb.walker 260000 # number of overall miss cycles 110system.l2c.overall_miss_latency::cpu.inst 667948500 # number of overall miss cycles 111system.l2c.overall_miss_latency::cpu.data 7328903000 # number of overall miss cycles 112system.l2c.overall_miss_latency::total 7997111500 # number of overall miss cycles 113system.l2c.ReadReq_accesses::cpu.dtb.walker 6306 # number of ReadReq accesses(hits+misses) 114system.l2c.ReadReq_accesses::cpu.itb.walker 2762 # number of ReadReq accesses(hits+misses) 115system.l2c.ReadReq_accesses::cpu.inst 790398 # number of ReadReq accesses(hits+misses) |
116system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses) 117system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses) 118system.l2c.Writeback_accesses::writebacks 1542135 # number of Writeback accesses(hits+misses) 119system.l2c.Writeback_accesses::total 1542135 # number of Writeback accesses(hits+misses) |
120system.l2c.UpgradeReq_accesses::cpu.data 1665 # number of UpgradeReq accesses(hits+misses) 121system.l2c.UpgradeReq_accesses::total 1665 # number of UpgradeReq accesses(hits+misses) 122system.l2c.ReadExReq_accesses::cpu.data 312686 # number of ReadExReq accesses(hits+misses) 123system.l2c.ReadExReq_accesses::total 312686 # number of ReadExReq accesses(hits+misses) 124system.l2c.demand_accesses::cpu.dtb.walker 6306 # number of demand (read+write) accesses 125system.l2c.demand_accesses::cpu.itb.walker 2762 # number of demand (read+write) accesses 126system.l2c.demand_accesses::cpu.inst 790398 # number of demand (read+write) accesses |
127system.l2c.demand_accesses::cpu.data 1620410 # number of demand (read+write) accesses 128system.l2c.demand_accesses::total 2419876 # number of demand (read+write) accesses |
129system.l2c.overall_accesses::cpu.dtb.walker 6306 # number of overall (read+write) accesses 130system.l2c.overall_accesses::cpu.itb.walker 2762 # number of overall (read+write) accesses 131system.l2c.overall_accesses::cpu.inst 790398 # number of overall (read+write) accesses |
132system.l2c.overall_accesses::cpu.data 1620410 # number of overall (read+write) accesses 133system.l2c.overall_accesses::total 2419876 # number of overall (read+write) accesses |
134system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001810 # miss rate for ReadReq accesses 135system.l2c.ReadReq_miss_rate::cpu.inst 0.016236 # miss rate for ReadReq accesses 136system.l2c.ReadReq_miss_rate::cpu.data 0.021696 # miss rate for ReadReq accesses 137system.l2c.ReadReq_miss_rate::total 0.019557 # miss rate for ReadReq accesses 138system.l2c.UpgradeReq_miss_rate::cpu.data 0.808408 # miss rate for UpgradeReq accesses 139system.l2c.UpgradeReq_miss_rate::total 0.808408 # miss rate for UpgradeReq accesses 140system.l2c.ReadExReq_miss_rate::cpu.data 0.358938 # miss rate for ReadExReq accesses 141system.l2c.ReadExReq_miss_rate::total 0.358938 # miss rate for ReadExReq accesses --- 210 unchanged lines hidden (view full) --- 352system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 353system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 354system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 355system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 356system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 357system.cpu.numCycles 10383532628 # number of cpu cycles simulated 358system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 359system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
360system.cpu.committedInsts 138165780 # Number of instructions committed 361system.cpu.committedOps 265203824 # Number of ops (including micro ops) committed 362system.cpu.num_int_alu_accesses 249613019 # Number of integer alu accesses |
363system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 364system.cpu.num_func_calls 0 # number of times a function call or return occured |
365system.cpu.num_conditional_control_insts 24887741 # number of instructions that are conditional controls 366system.cpu.num_int_insts 249613019 # number of integer instructions |
367system.cpu.num_fp_insts 0 # number of float instructions |
368system.cpu.num_int_register_reads 778264795 # number of times the integer registers were read 369system.cpu.num_int_register_writes 423017346 # number of times the integer registers were written |
370system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 371system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
372system.cpu.num_mem_refs 23180616 # number of memory refs 373system.cpu.num_load_insts 14822216 # Number of load instructions 374system.cpu.num_store_insts 8358400 # Number of store instructions 375system.cpu.num_idle_cycles 9771874926.286118 # Number of idle cycles 376system.cpu.num_busy_cycles 611657701.713882 # Number of busy cycles |
377system.cpu.not_idle_fraction 0.058907 # Percentage of non-idle cycles 378system.cpu.idle_fraction 0.941093 # Percentage of idle cycles 379system.cpu.kern.inst.arm 0 # number of arm instructions executed 380system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 381system.cpu.icache.replacements 789892 # number of replacements 382system.cpu.icache.tagsinuse 510.351457 # Cycle average of tags in use |
383system.cpu.icache.total_refs 158472876 # Total number of references to valid blocks. |
384system.cpu.icache.sampled_refs 790404 # Sample count of references to valid blocks. |
385system.cpu.icache.avg_refs 200.496045 # Average number of references to valid blocks. 386system.cpu.icache.warmup_cycle 160421909000 # Cycle when the warmup percentage was hit. |
387system.cpu.icache.occ_blocks::cpu.inst 510.351457 # Average occupied blocks per requestor 388system.cpu.icache.occ_percent::cpu.inst 0.996780 # Average percentage of cache occupancy 389system.cpu.icache.occ_percent::total 0.996780 # Average percentage of cache occupancy |
390system.cpu.icache.ReadReq_hits::cpu.inst 158472876 # number of ReadReq hits 391system.cpu.icache.ReadReq_hits::total 158472876 # number of ReadReq hits 392system.cpu.icache.demand_hits::cpu.inst 158472876 # number of demand (read+write) hits 393system.cpu.icache.demand_hits::total 158472876 # number of demand (read+write) hits 394system.cpu.icache.overall_hits::cpu.inst 158472876 # number of overall hits 395system.cpu.icache.overall_hits::total 158472876 # number of overall hits |
396system.cpu.icache.ReadReq_misses::cpu.inst 790411 # number of ReadReq misses 397system.cpu.icache.ReadReq_misses::total 790411 # number of ReadReq misses 398system.cpu.icache.demand_misses::cpu.inst 790411 # number of demand (read+write) misses 399system.cpu.icache.demand_misses::total 790411 # number of demand (read+write) misses 400system.cpu.icache.overall_misses::cpu.inst 790411 # number of overall misses 401system.cpu.icache.overall_misses::total 790411 # number of overall misses |
402system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780909500 # number of ReadReq miss cycles 403system.cpu.icache.ReadReq_miss_latency::total 11780909500 # number of ReadReq miss cycles 404system.cpu.icache.demand_miss_latency::cpu.inst 11780909500 # number of demand (read+write) miss cycles 405system.cpu.icache.demand_miss_latency::total 11780909500 # number of demand (read+write) miss cycles 406system.cpu.icache.overall_miss_latency::cpu.inst 11780909500 # number of overall miss cycles 407system.cpu.icache.overall_miss_latency::total 11780909500 # number of overall miss cycles 408system.cpu.icache.ReadReq_accesses::cpu.inst 159263287 # number of ReadReq accesses(hits+misses) 409system.cpu.icache.ReadReq_accesses::total 159263287 # number of ReadReq accesses(hits+misses) 410system.cpu.icache.demand_accesses::cpu.inst 159263287 # number of demand (read+write) accesses 411system.cpu.icache.demand_accesses::total 159263287 # number of demand (read+write) accesses 412system.cpu.icache.overall_accesses::cpu.inst 159263287 # number of overall (read+write) accesses 413system.cpu.icache.overall_accesses::total 159263287 # number of overall (read+write) accesses |
414system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004963 # miss rate for ReadReq accesses 415system.cpu.icache.ReadReq_miss_rate::total 0.004963 # miss rate for ReadReq accesses 416system.cpu.icache.demand_miss_rate::cpu.inst 0.004963 # miss rate for demand accesses 417system.cpu.icache.demand_miss_rate::total 0.004963 # miss rate for demand accesses 418system.cpu.icache.overall_miss_rate::cpu.inst 0.004963 # miss rate for overall accesses 419system.cpu.icache.overall_miss_rate::total 0.004963 # miss rate for overall accesses |
420system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.789407 # average ReadReq miss latency 421system.cpu.icache.ReadReq_avg_miss_latency::total 14904.789407 # average ReadReq miss latency 422system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency 423system.cpu.icache.demand_avg_miss_latency::total 14904.789407 # average overall miss latency 424system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency 425system.cpu.icache.overall_avg_miss_latency::total 14904.789407 # average overall miss latency |
426system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 427system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 428system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 429system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 430system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 431system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 432system.cpu.icache.fast_writes 0 # number of fast writes performed 433system.cpu.icache.cache_copies 0 # number of cache copies performed 434system.cpu.icache.writebacks::writebacks 806 # number of writebacks 435system.cpu.icache.writebacks::total 806 # number of writebacks 436system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790411 # number of ReadReq MSHR misses 437system.cpu.icache.ReadReq_mshr_misses::total 790411 # number of ReadReq MSHR misses 438system.cpu.icache.demand_mshr_misses::cpu.inst 790411 # number of demand (read+write) MSHR misses 439system.cpu.icache.demand_mshr_misses::total 790411 # number of demand (read+write) MSHR misses 440system.cpu.icache.overall_mshr_misses::cpu.inst 790411 # number of overall MSHR misses 441system.cpu.icache.overall_mshr_misses::total 790411 # number of overall MSHR misses |
442system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408658500 # number of ReadReq MSHR miss cycles 443system.cpu.icache.ReadReq_mshr_miss_latency::total 9408658500 # number of ReadReq MSHR miss cycles 444system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9408658500 # number of demand (read+write) MSHR miss cycles 445system.cpu.icache.demand_mshr_miss_latency::total 9408658500 # number of demand (read+write) MSHR miss cycles 446system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9408658500 # number of overall MSHR miss cycles 447system.cpu.icache.overall_mshr_miss_latency::total 9408658500 # number of overall MSHR miss cycles |
448system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for ReadReq accesses 449system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004963 # mshr miss rate for ReadReq accesses 450system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for demand accesses 451system.cpu.icache.demand_mshr_miss_rate::total 0.004963 # mshr miss rate for demand accesses 452system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004963 # mshr miss rate for overall accesses 453system.cpu.icache.overall_mshr_miss_rate::total 0.004963 # mshr miss rate for overall accesses |
454system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.501469 # average ReadReq mshr miss latency 455system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.501469 # average ReadReq mshr miss latency 456system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency 457system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency 458system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency 459system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency |
460system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 461system.cpu.itb_walker_cache.replacements 3403 # number of replacements 462system.cpu.itb_walker_cache.tagsinuse 3.070913 # Cycle average of tags in use 463system.cpu.itb_walker_cache.total_refs 8040 # Total number of references to valid blocks. 464system.cpu.itb_walker_cache.sampled_refs 3415 # Sample count of references to valid blocks. 465system.cpu.itb_walker_cache.avg_refs 2.354319 # Average number of references to valid blocks. |
466system.cpu.itb_walker_cache.warmup_cycle 5164836918000 # Cycle when the warmup percentage was hit. |
467system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070913 # Average occupied blocks per requestor 468system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191932 # Average percentage of cache occupancy 469system.cpu.itb_walker_cache.occ_percent::total 0.191932 # Average percentage of cache occupancy 470system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8060 # number of ReadReq hits 471system.cpu.itb_walker_cache.ReadReq_hits::total 8060 # number of ReadReq hits 472system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 473system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 474system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8062 # number of demand (read+write) hits --- 67 unchanged lines hidden (view full) --- 542system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8818.565401 # average overall mshr miss latency 543system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8818.565401 # average overall mshr miss latency 544system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 545system.cpu.dtb_walker_cache.replacements 7529 # number of replacements 546system.cpu.dtb_walker_cache.tagsinuse 5.053120 # Cycle average of tags in use 547system.cpu.dtb_walker_cache.total_refs 13331 # Total number of references to valid blocks. 548system.cpu.dtb_walker_cache.sampled_refs 7543 # Sample count of references to valid blocks. 549system.cpu.dtb_walker_cache.avg_refs 1.767334 # Average number of references to valid blocks. |
550system.cpu.dtb_walker_cache.warmup_cycle 5161009077000 # Cycle when the warmup percentage was hit. |
551system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.053120 # Average occupied blocks per requestor 552system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315820 # Average percentage of cache occupancy 553system.cpu.dtb_walker_cache.occ_percent::total 0.315820 # Average percentage of cache occupancy 554system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13332 # number of ReadReq hits 555system.cpu.dtb_walker_cache.ReadReq_hits::total 13332 # number of ReadReq hits 556system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13332 # number of demand (read+write) hits 557system.cpu.dtb_walker_cache.demand_hits::total 13332 # number of demand (read+write) hits 558system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13332 # number of overall hits --- 58 unchanged lines hidden (view full) --- 617system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395676 # mshr miss rate for overall accesses 618system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average ReadReq mshr miss latency 619system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9861.152480 # average ReadReq mshr miss latency 620system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency 621system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency 622system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9861.152480 # average overall mshr miss latency 623system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9861.152480 # average overall mshr miss latency 624system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
625system.cpu.dcache.replacements 1620698 # number of replacements |
626system.cpu.dcache.tagsinuse 511.997463 # Cycle average of tags in use |
627system.cpu.dcache.total_refs 20024816 # Total number of references to valid blocks. 628system.cpu.dcache.sampled_refs 1621210 # Sample count of references to valid blocks. 629system.cpu.dcache.avg_refs 12.351772 # Average number of references to valid blocks. |
630system.cpu.dcache.warmup_cycle 45838000 # Cycle when the warmup percentage was hit. 631system.cpu.dcache.occ_blocks::cpu.data 511.997463 # Average occupied blocks per requestor 632system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy 633system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy |
634system.cpu.dcache.ReadReq_hits::cpu.data 11989143 # number of ReadReq hits 635system.cpu.dcache.ReadReq_hits::total 11989143 # number of ReadReq hits 636system.cpu.dcache.WriteReq_hits::cpu.data 8033492 # number of WriteReq hits 637system.cpu.dcache.WriteReq_hits::total 8033492 # number of WriteReq hits 638system.cpu.dcache.demand_hits::cpu.data 20022635 # number of demand (read+write) hits 639system.cpu.dcache.demand_hits::total 20022635 # number of demand (read+write) hits 640system.cpu.dcache.overall_hits::cpu.data 20022635 # number of overall hits 641system.cpu.dcache.overall_hits::total 20022635 # number of overall hits 642system.cpu.dcache.ReadReq_misses::cpu.data 1308550 # number of ReadReq misses 643system.cpu.dcache.ReadReq_misses::total 1308550 # number of ReadReq misses |
644system.cpu.dcache.WriteReq_misses::cpu.data 314872 # number of WriteReq misses 645system.cpu.dcache.WriteReq_misses::total 314872 # number of WriteReq misses |
646system.cpu.dcache.demand_misses::cpu.data 1623422 # number of demand (read+write) misses 647system.cpu.dcache.demand_misses::total 1623422 # number of demand (read+write) misses 648system.cpu.dcache.overall_misses::cpu.data 1623422 # number of overall misses 649system.cpu.dcache.overall_misses::total 1623422 # number of overall misses 650system.cpu.dcache.ReadReq_miss_latency::cpu.data 19872663500 # number of ReadReq miss cycles 651system.cpu.dcache.ReadReq_miss_latency::total 19872663500 # number of ReadReq miss cycles 652system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327755500 # number of WriteReq miss cycles 653system.cpu.dcache.WriteReq_miss_latency::total 9327755500 # number of WriteReq miss cycles |
654system.cpu.dcache.demand_miss_latency::cpu.data 29200419000 # number of demand (read+write) miss cycles 655system.cpu.dcache.demand_miss_latency::total 29200419000 # number of demand (read+write) miss cycles 656system.cpu.dcache.overall_miss_latency::cpu.data 29200419000 # number of overall miss cycles 657system.cpu.dcache.overall_miss_latency::total 29200419000 # number of overall miss cycles |
658system.cpu.dcache.ReadReq_accesses::cpu.data 13297693 # number of ReadReq accesses(hits+misses) 659system.cpu.dcache.ReadReq_accesses::total 13297693 # number of ReadReq accesses(hits+misses) 660system.cpu.dcache.WriteReq_accesses::cpu.data 8348364 # number of WriteReq accesses(hits+misses) 661system.cpu.dcache.WriteReq_accesses::total 8348364 # number of WriteReq accesses(hits+misses) 662system.cpu.dcache.demand_accesses::cpu.data 21646057 # number of demand (read+write) accesses 663system.cpu.dcache.demand_accesses::total 21646057 # number of demand (read+write) accesses 664system.cpu.dcache.overall_accesses::cpu.data 21646057 # number of overall (read+write) accesses 665system.cpu.dcache.overall_accesses::total 21646057 # number of overall (read+write) accesses |
666system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098404 # miss rate for ReadReq accesses 667system.cpu.dcache.ReadReq_miss_rate::total 0.098404 # miss rate for ReadReq accesses 668system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037717 # miss rate for WriteReq accesses 669system.cpu.dcache.WriteReq_miss_rate::total 0.037717 # miss rate for WriteReq accesses |
670system.cpu.dcache.demand_miss_rate::cpu.data 0.074999 # miss rate for demand accesses 671system.cpu.dcache.demand_miss_rate::total 0.074999 # miss rate for demand accesses 672system.cpu.dcache.overall_miss_rate::cpu.data 0.074999 # miss rate for overall accesses 673system.cpu.dcache.overall_miss_rate::total 0.074999 # miss rate for overall accesses 674system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.781934 # average ReadReq miss latency 675system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.781934 # average ReadReq miss latency 676system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.959895 # average WriteReq miss latency 677system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.959895 # average WriteReq miss latency 678system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency 679system.cpu.dcache.demand_avg_miss_latency::total 17986.955333 # average overall miss latency 680system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency 681system.cpu.dcache.overall_avg_miss_latency::total 17986.955333 # average overall miss latency |
682system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 683system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 684system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 685system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 686system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 687system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 688system.cpu.dcache.fast_writes 0 # number of fast writes performed 689system.cpu.dcache.cache_copies 0 # number of cache copies performed |
690system.cpu.dcache.writebacks::writebacks 1537687 # number of writebacks 691system.cpu.dcache.writebacks::total 1537687 # number of writebacks 692system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308550 # number of ReadReq MSHR misses 693system.cpu.dcache.ReadReq_mshr_misses::total 1308550 # number of ReadReq MSHR misses |
694system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314872 # number of WriteReq MSHR misses 695system.cpu.dcache.WriteReq_mshr_misses::total 314872 # number of WriteReq MSHR misses |
696system.cpu.dcache.demand_mshr_misses::cpu.data 1623422 # number of demand (read+write) MSHR misses 697system.cpu.dcache.demand_mshr_misses::total 1623422 # number of demand (read+write) MSHR misses 698system.cpu.dcache.overall_mshr_misses::cpu.data 1623422 # number of overall MSHR misses 699system.cpu.dcache.overall_mshr_misses::total 1623422 # number of overall MSHR misses 700system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15946963002 # number of ReadReq MSHR miss cycles 701system.cpu.dcache.ReadReq_mshr_miss_latency::total 15946963002 # number of ReadReq MSHR miss cycles 702system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8383136001 # number of WriteReq MSHR miss cycles 703system.cpu.dcache.WriteReq_mshr_miss_latency::total 8383136001 # number of WriteReq MSHR miss cycles 704system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24330099003 # number of demand (read+write) MSHR miss cycles 705system.cpu.dcache.demand_mshr_miss_latency::total 24330099003 # number of demand (read+write) MSHR miss cycles 706system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24330099003 # number of overall MSHR miss cycles 707system.cpu.dcache.overall_mshr_miss_latency::total 24330099003 # number of overall MSHR miss cycles |
708system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75924400500 # number of ReadReq MSHR uncacheable cycles 709system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75924400500 # number of ReadReq MSHR uncacheable cycles 710system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1366040500 # number of WriteReq MSHR uncacheable cycles 711system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1366040500 # number of WriteReq MSHR uncacheable cycles 712system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77290441000 # number of overall MSHR uncacheable cycles 713system.cpu.dcache.overall_mshr_uncacheable_latency::total 77290441000 # number of overall MSHR uncacheable cycles 714system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098404 # mshr miss rate for ReadReq accesses 715system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098404 # mshr miss rate for ReadReq accesses 716system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037717 # mshr miss rate for WriteReq accesses 717system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037717 # mshr miss rate for WriteReq accesses |
718system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for demand accesses 719system.cpu.dcache.demand_mshr_miss_rate::total 0.074999 # mshr miss rate for demand accesses 720system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for overall accesses 721system.cpu.dcache.overall_mshr_miss_rate::total 0.074999 # mshr miss rate for overall accesses 722system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.743343 # average ReadReq mshr miss latency 723system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.743343 # average ReadReq mshr miss latency 724system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.948782 # average WriteReq mshr miss latency 725system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.948782 # average WriteReq mshr miss latency 726system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency 727system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency 728system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency 729system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency |
730system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 731system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 732system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 733system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 734system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 735system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 736system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 737 738---------- End Simulation Statistics ---------- |