7,13c7,13
< host_inst_rate 973985 # Simulator instruction rate (inst/s)
< host_op_rate 1877578 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 39447094407 # Simulator tick rate (ticks/s)
< host_mem_usage 612564 # Number of bytes of host memory used
< host_seconds 131.70 # Real time elapsed on the host
< sim_insts 128273348 # Number of instructions simulated
< sim_ops 247275973 # Number of ops (including micro ops) simulated
---
> host_inst_rate 926995 # Simulator instruction rate (inst/s)
> host_op_rate 1786992 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 37543942770 # Simulator tick rate (ticks/s)
> host_mem_usage 611560 # Number of bytes of host memory used
> host_seconds 138.38 # Real time elapsed on the host
> sim_insts 128273323 # Number of instructions simulated
> sim_ops 247275942 # Number of ops (including micro ops) simulated
51c51
< system.physmem.cpureqs 331611 # Reqs generatd by CPU via cache - shady
---
> system.physmem.cpureqs 327581 # Reqs generatd by CPU via cache - shady
100,131c100,118
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 127557 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 1624 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
< system.physmem.rdQLenPdf::0 155111 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 8768 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 6671 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3399 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 2809 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 2248 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 2166 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 2070 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2020 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1315 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1213 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 126924 # Categorize write packet sizes
> system.physmem.rdQLenPdf::0 155117 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 8774 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 6658 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 3415 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 3396 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 2811 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 2249 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 2165 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 2071 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 2021 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1317 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 1212 # What read queue length does an incoming req see
133c120
< system.physmem.rdQLenPdf::13 1043 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::13 1042 # What read queue length does an incoming req see
135,137c122,124
< system.physmem.rdQLenPdf::15 972 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1102 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 1082 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::15 971 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 1103 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 1084 # What read queue length does an incoming req see
152,154c139,140
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
< system.physmem.wrQLenPdf::0 4190 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 4518 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::0 4189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 4520 # What write queue length does an incoming req see
156,161c142,147
< system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 5474 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 5502 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 5510 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 5511 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::3 5434 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 5475 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 5503 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 5510 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 5511 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 5512 # What write queue length does an incoming req see
176,177c162,163
< system.physmem.wrQLenPdf::23 1329 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 1001 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::23 1330 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 999 # What write queue length does an incoming req see
179,187c165,172
< system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 45 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 4076582985 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 7872522985 # Sum of mem lat for all requests
---
> system.physmem.wrQLenPdf::26 85 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 44 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7 # What write queue length does an incoming req see
> system.physmem.totQLat 4073325250 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 7869155250 # Sum of mem lat for all requests
189,191c174,176
< system.physmem.totBankLat 2804230000 # Total cycles spent in bank access
< system.physmem.avgQLat 20553.30 # Average queueing delay per request
< system.physmem.avgBankLat 14138.36 # Average bank access latency per request
---
> system.physmem.totBankLat 2804120000 # Total cycles spent in bank access
> system.physmem.avgQLat 20536.88 # Average queueing delay per request
> system.physmem.avgBankLat 14137.80 # Average bank access latency per request
193c178
< system.physmem.avgMemAccLat 39691.66 # Average memory access latency
---
> system.physmem.avgMemAccLat 39674.68 # Average memory access latency
202,203c187,188
< system.physmem.readRowHits 175587 # Number of row buffer hits during reads
< system.physmem.writeRowHits 94819 # Number of row buffer hits during writes
---
> system.physmem.readRowHits 175586 # Number of row buffer hits during reads
> system.physmem.writeRowHits 94818 # Number of row buffer hits during writes
205c190
< system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes
---
> system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes
226,231c211,216
< system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10701739160 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 10701739160 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::pc.south_bridge.ide 10841219092 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 10841219092 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 10841219092 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 10841219092 # number of overall miss cycles
---
> system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10699969160 # number of WriteReq miss cycles
> system.iocache.WriteReq_miss_latency::total 10699969160 # number of WriteReq miss cycles
> system.iocache.demand_miss_latency::pc.south_bridge.ide 10839449092 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 10839449092 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 10839449092 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 10839449092 # number of overall miss cycles
250,256c235,241
< system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229061.197774 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 229061.197774 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 227929.086957 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 227929.086957 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 173428 # number of cycles access was blocked
---
> system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229023.312500 # average WriteReq miss latency
> system.iocache.WriteReq_avg_miss_latency::total 229023.312500 # average WriteReq miss latency
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 227891.873938 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227891.873938 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 227891.873938 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 173195 # number of cycles access was blocked
258c243
< system.iocache.blocked::no_mshrs 16211 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 16181 # number of cycles access was blocked
260c245
< system.iocache.avg_blocked_cycles::no_mshrs 10.698168 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 10.703603 # average number of cycles each access was blocked
274,281c259,266
< system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570991 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 95570991 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8270938224 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 8270938224 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 8366509215 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 8366509215 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570962 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 95570962 # number of ReadReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8269165315 # number of WriteReq MSHR miss cycles
> system.iocache.WriteReq_mshr_miss_latency::total 8269165315 # number of WriteReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 8364736277 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8364736277 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 8364736277 # number of overall MSHR miss cycles
290,297c275,282
< system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.771327 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.771327 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177032.068151 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 177032.068151 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.736967 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.736967 # average ReadReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 176994.120612 # average WriteReq mshr miss latency
> system.iocache.WriteReq_avg_mshr_miss_latency::total 176994.120612 # average WriteReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175862.759167 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 175862.759167 # average overall mshr miss latency
314,316c299,301
< system.cpu.committedInsts 128273348 # Number of instructions committed
< system.cpu.committedOps 247275973 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 232011682 # Number of integer alu accesses
---
> system.cpu.committedInsts 128273323 # Number of instructions committed
> system.cpu.committedOps 247275942 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 232011652 # Number of integer alu accesses
320c305
< system.cpu.num_int_insts 232011682 # number of integer instructions
---
> system.cpu.num_int_insts 232011652 # number of integer instructions
322,323c307,308
< system.cpu.num_int_register_reads 567056120 # number of times the integer registers were read
< system.cpu.num_int_register_writes 293242224 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 567056066 # number of times the integer registers were read
> system.cpu.num_int_register_writes 293242220 # number of times the integer registers were written
326,330c311,315
< system.cpu.num_mem_refs 22232138 # number of memory refs
< system.cpu.num_load_insts 13871783 # Number of load instructions
< system.cpu.num_store_insts 8360355 # Number of store instructions
< system.cpu.num_idle_cycles 9789668776.998116 # Number of idle cycles
< system.cpu.num_busy_cycles 600655265.001884 # Number of busy cycles
---
> system.cpu.num_mem_refs 22232130 # number of memory refs
> system.cpu.num_load_insts 13871776 # Number of load instructions
> system.cpu.num_store_insts 8360354 # Number of store instructions
> system.cpu.num_idle_cycles 9789674914.998116 # Number of idle cycles
> system.cpu.num_busy_cycles 600649127.001884 # Number of busy cycles
335c320
< system.cpu.icache.replacements 791521 # number of replacements
---
> system.cpu.icache.replacements 791510 # number of replacements
337,339c322,324
< system.cpu.icache.total_refs 144497694 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 792033 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 182.438982 # Average number of references to valid blocks.
---
> system.cpu.icache.total_refs 144497671 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 792022 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 182.441486 # Average number of references to valid blocks.
344,367c329,352
< system.cpu.icache.ReadReq_hits::cpu.inst 144497694 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 144497694 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 144497694 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 144497694 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 144497694 # number of overall hits
< system.cpu.icache.overall_hits::total 144497694 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 792040 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 792040 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 792040 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 792040 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 792040 # number of overall misses
< system.cpu.icache.overall_misses::total 792040 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 10957638500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 10957638500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 10957638500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 10957638500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 10957638500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 10957638500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 145289734 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 145289734 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 145289734 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 145289734 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 145289734 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 145289734 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_hits::cpu.inst 144497671 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 144497671 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 144497671 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 144497671 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 144497671 # number of overall hits
> system.cpu.icache.overall_hits::total 144497671 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 792029 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 792029 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 792029 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 792029 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 792029 # number of overall misses
> system.cpu.icache.overall_misses::total 792029 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 10955241500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 10955241500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 10955241500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 10955241500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 10955241500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 10955241500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 145289700 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 145289700 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 145289700 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 145289700 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 145289700 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 145289700 # number of overall (read+write) accesses
374,379c359,364
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.703424 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 13834.703424 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 13834.703424 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 13834.703424 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13831.869161 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 13831.869161 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 13831.869161 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 13831.869161 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 13831.869161 # average overall miss latency
388,399c373,384
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792040 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 792040 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 792040 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 792040 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 792040 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 792040 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9373558500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9373558500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9373558500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9373558500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9373558500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9373558500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792029 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 792029 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 792029 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 792029 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 792029 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 792029 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9371183500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 9371183500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9371183500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 9371183500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9371183500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 9371183500 # number of overall MSHR miss cycles
406,411c391,396
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11834.703424 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11834.703424 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11834.703424 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11834.703424 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11834.703424 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11834.703424 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11831.869161 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11831.869161 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11831.869161 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11831.869161 # average overall mshr miss latency
497c482
< system.cpu.dtb_walker_cache.replacements 7538 # number of replacements
---
> system.cpu.dtb_walker_cache.replacements 7540 # number of replacements
499,501c484,486
< system.cpu.dtb_walker_cache.total_refs 13179 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.sampled_refs 7552 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.avg_refs 1.745101 # Average number of references to valid blocks.
---
> system.cpu.dtb_walker_cache.total_refs 13178 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.sampled_refs 7554 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.avg_refs 1.744506 # Average number of references to valid blocks.
506,523c491,508
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13181 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 13181 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13181 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 13181 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13181 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 13181 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8725 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 8725 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8725 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 8725 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8725 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 8725 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92081500 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92081500 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92081500 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::total 92081500 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92081500 # number of overall miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::total 92081500 # number of overall miss cycles
---
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13180 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 13180 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13180 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 13180 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13180 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 13180 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8726 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 8726 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8726 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 8726 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8726 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 8726 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92094500 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92094500 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92094500 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::total 92094500 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92094500 # number of overall miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::total 92094500 # number of overall miss cycles
530,541c515,526
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398293 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398293 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398293 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398293 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398293 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398293 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.753582 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.753582 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.753582 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.753582 # average overall miss latency
---
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398338 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398338 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398338 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398338 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398338 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398338 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10554.033922 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10554.033922 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10554.033922 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10554.033922 # average overall miss latency
550,575c535,560
< system.cpu.dtb_walker_cache.writebacks::writebacks 2712 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 2712 # number of writebacks
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8725 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8725 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8725 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::total 8725 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8725 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::total 8725 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74631500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74631500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74631500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74631500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74631500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74631500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398293 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398293 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398293 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.753582 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 2713 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 2713 # number of writebacks
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8726 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8726 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8726 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::total 8726 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8726 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::total 8726 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74642500 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74642500 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74642500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74642500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74642500 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74642500 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398338 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398338 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398338 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8554.033922 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency
577c562
< system.cpu.dcache.replacements 1618787 # number of replacements
---
> system.cpu.dcache.replacements 1618785 # number of replacements
579,581c564,566
< system.cpu.dcache.total_refs 20025899 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1619299 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 12.367017 # Average number of references to valid blocks.
---
> system.cpu.dcache.total_refs 20025893 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1619297 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 12.367029 # Average number of references to valid blocks.
586,617c571,602
< system.cpu.dcache.ReadReq_hits::cpu.data 11988264 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 11988264 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8035473 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8035473 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20023737 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20023737 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20023737 # number of overall hits
< system.cpu.dcache.overall_hits::total 20023737 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1306607 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1306607 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 1621495 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1621495 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1621495 # number of overall misses
< system.cpu.dcache.overall_misses::total 1621495 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 18344083000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 18344083000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556368000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 8556368000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 26900451000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 26900451000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 26900451000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 26900451000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 13294871 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13294871 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8350361 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8350361 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21645232 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21645232 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21645232 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21645232 # number of overall (read+write) accesses
---
> system.cpu.dcache.ReadReq_hits::cpu.data 11988262 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 11988262 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8035470 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8035470 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20023732 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20023732 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20023732 # number of overall hits
> system.cpu.dcache.overall_hits::total 20023732 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1306602 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1306602 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 314890 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 314890 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 1621492 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1621492 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1621492 # number of overall misses
> system.cpu.dcache.overall_misses::total 1621492 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 18343104000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 18343104000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556691000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 8556691000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 26899795000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 26899795000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 26899795000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 26899795000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 13294864 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13294864 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8350360 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8350360 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21645224 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21645224 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21645224 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21645224 # number of overall (read+write) accesses
626,633c611,618
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14039.480119 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14039.480119 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27172.734433 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 27172.734433 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 16589.906845 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 16589.906845 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.784573 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.784573 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27173.587602 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 27173.587602 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 16589.532973 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.532973 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 16589.532973 # average overall miss latency
642,659c627,644
< system.cpu.dcache.writebacks::writebacks 1536049 # number of writebacks
< system.cpu.dcache.writebacks::total 1536049 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306607 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1306607 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1621495 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1621495 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1621495 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1621495 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15730869000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 15730869000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926592000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926592000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23657461000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23657461000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23657461000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23657461000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.writebacks::writebacks 1536047 # number of writebacks
> system.cpu.dcache.writebacks::total 1536047 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306602 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1306602 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314890 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 314890 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1621492 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1621492 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1621492 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1621492 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15729900000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 15729900000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926911000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926911000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23656811000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23656811000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23656811000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23656811000 # number of overall MSHR miss cycles
674,681c659,666
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.480119 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.480119 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25172.734433 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25172.734433 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12038.784573 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12038.784573 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25173.587602 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25173.587602 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.532973 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.532973 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.532973 # average overall mshr miss latency
690,691c675,676
< system.cpu.l2cache.tagsinuse 64770.429000 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 3484731 # Total number of references to valid blocks.
---
> system.cpu.l2cache.tagsinuse 64770.428925 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 3484716 # Total number of references to valid blocks.
693c678
< system.cpu.l2cache.avg_refs 22.981653 # Average number of references to valid blocks.
---
> system.cpu.l2cache.avg_refs 22.981554 # Average number of references to valid blocks.
695c680
< system.cpu.l2cache.occ_blocks::writebacks 50336.267441 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::writebacks 50336.266909 # Average occupied blocks per requestor
698,699c683,684
< system.cpu.l2cache.occ_blocks::cpu.inst 3358.135857 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 11075.878163 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 3358.136526 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 11075.877952 # Average occupied blocks per requestor
706c691
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6346 # number of ReadReq hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6347 # number of ReadReq hits
708,712c693,697
< system.cpu.l2cache.ReadReq_hits::cpu.inst 779155 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1277466 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2065721 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1539402 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1539402 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 779144 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1277462 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2065707 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1539401 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1539401 # number of Writeback hits
715,717c700,702
< system.cpu.l2cache.ReadExReq_hits::cpu.data 199364 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 199364 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 6346 # number of demand (read+write) hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 199367 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 199367 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 6347 # number of demand (read+write) hits
719,722c704,707
< system.cpu.l2cache.demand_hits::cpu.inst 779155 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1476830 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2265085 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 6346 # number of overall hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 779144 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1476829 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2265074 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 6347 # number of overall hits
724,726c709,711
< system.cpu.l2cache.overall_hits::cpu.inst 779155 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1476830 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2265085 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 779144 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1476829 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2265074 # number of overall hits
748,750c733,735
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 789955500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1648844500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2439213500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 787701500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1647921500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2436036500 # number of ReadReq miss cycles
753,754c738,739
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5583075000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 5583075000 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5583363000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 5583363000 # number of ReadExReq miss cycles
757,759c742,744
< system.cpu.l2cache.demand_miss_latency::cpu.inst 789955500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7231919500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 8022288500 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 787701500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7231284500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8019399500 # number of demand (read+write) miss cycles
762,765c747,750
< system.cpu.l2cache.overall_miss_latency::cpu.inst 789955500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7231919500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 8022288500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6347 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 787701500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7231284500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8019399500 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6348 # number of ReadReq accesses(hits+misses)
767,771c752,756
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 792027 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1305851 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2106984 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1539402 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1539402 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 792016 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1305847 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2106970 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1539401 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1539401 # number of Writeback accesses(hits+misses)
774,776c759,761
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 312722 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 312722 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6347 # number of demand (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 312725 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 312725 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6348 # number of demand (read+write) accesses
778,781c763,766
< system.cpu.l2cache.demand_accesses::cpu.inst 792027 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1618573 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2419706 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6347 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 792016 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1618572 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2419695 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6348 # number of overall (read+write) accesses
783,785c768,770
< system.cpu.l2cache.overall_accesses::cpu.inst 792027 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1618573 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2419706 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 792016 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1618572 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2419695 # number of overall (read+write) accesses
793,794c778,779
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362488 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.362488 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362485 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.362485 # miss rate for ReadExReq accesses
807,809c792,794
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61370.066812 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58088.585521 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 59113.818675 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61194.958048 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58056.068346 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 59036.824758 # average ReadReq miss latency
812,813c797,798
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49251.706981 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49251.706981 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49254.247605 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49254.247605 # average ReadExReq miss latency
816,818c801,803
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61370.066812 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51021.352024 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 51883.563682 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61194.958048 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51016.872085 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 51864.879285 # average overall miss latency
821,823c806,808
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61370.066812 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51021.352024 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 51883.563682 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61194.958048 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51016.872085 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 51864.879285 # average overall miss latency
853,857c838,842
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56252 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281260 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 630045573 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1296264296 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1926647381 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56251 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281255 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 627778857 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1295316957 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1923433320 # number of ReadReq MSHR miss cycles
860,871c845,856
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190240726 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190240726 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56252 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281260 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 630045573 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5486505022 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6116888107 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56252 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281260 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 630045573 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5486505022 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 6116888107 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4190411275 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4190411275 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 627778857 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5485728232 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6113844595 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56251 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 627778857 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5485728232 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6113844595 # number of overall MSHR miss cycles
885,886c870,871
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362485 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362485 # mshr miss rate for ReadExReq accesses
897,901c882,886
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56252 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48946.983608 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45667.229029 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46691.888156 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 48770.886964 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45633.854395 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46613.996074 # average ReadReq mshr miss latency
904,915c889,900
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36964.667037 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36964.667037 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56252 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56252 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48946.983608 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38707.414278 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39560.526106 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36966.171554 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36966.171554 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 48770.886964 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38701.934007 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39540.842415 # average overall mshr miss latency