7,13c7,13
< host_inst_rate 1106680 # Simulator instruction rate (inst/s)
< host_op_rate 2133324 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 44796411922 # Simulator tick rate (ticks/s)
< host_mem_usage 384016 # Number of bytes of host memory used
< host_seconds 115.88 # Real time elapsed on the host
< sim_insts 128244614 # Number of instructions simulated
< sim_ops 247214600 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1076481 # Simulator instruction rate (inst/s)
> host_op_rate 2075111 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 43574012985 # Simulator tick rate (ticks/s)
> host_mem_usage 651144 # Number of bytes of host memory used
> host_seconds 119.13 # Real time elapsed on the host
> sim_insts 128244620 # Number of instructions simulated
> sim_ops 247214608 # Number of ops (including micro ops) simulated
182,183c182,183
< system.physmem.totQLat 2876233269 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 6438459269 # Sum of mem lat for all requests
---
> system.physmem.totQLat 2876225269 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 6438451269 # Sum of mem lat for all requests
186c186
< system.physmem.avgQLat 14495.10 # Average queueing delay per request
---
> system.physmem.avgQLat 14495.06 # Average queueing delay per request
189c189
< system.physmem.avgMemAccLat 32447.33 # Average memory access latency
---
> system.physmem.avgMemAccLat 32447.29 # Average memory access latency
310,312c310,312
< system.cpu.committedInsts 128244614 # Number of instructions committed
< system.cpu.committedOps 247214600 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 231949861 # Number of integer alu accesses
---
> system.cpu.committedInsts 128244620 # Number of instructions committed
> system.cpu.committedOps 247214608 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 231949869 # Number of integer alu accesses
316c316
< system.cpu.num_int_insts 231949861 # number of integer instructions
---
> system.cpu.num_int_insts 231949869 # number of integer instructions
318,319c318,319
< system.cpu.num_int_register_reads 566905512 # number of times the integer registers were read
< system.cpu.num_int_register_writes 293156466 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 566905534 # number of times the integer registers were read
> system.cpu.num_int_register_writes 293156476 # number of times the integer registers were written
322c322
< system.cpu.num_mem_refs 22227093 # number of memory refs
---
> system.cpu.num_mem_refs 22227095 # number of memory refs
324c324
< system.cpu.num_store_insts 8360426 # Number of store instructions
---
> system.cpu.num_store_insts 8360428 # Number of store instructions
333c333
< system.cpu.icache.total_refs 144455339 # Total number of references to valid blocks.
---
> system.cpu.icache.total_refs 144455345 # Total number of references to valid blocks.
335c335
< system.cpu.icache.avg_refs 182.521700 # Average number of references to valid blocks.
---
> system.cpu.icache.avg_refs 182.521707 # Average number of references to valid blocks.
340,345c340,345
< system.cpu.icache.ReadReq_hits::cpu.inst 144455339 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 144455339 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 144455339 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 144455339 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 144455339 # number of overall hits
< system.cpu.icache.overall_hits::total 144455339 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 144455345 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 144455345 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 144455345 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 144455345 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 144455345 # number of overall hits
> system.cpu.icache.overall_hits::total 144455345 # number of overall hits
358,363c358,363
< system.cpu.icache.ReadReq_accesses::cpu.inst 145246788 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 145246788 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 145246788 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 145246788 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 145246788 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 145246788 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 145246794 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 145246794 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 145246794 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 145246794 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 145246794 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 145246794 # number of overall (read+write) accesses
575c575
< system.cpu.dcache.total_refs 20018688 # Total number of references to valid blocks.
---
> system.cpu.dcache.total_refs 20018690 # Total number of references to valid blocks.
577c577
< system.cpu.dcache.avg_refs 12.346446 # Average number of references to valid blocks.
---
> system.cpu.dcache.avg_refs 12.346447 # Average number of references to valid blocks.
584,589c584,589
< system.cpu.dcache.WriteReq_hits::cpu.data 8034926 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8034926 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20016506 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20016506 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20016506 # number of overall hits
< system.cpu.dcache.overall_hits::total 20016506 # number of overall hits
---
> system.cpu.dcache.WriteReq_hits::cpu.data 8034928 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8034928 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20016508 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20016508 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20016508 # number of overall hits
> system.cpu.dcache.overall_hits::total 20016508 # number of overall hits
598,599c598,599
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313644000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 18313644000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313636000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 18313636000 # number of ReadReq miss cycles
602,605c602,605
< system.cpu.dcache.demand_miss_latency::cpu.data 27016361500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 27016361500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 27016361500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 27016361500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 27016353500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 27016353500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 27016353500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 27016353500 # number of overall miss cycles
608,613c608,613
< system.cpu.dcache.WriteReq_accesses::cpu.data 8350412 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8350412 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21640137 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21640137 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21640137 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21640137 # number of overall (read+write) accesses
---
> system.cpu.dcache.WriteReq_accesses::cpu.data 8350414 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8350414 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21640139 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21640139 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21640139 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21640139 # number of overall (read+write) accesses
622,623c622,623
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.704926 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.704926 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.698810 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.698810 # average ReadReq miss latency
626,629c626,629
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 16639.471345 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 16639.471345 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 16639.466418 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 16639.466418 # average overall miss latency
648,649c648,649
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697354000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697354000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697346000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697346000 # number of ReadReq MSHR miss cycles
652,655c652,655
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769099500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23769099500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769099500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23769099500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769091500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23769091500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769091500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23769091500 # number of overall MSHR miss cycles
670,671c670,671
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.704926 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.704926 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.698810 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.698810 # average ReadReq mshr miss latency
674,677c674,677
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency
739,740c739,740
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599602500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2311578500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599594500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2311570500 # number of ReadReq miss cycles
747,748c747,748
< system.cpu.l2cache.demand_miss_latency::cpu.data 7323346000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 8035322000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 7323338000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8035314000 # number of demand (read+write) miss cycles
751,752c751,752
< system.cpu.l2cache.overall_miss_latency::cpu.data 7323346000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 8035322000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 7323338000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8035314000 # number of overall miss cycles
792,793c792,793
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.660711 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.505382 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.379348 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.311888 # average ReadReq miss latency
800,801c800,801
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 51882.627926 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 51882.576271 # average overall miss latency
804,805c804,805
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 51882.627926 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 51882.576271 # average overall miss latency
834,835c834,835
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230984255 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775437660 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230976255 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775429660 # number of ReadReq MSHR miss cycles
842,843c842,843
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480317607 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6024771012 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480309607 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6024763012 # number of demand (read+write) MSHR miss cycles
846,847c846,847
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480317607 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 6024771012 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480309607 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6024763012 # number of overall MSHR miss cycles
872,873c872,873
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.209369 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.016205 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43293.928006 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42941.822711 # average ReadReq mshr miss latency
880,881c880,881
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency
884,885c884,885
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency
< host_inst_rate 1106680 # Simulator instruction rate (inst/s)
< host_op_rate 2133324 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 44796411922 # Simulator tick rate (ticks/s)
< host_mem_usage 384016 # Number of bytes of host memory used
< host_seconds 115.88 # Real time elapsed on the host
< sim_insts 128244614 # Number of instructions simulated
< sim_ops 247214600 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1076481 # Simulator instruction rate (inst/s)
> host_op_rate 2075111 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 43574012985 # Simulator tick rate (ticks/s)
> host_mem_usage 651144 # Number of bytes of host memory used
> host_seconds 119.13 # Real time elapsed on the host
> sim_insts 128244620 # Number of instructions simulated
> sim_ops 247214608 # Number of ops (including micro ops) simulated
182,183c182,183
< system.physmem.totQLat 2876233269 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 6438459269 # Sum of mem lat for all requests
---
> system.physmem.totQLat 2876225269 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 6438451269 # Sum of mem lat for all requests
186c186
< system.physmem.avgQLat 14495.10 # Average queueing delay per request
---
> system.physmem.avgQLat 14495.06 # Average queueing delay per request
189c189
< system.physmem.avgMemAccLat 32447.33 # Average memory access latency
---
> system.physmem.avgMemAccLat 32447.29 # Average memory access latency
310,312c310,312
< system.cpu.committedInsts 128244614 # Number of instructions committed
< system.cpu.committedOps 247214600 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 231949861 # Number of integer alu accesses
---
> system.cpu.committedInsts 128244620 # Number of instructions committed
> system.cpu.committedOps 247214608 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 231949869 # Number of integer alu accesses
316c316
< system.cpu.num_int_insts 231949861 # number of integer instructions
---
> system.cpu.num_int_insts 231949869 # number of integer instructions
318,319c318,319
< system.cpu.num_int_register_reads 566905512 # number of times the integer registers were read
< system.cpu.num_int_register_writes 293156466 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 566905534 # number of times the integer registers were read
> system.cpu.num_int_register_writes 293156476 # number of times the integer registers were written
322c322
< system.cpu.num_mem_refs 22227093 # number of memory refs
---
> system.cpu.num_mem_refs 22227095 # number of memory refs
324c324
< system.cpu.num_store_insts 8360426 # Number of store instructions
---
> system.cpu.num_store_insts 8360428 # Number of store instructions
333c333
< system.cpu.icache.total_refs 144455339 # Total number of references to valid blocks.
---
> system.cpu.icache.total_refs 144455345 # Total number of references to valid blocks.
335c335
< system.cpu.icache.avg_refs 182.521700 # Average number of references to valid blocks.
---
> system.cpu.icache.avg_refs 182.521707 # Average number of references to valid blocks.
340,345c340,345
< system.cpu.icache.ReadReq_hits::cpu.inst 144455339 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 144455339 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 144455339 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 144455339 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 144455339 # number of overall hits
< system.cpu.icache.overall_hits::total 144455339 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 144455345 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 144455345 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 144455345 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 144455345 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 144455345 # number of overall hits
> system.cpu.icache.overall_hits::total 144455345 # number of overall hits
358,363c358,363
< system.cpu.icache.ReadReq_accesses::cpu.inst 145246788 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 145246788 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 145246788 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 145246788 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 145246788 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 145246788 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 145246794 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 145246794 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 145246794 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 145246794 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 145246794 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 145246794 # number of overall (read+write) accesses
575c575
< system.cpu.dcache.total_refs 20018688 # Total number of references to valid blocks.
---
> system.cpu.dcache.total_refs 20018690 # Total number of references to valid blocks.
577c577
< system.cpu.dcache.avg_refs 12.346446 # Average number of references to valid blocks.
---
> system.cpu.dcache.avg_refs 12.346447 # Average number of references to valid blocks.
584,589c584,589
< system.cpu.dcache.WriteReq_hits::cpu.data 8034926 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8034926 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20016506 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20016506 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20016506 # number of overall hits
< system.cpu.dcache.overall_hits::total 20016506 # number of overall hits
---
> system.cpu.dcache.WriteReq_hits::cpu.data 8034928 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8034928 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20016508 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20016508 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20016508 # number of overall hits
> system.cpu.dcache.overall_hits::total 20016508 # number of overall hits
598,599c598,599
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313644000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 18313644000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 18313636000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 18313636000 # number of ReadReq miss cycles
602,605c602,605
< system.cpu.dcache.demand_miss_latency::cpu.data 27016361500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 27016361500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 27016361500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 27016361500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 27016353500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 27016353500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 27016353500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 27016353500 # number of overall miss cycles
608,613c608,613
< system.cpu.dcache.WriteReq_accesses::cpu.data 8350412 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8350412 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21640137 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21640137 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21640137 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21640137 # number of overall (read+write) accesses
---
> system.cpu.dcache.WriteReq_accesses::cpu.data 8350414 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8350414 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21640139 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21640139 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21640139 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21640139 # number of overall (read+write) accesses
622,623c622,623
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.704926 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.704926 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13999.698810 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 13999.698810 # average ReadReq miss latency
626,629c626,629
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 16639.471345 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.471345 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 16639.471345 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 16639.466418 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 16639.466418 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 16639.466418 # average overall miss latency
648,649c648,649
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697354000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697354000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15697346000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 15697346000 # number of ReadReq MSHR miss cycles
652,655c652,655
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769099500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 23769099500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769099500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 23769099500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23769091500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 23769091500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23769091500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 23769091500 # number of overall MSHR miss cycles
670,671c670,671
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.704926 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.704926 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11999.698810 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11999.698810 # average ReadReq mshr miss latency
674,677c674,677
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.471345 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.471345 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14639.466418 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 14639.466418 # average overall mshr miss latency
739,740c739,740
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599602500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 2311578500 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1599594500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 2311570500 # number of ReadReq miss cycles
747,748c747,748
< system.cpu.l2cache.demand_miss_latency::cpu.data 7323346000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 8035322000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 7323338000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 8035314000 # number of demand (read+write) miss cycles
751,752c751,752
< system.cpu.l2cache.overall_miss_latency::cpu.data 7323346000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 8035322000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 7323338000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 8035314000 # number of overall miss cycles
792,793c792,793
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.660711 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.505382 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 56258.379348 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 55909.311888 # average ReadReq miss latency
800,801c800,801
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 51882.627926 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 51882.576271 # average overall miss latency
804,805c804,805
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.300656 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 51882.627926 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51586.244303 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 51882.576271 # average overall miss latency
834,835c834,835
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230984255 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775437660 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1230976255 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1775429660 # number of ReadReq MSHR miss cycles
842,843c842,843
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480317607 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 6024771012 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480309607 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 6024763012 # number of demand (read+write) MSHR miss cycles
846,847c846,847
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480317607 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 6024771012 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480309607 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 6024763012 # number of overall MSHR miss cycles
872,873c872,873
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43294.209369 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42942.016205 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43293.928006 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42941.822711 # average ReadReq mshr miss latency
880,881c880,881
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency
884,885c884,885
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.844713 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.862063 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38603.788360 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38900.810408 # average overall mshr miss latency