7,13c7,13
< host_inst_rate 843973 # Simulator instruction rate (inst/s)
< host_op_rate 1619974 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 31713438762 # Simulator tick rate (ticks/s)
< host_mem_usage 354068 # Number of bytes of host memory used
< host_seconds 163.71 # Real time elapsed on the host
< sim_insts 138165779 # Number of instructions simulated
< sim_ops 265203823 # Number of ops (including micro ops) simulated
---
> host_inst_rate 672863 # Simulator instruction rate (inst/s)
> host_op_rate 1291533 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 25283717995 # Simulator tick rate (ticks/s)
> host_mem_usage 405876 # Number of bytes of host memory used
> host_seconds 205.34 # Real time elapsed on the host
> sim_insts 138165780 # Number of instructions simulated
> sim_ops 265203824 # Number of ops (including micro ops) simulated
46,47c46,47
< system.l2c.tagsinuse 64766.656106 # Cycle average of tags in use
< system.l2c.total_refs 3491041 # Total number of references to valid blocks.
---
> system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use
> system.l2c.total_refs 3491043 # Total number of references to valid blocks.
49c49
< system.l2c.avg_refs 23.127594 # Average number of references to valid blocks.
---
> system.l2c.avg_refs 23.127608 # Average number of references to valid blocks.
51c51
< system.l2c.occ_blocks::writebacks 50170.355132 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor
53,54c53,54
< system.l2c.occ_blocks::cpu.inst 3484.481213 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 11111.678563 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::cpu.inst 3484.481205 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.data 11111.678558 # Average occupied blocks per requestor
63,66c63,66
< system.l2c.ReadReq_hits::cpu.data 1279350 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 2065978 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 1542134 # number of Writeback hits
< system.l2c.Writeback_hits::total 1542134 # number of Writeback hits
---
> system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 1542135 # number of Writeback hits
> system.l2c.Writeback_hits::total 1542135 # number of Writeback hits
74,75c74,75
< system.l2c.demand_hits::cpu.data 1479801 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2266429 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu.data 1479802 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2266430 # number of demand (read+write) hits
79,80c79,80
< system.l2c.overall_hits::cpu.data 1479801 # number of overall hits
< system.l2c.overall_hits::total 2266429 # number of overall hits
---
> system.l2c.overall_hits::cpu.data 1479802 # number of overall hits
> system.l2c.overall_hits::total 2266430 # number of overall hits
116,119c116,119
< system.l2c.ReadReq_accesses::cpu.data 1307723 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2107189 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 1542134 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 1542134 # number of Writeback accesses(hits+misses)
---
> system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 1542135 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 1542135 # number of Writeback accesses(hits+misses)
127,128c127,128
< system.l2c.demand_accesses::cpu.data 1620409 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2419875 # number of demand (read+write) accesses
---
> system.l2c.demand_accesses::cpu.data 1620410 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2419876 # number of demand (read+write) accesses
132,133c132,133
< system.l2c.overall_accesses::cpu.data 1620409 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2419875 # number of overall (read+write) accesses
---
> system.l2c.overall_accesses::cpu.data 1620410 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2419876 # number of overall (read+write) accesses
360,362c360,362
< system.cpu.committedInsts 138165779 # Number of instructions committed
< system.cpu.committedOps 265203823 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 249613018 # Number of integer alu accesses
---
> system.cpu.committedInsts 138165780 # Number of instructions committed
> system.cpu.committedOps 265203824 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 249613019 # Number of integer alu accesses
365,366c365,366
< system.cpu.num_conditional_control_insts 24887740 # number of instructions that are conditional controls
< system.cpu.num_int_insts 249613018 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 24887741 # number of instructions that are conditional controls
> system.cpu.num_int_insts 249613019 # number of integer instructions
368,369c368,369
< system.cpu.num_int_register_reads 778264797 # number of times the integer registers were read
< system.cpu.num_int_register_writes 423017345 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 778264795 # number of times the integer registers were read
> system.cpu.num_int_register_writes 423017346 # number of times the integer registers were written
372,376c372,376
< system.cpu.num_mem_refs 23180618 # number of memory refs
< system.cpu.num_load_insts 14822217 # Number of load instructions
< system.cpu.num_store_insts 8358401 # Number of store instructions
< system.cpu.num_idle_cycles 9771874940.286118 # Number of idle cycles
< system.cpu.num_busy_cycles 611657687.713882 # Number of busy cycles
---
> system.cpu.num_mem_refs 23180616 # number of memory refs
> system.cpu.num_load_insts 14822216 # Number of load instructions
> system.cpu.num_store_insts 8358400 # Number of store instructions
> system.cpu.num_idle_cycles 9771874926.286118 # Number of idle cycles
> system.cpu.num_busy_cycles 611657701.713882 # Number of busy cycles
383c383
< system.cpu.icache.total_refs 158472874 # Total number of references to valid blocks.
---
> system.cpu.icache.total_refs 158472876 # Total number of references to valid blocks.
385,386c385,386
< system.cpu.icache.avg_refs 200.496043 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 160421907000 # Cycle when the warmup percentage was hit.
---
> system.cpu.icache.avg_refs 200.496045 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 160421909000 # Cycle when the warmup percentage was hit.
390,395c390,395
< system.cpu.icache.ReadReq_hits::cpu.inst 158472874 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 158472874 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 158472874 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 158472874 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 158472874 # number of overall hits
< system.cpu.icache.overall_hits::total 158472874 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 158472876 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 158472876 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 158472876 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 158472876 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 158472876 # number of overall hits
> system.cpu.icache.overall_hits::total 158472876 # number of overall hits
402,413c402,413
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780929500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11780929500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11780929500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11780929500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11780929500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11780929500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 159263285 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 159263285 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 159263285 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 159263285 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 159263285 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 159263285 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780909500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 11780909500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 11780909500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 11780909500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 11780909500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 11780909500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 159263287 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 159263287 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 159263287 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 159263287 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 159263287 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 159263287 # number of overall (read+write) accesses
420,425c420,425
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.814710 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14904.814710 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.814710 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14904.814710 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.814710 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14904.814710 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.789407 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14904.789407 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14904.789407 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14904.789407 # average overall miss latency
442,447c442,447
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408678500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9408678500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9408678500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9408678500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9408678500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9408678500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408658500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 9408658500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9408658500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 9408658500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9408658500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 9408658500 # number of overall MSHR miss cycles
454,459c454,459
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.526773 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.526773 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.526773 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.526773 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.526773 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.526773 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.501469 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.501469 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency
466c466
< system.cpu.itb_walker_cache.warmup_cycle 5164836909000 # Cycle when the warmup percentage was hit.
---
> system.cpu.itb_walker_cache.warmup_cycle 5164836918000 # Cycle when the warmup percentage was hit.
550c550
< system.cpu.dtb_walker_cache.warmup_cycle 5161009068000 # Cycle when the warmup percentage was hit.
---
> system.cpu.dtb_walker_cache.warmup_cycle 5161009077000 # Cycle when the warmup percentage was hit.
625c625
< system.cpu.dcache.replacements 1620697 # number of replacements
---
> system.cpu.dcache.replacements 1620698 # number of replacements
627,629c627,629
< system.cpu.dcache.total_refs 20024819 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1621209 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 12.351781 # Average number of references to valid blocks.
---
> system.cpu.dcache.total_refs 20024816 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1621210 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 12.351772 # Average number of references to valid blocks.
634,643c634,643
< system.cpu.dcache.ReadReq_hits::cpu.data 11989145 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 11989145 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8033493 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8033493 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20022638 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20022638 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20022638 # number of overall hits
< system.cpu.dcache.overall_hits::total 20022638 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1308549 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1308549 # number of ReadReq misses
---
> system.cpu.dcache.ReadReq_hits::cpu.data 11989143 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 11989143 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8033492 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8033492 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20022635 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20022635 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20022635 # number of overall hits
> system.cpu.dcache.overall_hits::total 20022635 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1308550 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1308550 # number of ReadReq misses
646,653c646,653
< system.cpu.dcache.demand_misses::cpu.data 1623421 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1623421 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1623421 # number of overall misses
< system.cpu.dcache.overall_misses::total 1623421 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 19872658500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 19872658500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327760500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9327760500 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 1623422 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1623422 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1623422 # number of overall misses
> system.cpu.dcache.overall_misses::total 1623422 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 19872663500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 19872663500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327755500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9327755500 # number of WriteReq miss cycles
658,665c658,665
< system.cpu.dcache.ReadReq_accesses::cpu.data 13297694 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13297694 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8348365 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8348365 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21646059 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21646059 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21646059 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21646059 # number of overall (read+write) accesses
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 13297693 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13297693 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8348364 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8348364 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21646057 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21646057 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21646057 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21646057 # number of overall (read+write) accesses
670,681c670,681
< system.cpu.dcache.demand_miss_rate::cpu.data 0.074998 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.074998 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.074998 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.074998 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.789719 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.789719 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.975774 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.975774 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.966412 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 17986.966412 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.966412 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 17986.966412 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.074999 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.074999 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.074999 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.074999 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.781934 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.781934 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.959895 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.959895 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 17986.955333 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 17986.955333 # average overall miss latency
690,693c690,693
< system.cpu.dcache.writebacks::writebacks 1537686 # number of writebacks
< system.cpu.dcache.writebacks::total 1537686 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308549 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1308549 # number of ReadReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 1537687 # number of writebacks
> system.cpu.dcache.writebacks::total 1537687 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308550 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1308550 # number of ReadReq MSHR misses
696,707c696,707
< system.cpu.dcache.demand_mshr_misses::cpu.data 1623421 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1623421 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1623421 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1623421 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15946961002 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 15946961002 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8383141001 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8383141001 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24330102003 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 24330102003 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24330102003 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 24330102003 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 1623422 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1623422 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1623422 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1623422 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15946963002 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 15946963002 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8383136001 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8383136001 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24330099003 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 24330099003 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24330099003 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 24330099003 # number of overall MSHR miss cycles
718,729c718,729
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.074998 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.074998 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.751128 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.751128 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.964662 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.964662 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.933151 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.933151 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.933151 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.933151 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.074999 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.074999 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.743343 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.743343 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.948782 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.948782 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency
< host_inst_rate 843973 # Simulator instruction rate (inst/s)
< host_op_rate 1619974 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 31713438762 # Simulator tick rate (ticks/s)
< host_mem_usage 354068 # Number of bytes of host memory used
< host_seconds 163.71 # Real time elapsed on the host
< sim_insts 138165779 # Number of instructions simulated
< sim_ops 265203823 # Number of ops (including micro ops) simulated
---
> host_inst_rate 672863 # Simulator instruction rate (inst/s)
> host_op_rate 1291533 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 25283717995 # Simulator tick rate (ticks/s)
> host_mem_usage 405876 # Number of bytes of host memory used
> host_seconds 205.34 # Real time elapsed on the host
> sim_insts 138165780 # Number of instructions simulated
> sim_ops 265203824 # Number of ops (including micro ops) simulated
46,47c46,47
< system.l2c.tagsinuse 64766.656106 # Cycle average of tags in use
< system.l2c.total_refs 3491041 # Total number of references to valid blocks.
---
> system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use
> system.l2c.total_refs 3491043 # Total number of references to valid blocks.
49c49
< system.l2c.avg_refs 23.127594 # Average number of references to valid blocks.
---
> system.l2c.avg_refs 23.127608 # Average number of references to valid blocks.
51c51
< system.l2c.occ_blocks::writebacks 50170.355132 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor
53,54c53,54
< system.l2c.occ_blocks::cpu.inst 3484.481213 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 11111.678563 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::cpu.inst 3484.481205 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.data 11111.678558 # Average occupied blocks per requestor
63,66c63,66
< system.l2c.ReadReq_hits::cpu.data 1279350 # number of ReadReq hits
< system.l2c.ReadReq_hits::total 2065978 # number of ReadReq hits
< system.l2c.Writeback_hits::writebacks 1542134 # number of Writeback hits
< system.l2c.Writeback_hits::total 1542134 # number of Writeback hits
---
> system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits
> system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits
> system.l2c.Writeback_hits::writebacks 1542135 # number of Writeback hits
> system.l2c.Writeback_hits::total 1542135 # number of Writeback hits
74,75c74,75
< system.l2c.demand_hits::cpu.data 1479801 # number of demand (read+write) hits
< system.l2c.demand_hits::total 2266429 # number of demand (read+write) hits
---
> system.l2c.demand_hits::cpu.data 1479802 # number of demand (read+write) hits
> system.l2c.demand_hits::total 2266430 # number of demand (read+write) hits
79,80c79,80
< system.l2c.overall_hits::cpu.data 1479801 # number of overall hits
< system.l2c.overall_hits::total 2266429 # number of overall hits
---
> system.l2c.overall_hits::cpu.data 1479802 # number of overall hits
> system.l2c.overall_hits::total 2266430 # number of overall hits
116,119c116,119
< system.l2c.ReadReq_accesses::cpu.data 1307723 # number of ReadReq accesses(hits+misses)
< system.l2c.ReadReq_accesses::total 2107189 # number of ReadReq accesses(hits+misses)
< system.l2c.Writeback_accesses::writebacks 1542134 # number of Writeback accesses(hits+misses)
< system.l2c.Writeback_accesses::total 1542134 # number of Writeback accesses(hits+misses)
---
> system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses)
> system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses)
> system.l2c.Writeback_accesses::writebacks 1542135 # number of Writeback accesses(hits+misses)
> system.l2c.Writeback_accesses::total 1542135 # number of Writeback accesses(hits+misses)
127,128c127,128
< system.l2c.demand_accesses::cpu.data 1620409 # number of demand (read+write) accesses
< system.l2c.demand_accesses::total 2419875 # number of demand (read+write) accesses
---
> system.l2c.demand_accesses::cpu.data 1620410 # number of demand (read+write) accesses
> system.l2c.demand_accesses::total 2419876 # number of demand (read+write) accesses
132,133c132,133
< system.l2c.overall_accesses::cpu.data 1620409 # number of overall (read+write) accesses
< system.l2c.overall_accesses::total 2419875 # number of overall (read+write) accesses
---
> system.l2c.overall_accesses::cpu.data 1620410 # number of overall (read+write) accesses
> system.l2c.overall_accesses::total 2419876 # number of overall (read+write) accesses
360,362c360,362
< system.cpu.committedInsts 138165779 # Number of instructions committed
< system.cpu.committedOps 265203823 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 249613018 # Number of integer alu accesses
---
> system.cpu.committedInsts 138165780 # Number of instructions committed
> system.cpu.committedOps 265203824 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 249613019 # Number of integer alu accesses
365,366c365,366
< system.cpu.num_conditional_control_insts 24887740 # number of instructions that are conditional controls
< system.cpu.num_int_insts 249613018 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 24887741 # number of instructions that are conditional controls
> system.cpu.num_int_insts 249613019 # number of integer instructions
368,369c368,369
< system.cpu.num_int_register_reads 778264797 # number of times the integer registers were read
< system.cpu.num_int_register_writes 423017345 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 778264795 # number of times the integer registers were read
> system.cpu.num_int_register_writes 423017346 # number of times the integer registers were written
372,376c372,376
< system.cpu.num_mem_refs 23180618 # number of memory refs
< system.cpu.num_load_insts 14822217 # Number of load instructions
< system.cpu.num_store_insts 8358401 # Number of store instructions
< system.cpu.num_idle_cycles 9771874940.286118 # Number of idle cycles
< system.cpu.num_busy_cycles 611657687.713882 # Number of busy cycles
---
> system.cpu.num_mem_refs 23180616 # number of memory refs
> system.cpu.num_load_insts 14822216 # Number of load instructions
> system.cpu.num_store_insts 8358400 # Number of store instructions
> system.cpu.num_idle_cycles 9771874926.286118 # Number of idle cycles
> system.cpu.num_busy_cycles 611657701.713882 # Number of busy cycles
383c383
< system.cpu.icache.total_refs 158472874 # Total number of references to valid blocks.
---
> system.cpu.icache.total_refs 158472876 # Total number of references to valid blocks.
385,386c385,386
< system.cpu.icache.avg_refs 200.496043 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 160421907000 # Cycle when the warmup percentage was hit.
---
> system.cpu.icache.avg_refs 200.496045 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 160421909000 # Cycle when the warmup percentage was hit.
390,395c390,395
< system.cpu.icache.ReadReq_hits::cpu.inst 158472874 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 158472874 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 158472874 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 158472874 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 158472874 # number of overall hits
< system.cpu.icache.overall_hits::total 158472874 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 158472876 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 158472876 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 158472876 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 158472876 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 158472876 # number of overall hits
> system.cpu.icache.overall_hits::total 158472876 # number of overall hits
402,413c402,413
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780929500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11780929500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11780929500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11780929500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11780929500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11780929500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 159263285 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 159263285 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 159263285 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 159263285 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 159263285 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 159263285 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 11780909500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 11780909500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 11780909500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 11780909500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 11780909500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 11780909500 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 159263287 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 159263287 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 159263287 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 159263287 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 159263287 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 159263287 # number of overall (read+write) accesses
420,425c420,425
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.814710 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14904.814710 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.814710 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14904.814710 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.814710 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14904.814710 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.789407 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14904.789407 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14904.789407 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.789407 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14904.789407 # average overall miss latency
442,447c442,447
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408678500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9408678500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9408678500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9408678500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9408678500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9408678500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9408658500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 9408658500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9408658500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 9408658500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9408658500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 9408658500 # number of overall MSHR miss cycles
454,459c454,459
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.526773 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.526773 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.526773 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.526773 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.526773 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.526773 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11903.501469 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11903.501469 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11903.501469 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 11903.501469 # average overall mshr miss latency
466c466
< system.cpu.itb_walker_cache.warmup_cycle 5164836909000 # Cycle when the warmup percentage was hit.
---
> system.cpu.itb_walker_cache.warmup_cycle 5164836918000 # Cycle when the warmup percentage was hit.
550c550
< system.cpu.dtb_walker_cache.warmup_cycle 5161009068000 # Cycle when the warmup percentage was hit.
---
> system.cpu.dtb_walker_cache.warmup_cycle 5161009077000 # Cycle when the warmup percentage was hit.
625c625
< system.cpu.dcache.replacements 1620697 # number of replacements
---
> system.cpu.dcache.replacements 1620698 # number of replacements
627,629c627,629
< system.cpu.dcache.total_refs 20024819 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1621209 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 12.351781 # Average number of references to valid blocks.
---
> system.cpu.dcache.total_refs 20024816 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1621210 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 12.351772 # Average number of references to valid blocks.
634,643c634,643
< system.cpu.dcache.ReadReq_hits::cpu.data 11989145 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 11989145 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8033493 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8033493 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20022638 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20022638 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20022638 # number of overall hits
< system.cpu.dcache.overall_hits::total 20022638 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1308549 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1308549 # number of ReadReq misses
---
> system.cpu.dcache.ReadReq_hits::cpu.data 11989143 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 11989143 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8033492 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8033492 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20022635 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20022635 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20022635 # number of overall hits
> system.cpu.dcache.overall_hits::total 20022635 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1308550 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1308550 # number of ReadReq misses
646,653c646,653
< system.cpu.dcache.demand_misses::cpu.data 1623421 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1623421 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1623421 # number of overall misses
< system.cpu.dcache.overall_misses::total 1623421 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 19872658500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 19872658500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327760500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 9327760500 # number of WriteReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 1623422 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1623422 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1623422 # number of overall misses
> system.cpu.dcache.overall_misses::total 1623422 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 19872663500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 19872663500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 9327755500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 9327755500 # number of WriteReq miss cycles
658,665c658,665
< system.cpu.dcache.ReadReq_accesses::cpu.data 13297694 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13297694 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8348365 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8348365 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21646059 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21646059 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21646059 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21646059 # number of overall (read+write) accesses
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 13297693 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13297693 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8348364 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8348364 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21646057 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21646057 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21646057 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21646057 # number of overall (read+write) accesses
670,681c670,681
< system.cpu.dcache.demand_miss_rate::cpu.data 0.074998 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.074998 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.074998 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.074998 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.789719 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.789719 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.975774 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.975774 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.966412 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 17986.966412 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.966412 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 17986.966412 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.074999 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.074999 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.074999 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.074999 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15186.781934 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 15186.781934 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29623.959895 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 29623.959895 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 17986.955333 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 17986.955333 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 17986.955333 # average overall miss latency
690,693c690,693
< system.cpu.dcache.writebacks::writebacks 1537686 # number of writebacks
< system.cpu.dcache.writebacks::total 1537686 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308549 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1308549 # number of ReadReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 1537687 # number of writebacks
> system.cpu.dcache.writebacks::total 1537687 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308550 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 1308550 # number of ReadReq MSHR misses
696,707c696,707
< system.cpu.dcache.demand_mshr_misses::cpu.data 1623421 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1623421 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1623421 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1623421 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15946961002 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 15946961002 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8383141001 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 8383141001 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24330102003 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 24330102003 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24330102003 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 24330102003 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 1623422 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1623422 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1623422 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1623422 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15946963002 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 15946963002 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8383136001 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 8383136001 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24330099003 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 24330099003 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24330099003 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 24330099003 # number of overall MSHR miss cycles
718,729c718,729
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.074998 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.074998 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.751128 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.751128 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.964662 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.964662 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.933151 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.933151 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.933151 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.933151 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.074999 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074999 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.074999 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12186.743343 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12186.743343 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26623.948782 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26623.948782 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14986.922071 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 14986.922071 # average overall mshr miss latency