7,11c7,11
< host_inst_rate 842553 # Simulator instruction rate (inst/s)
< host_op_rate 1624008 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 34079125299 # Simulator tick rate (ticks/s)
< host_mem_usage 659848 # Number of bytes of host memory used
< host_seconds 152.44 # Real time elapsed on the host
---
> host_inst_rate 910377 # Simulator instruction rate (inst/s)
> host_op_rate 1754736 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 36822413305 # Simulator tick rate (ticks/s)
> host_mem_usage 616280 # Number of bytes of host memory used
> host_seconds 141.08 # Real time elapsed on the host
454,455d453
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
494,497c492,493
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786349500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786349500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97918434500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 97918434500 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 95132085000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 95132085000 # number of overall MSHR uncacheable cycles
520,524c516,517
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200168.785920 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200168.785920 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.330939 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.330939 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 169798.069131 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 169798.069131 # average overall mshr uncacheable latency
584,585d576
< system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
< system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
612d602
< system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
672,673d661
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
700d687
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
764,765d750
< system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
< system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
792d776
< system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
953,954d936
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1007,1010c989,990
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2626267500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2626267500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90929022500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90929022500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88302755000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88302755000 # number of overall MSHR uncacheable cycles
1055,1059c1035,1036
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188668.642241 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188668.642241 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.163786 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.163786 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 157608.626974 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157608.626974 # average overall mshr uncacheable latency
1231,1234c1208,1211
< system.iocache.demand_misses::pc.south_bridge.ide 842 # number of demand (read+write) misses
< system.iocache.demand_misses::total 842 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 842 # number of overall misses
< system.iocache.overall_misses::total 842 # number of overall misses
---
> system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses
> system.iocache.demand_misses::total 47562 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses
> system.iocache.overall_misses::total 47562 # number of overall misses
1239,1242c1216,1219
< system.iocache.demand_miss_latency::pc.south_bridge.ide 138525690 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 138525690 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 138525690 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 138525690 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::pc.south_bridge.ide 6006389874 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 6006389874 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 6006389874 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 6006389874 # number of overall miss cycles
1247,1250c1224,1227
< system.iocache.demand_accesses::pc.south_bridge.ide 842 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 842 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 842 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 842 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses
1263,1266c1240,1243
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 164519.821853 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 164519.821853 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126285.477356 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126285.477356 # average overall miss latency
1273,1274d1249
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1281,1284c1256,1259
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 842 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 842 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 842 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 842 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses
1289,1292c1264,1267
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 96425690 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 96425690 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3626485146 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3626485146 # number of overall MSHR miss cycles
1305,1309c1280,1283
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency
< host_inst_rate 842553 # Simulator instruction rate (inst/s)
< host_op_rate 1624008 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 34079125299 # Simulator tick rate (ticks/s)
< host_mem_usage 659848 # Number of bytes of host memory used
< host_seconds 152.44 # Real time elapsed on the host
---
> host_inst_rate 910377 # Simulator instruction rate (inst/s)
> host_op_rate 1754736 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 36822413305 # Simulator tick rate (ticks/s)
> host_mem_usage 616280 # Number of bytes of host memory used
> host_seconds 141.08 # Real time elapsed on the host
454,455d453
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
494,497c492,493
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786349500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786349500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97918434500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 97918434500 # number of overall MSHR uncacheable cycles
---
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 95132085000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 95132085000 # number of overall MSHR uncacheable cycles
520,524c516,517
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200168.785920 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200168.785920 # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174771.330939 # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174771.330939 # average overall mshr uncacheable latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 169798.069131 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 169798.069131 # average overall mshr uncacheable latency
584,585d576
< system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
< system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
612d602
< system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
672,673d661
< system.cpu.icache.fast_writes 0 # number of fast writes performed
< system.cpu.icache.cache_copies 0 # number of cache copies performed
700d687
< system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
764,765d750
< system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
< system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
792d776
< system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
953,954d936
< system.cpu.l2cache.fast_writes 0 # number of fast writes performed
< system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1007,1010c989,990
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2626267500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2626267500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90929022500 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90929022500 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88302755000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88302755000 # number of overall MSHR uncacheable cycles
1055,1059c1035,1036
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188668.642241 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188668.642241 # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162296.163786 # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162296.163786 # average overall mshr uncacheable latency
< system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 157608.626974 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157608.626974 # average overall mshr uncacheable latency
1231,1234c1208,1211
< system.iocache.demand_misses::pc.south_bridge.ide 842 # number of demand (read+write) misses
< system.iocache.demand_misses::total 842 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 842 # number of overall misses
< system.iocache.overall_misses::total 842 # number of overall misses
---
> system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses
> system.iocache.demand_misses::total 47562 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses
> system.iocache.overall_misses::total 47562 # number of overall misses
1239,1242c1216,1219
< system.iocache.demand_miss_latency::pc.south_bridge.ide 138525690 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 138525690 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 138525690 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 138525690 # number of overall miss cycles
---
> system.iocache.demand_miss_latency::pc.south_bridge.ide 6006389874 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 6006389874 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 6006389874 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 6006389874 # number of overall miss cycles
1247,1250c1224,1227
< system.iocache.demand_accesses::pc.south_bridge.ide 842 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 842 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 842 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 842 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses
1263,1266c1240,1243
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 164519.821853 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 164519.821853 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 164519.821853 # average overall miss latency
---
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 126285.477356 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 126285.477356 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 126285.477356 # average overall miss latency
1273,1274d1249
< system.iocache.fast_writes 0 # number of fast writes performed
< system.iocache.cache_copies 0 # number of cache copies performed
1281,1284c1256,1259
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 842 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 842 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 842 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 842 # number of overall MSHR misses
---
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses
1289,1292c1264,1267
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 96425690 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96425690 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 96425690 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 3626485146 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 3626485146 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 3626485146 # number of overall MSHR miss cycles
1305,1309c1280,1283
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114519.821853 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 114519.821853 # average overall mshr miss latency
< system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 76247.532610 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 76247.532610 # average overall mshr miss latency