7,11c7,11
< host_inst_rate 858252 # Simulator instruction rate (inst/s)
< host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 34581252938 # Simulator tick rate (ticks/s)
< host_mem_usage 653812 # Number of bytes of host memory used
< host_seconds 149.93 # Real time elapsed on the host
---
> host_inst_rate 812427 # Simulator instruction rate (inst/s)
> host_op_rate 1566083 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 32734861616 # Simulator tick rate (ticks/s)
> host_mem_usage 599680 # Number of bytes of host memory used
> host_seconds 158.39 # Real time elapsed on the host
58c58
< system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 1619 # Number of requests that are neither read nor write
262,263c262,263
< system.physmem.totQLat 1425327951 # Total ticks spent queuing
< system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 1425306951 # Total ticks spent queuing
> system.physmem.totMemAccLat 4315600701 # Total ticks spent from burst creation until serviced by the DRAM
265c265
< system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 9246.29 # Average queueing delay per DRAM burst
267c267
< system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 27996.29 # Average memory access latency per DRAM burst
289,291c289,291
< system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ)
---
> system.physmem_0.actBackEnergy 133930593495 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 2993365419750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 3467346235185 # Total energy per rank (pJ)
293c293
< system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 4979642480610 # Time in different power states
296c296
< system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 31977087390 # Time in different power states
414,419c414,419
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149973597 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 12149973597 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 24985949815 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 24985949815 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 24985949815 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 24985949815 # number of overall miss cycles
442,447c442,447
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.674465 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.674465 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.768935 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 20287.768935 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.372541 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 15284.372541 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.737593 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.737593 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.785581 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 20287.785581 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.385082 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 15284.385082 # average overall miss latency
475a476,481
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses
478,479c484,485
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117308860 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117308860 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117329359 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117329359 # number of WriteReq MSHR miss cycles
482,485c488,491
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586067642 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 22586067642 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213365142 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 28213365142 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586088141 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 22586088141 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213385641 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28213385641 # number of overall MSHR miss cycles
504,505c510,511
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.728286 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.728286 # average WriteReq mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.793240 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.793240 # average WriteReq mshr miss latency
508,517c514,523
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18480.995089 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 18480.995089 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.410861 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.410861 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18481.011862 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 18481.011862 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.423474 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.423474 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 164165.785509 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164165.785509 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186353.370221 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186353.370221 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 164690.242353 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 164690.242353 # average overall mshr uncacheable latency
635,640c641,646
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253089237 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11253089237 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11253089237 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11253089237 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11253089237 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11253089237 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253068237 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 11253068237 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 11253068237 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 11253068237 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 11253068237 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 11253068237 # number of overall miss cycles
653,658c659,664
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.114112 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14155.114112 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14155.114112 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14155.114112 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.087696 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14155.087696 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14155.087696 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14155.087696 # average overall miss latency
673,678c679,684
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055827763 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 10055827763 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055827763 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 10055827763 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055827763 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 10055827763 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055806763 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 10055806763 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055806763 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 10055806763 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055806763 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 10055806763 # number of overall MSHR miss cycles
685,690c691,696
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.094526 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.094526 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.068111 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.068111 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency
815,816c821,822
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits
---
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 316 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 316 # number of UpgradeReq hits
833,834c839,840
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1357 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1357 # number of UpgradeReq misses
---
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1358 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1358 # number of UpgradeReq misses
846c852
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049449751 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049428751 # number of ReadReq miss cycles
848,850c854,856
< system.cpu.l2cache.ReadReq_miss_latency::total 3391250783 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21334859 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 21334859 # number of UpgradeReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 3391229783 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21365858 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 21365858 # number of UpgradeReq miss cycles
854c860
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1049449751 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1049428751 # number of demand (read+write) miss cycles
856c862
< system.cpu.l2cache.demand_miss_latency::total 12043737754 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 12043716754 # number of demand (read+write) miss cycles
858c864
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1049449751 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1049428751 # number of overall miss cycles
860c866
< system.cpu.l2cache.overall_miss_latency::total 12043737754 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 12043716754 # number of overall miss cycles
886,887c892,893
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.810633 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.810633 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.811231 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.811231 # miss rate for UpgradeReq accesses
899c905
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81120.024040 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81118.400788 # average ReadReq miss latency
901,903c907,909
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.725591 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15722.077377 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15722.077377 # average UpgradeReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.219079 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15733.326951 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15733.326951 # average UpgradeReq miss latency
907c913
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency
909c915
< system.cpu.l2cache.demand_avg_miss_latency::total 77836.115051 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 77835.979332 # average overall miss latency
911c917
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency
913c919
< system.cpu.l2cache.overall_avg_miss_latency::total 77836.115051 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 77835.979332 # average overall miss latency
928,929c934,935
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1357 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1358 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 1358 # number of UpgradeReq MSHR misses
939a946,951
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses
941c953
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887274749 # number of ReadReq MSHR miss cycles
943,945c955,957
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872181717 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872160717 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24705840 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24705840 # number of UpgradeReq MSHR miss cycles
949c961
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887295749 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887274749 # number of demand (read+write) MSHR miss cycles
951c963
< system.cpu.l2cache.demand_mshr_miss_latency::total 10108406746 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 10108385746 # number of demand (read+write) MSHR miss cycles
953c965
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887274749 # number of overall MSHR miss cycles
955c967
< system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 10108385746 # number of overall MSHR miss cycles
966,967c978,979
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.810633 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.810633 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811231 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811231 # mshr miss rate for UpgradeReq accesses
979c991
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68585.896962 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68584.273711 # average ReadReq mshr miss latency
981,983c993,995
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.970019 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18193.322771 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18193.322771 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.463507 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18192.812960 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18192.812960 # average UpgradeReq mshr miss latency
987c999
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency
989c1001
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency
991c1003
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency
993,999c1005,1011
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149863.747625 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149863.747625 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173260.311871 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173260.311871 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150416.781604 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150416.781604 # average overall mshr uncacheable latency
1010a1023
> system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution
1021,1024c1034,1037
< system.cpu.toL2Bus.snoops 54167 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram
---
> system.cpu.toL2Bus.snoops 55819 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4616997 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.010670 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.102742 # Request fanout histogram
1029,1030c1042,1043
< system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 4567735 98.93% 98.93% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 49262 1.07% 100.00% # Request fanout histogram
1034c1047
< system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 4616997 # Request fanout histogram
1041c1054
< system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3047835587 # Layer occupancy (ticks)
1252,1253c1265,1266
< system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 1637 # Transaction distribution
1262,1263c1275,1276
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392332 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569788 # Packet count per connected master and slave (bytes)
1266c1279
< system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1714479 # Packet count per connected master and slave (bytes)
1277,1279c1290,1292
< system.membus.snoop_fanout::samples 331203 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 921584 # Request fanout histogram
> system.membus.snoop_fanout::mean 1.001793 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.042301 # Request fanout histogram
1282,1283c1295,1296
< system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 919932 99.82% 99.82% # Request fanout histogram
> system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram
1286,1287c1299,1300
< system.membus.snoop_fanout::max_value 1 # Request fanout histogram
< system.membus.snoop_fanout::total 331203 # Request fanout histogram
---
> system.membus.snoop_fanout::max_value 2 # Request fanout histogram
> system.membus.snoop_fanout::total 921584 # Request fanout histogram
1294c1307
< system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks)
---
> system.membus.reqLayer3.occupancy 1034075968 # Layer occupancy (ticks)
1298c1311
< system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 2159262414 # Layer occupancy (ticks)
< host_inst_rate 858252 # Simulator instruction rate (inst/s)
< host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 34581252938 # Simulator tick rate (ticks/s)
< host_mem_usage 653812 # Number of bytes of host memory used
< host_seconds 149.93 # Real time elapsed on the host
---
> host_inst_rate 812427 # Simulator instruction rate (inst/s)
> host_op_rate 1566083 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 32734861616 # Simulator tick rate (ticks/s)
> host_mem_usage 599680 # Number of bytes of host memory used
> host_seconds 158.39 # Real time elapsed on the host
58c58
< system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write
---
> system.physmem.neitherReadNorWriteReqs 1619 # Number of requests that are neither read nor write
262,263c262,263
< system.physmem.totQLat 1425327951 # Total ticks spent queuing
< system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 1425306951 # Total ticks spent queuing
> system.physmem.totMemAccLat 4315600701 # Total ticks spent from burst creation until serviced by the DRAM
265c265
< system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 9246.29 # Average queueing delay per DRAM burst
267c267
< system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 27996.29 # Average memory access latency per DRAM burst
289,291c289,291
< system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ)
---
> system.physmem_0.actBackEnergy 133930593495 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 2993365419750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 3467346235185 # Total energy per rank (pJ)
293c293
< system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states
---
> system.physmem_0.memoryStateTime::IDLE 4979642480610 # Time in different power states
296c296
< system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 31977087390 # Time in different power states
414,419c414,419
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149973597 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 12149973597 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 24985949815 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 24985949815 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 24985949815 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 24985949815 # number of overall miss cycles
442,447c442,447
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.674465 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.674465 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.768935 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 20287.768935 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.372541 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 15284.372541 # average overall miss latency
---
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.737593 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.737593 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.785581 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 20287.785581 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.385082 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 15284.385082 # average overall miss latency
475a476,481
> system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable
> system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses
> system.cpu.dcache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses
478,479c484,485
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117308860 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117308860 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117329359 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117329359 # number of WriteReq MSHR miss cycles
482,485c488,491
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586067642 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 22586067642 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213365142 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 28213365142 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586088141 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 22586088141 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213385641 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 28213385641 # number of overall MSHR miss cycles
504,505c510,511
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.728286 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.728286 # average WriteReq mshr miss latency
---
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.793240 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.793240 # average WriteReq mshr miss latency
508,517c514,523
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18480.995089 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 18480.995089 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.410861 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.410861 # average overall mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18481.011862 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 18481.011862 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.423474 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.423474 # average overall mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 164165.785509 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 164165.785509 # average ReadReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 186353.370221 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186353.370221 # average WriteReq mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 164690.242353 # average overall mshr uncacheable latency
> system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 164690.242353 # average overall mshr uncacheable latency
635,640c641,646
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253089237 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11253089237 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11253089237 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11253089237 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11253089237 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11253089237 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253068237 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 11253068237 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 11253068237 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 11253068237 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 11253068237 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 11253068237 # number of overall miss cycles
653,658c659,664
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.114112 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14155.114112 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14155.114112 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14155.114112 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.087696 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14155.087696 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14155.087696 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.087696 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14155.087696 # average overall miss latency
673,678c679,684
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055827763 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 10055827763 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055827763 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 10055827763 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055827763 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 10055827763 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055806763 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 10055806763 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055806763 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 10055806763 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055806763 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 10055806763 # number of overall MSHR miss cycles
685,690c691,696
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.094526 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.094526 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.068111 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.068111 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.068111 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.068111 # average overall mshr miss latency
815,816c821,822
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits
---
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 316 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 316 # number of UpgradeReq hits
833,834c839,840
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1357 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1357 # number of UpgradeReq misses
---
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1358 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1358 # number of UpgradeReq misses
846c852
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049449751 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049428751 # number of ReadReq miss cycles
848,850c854,856
< system.cpu.l2cache.ReadReq_miss_latency::total 3391250783 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21334859 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 21334859 # number of UpgradeReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 3391229783 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21365858 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 21365858 # number of UpgradeReq miss cycles
854c860
< system.cpu.l2cache.demand_miss_latency::cpu.inst 1049449751 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 1049428751 # number of demand (read+write) miss cycles
856c862
< system.cpu.l2cache.demand_miss_latency::total 12043737754 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 12043716754 # number of demand (read+write) miss cycles
858c864
< system.cpu.l2cache.overall_miss_latency::cpu.inst 1049449751 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 1049428751 # number of overall miss cycles
860c866
< system.cpu.l2cache.overall_miss_latency::total 12043737754 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 12043716754 # number of overall miss cycles
886,887c892,893
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.810633 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.810633 # miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.811231 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.811231 # miss rate for UpgradeReq accesses
899c905
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81120.024040 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81118.400788 # average ReadReq miss latency
901,903c907,909
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.725591 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15722.077377 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15722.077377 # average UpgradeReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.219079 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15733.326951 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15733.326951 # average UpgradeReq miss latency
907c913
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency
909c915
< system.cpu.l2cache.demand_avg_miss_latency::total 77836.115051 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 77835.979332 # average overall miss latency
911c917
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81118.400788 # average overall miss latency
913c919
< system.cpu.l2cache.overall_avg_miss_latency::total 77836.115051 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 77835.979332 # average overall miss latency
928,929c934,935
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1357 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses
---
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1358 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 1358 # number of UpgradeReq MSHR misses
939a946,951
> system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 574812 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.ReadReq_mshr_uncacheable::total 574812 # number of ReadReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13916 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable
> system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses
> system.cpu.l2cache.overall_mshr_uncacheable_misses::total 588728 # number of overall MSHR uncacheable misses
941c953
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887274749 # number of ReadReq MSHR miss cycles
943,945c955,957
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872181717 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # number of UpgradeReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872160717 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24705840 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24705840 # number of UpgradeReq MSHR miss cycles
949c961
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887295749 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887274749 # number of demand (read+write) MSHR miss cycles
951c963
< system.cpu.l2cache.demand_mshr_miss_latency::total 10108406746 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 10108385746 # number of demand (read+write) MSHR miss cycles
953c965
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887274749 # number of overall MSHR miss cycles
955c967
< system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 10108385746 # number of overall MSHR miss cycles
966,967c978,979
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.810633 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.810633 # mshr miss rate for UpgradeReq accesses
---
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811231 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811231 # mshr miss rate for UpgradeReq accesses
979c991
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68585.896962 # average ReadReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68584.273711 # average ReadReq mshr miss latency
981,983c993,995
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.970019 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18193.322771 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18193.322771 # average UpgradeReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.463507 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18192.812960 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18192.812960 # average UpgradeReq mshr miss latency
987c999
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency
989c1001
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency
991c1003
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68584.273711 # average overall mshr miss latency
993,999c1005,1011
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
< system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149863.747625 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149863.747625 # average ReadReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173260.311871 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173260.311871 # average WriteReq mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150416.781604 # average overall mshr uncacheable latency
> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150416.781604 # average overall mshr uncacheable latency
1010a1023
> system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution
1021,1024c1034,1037
< system.cpu.toL2Bus.snoops 54167 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram
---
> system.cpu.toL2Bus.snoops 55819 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4616997 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.010670 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.102742 # Request fanout histogram
1029,1030c1042,1043
< system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 4567735 98.93% 98.93% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 49262 1.07% 100.00% # Request fanout histogram
1034c1047
< system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 4616997 # Request fanout histogram
1041c1054
< system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3047835587 # Layer occupancy (ticks)
1252,1253c1265,1266
< system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 1637 # Transaction distribution
1262,1263c1275,1276
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392332 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569788 # Packet count per connected master and slave (bytes)
1266c1279
< system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count::total 1714479 # Packet count per connected master and slave (bytes)
1277,1279c1290,1292
< system.membus.snoop_fanout::samples 331203 # Request fanout histogram
< system.membus.snoop_fanout::mean 1 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 921584 # Request fanout histogram
> system.membus.snoop_fanout::mean 1.001793 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0.042301 # Request fanout histogram
1282,1283c1295,1296
< system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 919932 99.82% 99.82% # Request fanout histogram
> system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram
1286,1287c1299,1300
< system.membus.snoop_fanout::max_value 1 # Request fanout histogram
< system.membus.snoop_fanout::total 331203 # Request fanout histogram
---
> system.membus.snoop_fanout::max_value 2 # Request fanout histogram
> system.membus.snoop_fanout::total 921584 # Request fanout histogram
1294c1307
< system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks)
---
> system.membus.reqLayer3.occupancy 1034075968 # Layer occupancy (ticks)
1298c1311
< system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 2159262414 # Layer occupancy (ticks)