3,5c3,5
< sim_seconds 5.194411 # Number of seconds simulated
< sim_ticks 5194410635000 # Number of ticks simulated
< final_tick 5194410635000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.196466 # Number of seconds simulated
> sim_ticks 5196466347000 # Number of ticks simulated
> final_tick 5196466347000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1318005 # Simulator instruction rate (inst/s)
< host_op_rate 2540682 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 53310327218 # Simulator tick rate (ticks/s)
< host_mem_usage 594964 # Number of bytes of host memory used
< host_seconds 97.44 # Real time elapsed on the host
< sim_insts 128422722 # Number of instructions simulated
< sim_ops 247557000 # Number of ops (including micro ops) simulated
---
> host_inst_rate 596082 # Simulator instruction rate (inst/s)
> host_op_rate 1149061 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 24120553188 # Simulator tick rate (ticks/s)
> host_mem_usage 596696 # Number of bytes of host memory used
> host_seconds 215.44 # Real time elapsed on the host
> sim_insts 128418244 # Number of instructions simulated
> sim_ops 247550593 # Number of ops (including micro ops) simulated
18,19c18,19
< system.physmem.bytes_read::cpu.inst 829440 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9099264 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 828416 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9035072 # Number of bytes read from this memory
21,26c21,25
< system.physmem.bytes_read::total 9957440 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 829440 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 829440 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 5149824 # Number of bytes written to this memory
< system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
< system.physmem.bytes_written::total 8139904 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 9892224 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 828416 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 828416 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 8113920 # Number of bytes written to this memory
> system.physmem.bytes_written::total 8113920 # Number of bytes written to this memory
29,30c28,29
< system.physmem.num_reads::cpu.inst 12960 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 142176 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 12944 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 141173 # Number of read requests responded to by this memory
32,35c31,33
< system.physmem.num_reads::total 155585 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 80466 # Number of write requests responded to by this memory
< system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 127186 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 154566 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 126780 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 126780 # Number of write requests responded to by this memory
38,47c36,44
< system.physmem.bw_read::cpu.inst 159679 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1751741 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1916953 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 159679 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 159679 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 991416 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::pc.south_bridge.ide 575634 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1567051 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 991416 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 159419 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1738695 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::pc.south_bridge.ide 5456 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1903644 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 159419 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 159419 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1561430 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1561430 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1561430 # Total bandwidth to/from this memory (bytes/s)
50,97c47,94
< system.physmem.bw_total::cpu.inst 159679 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1751741 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 581092 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3484003 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 155585 # Number of read requests accepted
< system.physmem.writeReqs 127186 # Number of write requests accepted
< system.physmem.readBursts 155585 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 127186 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 9942720 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 14720 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8138624 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 9957440 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8139904 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 230 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
< system.physmem.neitherReadNorWriteReqs 1629 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 10087 # Per bank write bursts
< system.physmem.perBankRdBursts::1 9924 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10111 # Per bank write bursts
< system.physmem.perBankRdBursts::3 9612 # Per bank write bursts
< system.physmem.perBankRdBursts::4 10046 # Per bank write bursts
< system.physmem.perBankRdBursts::5 9507 # Per bank write bursts
< system.physmem.perBankRdBursts::6 9544 # Per bank write bursts
< system.physmem.perBankRdBursts::7 9545 # Per bank write bursts
< system.physmem.perBankRdBursts::8 9177 # Per bank write bursts
< system.physmem.perBankRdBursts::9 9299 # Per bank write bursts
< system.physmem.perBankRdBursts::10 9268 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9485 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9621 # Per bank write bursts
< system.physmem.perBankRdBursts::13 9970 # Per bank write bursts
< system.physmem.perBankRdBursts::14 10158 # Per bank write bursts
< system.physmem.perBankRdBursts::15 10001 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8060 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7801 # Per bank write bursts
< system.physmem.perBankWrBursts::2 7998 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7765 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8116 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7896 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7662 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7717 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7519 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7838 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7675 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7654 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8493 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8626 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8402 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7944 # Per bank write bursts
---
> system.physmem.bw_total::cpu.inst 159419 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1738695 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 5456 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3465075 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 154566 # Number of read requests accepted
> system.physmem.writeReqs 173500 # Number of write requests accepted
> system.physmem.readBursts 154566 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 173500 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 9886080 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue
> system.physmem.bytesWritten 10951744 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 9892224 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 11104000 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 2352 # Number of DRAM write bursts merged with an existing one
> system.physmem.neitherReadNorWriteReqs 1595 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 9833 # Per bank write bursts
> system.physmem.perBankRdBursts::1 9504 # Per bank write bursts
> system.physmem.perBankRdBursts::2 9844 # Per bank write bursts
> system.physmem.perBankRdBursts::3 9497 # Per bank write bursts
> system.physmem.perBankRdBursts::4 9570 # Per bank write bursts
> system.physmem.perBankRdBursts::5 9679 # Per bank write bursts
> system.physmem.perBankRdBursts::6 9540 # Per bank write bursts
> system.physmem.perBankRdBursts::7 9680 # Per bank write bursts
> system.physmem.perBankRdBursts::8 9214 # Per bank write bursts
> system.physmem.perBankRdBursts::9 9453 # Per bank write bursts
> system.physmem.perBankRdBursts::10 9241 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9575 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9600 # Per bank write bursts
> system.physmem.perBankRdBursts::13 10182 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10246 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9812 # Per bank write bursts
> system.physmem.perBankWrBursts::0 10679 # Per bank write bursts
> system.physmem.perBankWrBursts::1 10594 # Per bank write bursts
> system.physmem.perBankWrBursts::2 10884 # Per bank write bursts
> system.physmem.perBankWrBursts::3 10241 # Per bank write bursts
> system.physmem.perBankWrBursts::4 10237 # Per bank write bursts
> system.physmem.perBankWrBursts::5 10759 # Per bank write bursts
> system.physmem.perBankWrBursts::6 10579 # Per bank write bursts
> system.physmem.perBankWrBursts::7 10814 # Per bank write bursts
> system.physmem.perBankWrBursts::8 10762 # Per bank write bursts
> system.physmem.perBankWrBursts::9 11220 # Per bank write bursts
> system.physmem.perBankWrBursts::10 10499 # Per bank write bursts
> system.physmem.perBankWrBursts::11 10145 # Per bank write bursts
> system.physmem.perBankWrBursts::12 11054 # Per bank write bursts
> system.physmem.perBankWrBursts::13 11426 # Per bank write bursts
> system.physmem.perBankWrBursts::14 10852 # Per bank write bursts
> system.physmem.perBankWrBursts::15 10376 # Per bank write bursts
99,100c96,97
< system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
< system.physmem.totGap 5194410571500 # Total gap between requests
---
> system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
> system.physmem.totGap 5196466283500 # Total gap between requests
107c104
< system.physmem.readPktSize::6 155585 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 154566 # Read request sizes (log2)
114,116c111,113
< system.physmem.writePktSize::6 127186 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 151951 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2969 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 173500 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 151257 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2780 # What read queue length does an incoming req see
118,120c115,117
< system.physmem.rdQLenPdf::3 57 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 35 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see
162,228c159,225
< system.physmem.wrQLenPdf::15 2364 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3127 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6124 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6381 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6410 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 7140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7424 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8105 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8845 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 9948 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9118 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8439 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7706 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7452 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6421 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6193 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6287 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6139 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 216 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 191 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 191 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 204 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 214 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 184 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 154 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 61 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 12 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 55971 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 323.047292 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 191.702498 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 334.763320 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 19466 34.78% 34.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 13850 24.74% 59.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5737 10.25% 69.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3527 6.30% 76.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2331 4.16% 80.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1635 2.92% 83.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1137 2.03% 85.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 981 1.75% 86.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7307 13.05% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 55971 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5932 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 26.188806 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 621.686791 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 5931 99.98% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2693 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 5142 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 8647 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 9871 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 10255 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 11236 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 11623 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 12575 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 12144 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 12750 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 11495 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 10962 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 9581 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 8954 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 7428 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 7073 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 7063 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6898 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 506 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 442 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 395 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 348 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 261 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 267 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 241 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 153 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 13 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 58532 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 356.006287 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 207.370190 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 358.892439 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 19432 33.20% 33.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 13728 23.45% 56.65% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5812 9.93% 66.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3460 5.91% 72.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2276 3.89% 76.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1654 2.83% 79.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1160 1.98% 81.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1010 1.73% 82.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 10000 17.08% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 58532 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 6314 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 24.461831 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 602.615488 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 6313 99.98% 99.98% # Reads before turning the bus around for writes
230,266c227,287
< system.physmem.rdPerTurnAround::total 5932 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5932 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 21.437289 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.381245 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 13.855005 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4878 82.23% 82.23% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 44 0.74% 82.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 36 0.61% 83.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 295 4.97% 88.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 297 5.01% 93.56% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 20 0.34% 93.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 18 0.30% 94.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 14 0.24% 94.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 21 0.35% 94.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 5 0.08% 94.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 1 0.02% 94.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 3 0.05% 94.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 234 3.94% 98.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 3 0.05% 98.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 4 0.07% 99.01% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::76-79 4 0.07% 99.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::80-83 9 0.15% 99.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 12 0.20% 99.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 5 0.08% 99.54% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.03% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 8 0.13% 99.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 2 0.03% 99.75% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 10 0.17% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::140-143 3 0.05% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::200-203 1 0.02% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 5932 # Writes before turning the bus around for reads
< system.physmem.totQLat 1472209750 # Total ticks spent queuing
< system.physmem.totMemAccLat 4385116000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 776775000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9476.42 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 6314 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 6314 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 27.101837 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 21.618222 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 26.504313 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 4900 77.61% 77.61% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 45 0.71% 78.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 20 0.32% 78.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 269 4.26% 82.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 162 2.57% 85.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 59 0.93% 86.40% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 31 0.49% 86.89% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 30 0.48% 87.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 184 2.91% 90.28% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 10 0.16% 90.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 13 0.21% 90.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 9 0.14% 90.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 33 0.52% 91.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 21 0.33% 91.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 17 0.27% 91.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 41 0.65% 92.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 96 1.52% 94.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 7 0.11% 94.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 8 0.13% 94.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 18 0.29% 94.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 170 2.69% 97.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 5 0.08% 97.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 12 0.19% 97.56% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 4 0.06% 97.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 20 0.32% 97.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 4 0.06% 98.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 7 0.11% 98.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::124-127 6 0.10% 98.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 38 0.60% 98.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 9 0.14% 98.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::136-139 3 0.05% 99.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 7 0.11% 99.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::144-147 12 0.19% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::148-151 3 0.05% 99.35% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::152-155 2 0.03% 99.38% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::156-159 3 0.05% 99.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::160-163 7 0.11% 99.54% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::164-167 3 0.05% 99.59% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::168-171 1 0.02% 99.60% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::172-175 2 0.03% 99.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::176-179 3 0.05% 99.68% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::180-183 4 0.06% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::184-187 2 0.03% 99.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::188-191 1 0.02% 99.79% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::192-195 4 0.06% 99.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::200-203 3 0.05% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::204-207 1 0.02% 99.92% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::216-219 1 0.02% 99.94% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::220-223 1 0.02% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::228-231 2 0.03% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::248-251 1 0.02% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 6314 # Writes before turning the bus around for reads
> system.physmem.totQLat 1460181000 # Total ticks spent queuing
> system.physmem.totMemAccLat 4356493500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 772350000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9452.85 # Average queueing delay per DRAM burst
268,272c289,293
< system.physmem.avgMemAccLat 28226.42 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28202.85 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s
276c297
< system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
---
> system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
278,280c299,301
< system.physmem.avgWrQLen 21.88 # Average write queue length when enqueuing
< system.physmem.readRowHits 127796 # Number of row buffer hits during reads
< system.physmem.writeRowHits 98753 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 21.87 # Average write queue length when enqueuing
> system.physmem.readRowHits 127064 # Number of row buffer hits during reads
> system.physmem.writeRowHits 139994 # Number of row buffer hits during writes
282,286c303,307
< system.physmem.writeRowHitRate 77.64 # Row buffer hit rate for writes
< system.physmem.avgGap 18369672.18 # Average gap between requests
< system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 4972956663750 # Time in different power states
< system.physmem.memoryStateTime::REF 173452760000 # Time in different power states
---
> system.physmem.writeRowHitRate 81.80 # Row buffer hit rate for writes
> system.physmem.avgGap 15839697.75 # Average gap between requests
> system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 4974958806500 # Time in different power states
> system.physmem.memoryStateTime::REF 173521400000 # Time in different power states
288c309
< system.physmem.memoryStateTime::ACT 48001096250 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 47986025500 # Time in different power states
290,307c311,328
< system.physmem.actEnergy::0 211543920 # Energy for activate commands per rank (pJ)
< system.physmem.actEnergy::1 211596840 # Energy for activate commands per rank (pJ)
< system.physmem.preEnergy::0 115425750 # Energy for precharge commands per rank (pJ)
< system.physmem.preEnergy::1 115454625 # Energy for precharge commands per rank (pJ)
< system.physmem.readEnergy::0 611332800 # Energy for read commands per rank (pJ)
< system.physmem.readEnergy::1 600428400 # Energy for read commands per rank (pJ)
< system.physmem.writeEnergy::0 408337200 # Energy for write commands per rank (pJ)
< system.physmem.writeEnergy::1 415698480 # Energy for write commands per rank (pJ)
< system.physmem.refreshEnergy::0 339273598560 # Energy for refresh commands per rank (pJ)
< system.physmem.refreshEnergy::1 339273598560 # Energy for refresh commands per rank (pJ)
< system.physmem.actBackEnergy::0 134393532390 # Energy for active background per rank (pJ)
< system.physmem.actBackEnergy::1 134240531850 # Energy for active background per rank (pJ)
< system.physmem.preBackEnergy::0 2998756974750 # Energy for precharge background per rank (pJ)
< system.physmem.preBackEnergy::1 2998891185750 # Energy for precharge background per rank (pJ)
< system.physmem.totalEnergy::0 3473770745370 # Total energy per rank (pJ)
< system.physmem.totalEnergy::1 3473748494505 # Total energy per rank (pJ)
< system.physmem.averagePower::0 668.751736 # Core power per rank (mW)
< system.physmem.averagePower::1 668.747452 # Core power per rank (mW)
---
> system.physmem.actEnergy::0 218272320 # Energy for activate commands per rank (pJ)
> system.physmem.actEnergy::1 224229600 # Energy for activate commands per rank (pJ)
> system.physmem.preEnergy::0 119097000 # Energy for precharge commands per rank (pJ)
> system.physmem.preEnergy::1 122347500 # Energy for precharge commands per rank (pJ)
> system.physmem.readEnergy::0 601746600 # Energy for read commands per rank (pJ)
> system.physmem.readEnergy::1 603111600 # Energy for read commands per rank (pJ)
> system.physmem.writeEnergy::0 549419760 # Energy for write commands per rank (pJ)
> system.physmem.writeEnergy::1 559444320 # Energy for write commands per rank (pJ)
> system.physmem.refreshEnergy::0 339407858400 # Energy for refresh commands per rank (pJ)
> system.physmem.refreshEnergy::1 339407858400 # Energy for refresh commands per rank (pJ)
> system.physmem.actBackEnergy::0 134224004700 # Energy for active background per rank (pJ)
> system.physmem.actBackEnergy::1 134453555955 # Energy for active background per rank (pJ)
> system.physmem.preBackEnergy::0 3000139025250 # Energy for precharge background per rank (pJ)
> system.physmem.preBackEnergy::1 2999937664500 # Energy for precharge background per rank (pJ)
> system.physmem.totalEnergy::0 3475259424030 # Total energy per rank (pJ)
> system.physmem.totalEnergy::1 3475308211875 # Total energy per rank (pJ)
> system.physmem.averagePower::0 668.773676 # Core power per rank (mW)
> system.physmem.averagePower::1 668.783065 # Core power per rank (mW)
310c331
< system.cpu.numCycles 10388821270 # number of cpu cycles simulated
---
> system.cpu.numCycles 10392932694 # number of cpu cycles simulated
313,315c334,336
< system.cpu.committedInsts 128422722 # Number of instructions committed
< system.cpu.committedOps 247557000 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 232138334 # Number of integer alu accesses
---
> system.cpu.committedInsts 128418244 # Number of instructions committed
> system.cpu.committedOps 247550593 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 232131886 # Number of integer alu accesses
317,319c338,340
< system.cpu.num_func_calls 2301199 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 23183159 # number of instructions that are conditional controls
< system.cpu.num_int_insts 232138334 # number of integer instructions
---
> system.cpu.num_func_calls 2300917 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 23183149 # number of instructions that are conditional controls
> system.cpu.num_int_insts 232131886 # number of integer instructions
321,322c342,343
< system.cpu.num_int_register_reads 434808798 # number of times the integer registers were read
< system.cpu.num_int_register_writes 197991574 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 434791523 # number of times the integer registers were read
> system.cpu.num_int_register_writes 197987761 # number of times the integer registers were written
325,338c346,359
< system.cpu.num_cc_register_reads 132893231 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 95600147 # number of times the CC registers were written
< system.cpu.num_mem_refs 22258678 # number of memory refs
< system.cpu.num_load_insts 13887993 # Number of load instructions
< system.cpu.num_store_insts 8370685 # Number of store instructions
< system.cpu.num_idle_cycles 9791802498.998116 # Number of idle cycles
< system.cpu.num_busy_cycles 597018771.001885 # Number of busy cycles
< system.cpu.not_idle_fraction 0.057467 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.942533 # Percentage of idle cycles
< system.cpu.Branches 26323220 # Number of branches fetched
< system.cpu.op_class::No_OpClass 174807 0.07% 0.07% # Class of executed instruction
< system.cpu.op_class::IntAlu 224862012 90.83% 90.90% # Class of executed instruction
< system.cpu.op_class::IntMult 139985 0.06% 90.96% # Class of executed instruction
< system.cpu.op_class::IntDiv 123095 0.05% 91.01% # Class of executed instruction
---
> system.cpu.num_cc_register_reads 132892118 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 95599960 # number of times the CC registers were written
> system.cpu.num_mem_refs 22255642 # number of memory refs
> system.cpu.num_load_insts 13887148 # Number of load instructions
> system.cpu.num_store_insts 8368494 # Number of store instructions
> system.cpu.num_idle_cycles 9795963958.998116 # Number of idle cycles
> system.cpu.num_busy_cycles 596968735.001885 # Number of busy cycles
> system.cpu.not_idle_fraction 0.057440 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.942560 # Percentage of idle cycles
> system.cpu.Branches 26322824 # Number of branches fetched
> system.cpu.op_class::No_OpClass 174818 0.07% 0.07% # Class of executed instruction
> system.cpu.op_class::IntAlu 224858584 90.83% 90.90% # Class of executed instruction
> system.cpu.op_class::IntMult 140018 0.06% 90.96% # Class of executed instruction
> system.cpu.op_class::IntDiv 123105 0.05% 91.01% # Class of executed instruction
365,366c386,387
< system.cpu.op_class::MemRead 13887993 5.61% 96.62% # Class of executed instruction
< system.cpu.op_class::MemWrite 8370685 3.38% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 13887148 5.61% 96.62% # Class of executed instruction
> system.cpu.op_class::MemWrite 8368494 3.38% 100.00% # Class of executed instruction
369c390
< system.cpu.op_class::total 247558577 # Class of executed instruction
---
> system.cpu.op_class::total 247552167 # Class of executed instruction
372,376c393,397
< system.cpu.dcache.tags.replacements 1622351 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.996907 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 20038370 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1622863 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 12.347543 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 1622836 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.996904 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 20034858 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1623348 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 12.341690 # Average number of references to valid blocks.
378c399
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.996907 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.996904 # Average occupied blocks per requestor
382,384c403,405
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 77 # Occupied blocks per task id
387,445c408,466
< system.cpu.dcache.tags.tag_accesses 88306374 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 88306374 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 11941774 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 11941774 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8035174 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8035174 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 59224 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 59224 # number of SoftPFReq hits
< system.cpu.dcache.demand_hits::cpu.data 19976948 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 19976948 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20036172 # number of overall hits
< system.cpu.dcache.overall_hits::total 20036172 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 907115 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 907115 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 325077 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 325077 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 402500 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 402500 # number of SoftPFReq misses
< system.cpu.dcache.demand_misses::cpu.data 1232192 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1232192 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1634692 # number of overall misses
< system.cpu.dcache.overall_misses::total 1634692 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12725992750 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12725992750 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 11362158354 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 11362158354 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 24088151104 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 24088151104 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 24088151104 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 24088151104 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 12848889 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 12848889 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8360251 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8360251 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 461724 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 461724 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21209140 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21209140 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21670864 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21670864 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070599 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.070599 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038884 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.038884 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871733 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.871733 # miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.058097 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.058097 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14029.084240 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14029.084240 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34952.206259 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34952.206259 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 19549.024100 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 19549.024100 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14735.590010 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14735.590010 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 7616 # number of cycles access was blocked
---
> system.cpu.dcache.tags.tag_accesses 88294796 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 88294796 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 11940626 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 11940626 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8032822 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8032822 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 59222 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 59222 # number of SoftPFReq hits
> system.cpu.dcache.demand_hits::cpu.data 19973448 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 19973448 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20032670 # number of overall hits
> system.cpu.dcache.overall_hits::total 20032670 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 907502 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 907502 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 325247 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 325247 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 402429 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 402429 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 1232749 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1232749 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1635178 # number of overall misses
> system.cpu.dcache.overall_misses::total 1635178 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12738871000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12738871000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 11339051069 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 11339051069 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 24077922069 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 24077922069 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 24077922069 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 24077922069 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 12848128 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 12848128 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8358069 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8358069 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 461651 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 461651 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21206197 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21206197 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21667848 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21667848 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070633 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.070633 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038914 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.038914 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871717 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.871717 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.058132 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.058132 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.075466 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.075466 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14037.292480 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14037.292480 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34862.892107 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34862.892107 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 19531.893410 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 19531.893410 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14724.954757 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14724.954757 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 6197 # number of cycles access was blocked
447c468
< system.cpu.dcache.blocked::no_mshrs 81 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 83 # number of cycles access was blocked
449c470
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.024691 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.662651 # average number of cycles each access was blocked
453,482c474,503
< system.cpu.dcache.writebacks::writebacks 1538923 # number of writebacks
< system.cpu.dcache.writebacks::total 1538923 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 288 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9252 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 9252 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 9540 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 9540 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 9540 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 9540 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906827 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 906827 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315825 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 315825 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402464 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 402464 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1222652 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1222652 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1625116 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1625116 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10904887500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10904887500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10229869846 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10229869846 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337291000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337291000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21134757346 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 21134757346 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26472048346 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26472048346 # number of overall MSHR miss cycles
---
> system.cpu.dcache.writebacks::writebacks 1539435 # number of writebacks
> system.cpu.dcache.writebacks::total 1539435 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 291 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9259 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 9259 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 9550 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 9550 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 9550 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 9550 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907211 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 907211 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315988 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 315988 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402393 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 402393 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1223199 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1223199 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1625592 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1625592 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10916933250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10916933250 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10204146879 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10204146879 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5337559000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5337559000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21121080129 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 21121080129 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26458639129 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26458639129 # number of overall MSHR miss cycles
485,508c506,529
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561690500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561690500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802063500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802063500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070576 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070576 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037777 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037777 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871655 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871655 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057647 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.057647 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074991 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.074991 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12025.322912 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12025.322912 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32390.943864 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32390.943864 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13261.536436 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13261.536436 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17285.995807 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 17285.995807 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16289.328482 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 16289.328482 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2561805000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2561805000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96802178000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 96802178000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070610 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070610 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037806 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037806 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871639 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871639 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057681 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.057681 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075023 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.075023 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12033.510672 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12033.510672 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32292.830357 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32292.830357 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13264.542375 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13264.542375 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17267.084202 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 17267.084202 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16276.309879 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 16276.309879 # average overall mshr miss latency
516,524c537,545
< system.cpu.dtb_walker_cache.tags.replacements 7576 # number of replacements
< system.cpu.dtb_walker_cache.tags.tagsinuse 5.056356 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 13259 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.sampled_refs 7591 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.avg_refs 1.746674 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 5163552885000 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.056356 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316022 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316022 # Average percentage of cache occupancy
---
> system.cpu.dtb_walker_cache.tags.replacements 7764 # number of replacements
> system.cpu.dtb_walker_cache.tags.tagsinuse 5.069200 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 13087 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.sampled_refs 7779 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.avg_refs 1.682350 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 5159703878000 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.069200 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316825 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316825 # Average percentage of cache occupancy
530,567c551,588
< system.cpu.dtb_walker_cache.tags.tag_accesses 52917 # Number of tag accesses
< system.cpu.dtb_walker_cache.tags.data_accesses 52917 # Number of data accesses
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13260 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 13260 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13260 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 13260 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13260 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 13260 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8799 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 8799 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8799 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 8799 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8799 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 8799 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 94478000 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 94478000 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 94478000 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::total 94478000 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 94478000 # number of overall miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::total 94478000 # number of overall miss cycles
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22059 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 22059 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22059 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 22059 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22059 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 22059 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398885 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398885 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398885 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398885 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398885 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398885 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10737.356518 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10737.356518 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10737.356518 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10737.356518 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10737.356518 # average overall miss latency
---
> system.cpu.dtb_walker_cache.tags.tag_accesses 53125 # Number of tag accesses
> system.cpu.dtb_walker_cache.tags.data_accesses 53125 # Number of data accesses
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13088 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 13088 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13088 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 13088 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13088 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 13088 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8983 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 8983 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8983 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 8983 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8983 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 8983 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95259000 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95259000 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95259000 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::total 95259000 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95259000 # number of overall miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::total 95259000 # number of overall miss cycles
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22071 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 22071 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22071 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 22071 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22071 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 22071 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407005 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407005 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407005 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407005 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407005 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407005 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10604.363798 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10604.363798 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10604.363798 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10604.363798 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10604.363798 # average overall miss latency
576,601c597,622
< system.cpu.dtb_walker_cache.writebacks::writebacks 3010 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 3010 # number of writebacks
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8799 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8799 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8799 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::total 8799 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8799 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::total 8799 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76879500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 76879500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 76879500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 76879500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 76879500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 76879500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398885 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398885 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398885 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398885 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8737.299693 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8737.299693 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8737.299693 # average overall mshr miss latency
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 3015 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 3015 # number of writebacks
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8983 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8983 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8983 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::total 8983 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8983 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::total 8983 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77292500 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77292500 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77292500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77292500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77292500 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77292500 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407005 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407005 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407005 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407005 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8604.308138 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8604.308138 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8604.308138 # average overall mshr miss latency
603,607c624,628
< system.cpu.icache.tags.replacements 791372 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.348934 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 144679417 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 791884 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 182.702791 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 791291 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.349956 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 144673577 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 791803 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 182.714106 # Average number of references to valid blocks.
609,611c630,632
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.348934 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.996775 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.996775 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.349956 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.996777 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.996777 # Average percentage of cache occupancy
613,616c634,637
< system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 150 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id
618,655c639,676
< system.cpu.icache.tags.tag_accesses 146263199 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 146263199 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 144679417 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 144679417 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 144679417 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 144679417 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 144679417 # number of overall hits
< system.cpu.icache.overall_hits::total 144679417 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 791891 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 791891 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 791891 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 791891 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 791891 # number of overall misses
< system.cpu.icache.overall_misses::total 791891 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11123124618 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11123124618 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11123124618 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11123124618 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11123124618 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11123124618 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 145471308 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 145471308 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 145471308 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 145471308 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 145471308 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 145471308 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005444 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.005444 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.005444 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.005444 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.005444 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.005444 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14046.282403 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14046.282403 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14046.282403 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14046.282403 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14046.282403 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 146257197 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 146257197 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 144673577 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 144673577 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 144673577 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 144673577 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 144673577 # number of overall hits
> system.cpu.icache.overall_hits::total 144673577 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 791810 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 791810 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 791810 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 791810 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 791810 # number of overall misses
> system.cpu.icache.overall_misses::total 791810 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 11120002617 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 11120002617 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 11120002617 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 11120002617 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 11120002617 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 11120002617 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 145465387 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 145465387 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 145465387 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 145465387 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 145465387 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 145465387 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005443 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.005443 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.005443 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.005443 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.005443 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.005443 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14043.776432 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14043.776432 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14043.776432 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14043.776432 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14043.776432 # average overall miss latency
664,687c685,708
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791891 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 791891 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 791891 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 791891 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 791891 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 791891 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9534445382 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9534445382 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9534445382 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9534445382 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9534445382 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9534445382 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005444 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.005444 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005444 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.005444 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12040.098173 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12040.098173 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12040.098173 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12040.098173 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791810 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 791810 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 791810 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 791810 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 791810 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 791810 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9531495383 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 9531495383 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9531495383 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 9531495383 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9531495383 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 9531495383 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005443 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.005443 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005443 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.005443 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12037.604202 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12037.604202 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12037.604202 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12037.604202 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12037.604202 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12037.604202 # average overall mshr miss latency
689,697c710,718
< system.cpu.itb_walker_cache.tags.replacements 3756 # number of replacements
< system.cpu.itb_walker_cache.tags.tagsinuse 3.071335 # Cycle average of tags in use
< system.cpu.itb_walker_cache.tags.total_refs 7599 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.sampled_refs 3768 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.tags.avg_refs 2.016720 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.warmup_cycle 5167567118000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.071335 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191958 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_percent::total 0.191958 # Average percentage of cache occupancy
---
> system.cpu.itb_walker_cache.tags.replacements 3671 # number of replacements
> system.cpu.itb_walker_cache.tags.tagsinuse 3.091001 # Cycle average of tags in use
> system.cpu.itb_walker_cache.tags.total_refs 7743 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.sampled_refs 3683 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.tags.avg_refs 2.102362 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.warmup_cycle 5161228729000 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.091001 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.193188 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_percent::total 0.193188 # Average percentage of cache occupancy
704,707c725,728
< system.cpu.itb_walker_cache.tags.tag_accesses 29071 # Number of tag accesses
< system.cpu.itb_walker_cache.tags.data_accesses 29071 # Number of data accesses
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7599 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 7599 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.tags.tag_accesses 29095 # Number of tag accesses
> system.cpu.itb_walker_cache.tags.data_accesses 29095 # Number of data accesses
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7743 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 7743 # number of ReadReq hits
710,727c731,748
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7601 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 7601 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7601 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 7601 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4623 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 4623 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4623 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 4623 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4623 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 4623 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 47504750 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.ReadReq_miss_latency::total 47504750 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 47504750 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::total 47504750 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 47504750 # number of overall miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::total 47504750 # number of overall miss cycles
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12222 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 12222 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7745 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 7745 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7745 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 7745 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4535 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 4535 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4535 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 4535 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4535 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 4535 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 45208750 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.ReadReq_miss_latency::total 45208750 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 45208750 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::total 45208750 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 45208750 # number of overall miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::total 45208750 # number of overall miss cycles
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12278 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 12278 # number of ReadReq accesses(hits+misses)
730,745c751,766
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12224 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 12224 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12224 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 12224 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.378252 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.378252 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.378190 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.378190 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.378190 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.378190 # miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10275.740861 # average ReadReq miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10275.740861 # average ReadReq miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10275.740861 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10275.740861 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10275.740861 # average overall miss latency
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12280 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 12280 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12280 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 12280 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.369360 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.369360 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.369300 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.369300 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.369300 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.369300 # miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9968.853363 # average ReadReq miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9968.853363 # average ReadReq miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9968.853363 # average overall miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9968.853363 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9968.853363 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9968.853363 # average overall miss latency
754,779c775,800
< system.cpu.itb_walker_cache.writebacks::writebacks 825 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 825 # number of writebacks
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4623 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4623 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4623 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::total 4623 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4623 # number of overall MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::total 4623 # number of overall MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 38257250 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 38257250 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 38257250 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 38257250 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 38257250 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 38257250 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.378252 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.378252 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.378190 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.378190 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.378190 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8275.416396 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8275.416396 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8275.416396 # average overall mshr miss latency
---
> system.cpu.itb_walker_cache.writebacks::writebacks 782 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 782 # number of writebacks
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4535 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4535 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4535 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::total 4535 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4535 # number of overall MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::total 4535 # number of overall MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 36137250 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 36137250 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 36137250 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 36137250 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 36137250 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 36137250 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.369360 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.369360 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.369300 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.369300 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.369300 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.369300 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7968.522602 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average overall mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7968.522602 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7968.522602 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7968.522602 # average overall mshr miss latency
781,785c802,806
< system.cpu.l2cache.tags.replacements 87384 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64746.924059 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3489247 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 152088 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 22.942290 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 87090 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64747.295038 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3489215 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 151848 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 22.978340 # Average number of references to valid blocks.
787,792c808,813
< system.cpu.l2cache.tags.occ_blocks::writebacks 50375.433193 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006760 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141629 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3244.771000 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 11126.571476 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.768668 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 50370.250728 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.007923 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141558 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3248.489299 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 11128.405530 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.768589 # Average percentage of cache occupancy
795,827c816,848
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049511 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.169778 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.987960 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 64704 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2830 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4041 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57717 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987305 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 32214708 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 32214708 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6577 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3185 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 778918 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1279822 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2068502 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1542758 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1542758 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 199803 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 199803 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 6577 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 3185 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 778918 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1479625 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2268305 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 6577 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 3185 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 778918 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1479625 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2268305 # number of overall hits
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049568 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.169806 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.987965 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 64758 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2868 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4655 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57121 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.988129 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 32220029 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 32220029 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6582 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2969 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 778852 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1280153 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2068556 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1543232 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1543232 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 331 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 331 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 200337 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 200337 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 6582 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 2969 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 778852 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1480490 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2268893 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 6582 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 2969 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 778852 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1480490 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2268893 # number of overall hits
830,836c851,857
< system.cpu.l2cache.ReadReq_misses::cpu.inst 12960 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 28635 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 41601 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1351 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1351 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 113819 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 113819 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 12945 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 28645 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 41596 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1332 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1332 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 113458 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 113458 # number of ReadExReq misses
839,841c860,862
< system.cpu.l2cache.demand_misses::cpu.inst 12960 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 142454 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 155420 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 12945 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 142103 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 155054 # number of demand (read+write) misses
844,846c865,867
< system.cpu.l2cache.overall_misses::cpu.inst 12960 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 142454 # number of overall misses
< system.cpu.l2cache.overall_misses::total 155420 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.inst 12945 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 142103 # number of overall misses
> system.cpu.l2cache.overall_misses::total 155054 # number of overall misses
849,855c870,876
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 953249250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2133765000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 3087454250 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15012361 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 15012361 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7880712972 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7880712972 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 951041750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2142471500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 3093953250 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16007872 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 16007872 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7848897720 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7848897720 # number of ReadExReq miss cycles
858,860c879,881
< system.cpu.l2cache.demand_miss_latency::cpu.inst 953249250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10014477972 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10968167222 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 951041750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 9991369220 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 10942850970 # number of demand (read+write) miss cycles
863,886c884,907
< system.cpu.l2cache.overall_miss_latency::cpu.inst 953249250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10014477972 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10968167222 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6578 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3190 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 791878 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1308457 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2110103 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1542758 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1542758 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1672 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1672 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 313622 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 313622 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6578 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 3190 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 791878 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1622079 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2423725 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6578 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 3190 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 791878 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1622079 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2423725 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_miss_latency::cpu.inst 951041750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 9991369220 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 10942850970 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6583 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2974 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 791797 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1308798 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2110152 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1543232 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1543232 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1663 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1663 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 313795 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 313795 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6583 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 2974 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 791797 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1622593 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2423947 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6583 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 2974 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 791797 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1622593 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2423947 # number of overall (read+write) accesses
888,895c909,916
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001567 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016366 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021885 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.019715 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808014 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808014 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362918 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.362918 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001681 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016349 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021886 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.019712 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.800962 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.800962 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361567 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.361567 # miss rate for ReadExReq accesses
897,900c918,921
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001567 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016366 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.087822 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.064124 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001681 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016349 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.087578 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.063968 # miss rate for demand accesses
902,905c923,926
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001567 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016366 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.087822 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.064124 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001681 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016349 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.087578 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.063968 # miss rate for overall accesses
908,914c929,935
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73553.182870 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74515.976951 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74215.866205 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11112.036269 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11112.036269 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69238.993244 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69238.993244 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73467.883353 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74793.908186 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 74381.028224 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12017.921922 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12017.921922 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69178.883111 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69178.883111 # average ReadExReq miss latency
917,919c938,940
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73553.182870 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70299.731647 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70571.144138 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73467.883353 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70310.755016 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 70574.451288 # average overall miss latency
922,924c943,945
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73553.182870 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70299.731647 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70571.144138 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73467.883353 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70310.755016 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 70574.451288 # average overall miss latency
933,934c954,955
< system.cpu.l2cache.writebacks::writebacks 80466 # number of writebacks
< system.cpu.l2cache.writebacks::total 80466 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 80112 # number of writebacks
> system.cpu.l2cache.writebacks::total 80112 # number of writebacks
937,943c958,964
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12960 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28635 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 41601 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1351 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 1351 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113819 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 113819 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12945 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28645 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 41596 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1332 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 1332 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113458 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 113458 # number of ReadExReq MSHR misses
946,948c967,969
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 12960 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 142454 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 155420 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 12945 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 142103 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 155054 # number of demand (read+write) MSHR misses
951,953c972,974
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 12960 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 142454 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 155420 # number of overall MSHR misses
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 12945 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 142103 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 155054 # number of overall MSHR misses
956,962c977,983
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 790892250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1774999000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2566255250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13524351 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13524351 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6458128028 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6458128028 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 788869250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1783855500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2573088750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14201815 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14201815 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6430736280 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6430736280 # number of ReadExReq MSHR miss cycles
965,967c986,988
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 790892250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8233127028 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9024383278 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 788869250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8214591780 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9003825030 # number of demand (read+write) MSHR miss cycles
970,972c991,993
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 790892250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8233127028 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9024383278 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 788869250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8214591780 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9003825030 # number of overall MSHR miss cycles
975,978c996,999
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2394893500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2394893500 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89074968000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89074968000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2395003500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2395003500 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89075078000 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89075078000 # number of overall MSHR uncacheable cycles
980,987c1001,1008
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021885 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019715 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808014 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808014 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362918 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362918 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021886 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019712 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.800962 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.800962 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361567 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361567 # mshr miss rate for ReadExReq accesses
989,992c1010,1013
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087822 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.064124 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087578 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.063968 # mshr miss rate for demand accesses
994,997c1015,1018
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001567 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016366 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087822 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.064124 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001681 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016349 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087578 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.063968 # mshr miss rate for overall accesses
1000,1006c1021,1027
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61025.636574 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61987.043827 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.345256 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.622502 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.622502 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56740.333582 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56740.333582 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60940.073387 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62274.585442 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61859.042937 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10662.023273 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10662.023273 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56679.443318 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56679.443318 # average ReadExReq mshr miss latency
1009,1011c1030,1032
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency
1014,1016c1035,1037
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61025.636574 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57794.986648 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58064.491558 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60940.073387 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57807.307235 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58068.963264 # average overall mshr miss latency
1024,1047c1045,1068
< system.cpu.toL2Bus.trans_dist::ReadReq 2697012 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2696490 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 1542758 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 313627 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 313627 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583769 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979028 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8638 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18387 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7589822 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50680192 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203991823 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 256960 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 613632 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 255542607 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 52938 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 4020768 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 3.011831 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.108123 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2697337 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2696818 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 13890 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 13890 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 1543232 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2201 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2201 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 313800 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 313800 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583607 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5980523 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8291 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18581 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7591002 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50675008 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204057491 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 240384 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 614272 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 255587155 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 53212 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4021729 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.011827 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.108106 # Request fanout histogram
1052,1053c1073,1074
< system.cpu.toL2Bus.snoop_fanout::3 3973200 98.82% 98.82% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 47568 1.18% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 3974165 98.82% 98.82% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 47564 1.18% 100.00% # Request fanout histogram
1057,1058c1078,1079
< system.cpu.toL2Bus.snoop_fanout::total 4020768 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 3834027500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 4021729 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3834985000 # Layer occupancy (ticks)
1062c1083
< system.cpu.toL2Bus.respLayer0.occupancy 1190285118 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1190158617 # Layer occupancy (ticks)
1064c1085
< system.cpu.toL2Bus.respLayer1.occupancy 3054401379 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3054984845 # Layer occupancy (ticks)
1066c1087
< system.cpu.toL2Bus.respLayer2.occupancy 6935250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 6803250 # Layer occupancy (ticks)
1068c1089
< system.cpu.toL2Bus.respLayer3.occupancy 13198750 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 13474750 # Layer occupancy (ticks)
1070,1074c1091,1095
< system.iobus.trans_dist::ReadReq 230267 # Transaction distribution
< system.iobus.trans_dist::ReadResp 230267 # Transaction distribution
< system.iobus.trans_dist::WriteReq 57693 # Transaction distribution
< system.iobus.trans_dist::WriteResp 57694 # Transaction distribution
< system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 230264 # Transaction distribution
> system.iobus.trans_dist::ReadResp 230264 # Transaction distribution
> system.iobus.trans_dist::WriteReq 57694 # Transaction distribution
> system.iobus.trans_dist::WriteResp 10974 # Transaction distribution
> system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
1096,1097c1117,1118
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95134 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95134 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes)
1100c1121
< system.iobus.pkt_count::total 579232 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count::total 579226 # Packet count per connected master and slave (bytes)
1120,1121c1141,1142
< system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027320 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027320 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes)
1124c1145
< system.iobus.pkt_size::total 3280614 # Cumulative packet size per connected master and slave (bytes)
---
> system.iobus.pkt_size::total 3280590 # Cumulative packet size per connected master and slave (bytes)
1161c1182
< system.iobus.reqLayer19.occupancy 421906845 # Layer occupancy (ticks)
---
> system.iobus.reqLayer19.occupancy 448397612 # Layer occupancy (ticks)
1167c1188
< system.iobus.respLayer1.occupancy 52234501 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 52228501 # Layer occupancy (ticks)
1171,1172c1192,1193
< system.iocache.tags.replacements 47512 # number of replacements
< system.iocache.tags.tagsinuse 0.118180 # Cycle average of tags in use
---
> system.iocache.tags.replacements 47510 # number of replacements
> system.iocache.tags.tagsinuse 0.132770 # Cycle average of tags in use
1174c1195
< system.iocache.tags.sampled_refs 47528 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 47526 # Sample count of references to valid blocks.
1176,1179c1197,1200
< system.iocache.tags.warmup_cycle 5045851318000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.118180 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007386 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.007386 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 5045851378000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.132770 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008298 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.008298 # Average percentage of cache occupancy
1183,1208c1204,1229
< system.iocache.tags.tag_accesses 428111 # Number of tag accesses
< system.iocache.tags.data_accesses 428111 # Number of data accesses
< system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
< system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
< system.iocache.ReadReq_misses::pc.south_bridge.ide 847 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 847 # number of ReadReq misses
< system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 1 # number of WriteInvalidateReq misses
< system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses
< system.iocache.demand_misses::pc.south_bridge.ide 847 # number of demand (read+write) misses
< system.iocache.demand_misses::total 847 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 847 # number of overall misses
< system.iocache.overall_misses::total 847 # number of overall misses
< system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141540186 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 141540186 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::pc.south_bridge.ide 141540186 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 141540186 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 141540186 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 141540186 # number of overall miss cycles
< system.iocache.ReadReq_accesses::pc.south_bridge.ide 847 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 847 # number of ReadReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46721 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.WriteInvalidateReq_accesses::total 46721 # number of WriteInvalidateReq accesses(hits+misses)
< system.iocache.demand_accesses::pc.south_bridge.ide 847 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 847 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 847 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 847 # number of overall (read+write) accesses
---
> system.iocache.tags.tag_accesses 428076 # Number of tag accesses
> system.iocache.tags.data_accesses 428076 # Number of data accesses
> system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
> system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
> system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses
> system.iocache.demand_misses::total 844 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses
> system.iocache.overall_misses::total 844 # number of overall misses
> system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143496186 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 143496186 # number of ReadReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12353940925 # number of WriteInvalidateReq miss cycles
> system.iocache.WriteInvalidateReq_miss_latency::total 12353940925 # number of WriteInvalidateReq miss cycles
> system.iocache.demand_miss_latency::pc.south_bridge.ide 143496186 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 143496186 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 143496186 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 143496186 # number of overall miss cycles
> system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses
1211,1212c1232,1233
< system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 0.000021 # miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_miss_rate::total 0.000021 # miss rate for WriteInvalidateReq accesses
---
> system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
1217,1223c1238,1246
< system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 167107.657615 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 167107.657615 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167107.657615 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 167107.657615 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 170019.177725 # average ReadReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264425.105415 # average WriteInvalidateReq miss latency
> system.iocache.WriteInvalidateReq_avg_miss_latency::total 264425.105415 # average WriteInvalidateReq miss latency
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 170019.177725 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170019.177725 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 170019.177725 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 70456 # number of cycles access was blocked
1225c1248
< system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 9155 # number of cycles access was blocked
1227c1250
< system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 7.695904 # average number of cycles each access was blocked
1229c1252
< system.iocache.fast_writes 46720 # number of fast writes performed
---
> system.iocache.fast_writes 0 # number of fast writes performed
1231,1244c1254,1271
< system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 847 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 847 # number of ReadReq MSHR misses
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 847 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 847 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 847 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 847 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 97471186 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2827609160 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2827609160 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 97471186 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97471186 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 97471186 # number of overall MSHR miss cycles
---
> system.iocache.writebacks::writebacks 46668 # number of writebacks
> system.iocache.writebacks::total 46668 # number of writebacks
> system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses
> system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
> system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 99583186 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9924498927 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9924498927 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 99583186 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99583186 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 99583186 # number of overall MSHR miss cycles
1246a1274,1275
> system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
1251,1258c1280,1287
< system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 115078.141677 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115078.141677 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 115078.141677 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 117989.556872 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212425.062650 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212425.062650 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117989.556872 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 117989.556872 # average overall mshr miss latency
1260,1264c1289,1293
< system.membus.trans_dist::ReadReq 624009 # Transaction distribution
< system.membus.trans_dist::ReadResp 624009 # Transaction distribution
< system.membus.trans_dist::WriteReq 13889 # Transaction distribution
< system.membus.trans_dist::WriteResp 13889 # Transaction distribution
< system.membus.trans_dist::Writeback 80466 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 624001 # Transaction distribution
> system.membus.trans_dist::ReadResp 624001 # Transaction distribution
> system.membus.trans_dist::WriteReq 13890 # Transaction distribution
> system.membus.trans_dist::WriteResp 13890 # Transaction distribution
> system.membus.trans_dist::Writeback 126780 # Transaction distribution
1267,1270c1296,1299
< system.membus.trans_dist::UpgradeReq 2168 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 1629 # Transaction distribution
< system.membus.trans_dist::ReadExReq 113541 # Transaction distribution
< system.membus.trans_dist::ReadExResp 113541 # Transaction distribution
---
> system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 1612 # Transaction distribution
> system.membus.trans_dist::ReadExReq 113178 # Transaction distribution
> system.membus.trans_dist::ReadExResp 113178 # Transaction distribution
1276,1281c1305,1310
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710112 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394547 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1585447 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94730 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 94730 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1683487 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392754 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1583656 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141395 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 141395 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1728361 # Packet count per connected master and slave (bytes)
1285,1292c1314,1321
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420221 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15078912 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16745807 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 19770859 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 943 # Total snoops (count)
< system.membus.snoop_fanout::samples 285344 # Request fanout histogram
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14991040 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16657939 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 22669743 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 1607 # Total snoops (count)
> system.membus.snoop_fanout::samples 331268 # Request fanout histogram
1297c1326
< system.membus.snoop_fanout::1 285344 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 331268 100.00% 100.00% # Request fanout histogram
1302c1331
< system.membus.snoop_fanout::total 285344 # Request fanout histogram
---
> system.membus.snoop_fanout::total 331268 # Request fanout histogram
1305c1334
< system.membus.reqLayer1.occupancy 358105500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 358100000 # Layer occupancy (ticks)
1309c1338
< system.membus.reqLayer3.occupancy 1311782500 # Layer occupancy (ticks)
---
> system.membus.reqLayer3.occupancy 1728081500 # Layer occupancy (ticks)
1313c1342
< system.membus.respLayer2.occupancy 2622169871 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 2618580655 # Layer occupancy (ticks)
1315c1344
< system.membus.respLayer4.occupancy 54356499 # Layer occupancy (ticks)
---
> system.membus.respLayer4.occupancy 54329499 # Layer occupancy (ticks)