7,11c7,11
< host_inst_rate 693425 # Simulator instruction rate (inst/s)
< host_op_rate 1336696 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 28047460404 # Simulator tick rate (ticks/s)
< host_mem_usage 637768 # Number of bytes of host memory used
< host_seconds 185.20 # Real time elapsed on the host
---
> host_inst_rate 1079720 # Simulator instruction rate (inst/s)
> host_op_rate 2081347 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 43672253601 # Simulator tick rate (ticks/s)
> host_mem_usage 589096 # Number of bytes of host memory used
> host_seconds 118.94 # Real time elapsed on the host
427,428d426
< system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
< system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
443,444d440
< system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.999979 # mshr miss rate for WriteInvalidateReq accesses
< system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999979 # mshr miss rate for WriteInvalidateReq accesses
451,452c447,448
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60522.456336 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60522.456336 # average WriteInvalidateReq mshr miss latency
---
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency