Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

Deleted Added

sdiff udiff text old ( 10352:5f1f92bf76ee ) new ( 10409:8c80b91944c5 )

full compact

3,5c3,5
< sim_seconds 5.192526 # Number of seconds simulated
< sim_ticks 5192526233000 # Number of ticks simulated
< final_tick 5192526233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.192511 # Number of seconds simulated
> sim_ticks 5192511044000 # Number of ticks simulated
> final_tick 5192511044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1492668 # Simulator instruction rate (inst/s)
< host_op_rate 2877328 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 60393582039 # Simulator tick rate (ticks/s)
< host_mem_usage 592376 # Number of bytes of host memory used
< host_seconds 85.98 # Real time elapsed on the host
< sim_insts 128336778 # Number of instructions simulated
< sim_ops 247387190 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1018343 # Simulator instruction rate (inst/s)
> host_op_rate 1963050 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 41210458750 # Simulator tick rate (ticks/s)
> host_mem_usage 646888 # Number of bytes of host memory used
> host_seconds 126.00 # Real time elapsed on the host
> sim_insts 128310974 # Number of instructions simulated
> sim_ops 247343919 # Number of ops (including micro ops) simulated
17c17
< system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
19,24c19,24
< system.physmem.bytes_read::cpu.inst 829632 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 9090688 # Number of bytes read from this memory
< system.physmem.bytes_read::total 9949056 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 829632 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 829632 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 5138240 # Number of bytes written to this memory
---
> system.physmem.bytes_read::cpu.inst 827456 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9076288 # Number of bytes read from this memory
> system.physmem.bytes_read::total 9932544 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 827456 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 827456 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 5141952 # Number of bytes written to this memory
26c26
< system.physmem.bytes_written::total 8128320 # Number of bytes written to this memory
---
> system.physmem.bytes_written::total 8132032 # Number of bytes written to this memory
28c28
< system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
30,33c30,33
< system.physmem.num_reads::cpu.inst 12963 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 142042 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 155454 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 80285 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 12929 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 141817 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 155196 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 80343 # Number of write requests responded to by this memory
35c35
< system.physmem.num_writes::total 127005 # Number of write requests responded to by this memory
---
> system.physmem.num_writes::total 127063 # Number of write requests responded to by this memory
37c37
< system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
39,49c39,49
< system.physmem.bw_read::cpu.inst 159774 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1750725 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1916034 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 159774 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 159774 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 989545 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::pc.south_bridge.ide 575843 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1565388 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 989545 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 581303 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 159356 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1747957 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1912859 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 159356 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 159356 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 990263 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::pc.south_bridge.ide 575845 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1566108 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 990263 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 581305 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
51,63c51,63
< system.physmem.bw_total::cpu.inst 159774 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1750725 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3481422 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 155454 # Number of read requests accepted
< system.physmem.writeReqs 127005 # Number of write requests accepted
< system.physmem.readBursts 155454 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 127005 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 9932928 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 16128 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8126720 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 9949056 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8128320 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 252 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::cpu.inst 159356 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1747957 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3478967 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 155196 # Number of read requests accepted
> system.physmem.writeReqs 127063 # Number of write requests accepted
> system.physmem.readBursts 155196 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 127063 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 9914944 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 17600 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8130496 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 9932544 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8132032 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 275 # Number of DRAM read bursts serviced by the write queue
65,97c65,97
< system.physmem.neitherReadNorWriteReqs 1602 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 10234 # Per bank write bursts
< system.physmem.perBankRdBursts::1 9830 # Per bank write bursts
< system.physmem.perBankRdBursts::2 10412 # Per bank write bursts
< system.physmem.perBankRdBursts::3 9937 # Per bank write bursts
< system.physmem.perBankRdBursts::4 9788 # Per bank write bursts
< system.physmem.perBankRdBursts::5 9348 # Per bank write bursts
< system.physmem.perBankRdBursts::6 9238 # Per bank write bursts
< system.physmem.perBankRdBursts::7 9473 # Per bank write bursts
< system.physmem.perBankRdBursts::8 9270 # Per bank write bursts
< system.physmem.perBankRdBursts::9 9085 # Per bank write bursts
< system.physmem.perBankRdBursts::10 9528 # Per bank write bursts
< system.physmem.perBankRdBursts::11 9619 # Per bank write bursts
< system.physmem.perBankRdBursts::12 9707 # Per bank write bursts
< system.physmem.perBankRdBursts::13 10058 # Per bank write bursts
< system.physmem.perBankRdBursts::14 9877 # Per bank write bursts
< system.physmem.perBankRdBursts::15 9798 # Per bank write bursts
< system.physmem.perBankWrBursts::0 8316 # Per bank write bursts
< system.physmem.perBankWrBursts::1 7729 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8212 # Per bank write bursts
< system.physmem.perBankWrBursts::3 7860 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8063 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7657 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7184 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7824 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7616 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7570 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7824 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7928 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8040 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8642 # Per bank write bursts
< system.physmem.perBankWrBursts::14 8420 # Per bank write bursts
< system.physmem.perBankWrBursts::15 8095 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 1594 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 10479 # Per bank write bursts
> system.physmem.perBankRdBursts::1 9637 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10137 # Per bank write bursts
> system.physmem.perBankRdBursts::3 9789 # Per bank write bursts
> system.physmem.perBankRdBursts::4 9555 # Per bank write bursts
> system.physmem.perBankRdBursts::5 9513 # Per bank write bursts
> system.physmem.perBankRdBursts::6 9351 # Per bank write bursts
> system.physmem.perBankRdBursts::7 9512 # Per bank write bursts
> system.physmem.perBankRdBursts::8 9073 # Per bank write bursts
> system.physmem.perBankRdBursts::9 8991 # Per bank write bursts
> system.physmem.perBankRdBursts::10 9630 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9438 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9550 # Per bank write bursts
> system.physmem.perBankRdBursts::13 10095 # Per bank write bursts
> system.physmem.perBankRdBursts::14 10146 # Per bank write bursts
> system.physmem.perBankRdBursts::15 10025 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8301 # Per bank write bursts
> system.physmem.perBankWrBursts::1 8002 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8301 # Per bank write bursts
> system.physmem.perBankWrBursts::3 8212 # Per bank write bursts
> system.physmem.perBankWrBursts::4 7990 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7535 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7392 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7734 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7444 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7612 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7970 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7896 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8102 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8416 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8297 # Per bank write bursts
> system.physmem.perBankWrBursts::15 7835 # Per bank write bursts
99,100c99,100
< system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
< system.physmem.totGap 5192526169500 # Total gap between requests
---
> system.physmem.numWrRetry 1 # Number of times write queue was full causing retry
> system.physmem.totGap 5192510980500 # Total gap between requests
107c107
< system.physmem.readPktSize::6 155454 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 155196 # Read request sizes (log2)
114,118c114,118
< system.physmem.writePktSize::6 127005 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 151750 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 3023 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 127063 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 151525 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 2962 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 63 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see
162,228c162,228
< system.physmem.wrQLenPdf::15 2439 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 3242 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 6145 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 6383 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 6406 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 7175 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 7465 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 8169 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 8822 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 9909 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 9129 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 8509 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 7675 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7337 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 6397 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 6159 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 6188 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 6092 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 164 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 191 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 179 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 171 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 146 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 28 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 56259 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 321.007910 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 189.347718 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 335.337897 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 20082 35.70% 35.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 13652 24.27% 59.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5681 10.10% 70.06% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3443 6.12% 76.18% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2317 4.12% 80.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1632 2.90% 83.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1101 1.96% 85.16% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 1008 1.79% 86.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 7343 13.05% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 56259 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 5896 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 26.315638 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 622.349689 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 5895 99.98% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.wrQLenPdf::15 2384 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3176 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6154 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6388 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6392 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 7149 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7445 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8789 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 9861 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9041 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8343 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7645 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7364 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6417 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6189 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6141 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 237 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 221 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 254 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 206 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 199 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 193 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 182 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 177 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 173 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 150 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 152 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 66 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 64 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 41 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 37 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 57292 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 314.972003 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 184.928814 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 333.427002 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 21127 36.88% 36.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 13732 23.97% 60.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5729 10.00% 70.84% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3461 6.04% 76.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2250 3.93% 80.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1575 2.75% 83.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1105 1.93% 85.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1008 1.76% 87.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7305 12.75% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 57292 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5905 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 26.232854 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 621.882480 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 5904 99.98% 99.98% # Reads before turning the bus around for writes
230,249c230,249
< system.physmem.rdPerTurnAround::total 5896 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 5896 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 21.536635 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 19.431893 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 14.049302 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-19 4860 82.43% 82.43% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-23 44 0.75% 83.18% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-27 38 0.64% 83.82% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-31 287 4.87% 88.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-35 272 4.61% 93.30% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-39 20 0.34% 93.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-43 25 0.42% 94.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-47 11 0.19% 94.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-51 27 0.46% 94.71% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-55 4 0.07% 94.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-59 3 0.05% 94.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-63 1 0.02% 94.84% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::64-67 223 3.78% 98.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-71 4 0.07% 98.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::72-75 6 0.10% 98.80% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 5905 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5905 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 21.513802 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 19.393687 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 14.130484 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 4886 82.74% 82.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 42 0.71% 83.45% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 41 0.69% 84.15% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 275 4.66% 88.81% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 267 4.52% 93.33% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 20 0.34% 93.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 10 0.17% 93.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 19 0.32% 94.16% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 22 0.37% 94.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 8 0.14% 94.67% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 6 0.10% 94.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 2 0.03% 94.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 226 3.83% 98.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 6 0.10% 98.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 4 0.07% 98.80% # Writes before turning the bus around for reads
251,261c251,261
< system.physmem.wrPerTurnAround::80-83 20 0.34% 99.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::84-87 1 0.02% 99.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::92-95 1 0.02% 99.22% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::96-99 10 0.17% 99.39% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::100-103 2 0.03% 99.42% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::104-107 2 0.03% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::108-111 2 0.03% 99.49% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::112-115 8 0.14% 99.63% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::116-119 2 0.03% 99.66% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::120-123 4 0.07% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::128-131 13 0.22% 99.95% # Writes before turning the bus around for reads
---
> system.physmem.wrPerTurnAround::80-83 15 0.25% 99.10% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::88-91 1 0.02% 99.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.02% 99.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 13 0.22% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 1 0.02% 99.37% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 6 0.10% 99.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 3 0.05% 99.53% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 8 0.14% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.03% 99.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 3 0.05% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 12 0.20% 99.95% # Writes before turning the bus around for reads
264,268c264,268
< system.physmem.wrPerTurnAround::total 5896 # Writes before turning the bus around for reads
< system.physmem.totQLat 1473683250 # Total ticks spent queuing
< system.physmem.totMemAccLat 4383720750 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 776010000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 9495.26 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 5905 # Writes before turning the bus around for reads
> system.physmem.totQLat 1558594500 # Total ticks spent queuing
> system.physmem.totMemAccLat 4463363250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 774605000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 10060.58 # Average queueing delay per DRAM burst
270c270
< system.physmem.avgMemAccLat 28245.26 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 28810.58 # Average memory access latency per DRAM burst
273c273
< system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s
280,288c280,288
< system.physmem.avgWrQLen 22.52 # Average write queue length when enqueuing
< system.physmem.readRowHits 127189 # Number of row buffer hits during reads
< system.physmem.writeRowHits 98733 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes
< system.physmem.avgGap 18383291.63 # Average gap between requests
< system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 4971157882750 # Time in different power states
< system.physmem.memoryStateTime::REF 173389840000 # Time in different power states
---
> system.physmem.avgWrQLen 22.05 # Average write queue length when enqueuing
> system.physmem.readRowHits 125976 # Number of row buffer hits during reads
> system.physmem.writeRowHits 98691 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 81.32 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 77.67 # Row buffer hit rate for writes
> system.physmem.avgGap 18396263.65 # Average gap between requests
> system.physmem.pageHitRate 79.67 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 4970934831000 # Time in different power states
> system.physmem.memoryStateTime::REF 173389320000 # Time in different power states
290c290
< system.physmem.memoryStateTime::ACT 47978395250 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 48186778000 # Time in different power states
292,294c292,293
< system.membus.throughput 3808612 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 623901 # Transaction distribution
< system.membus.trans_dist::ReadResp 623901 # Transaction distribution
---
> system.membus.trans_dist::ReadReq 623858 # Transaction distribution
> system.membus.trans_dist::ReadResp 623858 # Transaction distribution
297c296
< system.membus.trans_dist::Writeback 80285 # Transaction distribution
---
> system.membus.trans_dist::Writeback 80343 # Transaction distribution
301,303c300,302
< system.membus.trans_dist::UpgradeResp 1602 # Transaction distribution
< system.membus.trans_dist::ReadExReq 113400 # Transaction distribution
< system.membus.trans_dist::ReadExResp 113400 # Transaction distribution
---
> system.membus.trans_dist::UpgradeResp 1594 # Transaction distribution
> system.membus.trans_dist::ReadExReq 113180 # Transaction distribution
> system.membus.trans_dist::ReadExResp 113180 # Transaction distribution
310,325c309,334
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394055 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584493 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94727 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 94727 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1682528 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15058944 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16725605 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 19750653 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 19750653 # Total data (bytes)
< system.membus.snoop_data_through_bus 25664 # Total snoop data (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393589 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584027 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94722 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 94722 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1682057 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15046144 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16712805 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 19737853 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 948 # Total snoops (count)
> system.membus.snoop_fanout::samples 284802 # Request fanout histogram
> system.membus.snoop_fanout::mean 1 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::1 284802 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 1 # Request fanout histogram
> system.membus.snoop_fanout::max_value 1 # Request fanout histogram
> system.membus.snoop_fanout::total 284802 # Request fanout histogram
328c337
< system.membus.reqLayer1.occupancy 359321500 # Layer occupancy (ticks)
---
> system.membus.reqLayer1.occupancy 358101500 # Layer occupancy (ticks)
332c341
< system.membus.reqLayer3.occupancy 1309717000 # Layer occupancy (ticks)
---
> system.membus.reqLayer3.occupancy 1310597750 # Layer occupancy (ticks)
336c345
< system.membus.respLayer2.occupancy 2621518398 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 2618526656 # Layer occupancy (ticks)
338c347
< system.membus.respLayer4.occupancy 54330498 # Layer occupancy (ticks)
---
> system.membus.respLayer4.occupancy 54286498 # Layer occupancy (ticks)
340,341c349,350
< system.iocache.tags.replacements 47509 # number of replacements
< system.iocache.tags.tagsinuse 0.112613 # Cycle average of tags in use
---
> system.iocache.tags.replacements 47504 # number of replacements
> system.iocache.tags.tagsinuse 0.112573 # Cycle average of tags in use
343c352
< system.iocache.tags.sampled_refs 47525 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 47520 # Sample count of references to valid blocks.
345,348c354,357
< system.iocache.tags.warmup_cycle 5045777659000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112613 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007038 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.007038 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 5045778761000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112573 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007036 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.007036 # Average percentage of cache occupancy
352,353c361,362
< system.iocache.tags.tag_accesses 428076 # Number of tag accesses
< system.iocache.tags.data_accesses 428076 # Number of data accesses
---
> system.iocache.tags.tag_accesses 428031 # Number of tag accesses
> system.iocache.tags.data_accesses 428031 # Number of data accesses
356,369c365,378
< system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
< system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses
< system.iocache.demand_misses::total 844 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses
< system.iocache.overall_misses::total 844 # number of overall misses
< system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141199186 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 141199186 # number of ReadReq miss cycles
< system.iocache.demand_miss_latency::pc.south_bridge.ide 141199186 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 141199186 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 141199186 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 141199186 # number of overall miss cycles
< system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
---
> system.iocache.ReadReq_misses::pc.south_bridge.ide 839 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 839 # number of ReadReq misses
> system.iocache.demand_misses::pc.south_bridge.ide 839 # number of demand (read+write) misses
> system.iocache.demand_misses::total 839 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 839 # number of overall misses
> system.iocache.overall_misses::total 839 # number of overall misses
> system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140842436 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 140842436 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::pc.south_bridge.ide 140842436 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 140842436 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 140842436 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 140842436 # number of overall miss cycles
> system.iocache.ReadReq_accesses::pc.south_bridge.ide 839 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 839 # number of ReadReq accesses(hits+misses)
372,375c381,384
< system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 839 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 839 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 839 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 839 # number of overall (read+write) accesses
382,387c391,396
< system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 167297.613744 # average ReadReq miss latency
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 167297.613744 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 167297.613744 # average overall miss latency
---
> system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 167869.411204 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 167869.411204 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167869.411204 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 167869.411204 # average overall miss latency
396,397c405,406
< system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses
---
> system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 839 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 839 # number of ReadReq MSHR misses
400,411c409,420
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 97286186 # number of ReadReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2834928162 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2834928162 # number of WriteInvalidateReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 97286186 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 97286186 # number of overall MSHR miss cycles
---
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 839 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 839 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 839 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 839 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 97188936 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2836981412 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2836981412 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 97188936 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97188936 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 97188936 # number of overall MSHR miss cycles
420,427c429,436
< system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 115267.992891 # average ReadReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60679.113057 # average WriteInvalidateReq mshr miss latency
< system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60679.113057 # average WriteInvalidateReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 115839.017878 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60723.061045 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60723.061045 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115839.017878 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 115839.017878 # average overall mshr miss latency
441,443c450,451
< system.iobus.throughput 631746 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 230149 # Transaction distribution
< system.iobus.trans_dist::ReadResp 230149 # Transaction distribution
---
> system.iobus.trans_dist::ReadReq 230144 # Transaction distribution
> system.iobus.trans_dist::ReadResp 230144 # Transaction distribution
467,468c475,476
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95118 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95118 # Packet count per connected master and slave (bytes)
471,496c479,503
< system.iobus.pkt_count::total 578764 # Packet count per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 3280356 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 3280356 # Total data (bytes)
---
> system.iobus.pkt_count::total 578754 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027256 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027256 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.pkt_size::total 3280316 # Cumulative packet size per connected master and slave (bytes)
533c540
< system.iobus.reqLayer18.occupancy 421898846 # Layer occupancy (ticks)
---
> system.iobus.reqLayer18.occupancy 421888846 # Layer occupancy (ticks)
539c546
< system.iobus.respLayer1.occupancy 52228502 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 52218502 # Layer occupancy (ticks)
545c552
< system.cpu.numCycles 10385052466 # number of cpu cycles simulated
---
> system.cpu.numCycles 10385022088 # number of cpu cycles simulated
548,550c555,557
< system.cpu.committedInsts 128336778 # Number of instructions committed
< system.cpu.committedOps 247387190 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 231979854 # Number of integer alu accesses
---
> system.cpu.committedInsts 128310974 # Number of instructions committed
> system.cpu.committedOps 247343919 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 231936467 # Number of integer alu accesses
552,554c559,561
< system.cpu.num_func_calls 2299861 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 23168822 # number of instructions that are conditional controls
< system.cpu.num_int_insts 231979854 # number of integer instructions
---
> system.cpu.num_func_calls 2299885 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 23161985 # number of instructions that are conditional controls
> system.cpu.num_int_insts 231936467 # number of integer instructions
556,557c563,564
< system.cpu.num_int_register_reads 434516750 # number of times the integer registers were read
< system.cpu.num_int_register_writes 197854064 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 434450917 # number of times the integer registers were read
> system.cpu.num_int_register_writes 197819265 # number of times the integer registers were written
560,573c567,580
< system.cpu.num_cc_register_reads 132811657 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 95534544 # number of times the CC registers were written
< system.cpu.num_mem_refs 22246380 # number of memory refs
< system.cpu.num_load_insts 13880618 # Number of load instructions
< system.cpu.num_store_insts 8365762 # Number of store instructions
< system.cpu.num_idle_cycles 9788359567.998116 # Number of idle cycles
< system.cpu.num_busy_cycles 596692898.001885 # Number of busy cycles
< system.cpu.not_idle_fraction 0.057457 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.942543 # Percentage of idle cycles
< system.cpu.Branches 26306776 # Number of branches fetched
< system.cpu.op_class::No_OpClass 174693 0.07% 0.07% # Class of executed instruction
< system.cpu.op_class::IntAlu 224704760 90.83% 90.90% # Class of executed instruction
< system.cpu.op_class::IntMult 139946 0.06% 90.96% # Class of executed instruction
< system.cpu.op_class::IntDiv 122983 0.05% 91.01% # Class of executed instruction
---
> system.cpu.num_cc_register_reads 132769519 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 95505601 # number of times the CC registers were written
> system.cpu.num_mem_refs 22243286 # number of memory refs
> system.cpu.num_load_insts 13879256 # Number of load instructions
> system.cpu.num_store_insts 8364030 # Number of store instructions
> system.cpu.num_idle_cycles 9788400874.998116 # Number of idle cycles
> system.cpu.num_busy_cycles 596621213.001885 # Number of busy cycles
> system.cpu.not_idle_fraction 0.057450 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.942550 # Percentage of idle cycles
> system.cpu.Branches 26299942 # Number of branches fetched
> system.cpu.op_class::No_OpClass 174748 0.07% 0.07% # Class of executed instruction
> system.cpu.op_class::IntAlu 224664535 90.83% 90.90% # Class of executed instruction
> system.cpu.op_class::IntMult 139903 0.06% 90.96% # Class of executed instruction
> system.cpu.op_class::IntDiv 122942 0.05% 91.01% # Class of executed instruction
600,601c607,608
< system.cpu.op_class::MemRead 13880618 5.61% 96.62% # Class of executed instruction
< system.cpu.op_class::MemWrite 8365762 3.38% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 13879256 5.61% 96.62% # Class of executed instruction
> system.cpu.op_class::MemWrite 8364030 3.38% 100.00% # Class of executed instruction
604c611
< system.cpu.op_class::total 247388762 # Class of executed instruction
---
> system.cpu.op_class::total 247345414 # Class of executed instruction
607,613c614,620
< system.cpu.icache.tags.replacements 794564 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.353610 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 144580687 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 795076 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 181.845115 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 161037642250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.353610 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.replacements 790109 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.353605 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 144545821 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 790621 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 182.825679 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 161037022250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.353605 # Average occupied blocks per requestor
617,619c624,626
< system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 297 # Occupied blocks per task id
622,659c629,666
< system.cpu.icache.tags.tag_accesses 146170853 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 146170853 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 144580687 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 144580687 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 144580687 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 144580687 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 144580687 # number of overall hits
< system.cpu.icache.overall_hits::total 144580687 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 795083 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 795083 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 795083 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 795083 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 795083 # number of overall misses
< system.cpu.icache.overall_misses::total 795083 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11158319369 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11158319369 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11158319369 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11158319369 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11158319369 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11158319369 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 145375770 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 145375770 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 145375770 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 145375770 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 145375770 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 145375770 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005469 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.005469 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.005469 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.005469 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.005469 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.005469 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14034.156647 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14034.156647 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14034.156647 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14034.156647 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14034.156647 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14034.156647 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 146127077 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 146127077 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 144545821 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 144545821 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 144545821 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 144545821 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 144545821 # number of overall hits
> system.cpu.icache.overall_hits::total 144545821 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 790628 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 790628 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 790628 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 790628 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 790628 # number of overall misses
> system.cpu.icache.overall_misses::total 790628 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108318120 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 11108318120 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 11108318120 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 11108318120 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 11108318120 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 11108318120 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 145336449 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 145336449 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 145336449 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 145336449 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 145336449 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 145336449 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14049.993322 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14049.993322 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14049.993322 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14049.993322 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14049.993322 # average overall miss latency
668,691c675,698
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795083 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 795083 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 795083 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 795083 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 795083 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 795083 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9563233631 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9563233631 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9563233631 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9563233631 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9563233631 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9563233631 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005469 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.005469 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.005469 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.968943 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.968943 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.968943 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.968943 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.968943 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.968943 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790628 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 790628 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 790628 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 790628 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 790628 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 790628 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9522182380 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 9522182380 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9522182380 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 9522182380 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9522182380 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 9522182380 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12043.821342 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12043.821342 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12043.821342 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12043.821342 # average overall mshr miss latency
693,710c700,717
< system.cpu.itb_walker_cache.tags.replacements 3511 # number of replacements
< system.cpu.itb_walker_cache.tags.tagsinuse 3.067889 # Cycle average of tags in use
< system.cpu.itb_walker_cache.tags.total_refs 7844 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.sampled_refs 3523 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.tags.avg_refs 2.226511 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.warmup_cycle 5164932679000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.067889 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191743 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_percent::total 0.191743 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
< system.cpu.itb_walker_cache.tags.tag_accesses 28837 # Number of tag accesses
< system.cpu.itb_walker_cache.tags.data_accesses 28837 # Number of data accesses
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7845 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 7845 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.tags.replacements 3485 # number of replacements
> system.cpu.itb_walker_cache.tags.tagsinuse 3.066895 # Cycle average of tags in use
> system.cpu.itb_walker_cache.tags.total_refs 7845 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.sampled_refs 3494 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.tags.avg_refs 2.245278 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.warmup_cycle 5167508806000 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.066895 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191681 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_percent::total 0.191681 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 9 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.562500 # Percentage of cache occupancy per task id
> system.cpu.itb_walker_cache.tags.tag_accesses 28811 # Number of tag accesses
> system.cpu.itb_walker_cache.tags.data_accesses 28811 # Number of data accesses
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7868 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 7868 # number of ReadReq hits
713,730c720,737
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7847 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 7847 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7847 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 7847 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4381 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 4381 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4381 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 4381 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4381 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 4381 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43773750 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43773750 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43773750 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::total 43773750 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43773750 # number of overall miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::total 43773750 # number of overall miss cycles
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12226 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7870 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 7870 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7870 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 7870 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4357 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 4357 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4357 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 4357 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4357 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 4357 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43584500 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43584500 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43584500 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::total 43584500 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43584500 # number of overall miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::total 43584500 # number of overall miss cycles
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
733,748c740,755
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12228 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12228 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358335 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358335 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358276 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.358276 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358276 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.358276 # miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9991.725633 # average ReadReq miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9991.725633 # average ReadReq miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9991.725633 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9991.725633 # average overall miss latency
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.356401 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.356401 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.356343 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.356343 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.356343 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.356343 # miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10003.327978 # average ReadReq miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10003.327978 # average ReadReq miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10003.327978 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10003.327978 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10003.327978 # average overall miss latency
757,782c764,789
< system.cpu.itb_walker_cache.writebacks::writebacks 771 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 771 # number of writebacks
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4381 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4381 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4381 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::total 4381 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4381 # number of overall MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::total 4381 # number of overall MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35010250 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35010250 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35010250 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35010250 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35010250 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35010250 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358335 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358335 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358276 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358276 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7991.383246 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency
---
> system.cpu.itb_walker_cache.writebacks::writebacks 747 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 747 # number of writebacks
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4357 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4357 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4357 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::total 4357 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4357 # number of overall MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::total 4357 # number of overall MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 34868500 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 34868500 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 34868500 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 34868500 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 34868500 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 34868500 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.356401 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.356401 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.356343 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.356343 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.356343 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8002.868947 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8002.868947 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8002.868947 # average overall mshr miss latency
784,790c791,797
< system.cpu.dtb_walker_cache.tags.replacements 7447 # number of replacements
< system.cpu.dtb_walker_cache.tags.tagsinuse 5.051866 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 13273 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.sampled_refs 7461 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.avg_refs 1.778984 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 5163481853000 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051866 # Average occupied blocks per requestor
---
> system.cpu.dtb_walker_cache.tags.replacements 7826 # number of replacements
> system.cpu.dtb_walker_cache.tags.tagsinuse 5.051872 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 12792 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.sampled_refs 7842 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.avg_refs 1.631217 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 5165211267000 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051872 # Average occupied blocks per requestor
793c800
< system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
---
> system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id
795,836c802,843
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
< system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
< system.cpu.dtb_walker_cache.tags.tag_accesses 52546 # Number of tag accesses
< system.cpu.dtb_walker_cache.tags.data_accesses 52546 # Number of data accesses
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13289 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 13289 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13289 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 13289 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13289 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 13289 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8656 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 8656 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8656 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 8656 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8656 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 8656 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91979000 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91979000 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91979000 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::total 91979000 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91979000 # number of overall miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::total 91979000 # number of overall miss cycles
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21945 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 21945 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21945 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 21945 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21945 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 21945 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.394441 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.394441 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.394441 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.394441 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.394441 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.394441 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10626.039741 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10626.039741 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10626.039741 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10626.039741 # average overall miss latency
---
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
> system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
> system.cpu.dtb_walker_cache.tags.tag_accesses 52641 # Number of tag accesses
> system.cpu.dtb_walker_cache.tags.data_accesses 52641 # Number of data accesses
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12792 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 12792 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12792 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 12792 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12792 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 12792 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9019 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 9019 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9019 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 9019 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9019 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 9019 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95783000 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95783000 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95783000 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::total 95783000 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95783000 # number of overall miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::total 95783000 # number of overall miss cycles
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21811 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 21811 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21811 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 21811 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21811 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 21811 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.413507 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.413507 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.413507 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.413507 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.413507 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.413507 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10620.135270 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10620.135270 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10620.135270 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10620.135270 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10620.135270 # average overall miss latency
845,870c852,877
< system.cpu.dtb_walker_cache.writebacks::writebacks 2980 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 2980 # number of writebacks
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8656 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8656 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8656 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::total 8656 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8656 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::total 8656 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74666500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74666500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74666500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74666500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74666500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74666500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.394441 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.394441 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.394441 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8625.981978 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 2842 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 2842 # number of writebacks
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9019 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9019 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9019 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::total 9019 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9019 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::total 9019 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77744500 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77744500 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77744500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77744500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77744500 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77744500 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.413507 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.413507 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.413507 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.413507 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8620.079831 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8620.079831 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8620.079831 # average overall mshr miss latency
872,876c879,883
< system.cpu.dcache.tags.replacements 1620883 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.997130 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 20027756 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1621395 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 12.352176 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 1621218 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.996934 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 20024389 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1621730 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 12.347548 # Average number of references to valid blocks.
878c885
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.997130 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.996934 # Average occupied blocks per requestor
882,885c889,891
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id
887,945c893,951
< system.cpu.dcache.tags.tag_accesses 88256675 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 88256675 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 11935486 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 11935486 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8030839 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8030839 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 59261 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 59261 # number of SoftPFReq hits
< system.cpu.dcache.demand_hits::cpu.data 19966325 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 19966325 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20025586 # number of overall hits
< system.cpu.dcache.overall_hits::total 20025586 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 906294 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 906294 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 324617 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 324617 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 402313 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 402313 # number of SoftPFReq misses
< system.cpu.dcache.demand_misses::cpu.data 1230911 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1230911 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1633224 # number of overall misses
< system.cpu.dcache.overall_misses::total 1633224 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12712957750 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12712957750 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 11341720828 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 11341720828 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 24054678578 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 24054678578 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 24054678578 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 24054678578 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 12841780 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 12841780 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8355456 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8355456 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::cpu.data 461574 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.SoftPFReq_accesses::total 461574 # number of SoftPFReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21197236 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21197236 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21658810 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21658810 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070574 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.070574 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038851 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.038851 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871611 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.871611 # miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.058069 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.058069 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.075407 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.075407 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14027.410255 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14027.410255 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34938.776552 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34938.776552 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 19542.175330 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 19542.175330 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 14728.340128 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 14728.340128 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 7655 # number of cycles access was blocked
---
> system.cpu.dcache.tags.tag_accesses 88244906 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 88244906 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 11933720 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 11933720 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8029176 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8029176 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 59323 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 59323 # number of SoftPFReq hits
> system.cpu.dcache.demand_hits::cpu.data 19962896 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 19962896 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20022219 # number of overall hits
> system.cpu.dcache.overall_hits::total 20022219 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 906567 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 906567 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 324536 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 324536 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 402460 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 402460 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 1231103 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1231103 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1633563 # number of overall misses
> system.cpu.dcache.overall_misses::total 1633563 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12726532750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12726532750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 11379509067 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 11379509067 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 24106041817 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 24106041817 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 24106041817 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 24106041817 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 12840287 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 12840287 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8353712 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8353712 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 461783 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 461783 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21193999 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21193999 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21655782 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21655782 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070603 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.070603 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038849 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.038849 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871535 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.871535 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.058087 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.058087 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.075433 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.075433 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14038.160169 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14038.160169 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35063.934562 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35063.934562 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 19580.848895 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 19580.848895 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14756.726136 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14756.726136 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 8324 # number of cycles access was blocked
947c953
< system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 80 # number of cycles access was blocked
949c955
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.863014 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.050000 # average number of cycles each access was blocked
953,954c959,960
< system.cpu.dcache.writebacks::writebacks 1537682 # number of writebacks
< system.cpu.dcache.writebacks::total 1537682 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 1537872 # number of writebacks
> system.cpu.dcache.writebacks::total 1537872 # number of writebacks
957,982c963,988
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9297 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 9297 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 9584 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 9584 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 9584 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 9584 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906007 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 906007 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315320 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 315320 # number of WriteReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402278 # number of SoftPFReq MSHR misses
< system.cpu.dcache.SoftPFReq_mshr_misses::total 402278 # number of SoftPFReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1221327 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1221327 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1623605 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1623605 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10893569500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 10893569500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10209797624 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10209797624 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5351981750 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5351981750 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21103367124 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 21103367124 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26455348874 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26455348874 # number of overall MSHR miss cycles
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9293 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 9293 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 9580 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 9580 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 9580 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 9580 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906280 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 906280 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315243 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 315243 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402425 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 402425 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1221523 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1221523 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1623948 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1623948 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10906302000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10906302000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245705379 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245705379 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5368514000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5368514000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21152007379 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 21152007379 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26520521379 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26520521379 # number of overall MSHR miss cycles
985,1008c991,1014
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537257000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537257000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96751929000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 96751929000 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070552 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070552 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037738 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037738 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871535 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871535 # mshr miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057617 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.057617 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074963 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.074963 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.714497 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.714497 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32379.162831 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32379.162831 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13304.187030 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13304.187030 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17279.047400 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 17279.047400 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16294.202638 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 16294.202638 # average overall mshr miss latency
---
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2536037000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2536037000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96750709000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 96750709000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070581 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070581 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037737 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037737 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871459 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871459 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057635 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.057635 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074989 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.074989 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12034.141766 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12034.141766 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32500.976640 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32500.976640 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13340.408772 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13340.408772 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17316.094236 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 17316.094236 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16330.893218 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 16330.893218 # average overall mshr miss latency
1016,1018c1022,1023
< system.cpu.toL2Bus.throughput 49844829 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 2698695 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2698173 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 2694994 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2694474 # Transaction distribution
1021,1022c1026,1027
< system.cpu.toL2Bus.trans_dist::Writeback 1541433 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 1541461 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46721 # Transaction distribution
1025,1039c1030,1056
< system.cpu.toL2Bus.trans_dist::ReadExReq 313150 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 313150 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1590153 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5974271 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8035 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18003 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7590462 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50884480 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203815525 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 233856 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 598208 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 255532069 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 255511461 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 3309120 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 3832514500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 313073 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 313073 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581243 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5975195 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7975 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18479 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7582892 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50599360 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203853221 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 231552 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605440 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 255289573 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 53135 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 4016986 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.011840 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.108164 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 3969426 98.82% 98.82% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 47560 1.18% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 4016986 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 3830670000 # Layer occupancy (ticks)
1041c1058
< system.cpu.toL2Bus.snoopLayer0.occupancy 483000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 478500 # Layer occupancy (ticks)
1043c1060
< system.cpu.toL2Bus.respLayer0.occupancy 1195084369 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1188381870 # Layer occupancy (ticks)
1045c1062
< system.cpu.toL2Bus.respLayer1.occupancy 3051993102 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3052447844 # Layer occupancy (ticks)
1047c1064
< system.cpu.toL2Bus.respLayer2.occupancy 6572250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 6536500 # Layer occupancy (ticks)
1049c1066
< system.cpu.toL2Bus.respLayer3.occupancy 12984250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 13528750 # Layer occupancy (ticks)
1051,1055c1068,1072
< system.cpu.l2cache.tags.replacements 87211 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64746.136544 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3491181 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 151954 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 22.975249 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 87289 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64708.241819 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3488268 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 151942 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 22.957892 # Average number of references to valid blocks.
1057,1062c1074,1079
< system.cpu.l2cache.tags.occ_blocks::writebacks 50332.685507 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006414 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141265 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3220.709839 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 11192.593518 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.768016 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 50201.970335 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.012829 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3236.502324 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 11269.615072 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.766021 # Average percentage of cache occupancy
1065,1098c1082,1115
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049144 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.170785 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.987948 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 64743 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2897 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4651 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57056 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987900 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 32212608 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 32212608 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6366 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2878 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 782107 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1278785 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2070136 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1541433 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1541433 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 199468 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 199468 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 6366 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 2878 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 782107 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1478253 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2269604 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 6366 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 2878 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 782107 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1478253 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2269604 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049385 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.171961 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.987369 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 64653 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2860 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4737 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56942 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986526 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 32181921 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 32181921 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6616 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2866 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 777686 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1279269 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2066437 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1541461 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1541461 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 312 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 312 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 199613 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 199613 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 6616 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 2866 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 777686 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1478882 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2266050 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 6616 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 2866 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 777686 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1478882 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2266050 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
1100,1107c1117,1124
< system.cpu.l2cache.ReadReq_misses::cpu.inst 12963 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 28642 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 41611 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1325 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1325 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 113677 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 113677 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 12929 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 28637 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 41573 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1319 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1319 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 113455 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 113455 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
1109,1112c1126,1129
< system.cpu.l2cache.demand_misses::cpu.inst 12963 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 142319 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 155288 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 12929 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 142092 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 155028 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
1114,1194c1131,1211
< system.cpu.l2cache.overall_misses::cpu.inst 12963 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 142319 # number of overall misses
< system.cpu.l2cache.overall_misses::total 155288 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 61250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 350750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 946969000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2148496250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 3095877250 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 14947864 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 14947864 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7865192973 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7865192973 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 61250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 350750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 946969000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10013689223 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10961070223 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 61250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 350750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 946969000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10013689223 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10961070223 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6367 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2883 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 795070 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1307427 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2111747 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1541433 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1541433 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1639 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1639 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 313145 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 313145 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6367 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 2883 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 795070 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1620572 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2424892 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6367 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 2883 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 795070 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1620572 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2424892 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000157 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001734 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016304 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021907 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.019705 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808420 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808420 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.363017 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.363017 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000157 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001734 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016304 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.087820 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.064039 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000157 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001734 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016304 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.087820 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.064039 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61250 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 70150 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73051.685567 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75012.088890 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74400.453005 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11281.406792 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11281.406792 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69188.956192 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69188.956192 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61250 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73051.685567 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70360.873973 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70585.429801 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61250 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73051.685567 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70360.873973 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70585.429801 # average overall miss latency
---
> system.cpu.l2cache.overall_misses::cpu.inst 12929 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 142092 # number of overall misses
> system.cpu.l2cache.overall_misses::total 155028 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 164250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 365000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 954586500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2172547250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 3127663000 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15242851 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 15242851 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7899568975 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7899568975 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 164250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 365000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 954586500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10072116225 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 11027231975 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 164250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 365000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 954586500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10072116225 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 11027231975 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6618 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2871 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 790615 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1307906 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2108010 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1541461 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1541461 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1631 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1631 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 313068 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 313068 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6618 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 2871 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 790615 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1620974 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2421078 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6618 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 2871 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 790615 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1620974 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2421078 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000302 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001742 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016353 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021895 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.019721 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808706 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808706 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362397 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.362397 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000302 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001742 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016353 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.087658 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.064033 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000302 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001742 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016353 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.087658 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.064033 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 82125 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 73000 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73832.972388 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75865.043475 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 75233.035865 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11556.369219 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11556.369219 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69627.332202 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69627.332202 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 82125 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73832.972388 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70884.470801 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 71130.582701 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 82125 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73832.972388 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70884.470801 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 71130.582701 # average overall miss latency
1203,1205c1220,1222
< system.cpu.l2cache.writebacks::writebacks 80285 # number of writebacks
< system.cpu.l2cache.writebacks::total 80285 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses
---
> system.cpu.l2cache.writebacks::writebacks 80343 # number of writebacks
> system.cpu.l2cache.writebacks::total 80343 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2 # number of ReadReq MSHR misses
1207,1214c1224,1231
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12963 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28642 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 41611 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1325 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 1325 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113677 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 113677 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12929 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28637 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 41573 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1319 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 1319 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113455 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 113455 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2 # number of demand (read+write) MSHR misses
1216,1219c1233,1236
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 12963 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 142319 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 155288 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 12929 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 142092 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 155028 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2 # number of overall MSHR misses
1221,1242c1238,1259
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 12963 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 142319 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 155288 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 48750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 784590000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1789530750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2574457250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13262825 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13262825 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6444689027 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6444689027 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 48750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 784590000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8234219777 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 9019146277 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 48750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 784590000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8234219777 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 9019146277 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 12929 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 142092 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 155028 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 138750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 792612500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1813424750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2606477500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13194319 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13194319 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6481465525 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6481465525 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 138750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 792612500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8294890275 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9087943025 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 138750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 792612500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8294890275 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9087943025 # number of overall MSHR miss cycles
1249,1286c1266,1303
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021907 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019705 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808420 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808420 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.363017 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.363017 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.064039 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.064039 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60525.341356 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.252496 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61869.631828 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.679245 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.679245 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56692.990024 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56692.990024 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021895 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019721 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808706 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808706 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362397 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362397 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.064033 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000302 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001742 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016353 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087658 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.064033 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61305.011989 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63324.536439 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62696.401511 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10003.274450 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10003.274450 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57128.073025 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57128.073025 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 69375 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61305.011989 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58376.898594 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58621.300830 # average overall mshr miss latency