3,5c3,5
< sim_seconds 5.200396 # Number of seconds simulated
< sim_ticks 5200396150000 # Number of ticks simulated
< final_tick 5200396150000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.192526 # Number of seconds simulated
> sim_ticks 5192526233000 # Number of ticks simulated
> final_tick 5192526233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 778841 # Simulator instruction rate (inst/s)
< host_op_rate 1501355 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 31560622919 # Simulator tick rate (ticks/s)
< host_mem_usage 627712 # Number of bytes of host memory used
< host_seconds 164.77 # Real time elapsed on the host
< sim_insts 128333376 # Number of instructions simulated
< sim_ops 247385531 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1492668 # Simulator instruction rate (inst/s)
> host_op_rate 2877328 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 60393582039 # Simulator tick rate (ticks/s)
> host_mem_usage 592376 # Number of bytes of host memory used
> host_seconds 85.98 # Real time elapsed on the host
> sim_insts 128336778 # Number of instructions simulated
> sim_ops 247387190 # Number of ops (including micro ops) simulated
16c16
< system.physmem.bytes_read::pc.south_bridge.ide 2886336 # Number of bytes read from this memory
---
> system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
19,26c19,27
< system.physmem.bytes_read::cpu.inst 825216 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 8967296 # Number of bytes read from this memory
< system.physmem.bytes_read::total 12679232 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 825216 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 825216 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 8106560 # Number of bytes written to this memory
< system.physmem.bytes_written::total 8106560 # Number of bytes written to this memory
< system.physmem.num_reads::pc.south_bridge.ide 45099 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::cpu.inst 829632 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9090688 # Number of bytes read from this memory
> system.physmem.bytes_read::total 9949056 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 829632 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 829632 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 5138240 # Number of bytes written to this memory
> system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
> system.physmem.bytes_written::total 8128320 # Number of bytes written to this memory
> system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
29,34c30,36
< system.physmem.num_reads::cpu.inst 12894 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 140114 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 198113 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 126665 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 126665 # Number of write requests responded to by this memory
< system.physmem.bw_read::pc.south_bridge.ide 555022 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::cpu.inst 12963 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 142042 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 155454 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 80285 # Number of write requests responded to by this memory
> system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 127005 # Number of write requests responded to by this memory
> system.physmem.bw_read::pc.south_bridge.ide 5460 # Total read bandwidth from this memory (bytes/s)
37,45c39,48
< system.physmem.bw_read::cpu.inst 158683 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 1724349 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2438128 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 158683 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 158683 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1558835 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1558835 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1558835 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 555022 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 159774 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 1750725 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1916034 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 159774 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 159774 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 989545 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::pc.south_bridge.ide 575843 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1565388 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 989545 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 581303 # Total bandwidth to/from this memory (bytes/s)
48,60c51,63
< system.physmem.bw_total::cpu.inst 158683 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 1724349 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 3996963 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 198113 # Number of read requests accepted
< system.physmem.writeReqs 126665 # Number of write requests accepted
< system.physmem.readBursts 198113 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 126665 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 12670976 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue
< system.physmem.bytesWritten 8105536 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 12679232 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 8106560 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bw_total::cpu.inst 159774 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 1750725 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 3481422 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 155454 # Number of read requests accepted
> system.physmem.writeReqs 127005 # Number of write requests accepted
> system.physmem.readBursts 155454 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 127005 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 9932928 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 16128 # Total number of bytes read from write queue
> system.physmem.bytesWritten 8126720 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 9949056 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 8128320 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 252 # Number of DRAM read bursts serviced by the write queue
62,94c65,97
< system.physmem.neitherReadNorWriteReqs 1623 # Number of requests that are neither read nor write
< system.physmem.perBankRdBursts::0 12177 # Per bank write bursts
< system.physmem.perBankRdBursts::1 12548 # Per bank write bursts
< system.physmem.perBankRdBursts::2 13053 # Per bank write bursts
< system.physmem.perBankRdBursts::3 12620 # Per bank write bursts
< system.physmem.perBankRdBursts::4 12592 # Per bank write bursts
< system.physmem.perBankRdBursts::5 12288 # Per bank write bursts
< system.physmem.perBankRdBursts::6 11961 # Per bank write bursts
< system.physmem.perBankRdBursts::7 12236 # Per bank write bursts
< system.physmem.perBankRdBursts::8 11972 # Per bank write bursts
< system.physmem.perBankRdBursts::9 11957 # Per bank write bursts
< system.physmem.perBankRdBursts::10 12338 # Per bank write bursts
< system.physmem.perBankRdBursts::11 12177 # Per bank write bursts
< system.physmem.perBankRdBursts::12 12807 # Per bank write bursts
< system.physmem.perBankRdBursts::13 12813 # Per bank write bursts
< system.physmem.perBankRdBursts::14 12433 # Per bank write bursts
< system.physmem.perBankRdBursts::15 12012 # Per bank write bursts
< system.physmem.perBankWrBursts::0 7757 # Per bank write bursts
< system.physmem.perBankWrBursts::1 8145 # Per bank write bursts
< system.physmem.perBankWrBursts::2 8603 # Per bank write bursts
< system.physmem.perBankWrBursts::3 8164 # Per bank write bursts
< system.physmem.perBankWrBursts::4 8201 # Per bank write bursts
< system.physmem.perBankWrBursts::5 7973 # Per bank write bursts
< system.physmem.perBankWrBursts::6 7511 # Per bank write bursts
< system.physmem.perBankWrBursts::7 7789 # Per bank write bursts
< system.physmem.perBankWrBursts::8 7356 # Per bank write bursts
< system.physmem.perBankWrBursts::9 7523 # Per bank write bursts
< system.physmem.perBankWrBursts::10 7874 # Per bank write bursts
< system.physmem.perBankWrBursts::11 7684 # Per bank write bursts
< system.physmem.perBankWrBursts::12 8313 # Per bank write bursts
< system.physmem.perBankWrBursts::13 8300 # Per bank write bursts
< system.physmem.perBankWrBursts::14 7968 # Per bank write bursts
< system.physmem.perBankWrBursts::15 7488 # Per bank write bursts
---
> system.physmem.neitherReadNorWriteReqs 1602 # Number of requests that are neither read nor write
> system.physmem.perBankRdBursts::0 10234 # Per bank write bursts
> system.physmem.perBankRdBursts::1 9830 # Per bank write bursts
> system.physmem.perBankRdBursts::2 10412 # Per bank write bursts
> system.physmem.perBankRdBursts::3 9937 # Per bank write bursts
> system.physmem.perBankRdBursts::4 9788 # Per bank write bursts
> system.physmem.perBankRdBursts::5 9348 # Per bank write bursts
> system.physmem.perBankRdBursts::6 9238 # Per bank write bursts
> system.physmem.perBankRdBursts::7 9473 # Per bank write bursts
> system.physmem.perBankRdBursts::8 9270 # Per bank write bursts
> system.physmem.perBankRdBursts::9 9085 # Per bank write bursts
> system.physmem.perBankRdBursts::10 9528 # Per bank write bursts
> system.physmem.perBankRdBursts::11 9619 # Per bank write bursts
> system.physmem.perBankRdBursts::12 9707 # Per bank write bursts
> system.physmem.perBankRdBursts::13 10058 # Per bank write bursts
> system.physmem.perBankRdBursts::14 9877 # Per bank write bursts
> system.physmem.perBankRdBursts::15 9798 # Per bank write bursts
> system.physmem.perBankWrBursts::0 8316 # Per bank write bursts
> system.physmem.perBankWrBursts::1 7729 # Per bank write bursts
> system.physmem.perBankWrBursts::2 8212 # Per bank write bursts
> system.physmem.perBankWrBursts::3 7860 # Per bank write bursts
> system.physmem.perBankWrBursts::4 8063 # Per bank write bursts
> system.physmem.perBankWrBursts::5 7657 # Per bank write bursts
> system.physmem.perBankWrBursts::6 7184 # Per bank write bursts
> system.physmem.perBankWrBursts::7 7824 # Per bank write bursts
> system.physmem.perBankWrBursts::8 7616 # Per bank write bursts
> system.physmem.perBankWrBursts::9 7570 # Per bank write bursts
> system.physmem.perBankWrBursts::10 7824 # Per bank write bursts
> system.physmem.perBankWrBursts::11 7928 # Per bank write bursts
> system.physmem.perBankWrBursts::12 8040 # Per bank write bursts
> system.physmem.perBankWrBursts::13 8642 # Per bank write bursts
> system.physmem.perBankWrBursts::14 8420 # Per bank write bursts
> system.physmem.perBankWrBursts::15 8095 # Per bank write bursts
97c100
< system.physmem.totGap 5200396086500 # Total gap between requests
---
> system.physmem.totGap 5192526169500 # Total gap between requests
104c107
< system.physmem.readPktSize::6 198113 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 155454 # Read request sizes (log2)
111,132c114,135
< system.physmem.writePktSize::6 126665 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 153621 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 2695 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 4322 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 2990 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 3543 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 4544 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 4208 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 3990 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 3280 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 2652 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 2195 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 1870 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 1376 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 1254 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 1133 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1028 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::16 1144 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::17 834 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::18 668 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::19 612 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::20 25 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 127005 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 151750 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 3023 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 54 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
159,261c162,268
< system.physmem.wrQLenPdf::15 1639 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 1812 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 5075 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 5119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 5183 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 5335 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 5509 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 5794 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 5985 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 6651 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 6946 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 6999 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 7260 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 7338 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 7801 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 7668 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 7468 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 2018 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1858 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 2408 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 2636 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 2551 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 2242 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 1885 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 1536 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 1298 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 897 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 721 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 585 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 223 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 59433 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 349.577642 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 202.117781 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 357.932182 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 20505 34.50% 34.50% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 13774 23.18% 57.68% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 5765 9.70% 67.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 3461 5.82% 73.20% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2240 3.77% 76.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1591 2.68% 79.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 1115 1.88% 81.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 921 1.55% 83.07% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 10061 16.93% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 59433 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 6976 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 28.380447 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 572.057676 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-2047 6975 99.99% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 6976 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 6976 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 18.154960 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.623474 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 5.583584 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16-17 4785 68.59% 68.59% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18-19 1454 20.84% 89.44% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20-21 33 0.47% 89.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22-23 125 1.79% 91.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24-25 57 0.82% 92.52% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26-27 47 0.67% 93.19% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28-29 75 1.08% 94.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::30-31 59 0.85% 95.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::32-33 41 0.59% 95.70% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::34-35 19 0.27% 95.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::36-37 30 0.43% 96.40% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::38-39 56 0.80% 97.20% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::40-41 145 2.08% 99.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::42-43 17 0.24% 99.53% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::44-45 4 0.06% 99.58% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::46-47 11 0.16% 99.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::48-49 3 0.04% 99.78% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::50-51 3 0.04% 99.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::52-53 2 0.03% 99.86% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::54-55 2 0.03% 99.89% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::56-57 1 0.01% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::58-59 1 0.01% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::60-61 2 0.03% 99.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::62-63 3 0.04% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::68-69 1 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 6976 # Writes before turning the bus around for reads
< system.physmem.totQLat 5514862500 # Total ticks spent queuing
< system.physmem.totMemAccLat 9227062500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 989920000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 27855.09 # Average queueing delay per DRAM burst
---
> system.physmem.wrQLenPdf::15 2439 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 3242 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 6145 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 6383 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 6406 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 7175 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 7465 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 8169 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 8822 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 9909 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 9129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 8509 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 7675 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 7337 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 6397 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 6159 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6188 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 6092 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 180 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 164 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 203 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 191 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 183 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 171 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 170 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 146 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 140 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::52 55 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::54 37 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::57 28 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 56259 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 321.007910 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 189.347718 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 335.337897 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 20082 35.70% 35.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 13652 24.27% 59.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 5681 10.10% 70.06% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 3443 6.12% 76.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 2317 4.12% 80.30% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1632 2.90% 83.20% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 1101 1.96% 85.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1008 1.79% 86.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 7343 13.05% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 56259 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 5896 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 26.315638 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 622.349689 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-2047 5895 99.98% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 5896 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 5896 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 21.536635 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 19.431893 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 14.049302 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16-19 4860 82.43% 82.43% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20-23 44 0.75% 83.18% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24-27 38 0.64% 83.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28-31 287 4.87% 88.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::32-35 272 4.61% 93.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::36-39 20 0.34% 93.64% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::40-43 25 0.42% 94.06% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::44-47 11 0.19% 94.25% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::48-51 27 0.46% 94.71% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::52-55 4 0.07% 94.78% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::56-59 3 0.05% 94.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::60-63 1 0.02% 94.84% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::64-67 223 3.78% 98.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::68-71 4 0.07% 98.69% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::72-75 6 0.10% 98.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::76-79 3 0.05% 98.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::80-83 20 0.34% 99.19% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::84-87 1 0.02% 99.20% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::92-95 1 0.02% 99.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::96-99 10 0.17% 99.39% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::100-103 2 0.03% 99.42% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::104-107 2 0.03% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::108-111 2 0.03% 99.49% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::112-115 8 0.14% 99.63% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::116-119 2 0.03% 99.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::120-123 4 0.07% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::128-131 13 0.22% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 5896 # Writes before turning the bus around for reads
> system.physmem.totQLat 1473683250 # Total ticks spent queuing
> system.physmem.totMemAccLat 4383720750 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 776010000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 9495.26 # Average queueing delay per DRAM burst
263,267c270,274
< system.physmem.avgMemAccLat 46605.09 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28245.26 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 1.92 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s
270c277
< system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
---
> system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
272,281c279,288
< system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing
< system.physmem.readRowHits 166366 # Number of row buffer hits during reads
< system.physmem.writeRowHits 98833 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes
< system.physmem.avgGap 16012156.26 # Average gap between requests
< system.physmem.pageHitRate 81.69 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 4979189621500 # Time in different power states
< system.physmem.memoryStateTime::REF 173652440000 # Time in different power states
---
> system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 22.52 # Average write queue length when enqueuing
> system.physmem.readRowHits 127189 # Number of row buffer hits during reads
> system.physmem.writeRowHits 98733 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 81.95 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 77.74 # Row buffer hit rate for writes
> system.physmem.avgGap 18383291.63 # Average gap between requests
> system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 4971157882750 # Time in different power states
> system.physmem.memoryStateTime::REF 173389840000 # Time in different power states
283c290
< system.physmem.memoryStateTime::ACT 47553973500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 47978395250 # Time in different power states
285,298c292,307
< system.membus.throughput 4356964 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 623381 # Transaction distribution
< system.membus.trans_dist::ReadResp 623381 # Transaction distribution
< system.membus.trans_dist::WriteReq 13777 # Transaction distribution
< system.membus.trans_dist::WriteResp 13777 # Transaction distribution
< system.membus.trans_dist::Writeback 126665 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution
< system.membus.trans_dist::UpgradeResp 1641 # Transaction distribution
< system.membus.trans_dist::ReadExReq 159285 # Transaction distribution
< system.membus.trans_dist::ReadExResp 159285 # Transaction distribution
< system.membus.trans_dist::MessageReq 1656 # Transaction distribution
< system.membus.trans_dist::MessageResp 1656 # Transaction distribution
< system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes)
---
> system.membus.throughput 3808612 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 623901 # Transaction distribution
> system.membus.trans_dist::ReadResp 623901 # Transaction distribution
> system.membus.trans_dist::WriteReq 13773 # Transaction distribution
> system.membus.trans_dist::WriteResp 13773 # Transaction distribution
> system.membus.trans_dist::Writeback 80285 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
> system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 2146 # Transaction distribution
> system.membus.trans_dist::UpgradeResp 1602 # Transaction distribution
> system.membus.trans_dist::ReadExReq 113400 # Transaction distribution
> system.membus.trans_dist::ReadExResp 113400 # Transaction distribution
> system.membus.trans_dist::MessageReq 1654 # Transaction distribution
> system.membus.trans_dist::MessageResp 1654 # Transaction distribution
> system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes)
300,307c309,316
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710118 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390454 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580900 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139322 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 139322 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1723534 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394055 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584493 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94727 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 94727 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1682528 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes)
309,317c318,326
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420233 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14912768 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16579445 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5873024 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.iocache.mem_side::total 5873024 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 22459093 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 22459093 # Total data (bytes)
< system.membus.snoop_data_through_bus 198848 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 256797000 # Layer occupancy (ticks)
---
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15058944 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16725605 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size::total 19750653 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 19750653 # Total data (bytes)
> system.membus.snoop_data_through_bus 25664 # Total snoop data (bytes)
> system.membus.reqLayer0.occupancy 256795500 # Layer occupancy (ticks)
321c330
< system.membus.reqLayer2.occupancy 3312000 # Layer occupancy (ticks)
---
> system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks)
323c332
< system.membus.reqLayer3.occupancy 1351243000 # Layer occupancy (ticks)
---
> system.membus.reqLayer3.occupancy 1309717000 # Layer occupancy (ticks)
325c334
< system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks)
---
> system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks)
327c336
< system.membus.respLayer2.occupancy 2609486505 # Layer occupancy (ticks)
---
> system.membus.respLayer2.occupancy 2621518398 # Layer occupancy (ticks)
329c338
< system.membus.respLayer4.occupancy 429020250 # Layer occupancy (ticks)
---
> system.membus.respLayer4.occupancy 54330498 # Layer occupancy (ticks)
331,332c340,341
< system.iocache.tags.replacements 47501 # number of replacements
< system.iocache.tags.tagsinuse 0.128246 # Cycle average of tags in use
---
> system.iocache.tags.replacements 47509 # number of replacements
> system.iocache.tags.tagsinuse 0.112613 # Cycle average of tags in use
334c343
< system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks.
---
> system.iocache.tags.sampled_refs 47525 # Sample count of references to valid blocks.
336,339c345,348
< system.iocache.tags.warmup_cycle 5049779388000 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128246 # Average occupied blocks per requestor
< system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008015 # Average percentage of cache occupancy
< system.iocache.tags.occ_percent::total 0.008015 # Average percentage of cache occupancy
---
> system.iocache.tags.warmup_cycle 5045777659000 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112613 # Average occupied blocks per requestor
> system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007038 # Average percentage of cache occupancy
> system.iocache.tags.occ_percent::total 0.007038 # Average percentage of cache occupancy
343,368c352,375
< system.iocache.tags.tag_accesses 428004 # Number of tag accesses
< system.iocache.tags.data_accesses 428004 # Number of data accesses
< system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 836 # number of ReadReq misses
< system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
< system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
< system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses
< system.iocache.demand_misses::total 47556 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses
< system.iocache.overall_misses::total 47556 # number of overall misses
< system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140309686 # number of ReadReq miss cycles
< system.iocache.ReadReq_miss_latency::total 140309686 # number of ReadReq miss cycles
< system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12229393602 # number of WriteReq miss cycles
< system.iocache.WriteReq_miss_latency::total 12229393602 # number of WriteReq miss cycles
< system.iocache.demand_miss_latency::pc.south_bridge.ide 12369703288 # number of demand (read+write) miss cycles
< system.iocache.demand_miss_latency::total 12369703288 # number of demand (read+write) miss cycles
< system.iocache.overall_miss_latency::pc.south_bridge.ide 12369703288 # number of overall miss cycles
< system.iocache.overall_miss_latency::total 12369703288 # number of overall miss cycles
< system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses)
< system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
< system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
< system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses
---
> system.iocache.tags.tag_accesses 428076 # Number of tag accesses
> system.iocache.tags.data_accesses 428076 # Number of data accesses
> system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
> system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
> system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
> system.iocache.demand_misses::pc.south_bridge.ide 844 # number of demand (read+write) misses
> system.iocache.demand_misses::total 844 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 844 # number of overall misses
> system.iocache.overall_misses::total 844 # number of overall misses
> system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141199186 # number of ReadReq miss cycles
> system.iocache.ReadReq_miss_latency::total 141199186 # number of ReadReq miss cycles
> system.iocache.demand_miss_latency::pc.south_bridge.ide 141199186 # number of demand (read+write) miss cycles
> system.iocache.demand_miss_latency::total 141199186 # number of demand (read+write) miss cycles
> system.iocache.overall_miss_latency::pc.south_bridge.ide 141199186 # number of overall miss cycles
> system.iocache.overall_miss_latency::total 141199186 # number of overall miss cycles
> system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
> system.iocache.demand_accesses::pc.south_bridge.ide 844 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 844 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 844 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 844 # number of overall (read+write) accesses
371,372d377
< system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
< system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
377,385c382,388
< system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167834.552632 # average ReadReq miss latency
< system.iocache.ReadReq_avg_miss_latency::total 167834.552632 # average ReadReq miss latency
< system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 261759.280865 # average WriteReq miss latency
< system.iocache.WriteReq_avg_miss_latency::total 261759.280865 # average WriteReq miss latency
< system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 260108.152242 # average overall miss latency
< system.iocache.demand_avg_miss_latency::total 260108.152242 # average overall miss latency
< system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 260108.152242 # average overall miss latency
< system.iocache.overall_avg_miss_latency::total 260108.152242 # average overall miss latency
< system.iocache.blocked_cycles::no_mshrs 207651 # number of cycles access was blocked
---
> system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average ReadReq miss latency
> system.iocache.ReadReq_avg_miss_latency::total 167297.613744 # average ReadReq miss latency
> system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency
> system.iocache.demand_avg_miss_latency::total 167297.613744 # average overall miss latency
> system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167297.613744 # average overall miss latency
> system.iocache.overall_avg_miss_latency::total 167297.613744 # average overall miss latency
> system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked
387c390
< system.iocache.blocked::no_mshrs 17427 # number of cycles access was blocked
---
> system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked
389c392
< system.iocache.avg_blocked_cycles::no_mshrs 11.915476 # average number of cycles each access was blocked
---
> system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked
391c394
< system.iocache.fast_writes 0 # number of fast writes performed
---
> system.iocache.fast_writes 46720 # number of fast writes performed
393,410c396,411
< system.iocache.writebacks::writebacks 46667 # number of writebacks
< system.iocache.writebacks::total 46667 # number of writebacks
< system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses
< system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses
< system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
< system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
< system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses
< system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses
< system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses
< system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses
< system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96812686 # number of ReadReq MSHR miss cycles
< system.iocache.ReadReq_mshr_miss_latency::total 96812686 # number of ReadReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9797946102 # number of WriteReq MSHR miss cycles
< system.iocache.WriteReq_mshr_miss_latency::total 9797946102 # number of WriteReq MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9894758788 # number of demand (read+write) MSHR miss cycles
< system.iocache.demand_mshr_miss_latency::total 9894758788 # number of demand (read+write) MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9894758788 # number of overall MSHR miss cycles
< system.iocache.overall_mshr_miss_latency::total 9894758788 # number of overall MSHR miss cycles
---
> system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses
> system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses
> system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses
> system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses
> system.iocache.demand_mshr_misses::pc.south_bridge.ide 844 # number of demand (read+write) MSHR misses
> system.iocache.demand_mshr_misses::total 844 # number of demand (read+write) MSHR misses
> system.iocache.overall_mshr_misses::pc.south_bridge.ide 844 # number of overall MSHR misses
> system.iocache.overall_mshr_misses::total 844 # number of overall MSHR misses
> system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of ReadReq MSHR miss cycles
> system.iocache.ReadReq_mshr_miss_latency::total 97286186 # number of ReadReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2834928162 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2834928162 # number of WriteInvalidateReq MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of demand (read+write) MSHR miss cycles
> system.iocache.demand_mshr_miss_latency::total 97286186 # number of demand (read+write) MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 97286186 # number of overall MSHR miss cycles
> system.iocache.overall_mshr_miss_latency::total 97286186 # number of overall MSHR miss cycles
413,414c414,415
< system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
< system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
---
> system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses
419,426c420,427
< system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115804.648325 # average ReadReq mshr miss latency
< system.iocache.ReadReq_avg_mshr_miss_latency::total 115804.648325 # average ReadReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 209716.312115 # average WriteReq mshr miss latency
< system.iocache.WriteReq_avg_mshr_miss_latency::total 209716.312115 # average WriteReq mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155 # average overall mshr miss latency
< system.iocache.demand_avg_mshr_miss_latency::total 208065.413155 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155 # average overall mshr miss latency
< system.iocache.overall_avg_mshr_miss_latency::total 208065.413155 # average overall mshr miss latency
---
> system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average ReadReq mshr miss latency
> system.iocache.ReadReq_avg_mshr_miss_latency::total 115267.992891 # average ReadReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60679.113057 # average WriteInvalidateReq mshr miss latency
> system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60679.113057 # average WriteInvalidateReq mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency
> system.iocache.demand_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115267.992891 # average overall mshr miss latency
> system.iocache.overall_avg_mshr_miss_latency::total 115267.992891 # average overall mshr miss latency
440,442c441,443
< system.iobus.throughput 630779 # Throughput (bytes/s)
< system.iobus.trans_dist::ReadReq 230141 # Transaction distribution
< system.iobus.trans_dist::ReadResp 230141 # Transaction distribution
---
> system.iobus.throughput 631746 # Throughput (bytes/s)
> system.iobus.trans_dist::ReadReq 230149 # Transaction distribution
> system.iobus.trans_dist::ReadResp 230149 # Transaction distribution
445,446c446,447
< system.iobus.trans_dist::MessageReq 1656 # Transaction distribution
< system.iobus.trans_dist::MessageResp 1656 # Transaction distribution
---
> system.iobus.trans_dist::MessageReq 1654 # Transaction distribution
> system.iobus.trans_dist::MessageResp 1654 # Transaction distribution
466,470c467,471
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes)
< system.iobus.pkt_count::total 578752 # Packet count per connected master and slave (bytes)
---
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95128 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95128 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes)
> system.iobus.pkt_count::total 578764 # Packet count per connected master and slave (bytes)
490,496c491,497
< system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.tot_pkt_size::total 3280300 # Cumulative packet size per connected master and slave (bytes)
< system.iobus.data_through_bus 3280300 # Total data (bytes)
< system.iobus.reqLayer0.occupancy 3954900 # Layer occupancy (ticks)
---
> system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027296 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027296 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.tot_pkt_size::total 3280356 # Cumulative packet size per connected master and slave (bytes)
> system.iobus.data_through_bus 3280356 # Total data (bytes)
> system.iobus.reqLayer0.occupancy 3944816 # Layer occupancy (ticks)
532c533
< system.iobus.reqLayer18.occupancy 424640038 # Layer occupancy (ticks)
---
> system.iobus.reqLayer18.occupancy 421898846 # Layer occupancy (ticks)
538c539
< system.iobus.respLayer1.occupancy 53686750 # Layer occupancy (ticks)
---
> system.iobus.respLayer1.occupancy 52228502 # Layer occupancy (ticks)
540c541
< system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks)
---
> system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks)
544c545
< system.cpu.numCycles 10400792300 # number of cpu cycles simulated
---
> system.cpu.numCycles 10385052466 # number of cpu cycles simulated
547,549c548,550
< system.cpu.committedInsts 128333376 # Number of instructions committed
< system.cpu.committedOps 247385531 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 231978349 # Number of integer alu accesses
---
> system.cpu.committedInsts 128336778 # Number of instructions committed
> system.cpu.committedOps 247387190 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 231979854 # Number of integer alu accesses
551,553c552,554
< system.cpu.num_func_calls 2299991 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 23168967 # number of instructions that are conditional controls
< system.cpu.num_int_insts 231978349 # number of integer instructions
---
> system.cpu.num_func_calls 2299861 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 23168822 # number of instructions that are conditional controls
> system.cpu.num_int_insts 231979854 # number of integer instructions
555,556c556,557
< system.cpu.num_int_register_reads 434511356 # number of times the integer registers were read
< system.cpu.num_int_register_writes 197852349 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 434516750 # number of times the integer registers were read
> system.cpu.num_int_register_writes 197854064 # number of times the integer registers were written
559,572c560,573
< system.cpu.num_cc_register_reads 132811982 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 95533715 # number of times the CC registers were written
< system.cpu.num_mem_refs 22244872 # number of memory refs
< system.cpu.num_load_insts 13879055 # Number of load instructions
< system.cpu.num_store_insts 8365817 # Number of store instructions
< system.cpu.num_idle_cycles 9793794512.998117 # Number of idle cycles
< system.cpu.num_busy_cycles 606997787.001883 # Number of busy cycles
< system.cpu.not_idle_fraction 0.058361 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.941639 # Percentage of idle cycles
< system.cpu.Branches 26307123 # Number of branches fetched
< system.cpu.op_class::No_OpClass 174810 0.07% 0.07% # Class of executed instruction
< system.cpu.op_class::IntAlu 224704553 90.83% 90.90% # Class of executed instruction
< system.cpu.op_class::IntMult 139755 0.06% 90.96% # Class of executed instruction
< system.cpu.op_class::IntDiv 123089 0.05% 91.01% # Class of executed instruction
---
> system.cpu.num_cc_register_reads 132811657 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 95534544 # number of times the CC registers were written
> system.cpu.num_mem_refs 22246380 # number of memory refs
> system.cpu.num_load_insts 13880618 # Number of load instructions
> system.cpu.num_store_insts 8365762 # Number of store instructions
> system.cpu.num_idle_cycles 9788359567.998116 # Number of idle cycles
> system.cpu.num_busy_cycles 596692898.001885 # Number of busy cycles
> system.cpu.not_idle_fraction 0.057457 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.942543 # Percentage of idle cycles
> system.cpu.Branches 26306776 # Number of branches fetched
> system.cpu.op_class::No_OpClass 174693 0.07% 0.07% # Class of executed instruction
> system.cpu.op_class::IntAlu 224704760 90.83% 90.90% # Class of executed instruction
> system.cpu.op_class::IntMult 139946 0.06% 90.96% # Class of executed instruction
> system.cpu.op_class::IntDiv 122983 0.05% 91.01% # Class of executed instruction
599,600c600,601
< system.cpu.op_class::MemRead 13879055 5.61% 96.62% # Class of executed instruction
< system.cpu.op_class::MemWrite 8365817 3.38% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 13880618 5.61% 96.62% # Class of executed instruction
> system.cpu.op_class::MemWrite 8365762 3.38% 100.00% # Class of executed instruction
603c604
< system.cpu.op_class::total 247387079 # Class of executed instruction
---
> system.cpu.op_class::total 247388762 # Class of executed instruction
606,614c607,615
< system.cpu.icache.tags.replacements 791030 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.352813 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 144579864 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 791542 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 182.655960 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 161437750250 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.352813 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.996783 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.996783 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.replacements 794564 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.353610 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 144580687 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 795076 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 181.845115 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 161037642250 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.353610 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.996784 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.996784 # Average percentage of cache occupancy
616,619c617,620
< system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 159 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
621,658c622,659
< system.cpu.icache.tags.tag_accesses 146162962 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 146162962 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 144579864 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 144579864 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 144579864 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 144579864 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 144579864 # number of overall hits
< system.cpu.icache.overall_hits::total 144579864 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 791549 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 791549 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 791549 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 791549 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 791549 # number of overall misses
< system.cpu.icache.overall_misses::total 791549 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108553755 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 11108553755 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 11108553755 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 11108553755 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 11108553755 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 11108553755 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 145371413 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 145371413 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 145371413 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 145371413 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 145371413 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 145371413 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005445 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.005445 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.005445 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.005445 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.005445 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.005445 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14033.943262 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 14033.943262 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 14033.943262 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 14033.943262 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 14033.943262 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 14033.943262 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 146170853 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 146170853 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 144580687 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 144580687 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 144580687 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 144580687 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 144580687 # number of overall hits
> system.cpu.icache.overall_hits::total 144580687 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 795083 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 795083 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 795083 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 795083 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 795083 # number of overall misses
> system.cpu.icache.overall_misses::total 795083 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 11158319369 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 11158319369 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 11158319369 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 11158319369 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 11158319369 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 11158319369 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 145375770 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 145375770 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 145375770 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 145375770 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 145375770 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 145375770 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005469 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.005469 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.005469 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.005469 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.005469 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.005469 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14034.156647 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 14034.156647 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 14034.156647 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 14034.156647 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 14034.156647 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 14034.156647 # average overall miss latency
667,690c668,691
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791549 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 791549 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 791549 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 791549 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 791549 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 791549 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9520697745 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 9520697745 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9520697745 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 9520697745 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9520697745 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 9520697745 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005445 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.005445 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.005445 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.932251 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.932251 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.932251 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.932251 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.932251 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.932251 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795083 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 795083 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 795083 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 795083 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 795083 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 795083 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9563233631 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 9563233631 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9563233631 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 9563233631 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9563233631 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 9563233631 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005469 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.005469 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005469 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.005469 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.968943 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.968943 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.968943 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.968943 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.968943 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.968943 # average overall mshr miss latency
692,703c693,704
< system.cpu.itb_walker_cache.tags.replacements 3407 # number of replacements
< system.cpu.itb_walker_cache.tags.tagsinuse 3.079507 # Cycle average of tags in use
< system.cpu.itb_walker_cache.tags.total_refs 7935 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.sampled_refs 3418 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.tags.avg_refs 2.321533 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.tags.warmup_cycle 5169623666000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.079507 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192469 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_percent::total 0.192469 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
---
> system.cpu.itb_walker_cache.tags.replacements 3511 # number of replacements
> system.cpu.itb_walker_cache.tags.tagsinuse 3.067889 # Cycle average of tags in use
> system.cpu.itb_walker_cache.tags.total_refs 7844 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.sampled_refs 3523 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.tags.avg_refs 2.226511 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.tags.warmup_cycle 5164932679000 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.067889 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191743 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_percent::total 0.191743 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
> system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id
705,710c706,710
< system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
< system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
< system.cpu.itb_walker_cache.tags.tag_accesses 28718 # Number of tag accesses
< system.cpu.itb_walker_cache.tags.data_accesses 28718 # Number of data accesses
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7937 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 7937 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
> system.cpu.itb_walker_cache.tags.tag_accesses 28837 # Number of tag accesses
> system.cpu.itb_walker_cache.tags.data_accesses 28837 # Number of data accesses
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7845 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 7845 # number of ReadReq hits
713,730c713,730
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7939 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 7939 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7939 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 7939 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4280 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 4280 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4280 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 4280 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4280 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 4280 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42457500 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42457500 # number of ReadReq miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42457500 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.demand_miss_latency::total 42457500 # number of demand (read+write) miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42457500 # number of overall miss cycles
< system.cpu.itb_walker_cache.overall_miss_latency::total 42457500 # number of overall miss cycles
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12217 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7847 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 7847 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7847 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 7847 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4381 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 4381 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4381 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 4381 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4381 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 4381 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 43773750 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.ReadReq_miss_latency::total 43773750 # number of ReadReq miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 43773750 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.demand_miss_latency::total 43773750 # number of demand (read+write) miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 43773750 # number of overall miss cycles
> system.cpu.itb_walker_cache.overall_miss_latency::total 43773750 # number of overall miss cycles
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12226 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses)
733,748c733,748
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12219 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12219 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.350332 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.350332 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.350274 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.350274 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.350274 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.350274 # miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9919.976636 # average ReadReq miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9919.976636 # average ReadReq miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9919.976636 # average overall miss latency
< system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9919.976636 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9919.976636 # average overall miss latency
< system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9919.976636 # average overall miss latency
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12228 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12228 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.358335 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.358335 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.358276 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.358276 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.358276 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.358276 # miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9991.725633 # average ReadReq miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9991.725633 # average ReadReq miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency
> system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9991.725633 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9991.725633 # average overall miss latency
> system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9991.725633 # average overall miss latency
757,782c757,782
< system.cpu.itb_walker_cache.writebacks::writebacks 704 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 704 # number of writebacks
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4280 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4280 # number of ReadReq MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4280 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.demand_mshr_misses::total 4280 # number of demand (read+write) MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4280 # number of overall MSHR misses
< system.cpu.itb_walker_cache.overall_mshr_misses::total 4280 # number of overall MSHR misses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33895500 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33895500 # number of ReadReq MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33895500 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33895500 # number of demand (read+write) MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33895500 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33895500 # number of overall MSHR miss cycles
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.350332 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.350332 # mshr miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.350274 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.350274 # mshr miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.350274 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.350274 # mshr miss rate for overall accesses
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7919.509346 # average ReadReq mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average overall mshr miss latency
< system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7919.509346 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average overall mshr miss latency
< system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7919.509346 # average overall mshr miss latency
---
> system.cpu.itb_walker_cache.writebacks::writebacks 771 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 771 # number of writebacks
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4381 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4381 # number of ReadReq MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4381 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.demand_mshr_misses::total 4381 # number of demand (read+write) MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4381 # number of overall MSHR misses
> system.cpu.itb_walker_cache.overall_mshr_misses::total 4381 # number of overall MSHR misses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35010250 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35010250 # number of ReadReq MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35010250 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35010250 # number of demand (read+write) MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35010250 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35010250 # number of overall MSHR miss cycles
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.358335 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.358335 # mshr miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.358276 # mshr miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.358276 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.358276 # mshr miss rate for overall accesses
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7991.383246 # average ReadReq mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency
> system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7991.383246 # average overall mshr miss latency
> system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7991.383246 # average overall mshr miss latency
784,792c784,792
< system.cpu.dtb_walker_cache.tags.replacements 7502 # number of replacements
< system.cpu.dtb_walker_cache.tags.tagsinuse 5.061351 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 13282 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.sampled_refs 7516 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.avg_refs 1.767163 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 5167976228000 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061351 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316334 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316334 # Average percentage of cache occupancy
---
> system.cpu.dtb_walker_cache.tags.replacements 7447 # number of replacements
> system.cpu.dtb_walker_cache.tags.tagsinuse 5.051866 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 13273 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.sampled_refs 7461 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.avg_refs 1.778984 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 5163481853000 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.051866 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315742 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315742 # Average percentage of cache occupancy
794,795c794,795
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
---
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
797c797
< system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
---
> system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
799,836c799,836
< system.cpu.dtb_walker_cache.tags.tag_accesses 52668 # Number of tag accesses
< system.cpu.dtb_walker_cache.tags.data_accesses 52668 # Number of data accesses
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13284 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 13284 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13284 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 13284 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13284 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 13284 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8700 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 8700 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8700 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 8700 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8700 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 8700 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92345000 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92345000 # number of ReadReq miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92345000 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.demand_miss_latency::total 92345000 # number of demand (read+write) miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92345000 # number of overall miss cycles
< system.cpu.dtb_walker_cache.overall_miss_latency::total 92345000 # number of overall miss cycles
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21984 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 21984 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21984 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 21984 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21984 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 21984 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395742 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395742 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395742 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395742 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395742 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395742 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10614.367816 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10614.367816 # average ReadReq miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10614.367816 # average overall miss latency
< system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10614.367816 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10614.367816 # average overall miss latency
< system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10614.367816 # average overall miss latency
---
> system.cpu.dtb_walker_cache.tags.tag_accesses 52546 # Number of tag accesses
> system.cpu.dtb_walker_cache.tags.data_accesses 52546 # Number of data accesses
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13289 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 13289 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13289 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 13289 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13289 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 13289 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8656 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 8656 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8656 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 8656 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8656 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 8656 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 91979000 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 91979000 # number of ReadReq miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 91979000 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.demand_miss_latency::total 91979000 # number of demand (read+write) miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 91979000 # number of overall miss cycles
> system.cpu.dtb_walker_cache.overall_miss_latency::total 91979000 # number of overall miss cycles
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21945 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 21945 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21945 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 21945 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21945 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 21945 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.394441 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.394441 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.394441 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.394441 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.394441 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.394441 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10626.039741 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10626.039741 # average ReadReq miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency
> system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10626.039741 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10626.039741 # average overall miss latency
> system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10626.039741 # average overall miss latency
845,870c845,870
< system.cpu.dtb_walker_cache.writebacks::writebacks 3054 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 3054 # number of writebacks
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8700 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8700 # number of ReadReq MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8700 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.demand_mshr_misses::total 8700 # number of demand (read+write) MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8700 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.overall_mshr_misses::total 8700 # number of overall MSHR misses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74944500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74944500 # number of ReadReq MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74944500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74944500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74944500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74944500 # number of overall MSHR miss cycles
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395742 # mshr miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395742 # mshr miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395742 # mshr miss rate for overall accesses
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8614.310345 # average ReadReq mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8614.310345 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average overall mshr miss latency
< system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8614.310345 # average overall mshr miss latency
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 2980 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 2980 # number of writebacks
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8656 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8656 # number of ReadReq MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8656 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.demand_mshr_misses::total 8656 # number of demand (read+write) MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8656 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.overall_mshr_misses::total 8656 # number of overall MSHR misses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74666500 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74666500 # number of ReadReq MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74666500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74666500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74666500 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74666500 # number of overall MSHR miss cycles
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.394441 # mshr miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.394441 # mshr miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.394441 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.394441 # mshr miss rate for overall accesses
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8625.981978 # average ReadReq mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8625.981978 # average overall mshr miss latency
> system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8625.981978 # average overall mshr miss latency
872,876c872,876
< system.cpu.dcache.tags.replacements 1620643 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.997078 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 20036158 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1621155 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 12.359187 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 1620883 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.997130 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 20027756 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1621395 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 12.352176 # Average number of references to valid blocks.
878c878
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.997078 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.997130 # Average occupied blocks per requestor
882,884c882,884
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id
887,937c887,945
< system.cpu.dcache.tags.tag_accesses 88250512 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 88250512 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 11993410 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 11993410 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8040535 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8040535 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20033945 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20033945 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20033945 # number of overall hits
< system.cpu.dcache.overall_hits::total 20033945 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1308416 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1308416 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 314973 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 314973 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 1623389 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1623389 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1623389 # number of overall misses
< system.cpu.dcache.overall_misses::total 1623389 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 18840132304 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 18840132304 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 10814294936 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 10814294936 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 29654427240 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 29654427240 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 29654427240 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 29654427240 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 13301826 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13301826 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8355508 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8355508 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21657334 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21657334 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21657334 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21657334 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098364 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.098364 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037696 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.037696 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.074958 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.074958 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.074958 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.074958 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.191315 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.191315 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34334.037952 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 34334.037952 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 18266.987912 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 18266.987912 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 18266.987912 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 18266.987912 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.dcache.tags.tag_accesses 88256675 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 88256675 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 11935486 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 11935486 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8030839 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8030839 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 59261 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 59261 # number of SoftPFReq hits
> system.cpu.dcache.demand_hits::cpu.data 19966325 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 19966325 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20025586 # number of overall hits
> system.cpu.dcache.overall_hits::total 20025586 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 906294 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 906294 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 324617 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 324617 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 402313 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 402313 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 1230911 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1230911 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1633224 # number of overall misses
> system.cpu.dcache.overall_misses::total 1633224 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12712957750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12712957750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 11341720828 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 11341720828 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 24054678578 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 24054678578 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 24054678578 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 24054678578 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 12841780 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 12841780 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8355456 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8355456 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::cpu.data 461574 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.SoftPFReq_accesses::total 461574 # number of SoftPFReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21197236 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21197236 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21658810 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21658810 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070574 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.070574 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038851 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.038851 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871611 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.871611 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.058069 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.058069 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.075407 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.075407 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14027.410255 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 14027.410255 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34938.776552 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 34938.776552 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 19542.175330 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 19542.175330 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 14728.340128 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 14728.340128 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 7655 # number of cycles access was blocked
939c947
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked
941c949
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.863014 # average number of cycles each access was blocked
945,984c953,1008
< system.cpu.dcache.writebacks::writebacks 1537613 # number of writebacks
< system.cpu.dcache.writebacks::total 1537613 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308416 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 1308416 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314973 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 314973 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 1623389 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 1623389 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 1623389 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 1623389 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16214330696 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 16214330696 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10132215064 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 10132215064 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26346545760 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 26346545760 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26346545760 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 26346545760 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672500 # number of ReadReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537738000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537738000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752410500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752410500 # number of overall MSHR uncacheable cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098364 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098364 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037696 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037696 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074958 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.074958 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074958 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.074958 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12392.335997 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12392.335997 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32168.519410 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32168.519410 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16229.348456 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 16229.348456 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16229.348456 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 16229.348456 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 1537682 # number of writebacks
> system.cpu.dcache.writebacks::total 1537682 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9297 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 9297 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 9584 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 9584 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 9584 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 9584 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906007 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 906007 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315320 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 315320 # number of WriteReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402278 # number of SoftPFReq MSHR misses
> system.cpu.dcache.SoftPFReq_mshr_misses::total 402278 # number of SoftPFReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 1221327 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 1221327 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 1623605 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 1623605 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10893569500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10893569500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10209797624 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 10209797624 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5351981750 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5351981750 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21103367124 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 21103367124 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26455348874 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 26455348874 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672000 # number of ReadReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537257000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537257000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96751929000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.overall_mshr_uncacheable_latency::total 96751929000 # number of overall MSHR uncacheable cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070552 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070552 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037738 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037738 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871535 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871535 # mshr miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057617 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.057617 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074963 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.074963 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12023.714497 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12023.714497 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32379.162831 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32379.162831 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13304.187030 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13304.187030 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17279.047400 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 17279.047400 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16294.202638 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 16294.202638 # average overall mshr miss latency
992,1014c1016,1039
< system.cpu.toL2Bus.throughput 49146383 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 2695227 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 2694701 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteReq 13777 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WriteResp 13777 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 1541371 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 2213 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 2213 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 359480 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 312780 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583085 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5973901 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7764 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18139 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 7582889 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50658304 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203802165 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 222976 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 604096 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 255287541 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 255266421 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 314240 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 3830515500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.throughput 49844829 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 2698695 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 2698173 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 1541433 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 2183 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 2183 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 313150 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 313150 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1590153 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5974271 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8035 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18003 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 7590462 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50884480 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203815525 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 233856 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 598208 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 255532069 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 255511461 # Total data (bytes)
> system.cpu.toL2Bus.snoop_data_through_bus 3309120 # Total snoop data (bytes)
> system.cpu.toL2Bus.reqLayer0.occupancy 3832514500 # Layer occupancy (ticks)
1016c1041
< system.cpu.toL2Bus.snoopLayer0.occupancy 495000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 483000 # Layer occupancy (ticks)
1018c1043
< system.cpu.toL2Bus.respLayer0.occupancy 1189702505 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1195084369 # Layer occupancy (ticks)
1020c1045
< system.cpu.toL2Bus.respLayer1.occupancy 3051756740 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 3051993102 # Layer occupancy (ticks)
1022c1047
< system.cpu.toL2Bus.respLayer2.occupancy 6421000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer2.occupancy 6572250 # Layer occupancy (ticks)
1024c1049
< system.cpu.toL2Bus.respLayer3.occupancy 13050250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer3.occupancy 12984250 # Layer occupancy (ticks)
1026,1030c1051,1055
< system.cpu.l2cache.tags.replacements 86651 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64733.611120 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3487942 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 151340 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 23.047060 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 87211 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64746.136544 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3491181 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 151954 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 22.975249 # Average number of references to valid blocks.
1032,1037c1057,1062
< system.cpu.l2cache.tags.occ_blocks::writebacks 50209.763854 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.027833 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141473 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 3434.458363 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 11089.219598 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.766140 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 50332.685507 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006414 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141265 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 3220.709839 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 11192.593518 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.768016 # Average percentage of cache occupancy
1040,1072c1065,1097
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052406 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.169208 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.987757 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 64689 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2880 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4787 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56896 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987076 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 32180689 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 32180689 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6384 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2775 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 778641 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1279470 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2067270 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1541371 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1541371 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 305 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 199944 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 199944 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 6384 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 2775 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 778641 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1479414 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2267214 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 6384 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 2775 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 778641 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1479414 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2267214 # number of overall hits
---
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049144 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.170785 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.987948 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 64743 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2897 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4651 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57056 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987900 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 32212608 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 32212608 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6366 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2878 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 782107 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1278785 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2070136 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1541433 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1541433 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 314 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 314 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 199468 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 199468 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 6366 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 2878 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 782107 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1478253 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2269604 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 6366 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 2878 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 782107 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1478253 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2269604 # number of overall hits
1075,1081c1100,1106
< system.cpu.l2cache.ReadReq_misses::cpu.inst 12895 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 28198 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 41099 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1394 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1394 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 112812 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 112812 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 12963 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 28642 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 41611 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1325 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1325 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 113677 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 113677 # number of ReadExReq misses
1084,1086c1109,1111
< system.cpu.l2cache.demand_misses::cpu.inst 12895 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 141010 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 153911 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 12963 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 142319 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 155288 # number of demand (read+write) misses
1089,1131c1114,1156
< system.cpu.l2cache.overall_misses::cpu.inst 12895 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 141010 # number of overall misses
< system.cpu.l2cache.overall_misses::total 153911 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 365000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 942725495 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2110465196 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 3053644941 # number of ReadReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16120870 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 16120870 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7781341940 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 7781341940 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 365000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 942725495 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 9891807136 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 10834986881 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 365000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 942725495 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 9891807136 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 10834986881 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6385 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2780 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 791536 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1307668 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2108369 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1541371 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1541371 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1699 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1699 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 312756 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 312756 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6385 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 2780 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 791536 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1620424 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2421125 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6385 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 2780 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 791536 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1620424 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2421125 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_misses::cpu.inst 12963 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 142319 # number of overall misses
> system.cpu.l2cache.overall_misses::total 155288 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 61250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 350750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 946969000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2148496250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 3095877250 # number of ReadReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 14947864 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 14947864 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7865192973 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 7865192973 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 61250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 350750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 946969000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10013689223 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 10961070223 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 61250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 350750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 946969000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10013689223 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 10961070223 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6367 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2883 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 795070 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1307427 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2111747 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1541433 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1541433 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1639 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1639 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 313145 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 313145 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6367 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 2883 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 795070 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1620572 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2424892 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6367 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 2883 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 795070 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1620572 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2424892 # number of overall (read+write) accesses
1133,1140c1158,1165
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001799 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016291 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021564 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.019493 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.820483 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.820483 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360703 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.360703 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001734 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016304 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021907 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.019705 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808420 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808420 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.363017 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.363017 # miss rate for ReadExReq accesses
1142,1145c1167,1170
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001799 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016291 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.087020 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.063570 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001734 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016304 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.087820 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.064039 # miss rate for demand accesses
1147,1169c1172,1194
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001799 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016291 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.087020 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.063570 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 73000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73107.832105 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74844.499468 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 74299.738217 # average ReadReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11564.469154 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11564.469154 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68976.189944 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68976.189944 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73107.832105 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70149.685384 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 70397.742078 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73107.832105 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70149.685384 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 70397.742078 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001734 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016304 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.087820 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.064039 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 61250 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 70150 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73051.685567 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75012.088890 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 74400.453005 # average ReadReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11281.406792 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11281.406792 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69188.956192 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69188.956192 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 61250 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73051.685567 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70360.873973 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 70585.429801 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 61250 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 70150 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73051.685567 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70360.873973 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 70585.429801 # average overall miss latency
1178,1179c1203,1204
< system.cpu.l2cache.writebacks::writebacks 79998 # number of writebacks
< system.cpu.l2cache.writebacks::total 79998 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 80285 # number of writebacks
> system.cpu.l2cache.writebacks::total 80285 # number of writebacks
1182,1188c1207,1213
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12895 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28198 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 41099 # number of ReadReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1394 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 1394 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112812 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 112812 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12963 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28642 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 41611 # number of ReadReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1325 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 1325 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113677 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 113677 # number of ReadExReq MSHR misses
1191,1193c1216,1218
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 12895 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 141010 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 153911 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 12963 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 142319 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 155288 # number of demand (read+write) MSHR misses
1196,1223c1221,1248
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 12895 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 141010 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 153911 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 781175005 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1757280304 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2538833059 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14868876 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14868876 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6370597060 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6370597060 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 781175005 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8127877364 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 8909430119 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 781175005 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8127877364 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 8909430119 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655869000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655869000 # number of ReadReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2371075000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2371075000 # number of WriteReq MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026944000 # number of overall MSHR uncacheable cycles
< system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026944000 # number of overall MSHR uncacheable cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 12963 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 142319 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 155288 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 48750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 287750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 784590000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1789530750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2574457250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 13262825 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 13262825 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6444689027 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6444689027 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 48750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 287750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 784590000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8234219777 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 9019146277 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 48750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 287750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 784590000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8234219777 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 9019146277 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655868500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655868500 # number of ReadReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370634000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370634000 # number of WriteReq MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026502500 # number of overall MSHR uncacheable cycles
> system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026502500 # number of overall MSHR uncacheable cycles
1225,1232c1250,1257
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021564 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019493 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820483 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820483 # mshr miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360703 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360703 # mshr miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021907 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019705 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808420 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808420 # mshr miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.363017 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.363017 # mshr miss rate for ReadExReq accesses
1234,1237c1259,1262
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087020 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.063570 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.064039 # mshr miss rate for demand accesses
1239,1261c1264,1286
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087020 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.063570 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.682435 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62319.324207 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61773.596900 # average ReadReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10666.338594 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10666.338594 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56470.916746 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56470.916746 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.682435 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57640.432338 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57886.896447 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.682435 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57640.432338 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57886.896447 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001734 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016304 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087820 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.064039 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57550 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60525.341356 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62479.252496 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61869.631828 # average ReadReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.679245 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.679245 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56692.990024 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56692.990024 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 48750 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57550 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60525.341356 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.487595 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58080.123880 # average overall mshr miss latency