Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

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stats.txt (8835:7c68f84d7c4e)	stats.txt (8983:8800b05e1cb3)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.195470 # Number of seconds simulated 4sim_ticks 5195470393000 # Number of ticks simulated 5final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.195470 # Number of seconds simulated 4sim_ticks 5195470393000 # Number of ticks simulated 5final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1225094 # Simulator instruction rate (inst/s) 8host_op_rate 2351489 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 46076516791 # Simulator tick rate (ticks/s) 10host_mem_usage 346880 # Number of bytes of host memory used 11host_seconds 112.76 # Real time elapsed on the host	7host_inst_rate 387917 # Simulator instruction rate (inst/s) 8host_op_rate 744582 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 14589799311 # Simulator tick rate (ticks/s) 10host_mem_usage 351980 # Number of bytes of host memory used 11host_seconds 356.10 # Real time elapsed on the host
12sim_insts 138138472 # Number of instructions simulated 13sim_ops 265147881 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 13764096 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 974400 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10427072 # Number of bytes written to this memory 17system.physmem.num_reads 215064 # Number of read requests responded to by this memory 18system.physmem.num_writes 162923 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 2649249 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 187548 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 2006954 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 4656204 # Total bandwidth to/from this memory (bytes/s) 24system.l2c.replacements 136133 # number of replacements 25system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use 26system.l2c.total_refs 3363370 # Total number of references to valid blocks. 27system.l2c.sampled_refs 168244 # Sample count of references to valid blocks. 28system.l2c.avg_refs 19.991025 # Average number of references to valid blocks. 29system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 30system.l2c.occ_blocks::writebacks 23478.740830 # Average occupied blocks per requestor 31system.l2c.occ_blocks::cpu.dtb.walker 0.248367 # Average occupied blocks per requestor 32system.l2c.occ_blocks::cpu.itb.walker 0.010497 # Average occupied blocks per requestor 33system.l2c.occ_blocks::cpu.inst 1900.597036 # Average occupied blocks per requestor 34system.l2c.occ_blocks::cpu.data 6010.298740 # Average occupied blocks per requestor 35system.l2c.occ_percent::writebacks 0.358257 # Average percentage of cache occupancy 36system.l2c.occ_percent::cpu.dtb.walker 0.000004 # Average percentage of cache occupancy 37system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 38system.l2c.occ_percent::cpu.inst 0.029001 # Average percentage of cache occupancy 39system.l2c.occ_percent::cpu.data 0.091710 # Average percentage of cache occupancy 40system.l2c.occ_percent::total 0.478972 # Average percentage of cache occupancy 41system.l2c.ReadReq_hits::cpu.dtb.walker 6528 # number of ReadReq hits 42system.l2c.ReadReq_hits::cpu.itb.walker 3033 # number of ReadReq hits 43system.l2c.ReadReq_hits::cpu.inst 773419 # number of ReadReq hits 44system.l2c.ReadReq_hits::cpu.data 1274463 # number of ReadReq hits 45system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits 46system.l2c.Writeback_hits::writebacks 1534567 # number of Writeback hits 47system.l2c.Writeback_hits::total 1534567 # number of Writeback hits 48system.l2c.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits 49system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits 50system.l2c.ReadExReq_hits::cpu.data 192958 # number of ReadExReq hits 51system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits 52system.l2c.demand_hits::cpu.dtb.walker 6528 # number of demand (read+write) hits 53system.l2c.demand_hits::cpu.itb.walker 3033 # number of demand (read+write) hits 54system.l2c.demand_hits::cpu.inst 773419 # number of demand (read+write) hits 55system.l2c.demand_hits::cpu.data 1467421 # number of demand (read+write) hits 56system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits 57system.l2c.overall_hits::cpu.dtb.walker 6528 # number of overall hits 58system.l2c.overall_hits::cpu.itb.walker 3033 # number of overall hits 59system.l2c.overall_hits::cpu.inst 773419 # number of overall hits 60system.l2c.overall_hits::cpu.data 1467421 # number of overall hits 61system.l2c.overall_hits::total 2250401 # number of overall hits 62system.l2c.ReadReq_misses::cpu.dtb.walker 13 # number of ReadReq misses 63system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses 64system.l2c.ReadReq_misses::cpu.inst 15226 # number of ReadReq misses 65system.l2c.ReadReq_misses::cpu.data 35581 # number of ReadReq misses 66system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses 67system.l2c.UpgradeReq_misses::cpu.data 1369 # number of UpgradeReq misses 68system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses 69system.l2c.ReadExReq_misses::cpu.data 120168 # number of ReadExReq misses 70system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses 71system.l2c.demand_misses::cpu.dtb.walker 13 # number of demand (read+write) misses 72system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses 73system.l2c.demand_misses::cpu.inst 15226 # number of demand (read+write) misses 74system.l2c.demand_misses::cpu.data 155749 # number of demand (read+write) misses 75system.l2c.demand_misses::total 170998 # number of demand (read+write) misses 76system.l2c.overall_misses::cpu.dtb.walker 13 # number of overall misses 77system.l2c.overall_misses::cpu.itb.walker 10 # number of overall misses 78system.l2c.overall_misses::cpu.inst 15226 # number of overall misses 79system.l2c.overall_misses::cpu.data 155749 # number of overall misses 80system.l2c.overall_misses::total 170998 # number of overall misses 81system.l2c.ReadReq_miss_latency::cpu.dtb.walker 676000 # number of ReadReq miss cycles 82system.l2c.ReadReq_miss_latency::cpu.itb.walker 520000 # number of ReadReq miss cycles 83system.l2c.ReadReq_miss_latency::cpu.inst 791868000 # number of ReadReq miss cycles 84system.l2c.ReadReq_miss_latency::cpu.data 1863058500 # number of ReadReq miss cycles 85system.l2c.ReadReq_miss_latency::total 2656122500 # number of ReadReq miss cycles 86system.l2c.UpgradeReq_miss_latency::cpu.data 33778000 # number of UpgradeReq miss cycles 87system.l2c.UpgradeReq_miss_latency::total 33778000 # number of UpgradeReq miss cycles 88system.l2c.ReadExReq_miss_latency::cpu.data 6249324500 # number of ReadExReq miss cycles 89system.l2c.ReadExReq_miss_latency::total 6249324500 # number of ReadExReq miss cycles 90system.l2c.demand_miss_latency::cpu.dtb.walker 676000 # number of demand (read+write) miss cycles 91system.l2c.demand_miss_latency::cpu.itb.walker 520000 # number of demand (read+write) miss cycles 92system.l2c.demand_miss_latency::cpu.inst 791868000 # number of demand (read+write) miss cycles 93system.l2c.demand_miss_latency::cpu.data 8112383000 # number of demand (read+write) miss cycles 94system.l2c.demand_miss_latency::total 8905447000 # number of demand (read+write) miss cycles 95system.l2c.overall_miss_latency::cpu.dtb.walker 676000 # number of overall miss cycles 96system.l2c.overall_miss_latency::cpu.itb.walker 520000 # number of overall miss cycles 97system.l2c.overall_miss_latency::cpu.inst 791868000 # number of overall miss cycles 98system.l2c.overall_miss_latency::cpu.data 8112383000 # number of overall miss cycles 99system.l2c.overall_miss_latency::total 8905447000 # number of overall miss cycles 100system.l2c.ReadReq_accesses::cpu.dtb.walker 6541 # number of ReadReq accesses(hits+misses) 101system.l2c.ReadReq_accesses::cpu.itb.walker 3043 # number of ReadReq accesses(hits+misses) 102system.l2c.ReadReq_accesses::cpu.inst 788645 # number of ReadReq accesses(hits+misses) 103system.l2c.ReadReq_accesses::cpu.data 1310044 # number of ReadReq accesses(hits+misses) 104system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses) 105system.l2c.Writeback_accesses::writebacks 1534567 # number of Writeback accesses(hits+misses) 106system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses) 107system.l2c.UpgradeReq_accesses::cpu.data 1689 # number of UpgradeReq accesses(hits+misses) 108system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses) 109system.l2c.ReadExReq_accesses::cpu.data 313126 # number of ReadExReq accesses(hits+misses) 110system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses) 111system.l2c.demand_accesses::cpu.dtb.walker 6541 # number of demand (read+write) accesses 112system.l2c.demand_accesses::cpu.itb.walker 3043 # number of demand (read+write) accesses 113system.l2c.demand_accesses::cpu.inst 788645 # number of demand (read+write) accesses 114system.l2c.demand_accesses::cpu.data 1623170 # number of demand (read+write) accesses 115system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses 116system.l2c.overall_accesses::cpu.dtb.walker 6541 # number of overall (read+write) accesses 117system.l2c.overall_accesses::cpu.itb.walker 3043 # number of overall (read+write) accesses 118system.l2c.overall_accesses::cpu.inst 788645 # number of overall (read+write) accesses 119system.l2c.overall_accesses::cpu.data 1623170 # number of overall (read+write) accesses 120system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses 121system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001987 # miss rate for ReadReq accesses 122system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003286 # miss rate for ReadReq accesses 123system.l2c.ReadReq_miss_rate::cpu.inst 0.019307 # miss rate for ReadReq accesses 124system.l2c.ReadReq_miss_rate::cpu.data 0.027160 # miss rate for ReadReq accesses 125system.l2c.UpgradeReq_miss_rate::cpu.data 0.810539 # miss rate for UpgradeReq accesses 126system.l2c.ReadExReq_miss_rate::cpu.data 0.383769 # miss rate for ReadExReq accesses 127system.l2c.demand_miss_rate::cpu.dtb.walker 0.001987 # miss rate for demand accesses 128system.l2c.demand_miss_rate::cpu.itb.walker 0.003286 # miss rate for demand accesses 129system.l2c.demand_miss_rate::cpu.inst 0.019307 # miss rate for demand accesses 130system.l2c.demand_miss_rate::cpu.data 0.095954 # miss rate for demand accesses 131system.l2c.overall_miss_rate::cpu.dtb.walker 0.001987 # miss rate for overall accesses 132system.l2c.overall_miss_rate::cpu.itb.walker 0.003286 # miss rate for overall accesses 133system.l2c.overall_miss_rate::cpu.inst 0.019307 # miss rate for overall accesses 134system.l2c.overall_miss_rate::cpu.data 0.095954 # miss rate for overall accesses 135system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency 136system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 137system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547 # average ReadReq miss latency 138system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436 # average ReadReq miss latency 139system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295 # average UpgradeReq miss latency 140system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310 # average ReadExReq miss latency 141system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 142system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 143system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency 144system.l2c.demand_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency 145system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 146system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 147system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency 148system.l2c.overall_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency 149system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 150system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 151system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 152system.l2c.blocked::no_targets 0 # number of cycles access was blocked	12sim_insts 138138472 # Number of instructions simulated 13sim_ops 265147881 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 13764096 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 974400 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10427072 # Number of bytes written to this memory 17system.physmem.num_reads 215064 # Number of read requests responded to by this memory 18system.physmem.num_writes 162923 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 2649249 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 187548 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 2006954 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 4656204 # Total bandwidth to/from this memory (bytes/s) 24system.l2c.replacements 136133 # number of replacements 25system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use 26system.l2c.total_refs 3363370 # Total number of references to valid blocks. 27system.l2c.sampled_refs 168244 # Sample count of references to valid blocks. 28system.l2c.avg_refs 19.991025 # Average number of references to valid blocks. 29system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 30system.l2c.occ_blocks::writebacks 23478.740830 # Average occupied blocks per requestor 31system.l2c.occ_blocks::cpu.dtb.walker 0.248367 # Average occupied blocks per requestor 32system.l2c.occ_blocks::cpu.itb.walker 0.010497 # Average occupied blocks per requestor 33system.l2c.occ_blocks::cpu.inst 1900.597036 # Average occupied blocks per requestor 34system.l2c.occ_blocks::cpu.data 6010.298740 # Average occupied blocks per requestor 35system.l2c.occ_percent::writebacks 0.358257 # Average percentage of cache occupancy 36system.l2c.occ_percent::cpu.dtb.walker 0.000004 # Average percentage of cache occupancy 37system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 38system.l2c.occ_percent::cpu.inst 0.029001 # Average percentage of cache occupancy 39system.l2c.occ_percent::cpu.data 0.091710 # Average percentage of cache occupancy 40system.l2c.occ_percent::total 0.478972 # Average percentage of cache occupancy 41system.l2c.ReadReq_hits::cpu.dtb.walker 6528 # number of ReadReq hits 42system.l2c.ReadReq_hits::cpu.itb.walker 3033 # number of ReadReq hits 43system.l2c.ReadReq_hits::cpu.inst 773419 # number of ReadReq hits 44system.l2c.ReadReq_hits::cpu.data 1274463 # number of ReadReq hits 45system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits 46system.l2c.Writeback_hits::writebacks 1534567 # number of Writeback hits 47system.l2c.Writeback_hits::total 1534567 # number of Writeback hits 48system.l2c.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits 49system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits 50system.l2c.ReadExReq_hits::cpu.data 192958 # number of ReadExReq hits 51system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits 52system.l2c.demand_hits::cpu.dtb.walker 6528 # number of demand (read+write) hits 53system.l2c.demand_hits::cpu.itb.walker 3033 # number of demand (read+write) hits 54system.l2c.demand_hits::cpu.inst 773419 # number of demand (read+write) hits 55system.l2c.demand_hits::cpu.data 1467421 # number of demand (read+write) hits 56system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits 57system.l2c.overall_hits::cpu.dtb.walker 6528 # number of overall hits 58system.l2c.overall_hits::cpu.itb.walker 3033 # number of overall hits 59system.l2c.overall_hits::cpu.inst 773419 # number of overall hits 60system.l2c.overall_hits::cpu.data 1467421 # number of overall hits 61system.l2c.overall_hits::total 2250401 # number of overall hits 62system.l2c.ReadReq_misses::cpu.dtb.walker 13 # number of ReadReq misses 63system.l2c.ReadReq_misses::cpu.itb.walker 10 # number of ReadReq misses 64system.l2c.ReadReq_misses::cpu.inst 15226 # number of ReadReq misses 65system.l2c.ReadReq_misses::cpu.data 35581 # number of ReadReq misses 66system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses 67system.l2c.UpgradeReq_misses::cpu.data 1369 # number of UpgradeReq misses 68system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses 69system.l2c.ReadExReq_misses::cpu.data 120168 # number of ReadExReq misses 70system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses 71system.l2c.demand_misses::cpu.dtb.walker 13 # number of demand (read+write) misses 72system.l2c.demand_misses::cpu.itb.walker 10 # number of demand (read+write) misses 73system.l2c.demand_misses::cpu.inst 15226 # number of demand (read+write) misses 74system.l2c.demand_misses::cpu.data 155749 # number of demand (read+write) misses 75system.l2c.demand_misses::total 170998 # number of demand (read+write) misses 76system.l2c.overall_misses::cpu.dtb.walker 13 # number of overall misses 77system.l2c.overall_misses::cpu.itb.walker 10 # number of overall misses 78system.l2c.overall_misses::cpu.inst 15226 # number of overall misses 79system.l2c.overall_misses::cpu.data 155749 # number of overall misses 80system.l2c.overall_misses::total 170998 # number of overall misses 81system.l2c.ReadReq_miss_latency::cpu.dtb.walker 676000 # number of ReadReq miss cycles 82system.l2c.ReadReq_miss_latency::cpu.itb.walker 520000 # number of ReadReq miss cycles 83system.l2c.ReadReq_miss_latency::cpu.inst 791868000 # number of ReadReq miss cycles 84system.l2c.ReadReq_miss_latency::cpu.data 1863058500 # number of ReadReq miss cycles 85system.l2c.ReadReq_miss_latency::total 2656122500 # number of ReadReq miss cycles 86system.l2c.UpgradeReq_miss_latency::cpu.data 33778000 # number of UpgradeReq miss cycles 87system.l2c.UpgradeReq_miss_latency::total 33778000 # number of UpgradeReq miss cycles 88system.l2c.ReadExReq_miss_latency::cpu.data 6249324500 # number of ReadExReq miss cycles 89system.l2c.ReadExReq_miss_latency::total 6249324500 # number of ReadExReq miss cycles 90system.l2c.demand_miss_latency::cpu.dtb.walker 676000 # number of demand (read+write) miss cycles 91system.l2c.demand_miss_latency::cpu.itb.walker 520000 # number of demand (read+write) miss cycles 92system.l2c.demand_miss_latency::cpu.inst 791868000 # number of demand (read+write) miss cycles 93system.l2c.demand_miss_latency::cpu.data 8112383000 # number of demand (read+write) miss cycles 94system.l2c.demand_miss_latency::total 8905447000 # number of demand (read+write) miss cycles 95system.l2c.overall_miss_latency::cpu.dtb.walker 676000 # number of overall miss cycles 96system.l2c.overall_miss_latency::cpu.itb.walker 520000 # number of overall miss cycles 97system.l2c.overall_miss_latency::cpu.inst 791868000 # number of overall miss cycles 98system.l2c.overall_miss_latency::cpu.data 8112383000 # number of overall miss cycles 99system.l2c.overall_miss_latency::total 8905447000 # number of overall miss cycles 100system.l2c.ReadReq_accesses::cpu.dtb.walker 6541 # number of ReadReq accesses(hits+misses) 101system.l2c.ReadReq_accesses::cpu.itb.walker 3043 # number of ReadReq accesses(hits+misses) 102system.l2c.ReadReq_accesses::cpu.inst 788645 # number of ReadReq accesses(hits+misses) 103system.l2c.ReadReq_accesses::cpu.data 1310044 # number of ReadReq accesses(hits+misses) 104system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses) 105system.l2c.Writeback_accesses::writebacks 1534567 # number of Writeback accesses(hits+misses) 106system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses) 107system.l2c.UpgradeReq_accesses::cpu.data 1689 # number of UpgradeReq accesses(hits+misses) 108system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses) 109system.l2c.ReadExReq_accesses::cpu.data 313126 # number of ReadExReq accesses(hits+misses) 110system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses) 111system.l2c.demand_accesses::cpu.dtb.walker 6541 # number of demand (read+write) accesses 112system.l2c.demand_accesses::cpu.itb.walker 3043 # number of demand (read+write) accesses 113system.l2c.demand_accesses::cpu.inst 788645 # number of demand (read+write) accesses 114system.l2c.demand_accesses::cpu.data 1623170 # number of demand (read+write) accesses 115system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses 116system.l2c.overall_accesses::cpu.dtb.walker 6541 # number of overall (read+write) accesses 117system.l2c.overall_accesses::cpu.itb.walker 3043 # number of overall (read+write) accesses 118system.l2c.overall_accesses::cpu.inst 788645 # number of overall (read+write) accesses 119system.l2c.overall_accesses::cpu.data 1623170 # number of overall (read+write) accesses 120system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses 121system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001987 # miss rate for ReadReq accesses 122system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003286 # miss rate for ReadReq accesses 123system.l2c.ReadReq_miss_rate::cpu.inst 0.019307 # miss rate for ReadReq accesses 124system.l2c.ReadReq_miss_rate::cpu.data 0.027160 # miss rate for ReadReq accesses 125system.l2c.UpgradeReq_miss_rate::cpu.data 0.810539 # miss rate for UpgradeReq accesses 126system.l2c.ReadExReq_miss_rate::cpu.data 0.383769 # miss rate for ReadExReq accesses 127system.l2c.demand_miss_rate::cpu.dtb.walker 0.001987 # miss rate for demand accesses 128system.l2c.demand_miss_rate::cpu.itb.walker 0.003286 # miss rate for demand accesses 129system.l2c.demand_miss_rate::cpu.inst 0.019307 # miss rate for demand accesses 130system.l2c.demand_miss_rate::cpu.data 0.095954 # miss rate for demand accesses 131system.l2c.overall_miss_rate::cpu.dtb.walker 0.001987 # miss rate for overall accesses 132system.l2c.overall_miss_rate::cpu.itb.walker 0.003286 # miss rate for overall accesses 133system.l2c.overall_miss_rate::cpu.inst 0.019307 # miss rate for overall accesses 134system.l2c.overall_miss_rate::cpu.data 0.095954 # miss rate for overall accesses 135system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52000 # average ReadReq miss latency 136system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52000 # average ReadReq miss latency 137system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547 # average ReadReq miss latency 138system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436 # average ReadReq miss latency 139system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295 # average UpgradeReq miss latency 140system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310 # average ReadExReq miss latency 141system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 142system.l2c.demand_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 143system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency 144system.l2c.demand_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency 145system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52000 # average overall miss latency 146system.l2c.overall_avg_miss_latency::cpu.itb.walker 52000 # average overall miss latency 147system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547 # average overall miss latency 148system.l2c.overall_avg_miss_latency::cpu.data 52086.260586 # average overall miss latency 149system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 150system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 151system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 152system.l2c.blocked::no_targets 0 # number of cycles access was blocked
153system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 154system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	153system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 154system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
155system.l2c.fast_writes 0 # number of fast writes performed 156system.l2c.cache_copies 0 # number of cache copies performed 157system.l2c.writebacks::writebacks 116255 # number of writebacks 158system.l2c.writebacks::total 116255 # number of writebacks 159system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 13 # number of ReadReq MSHR misses 160system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses 161system.l2c.ReadReq_mshr_misses::cpu.inst 15226 # number of ReadReq MSHR misses 162system.l2c.ReadReq_mshr_misses::cpu.data 35581 # number of ReadReq MSHR misses 163system.l2c.ReadReq_mshr_misses::total 50830 # number of ReadReq MSHR misses 164system.l2c.UpgradeReq_mshr_misses::cpu.data 1369 # number of UpgradeReq MSHR misses 165system.l2c.UpgradeReq_mshr_misses::total 1369 # number of UpgradeReq MSHR misses 166system.l2c.ReadExReq_mshr_misses::cpu.data 120168 # number of ReadExReq MSHR misses 167system.l2c.ReadExReq_mshr_misses::total 120168 # number of ReadExReq MSHR misses 168system.l2c.demand_mshr_misses::cpu.dtb.walker 13 # number of demand (read+write) MSHR misses 169system.l2c.demand_mshr_misses::cpu.itb.walker 10 # number of demand (read+write) MSHR misses 170system.l2c.demand_mshr_misses::cpu.inst 15226 # number of demand (read+write) MSHR misses 171system.l2c.demand_mshr_misses::cpu.data 155749 # number of demand (read+write) MSHR misses 172system.l2c.demand_mshr_misses::total 170998 # number of demand (read+write) MSHR misses 173system.l2c.overall_mshr_misses::cpu.dtb.walker 13 # number of overall MSHR misses 174system.l2c.overall_mshr_misses::cpu.itb.walker 10 # number of overall MSHR misses 175system.l2c.overall_mshr_misses::cpu.inst 15226 # number of overall MSHR misses 176system.l2c.overall_mshr_misses::cpu.data 155749 # number of overall MSHR misses 177system.l2c.overall_mshr_misses::total 170998 # number of overall MSHR misses 178system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 520000 # number of ReadReq MSHR miss cycles 179system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 400000 # number of ReadReq MSHR miss cycles 180system.l2c.ReadReq_mshr_miss_latency::cpu.inst 609142000 # number of ReadReq MSHR miss cycles 181system.l2c.ReadReq_mshr_miss_latency::cpu.data 1436082000 # number of ReadReq MSHR miss cycles 182system.l2c.ReadReq_mshr_miss_latency::total 2046144000 # number of ReadReq MSHR miss cycles 183system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 55109000 # number of UpgradeReq MSHR miss cycles 184system.l2c.UpgradeReq_mshr_miss_latency::total 55109000 # number of UpgradeReq MSHR miss cycles 185system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4807305000 # number of ReadExReq MSHR miss cycles 186system.l2c.ReadExReq_mshr_miss_latency::total 4807305000 # number of ReadExReq MSHR miss cycles 187system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 520000 # number of demand (read+write) MSHR miss cycles 188system.l2c.demand_mshr_miss_latency::cpu.itb.walker 400000 # number of demand (read+write) MSHR miss cycles 189system.l2c.demand_mshr_miss_latency::cpu.inst 609142000 # number of demand (read+write) MSHR miss cycles 190system.l2c.demand_mshr_miss_latency::cpu.data 6243387000 # number of demand (read+write) MSHR miss cycles 191system.l2c.demand_mshr_miss_latency::total 6853449000 # number of demand (read+write) MSHR miss cycles 192system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 520000 # number of overall MSHR miss cycles 193system.l2c.overall_mshr_miss_latency::cpu.itb.walker 400000 # number of overall MSHR miss cycles 194system.l2c.overall_mshr_miss_latency::cpu.inst 609142000 # number of overall MSHR miss cycles 195system.l2c.overall_mshr_miss_latency::cpu.data 6243387000 # number of overall MSHR miss cycles 196system.l2c.overall_mshr_miss_latency::total 6853449000 # number of overall MSHR miss cycles 197system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56051785000 # number of ReadReq MSHR uncacheable cycles 198system.l2c.ReadReq_mshr_uncacheable_latency::total 56051785000 # number of ReadReq MSHR uncacheable cycles 199system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1218050000 # number of WriteReq MSHR uncacheable cycles 200system.l2c.WriteReq_mshr_uncacheable_latency::total 1218050000 # number of WriteReq MSHR uncacheable cycles 201system.l2c.overall_mshr_uncacheable_latency::cpu.data 57269835000 # number of overall MSHR uncacheable cycles 202system.l2c.overall_mshr_uncacheable_latency::total 57269835000 # number of overall MSHR uncacheable cycles 203system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for ReadReq accesses 204system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for ReadReq accesses 205system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for ReadReq accesses 206system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.027160 # mshr miss rate for ReadReq accesses 207system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.810539 # mshr miss rate for UpgradeReq accesses 208system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383769 # mshr miss rate for ReadExReq accesses 209system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for demand accesses 210system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for demand accesses 211system.l2c.demand_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for demand accesses 212system.l2c.demand_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for demand accesses 213system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for overall accesses 214system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for overall accesses 215system.l2c.overall_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for overall accesses 216system.l2c.overall_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for overall accesses 217system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency 218system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 219system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067 # average ReadReq mshr miss latency 220system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965 # average ReadReq mshr miss latency 221system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606 # average UpgradeReq mshr miss latency 222system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185 # average ReadExReq mshr miss latency 223system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 224system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 225system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency 226system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency 227system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 228system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 229system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency 230system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency 231system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 232system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 233system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 234system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 235system.iocache.replacements 47510 # number of replacements 236system.iocache.tagsinuse 0.120586 # Cycle average of tags in use 237system.iocache.total_refs 0 # Total number of references to valid blocks. 238system.iocache.sampled_refs 47526 # Sample count of references to valid blocks. 239system.iocache.avg_refs 0 # Average number of references to valid blocks. 240system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit. 241system.iocache.occ_blocks::pc.south_bridge.ide 0.120586 # Average occupied blocks per requestor 242system.iocache.occ_percent::pc.south_bridge.ide 0.007537 # Average percentage of cache occupancy 243system.iocache.occ_percent::total 0.007537 # Average percentage of cache occupancy 244system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses 245system.iocache.ReadReq_misses::total 844 # number of ReadReq misses 246system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 247system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 248system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses 249system.iocache.demand_misses::total 47564 # number of demand (read+write) misses 250system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses 251system.iocache.overall_misses::total 47564 # number of overall misses 252system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 106575932 # number of ReadReq miss cycles 253system.iocache.ReadReq_miss_latency::total 106575932 # number of ReadReq miss cycles 254system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6391379160 # number of WriteReq miss cycles 255system.iocache.WriteReq_miss_latency::total 6391379160 # number of WriteReq miss cycles 256system.iocache.demand_miss_latency::pc.south_bridge.ide 6497955092 # number of demand (read+write) miss cycles 257system.iocache.demand_miss_latency::total 6497955092 # number of demand (read+write) miss cycles 258system.iocache.overall_miss_latency::pc.south_bridge.ide 6497955092 # number of overall miss cycles 259system.iocache.overall_miss_latency::total 6497955092 # number of overall miss cycles 260system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) 261system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) 262system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 263system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 264system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses 265system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses 266system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses 267system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses 268system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 269system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 270system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 271system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 272system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948 # average ReadReq miss latency 273system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency 274system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency 275system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency 276system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked 277system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked 279system.iocache.blocked::no_targets 0 # number of cycles access was blocked 280system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked	155system.l2c.fast_writes 0 # number of fast writes performed 156system.l2c.cache_copies 0 # number of cache copies performed 157system.l2c.writebacks::writebacks 116255 # number of writebacks 158system.l2c.writebacks::total 116255 # number of writebacks 159system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 13 # number of ReadReq MSHR misses 160system.l2c.ReadReq_mshr_misses::cpu.itb.walker 10 # number of ReadReq MSHR misses 161system.l2c.ReadReq_mshr_misses::cpu.inst 15226 # number of ReadReq MSHR misses 162system.l2c.ReadReq_mshr_misses::cpu.data 35581 # number of ReadReq MSHR misses 163system.l2c.ReadReq_mshr_misses::total 50830 # number of ReadReq MSHR misses 164system.l2c.UpgradeReq_mshr_misses::cpu.data 1369 # number of UpgradeReq MSHR misses 165system.l2c.UpgradeReq_mshr_misses::total 1369 # number of UpgradeReq MSHR misses 166system.l2c.ReadExReq_mshr_misses::cpu.data 120168 # number of ReadExReq MSHR misses 167system.l2c.ReadExReq_mshr_misses::total 120168 # number of ReadExReq MSHR misses 168system.l2c.demand_mshr_misses::cpu.dtb.walker 13 # number of demand (read+write) MSHR misses 169system.l2c.demand_mshr_misses::cpu.itb.walker 10 # number of demand (read+write) MSHR misses 170system.l2c.demand_mshr_misses::cpu.inst 15226 # number of demand (read+write) MSHR misses 171system.l2c.demand_mshr_misses::cpu.data 155749 # number of demand (read+write) MSHR misses 172system.l2c.demand_mshr_misses::total 170998 # number of demand (read+write) MSHR misses 173system.l2c.overall_mshr_misses::cpu.dtb.walker 13 # number of overall MSHR misses 174system.l2c.overall_mshr_misses::cpu.itb.walker 10 # number of overall MSHR misses 175system.l2c.overall_mshr_misses::cpu.inst 15226 # number of overall MSHR misses 176system.l2c.overall_mshr_misses::cpu.data 155749 # number of overall MSHR misses 177system.l2c.overall_mshr_misses::total 170998 # number of overall MSHR misses 178system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 520000 # number of ReadReq MSHR miss cycles 179system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 400000 # number of ReadReq MSHR miss cycles 180system.l2c.ReadReq_mshr_miss_latency::cpu.inst 609142000 # number of ReadReq MSHR miss cycles 181system.l2c.ReadReq_mshr_miss_latency::cpu.data 1436082000 # number of ReadReq MSHR miss cycles 182system.l2c.ReadReq_mshr_miss_latency::total 2046144000 # number of ReadReq MSHR miss cycles 183system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 55109000 # number of UpgradeReq MSHR miss cycles 184system.l2c.UpgradeReq_mshr_miss_latency::total 55109000 # number of UpgradeReq MSHR miss cycles 185system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4807305000 # number of ReadExReq MSHR miss cycles 186system.l2c.ReadExReq_mshr_miss_latency::total 4807305000 # number of ReadExReq MSHR miss cycles 187system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 520000 # number of demand (read+write) MSHR miss cycles 188system.l2c.demand_mshr_miss_latency::cpu.itb.walker 400000 # number of demand (read+write) MSHR miss cycles 189system.l2c.demand_mshr_miss_latency::cpu.inst 609142000 # number of demand (read+write) MSHR miss cycles 190system.l2c.demand_mshr_miss_latency::cpu.data 6243387000 # number of demand (read+write) MSHR miss cycles 191system.l2c.demand_mshr_miss_latency::total 6853449000 # number of demand (read+write) MSHR miss cycles 192system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 520000 # number of overall MSHR miss cycles 193system.l2c.overall_mshr_miss_latency::cpu.itb.walker 400000 # number of overall MSHR miss cycles 194system.l2c.overall_mshr_miss_latency::cpu.inst 609142000 # number of overall MSHR miss cycles 195system.l2c.overall_mshr_miss_latency::cpu.data 6243387000 # number of overall MSHR miss cycles 196system.l2c.overall_mshr_miss_latency::total 6853449000 # number of overall MSHR miss cycles 197system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 56051785000 # number of ReadReq MSHR uncacheable cycles 198system.l2c.ReadReq_mshr_uncacheable_latency::total 56051785000 # number of ReadReq MSHR uncacheable cycles 199system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1218050000 # number of WriteReq MSHR uncacheable cycles 200system.l2c.WriteReq_mshr_uncacheable_latency::total 1218050000 # number of WriteReq MSHR uncacheable cycles 201system.l2c.overall_mshr_uncacheable_latency::cpu.data 57269835000 # number of overall MSHR uncacheable cycles 202system.l2c.overall_mshr_uncacheable_latency::total 57269835000 # number of overall MSHR uncacheable cycles 203system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for ReadReq accesses 204system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for ReadReq accesses 205system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for ReadReq accesses 206system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.027160 # mshr miss rate for ReadReq accesses 207system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.810539 # mshr miss rate for UpgradeReq accesses 208system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383769 # mshr miss rate for ReadExReq accesses 209system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for demand accesses 210system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for demand accesses 211system.l2c.demand_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for demand accesses 212system.l2c.demand_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for demand accesses 213system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.001987 # mshr miss rate for overall accesses 214system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.003286 # mshr miss rate for overall accesses 215system.l2c.overall_mshr_miss_rate::cpu.inst 0.019307 # mshr miss rate for overall accesses 216system.l2c.overall_mshr_miss_rate::cpu.data 0.095954 # mshr miss rate for overall accesses 217system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency 218system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 219system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067 # average ReadReq mshr miss latency 220system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965 # average ReadReq mshr miss latency 221system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606 # average UpgradeReq mshr miss latency 222system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185 # average ReadExReq mshr miss latency 223system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 224system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 225system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency 226system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency 227system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency 228system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 229system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067 # average overall mshr miss latency 230system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221 # average overall mshr miss latency 231system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 232system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 233system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 234system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 235system.iocache.replacements 47510 # number of replacements 236system.iocache.tagsinuse 0.120586 # Cycle average of tags in use 237system.iocache.total_refs 0 # Total number of references to valid blocks. 238system.iocache.sampled_refs 47526 # Sample count of references to valid blocks. 239system.iocache.avg_refs 0 # Average number of references to valid blocks. 240system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit. 241system.iocache.occ_blocks::pc.south_bridge.ide 0.120586 # Average occupied blocks per requestor 242system.iocache.occ_percent::pc.south_bridge.ide 0.007537 # Average percentage of cache occupancy 243system.iocache.occ_percent::total 0.007537 # Average percentage of cache occupancy 244system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses 245system.iocache.ReadReq_misses::total 844 # number of ReadReq misses 246system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 247system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 248system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses 249system.iocache.demand_misses::total 47564 # number of demand (read+write) misses 250system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses 251system.iocache.overall_misses::total 47564 # number of overall misses 252system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 106575932 # number of ReadReq miss cycles 253system.iocache.ReadReq_miss_latency::total 106575932 # number of ReadReq miss cycles 254system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6391379160 # number of WriteReq miss cycles 255system.iocache.WriteReq_miss_latency::total 6391379160 # number of WriteReq miss cycles 256system.iocache.demand_miss_latency::pc.south_bridge.ide 6497955092 # number of demand (read+write) miss cycles 257system.iocache.demand_miss_latency::total 6497955092 # number of demand (read+write) miss cycles 258system.iocache.overall_miss_latency::pc.south_bridge.ide 6497955092 # number of overall miss cycles 259system.iocache.overall_miss_latency::total 6497955092 # number of overall miss cycles 260system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses) 261system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) 262system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 263system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 264system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses 265system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses 266system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses 267system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses 268system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 269system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 270system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 271system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 272system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948 # average ReadReq miss latency 273system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966 # average WriteReq miss latency 274system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency 275system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853 # average overall miss latency 276system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked 277system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked 279system.iocache.blocked::no_targets 0 # number of cycles access was blocked 280system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked
281system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	281system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
282system.iocache.fast_writes 0 # number of fast writes performed 283system.iocache.cache_copies 0 # number of cache copies performed 284system.iocache.writebacks::writebacks 46668 # number of writebacks 285system.iocache.writebacks::total 46668 # number of writebacks 286system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses 287system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses 288system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 289system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 290system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses 291system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses 292system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses 293system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses 294system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 62666978 # number of ReadReq MSHR miss cycles 295system.iocache.ReadReq_mshr_miss_latency::total 62666978 # number of ReadReq MSHR miss cycles 296system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3961676998 # number of WriteReq MSHR miss cycles 297system.iocache.WriteReq_mshr_miss_latency::total 3961676998 # number of WriteReq MSHR miss cycles 298system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of demand (read+write) MSHR miss cycles 299system.iocache.demand_mshr_miss_latency::total 4024343976 # number of demand (read+write) MSHR miss cycles 300system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of overall MSHR miss cycles 301system.iocache.overall_mshr_miss_latency::total 4024343976 # number of overall MSHR miss cycles 302system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 303system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 304system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 305system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 306system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934 # average ReadReq mshr miss latency 307system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622 # average WriteReq mshr miss latency 308system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency 309system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency 310system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 311system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 312system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 313system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 314system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 315system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 316system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 317system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 318system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 319system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 320system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 321system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 322system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 323system.cpu.numCycles 10390940786 # number of cpu cycles simulated 324system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 325system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 326system.cpu.committedInsts 138138472 # Number of instructions committed 327system.cpu.committedOps 265147881 # Number of ops (including micro ops) committed 328system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses 329system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 330system.cpu.num_func_calls 0 # number of times a function call or return occured 331system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls 332system.cpu.num_int_insts 249556386 # number of integer instructions 333system.cpu.num_fp_insts 0 # number of float instructions 334system.cpu.num_int_register_reads 543487907 # number of times the integer registers were read 335system.cpu.num_int_register_writes 266037487 # number of times the integer registers were written 336system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 337system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 338system.cpu.num_mem_refs 23169904 # number of memory refs 339system.cpu.num_load_insts 14812525 # Number of load instructions 340system.cpu.num_store_insts 8357379 # Number of store instructions 341system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles 342system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles 343system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles 344system.cpu.idle_fraction 0.941953 # Percentage of idle cycles 345system.cpu.kern.inst.arm 0 # number of arm instructions executed 346system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 347system.cpu.icache.replacements 788139 # number of replacements 348system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use 349system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks. 350system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks. 351system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks. 352system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit. 353system.cpu.icache.occ_blocks::cpu.inst 510.361283 # Average occupied blocks per requestor 354system.cpu.icache.occ_percent::cpu.inst 0.996799 # Average percentage of cache occupancy 355system.cpu.icache.occ_percent::total 0.996799 # Average percentage of cache occupancy 356system.cpu.icache.ReadReq_hits::cpu.inst 158433932 # number of ReadReq hits 357system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits 358system.cpu.icache.demand_hits::cpu.inst 158433932 # number of demand (read+write) hits 359system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits 360system.cpu.icache.overall_hits::cpu.inst 158433932 # number of overall hits 361system.cpu.icache.overall_hits::total 158433932 # number of overall hits 362system.cpu.icache.ReadReq_misses::cpu.inst 788658 # number of ReadReq misses 363system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses 364system.cpu.icache.demand_misses::cpu.inst 788658 # number of demand (read+write) misses 365system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses 366system.cpu.icache.overall_misses::cpu.inst 788658 # number of overall misses 367system.cpu.icache.overall_misses::total 788658 # number of overall misses 368system.cpu.icache.ReadReq_miss_latency::cpu.inst 11681762500 # number of ReadReq miss cycles 369system.cpu.icache.ReadReq_miss_latency::total 11681762500 # number of ReadReq miss cycles 370system.cpu.icache.demand_miss_latency::cpu.inst 11681762500 # number of demand (read+write) miss cycles 371system.cpu.icache.demand_miss_latency::total 11681762500 # number of demand (read+write) miss cycles 372system.cpu.icache.overall_miss_latency::cpu.inst 11681762500 # number of overall miss cycles 373system.cpu.icache.overall_miss_latency::total 11681762500 # number of overall miss cycles 374system.cpu.icache.ReadReq_accesses::cpu.inst 159222590 # number of ReadReq accesses(hits+misses) 375system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses) 376system.cpu.icache.demand_accesses::cpu.inst 159222590 # number of demand (read+write) accesses 377system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses 378system.cpu.icache.overall_accesses::cpu.inst 159222590 # number of overall (read+write) accesses 379system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses 380system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004953 # miss rate for ReadReq accesses 381system.cpu.icache.demand_miss_rate::cpu.inst 0.004953 # miss rate for demand accesses 382system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses 383system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency 384system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency 385system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency 386system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked	282system.iocache.fast_writes 0 # number of fast writes performed 283system.iocache.cache_copies 0 # number of cache copies performed 284system.iocache.writebacks::writebacks 46668 # number of writebacks 285system.iocache.writebacks::total 46668 # number of writebacks 286system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses 287system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses 288system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 289system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 290system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses 291system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses 292system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses 293system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses 294system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 62666978 # number of ReadReq MSHR miss cycles 295system.iocache.ReadReq_mshr_miss_latency::total 62666978 # number of ReadReq MSHR miss cycles 296system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3961676998 # number of WriteReq MSHR miss cycles 297system.iocache.WriteReq_mshr_miss_latency::total 3961676998 # number of WriteReq MSHR miss cycles 298system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of demand (read+write) MSHR miss cycles 299system.iocache.demand_mshr_miss_latency::total 4024343976 # number of demand (read+write) MSHR miss cycles 300system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4024343976 # number of overall MSHR miss cycles 301system.iocache.overall_mshr_miss_latency::total 4024343976 # number of overall MSHR miss cycles 302system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 303system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 304system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 305system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 306system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934 # average ReadReq mshr miss latency 307system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622 # average WriteReq mshr miss latency 308system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency 309system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536 # average overall mshr miss latency 310system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 311system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 312system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 313system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 314system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 315system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 316system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 317system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 318system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 319system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 320system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 321system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 322system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 323system.cpu.numCycles 10390940786 # number of cpu cycles simulated 324system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 325system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 326system.cpu.committedInsts 138138472 # Number of instructions committed 327system.cpu.committedOps 265147881 # Number of ops (including micro ops) committed 328system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses 329system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 330system.cpu.num_func_calls 0 # number of times a function call or return occured 331system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls 332system.cpu.num_int_insts 249556386 # number of integer instructions 333system.cpu.num_fp_insts 0 # number of float instructions 334system.cpu.num_int_register_reads 543487907 # number of times the integer registers were read 335system.cpu.num_int_register_writes 266037487 # number of times the integer registers were written 336system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 337system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 338system.cpu.num_mem_refs 23169904 # number of memory refs 339system.cpu.num_load_insts 14812525 # Number of load instructions 340system.cpu.num_store_insts 8357379 # Number of store instructions 341system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles 342system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles 343system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles 344system.cpu.idle_fraction 0.941953 # Percentage of idle cycles 345system.cpu.kern.inst.arm 0 # number of arm instructions executed 346system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 347system.cpu.icache.replacements 788139 # number of replacements 348system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use 349system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks. 350system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks. 351system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks. 352system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit. 353system.cpu.icache.occ_blocks::cpu.inst 510.361283 # Average occupied blocks per requestor 354system.cpu.icache.occ_percent::cpu.inst 0.996799 # Average percentage of cache occupancy 355system.cpu.icache.occ_percent::total 0.996799 # Average percentage of cache occupancy 356system.cpu.icache.ReadReq_hits::cpu.inst 158433932 # number of ReadReq hits 357system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits 358system.cpu.icache.demand_hits::cpu.inst 158433932 # number of demand (read+write) hits 359system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits 360system.cpu.icache.overall_hits::cpu.inst 158433932 # number of overall hits 361system.cpu.icache.overall_hits::total 158433932 # number of overall hits 362system.cpu.icache.ReadReq_misses::cpu.inst 788658 # number of ReadReq misses 363system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses 364system.cpu.icache.demand_misses::cpu.inst 788658 # number of demand (read+write) misses 365system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses 366system.cpu.icache.overall_misses::cpu.inst 788658 # number of overall misses 367system.cpu.icache.overall_misses::total 788658 # number of overall misses 368system.cpu.icache.ReadReq_miss_latency::cpu.inst 11681762500 # number of ReadReq miss cycles 369system.cpu.icache.ReadReq_miss_latency::total 11681762500 # number of ReadReq miss cycles 370system.cpu.icache.demand_miss_latency::cpu.inst 11681762500 # number of demand (read+write) miss cycles 371system.cpu.icache.demand_miss_latency::total 11681762500 # number of demand (read+write) miss cycles 372system.cpu.icache.overall_miss_latency::cpu.inst 11681762500 # number of overall miss cycles 373system.cpu.icache.overall_miss_latency::total 11681762500 # number of overall miss cycles 374system.cpu.icache.ReadReq_accesses::cpu.inst 159222590 # number of ReadReq accesses(hits+misses) 375system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses) 376system.cpu.icache.demand_accesses::cpu.inst 159222590 # number of demand (read+write) accesses 377system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses 378system.cpu.icache.overall_accesses::cpu.inst 159222590 # number of overall (read+write) accesses 379system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses 380system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004953 # miss rate for ReadReq accesses 381system.cpu.icache.demand_miss_rate::cpu.inst 0.004953 # miss rate for demand accesses 382system.cpu.icache.overall_miss_rate::cpu.inst 0.004953 # miss rate for overall accesses 383system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135 # average ReadReq miss latency 384system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency 385system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135 # average overall miss latency 386system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
390system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 391system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	390system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
392system.cpu.icache.fast_writes 0 # number of fast writes performed 393system.cpu.icache.cache_copies 0 # number of cache copies performed 394system.cpu.icache.writebacks::writebacks 805 # number of writebacks 395system.cpu.icache.writebacks::total 805 # number of writebacks 396system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788658 # number of ReadReq MSHR misses 397system.cpu.icache.ReadReq_mshr_misses::total 788658 # number of ReadReq MSHR misses 398system.cpu.icache.demand_mshr_misses::cpu.inst 788658 # number of demand (read+write) MSHR misses 399system.cpu.icache.demand_mshr_misses::total 788658 # number of demand (read+write) MSHR misses 400system.cpu.icache.overall_mshr_misses::cpu.inst 788658 # number of overall MSHR misses 401system.cpu.icache.overall_mshr_misses::total 788658 # number of overall MSHR misses 402system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9314744000 # number of ReadReq MSHR miss cycles 403system.cpu.icache.ReadReq_mshr_miss_latency::total 9314744000 # number of ReadReq MSHR miss cycles 404system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9314744000 # number of demand (read+write) MSHR miss cycles 405system.cpu.icache.demand_mshr_miss_latency::total 9314744000 # number of demand (read+write) MSHR miss cycles 406system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9314744000 # number of overall MSHR miss cycles 407system.cpu.icache.overall_mshr_miss_latency::total 9314744000 # number of overall MSHR miss cycles 408system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for ReadReq accesses 409system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for demand accesses 410system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for overall accesses 411system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733 # average ReadReq mshr miss latency 412system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency 413system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency 414system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 415system.cpu.itb_walker_cache.replacements 3754 # number of replacements 416system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use 417system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks. 418system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks. 419system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks. 420system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit. 421system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070606 # Average occupied blocks per requestor 422system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191913 # Average percentage of cache occupancy 423system.cpu.itb_walker_cache.occ_percent::total 0.191913 # Average percentage of cache occupancy 424system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7619 # number of ReadReq hits 425system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits 426system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 427system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 428system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7621 # number of demand (read+write) hits 429system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits 430system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7621 # number of overall hits 431system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits 432system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4602 # number of ReadReq misses 433system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses 434system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4602 # number of demand (read+write) misses 435system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses 436system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4602 # number of overall misses 437system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses 438system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50817000 # number of ReadReq miss cycles 439system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50817000 # number of ReadReq miss cycles 440system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50817000 # number of demand (read+write) miss cycles 441system.cpu.itb_walker_cache.demand_miss_latency::total 50817000 # number of demand (read+write) miss cycles 442system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50817000 # number of overall miss cycles 443system.cpu.itb_walker_cache.overall_miss_latency::total 50817000 # number of overall miss cycles 444system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) 445system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) 446system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 447system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 448system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses 449system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses 450system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses 451system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses 452system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376565 # miss rate for ReadReq accesses 453system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376503 # miss rate for demand accesses 454system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses 455system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency 456system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency 457system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency 458system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 459system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 460system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 461system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked	392system.cpu.icache.fast_writes 0 # number of fast writes performed 393system.cpu.icache.cache_copies 0 # number of cache copies performed 394system.cpu.icache.writebacks::writebacks 805 # number of writebacks 395system.cpu.icache.writebacks::total 805 # number of writebacks 396system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788658 # number of ReadReq MSHR misses 397system.cpu.icache.ReadReq_mshr_misses::total 788658 # number of ReadReq MSHR misses 398system.cpu.icache.demand_mshr_misses::cpu.inst 788658 # number of demand (read+write) MSHR misses 399system.cpu.icache.demand_mshr_misses::total 788658 # number of demand (read+write) MSHR misses 400system.cpu.icache.overall_mshr_misses::cpu.inst 788658 # number of overall MSHR misses 401system.cpu.icache.overall_mshr_misses::total 788658 # number of overall MSHR misses 402system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9314744000 # number of ReadReq MSHR miss cycles 403system.cpu.icache.ReadReq_mshr_miss_latency::total 9314744000 # number of ReadReq MSHR miss cycles 404system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9314744000 # number of demand (read+write) MSHR miss cycles 405system.cpu.icache.demand_mshr_miss_latency::total 9314744000 # number of demand (read+write) MSHR miss cycles 406system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9314744000 # number of overall MSHR miss cycles 407system.cpu.icache.overall_mshr_miss_latency::total 9314744000 # number of overall MSHR miss cycles 408system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for ReadReq accesses 409system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for demand accesses 410system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004953 # mshr miss rate for overall accesses 411system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733 # average ReadReq mshr miss latency 412system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency 413system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733 # average overall mshr miss latency 414system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 415system.cpu.itb_walker_cache.replacements 3754 # number of replacements 416system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use 417system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks. 418system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks. 419system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks. 420system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit. 421system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.070606 # Average occupied blocks per requestor 422system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191913 # Average percentage of cache occupancy 423system.cpu.itb_walker_cache.occ_percent::total 0.191913 # Average percentage of cache occupancy 424system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7619 # number of ReadReq hits 425system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits 426system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 427system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 428system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7621 # number of demand (read+write) hits 429system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits 430system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7621 # number of overall hits 431system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits 432system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4602 # number of ReadReq misses 433system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses 434system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4602 # number of demand (read+write) misses 435system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses 436system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4602 # number of overall misses 437system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses 438system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 50817000 # number of ReadReq miss cycles 439system.cpu.itb_walker_cache.ReadReq_miss_latency::total 50817000 # number of ReadReq miss cycles 440system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 50817000 # number of demand (read+write) miss cycles 441system.cpu.itb_walker_cache.demand_miss_latency::total 50817000 # number of demand (read+write) miss cycles 442system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 50817000 # number of overall miss cycles 443system.cpu.itb_walker_cache.overall_miss_latency::total 50817000 # number of overall miss cycles 444system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) 445system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) 446system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 447system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 448system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses 449system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses 450system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses 451system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses 452system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376565 # miss rate for ReadReq accesses 453system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376503 # miss rate for demand accesses 454system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376503 # miss rate for overall accesses 455system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881 # average ReadReq miss latency 456system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency 457system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881 # average overall miss latency 458system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 459system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 460system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 461system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
462system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 463system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	462system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 463system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
464system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 465system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 466system.cpu.itb_walker_cache.writebacks::writebacks 826 # number of writebacks 467system.cpu.itb_walker_cache.writebacks::total 826 # number of writebacks 468system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4602 # number of ReadReq MSHR misses 469system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4602 # number of ReadReq MSHR misses 470system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4602 # number of demand (read+write) MSHR misses 471system.cpu.itb_walker_cache.demand_mshr_misses::total 4602 # number of demand (read+write) MSHR misses 472system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4602 # number of overall MSHR misses 473system.cpu.itb_walker_cache.overall_mshr_misses::total 4602 # number of overall MSHR misses 474system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37011000 # number of ReadReq MSHR miss cycles 475system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37011000 # number of ReadReq MSHR miss cycles 476system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37011000 # number of demand (read+write) MSHR miss cycles 477system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37011000 # number of demand (read+write) MSHR miss cycles 478system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37011000 # number of overall MSHR miss cycles 479system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37011000 # number of overall MSHR miss cycles 480system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376565 # mshr miss rate for ReadReq accesses 481system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for demand accesses 482system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for overall accesses 483system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average ReadReq mshr miss latency 484system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency 485system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency 486system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 487system.cpu.dtb_walker_cache.replacements 7704 # number of replacements 488system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use 489system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks. 490system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks. 491system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks. 492system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit. 493system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052403 # Average occupied blocks per requestor 494system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315775 # Average percentage of cache occupancy 495system.cpu.dtb_walker_cache.occ_percent::total 0.315775 # Average percentage of cache occupancy 496system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13051 # number of ReadReq hits 497system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits 498system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13051 # number of demand (read+write) hits 499system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits 500system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13051 # number of overall hits 501system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits 502system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8896 # number of ReadReq misses 503system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses 504system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8896 # number of demand (read+write) misses 505system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses 506system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8896 # number of overall misses 507system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses 508system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 103895500 # number of ReadReq miss cycles 509system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 103895500 # number of ReadReq miss cycles 510system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 103895500 # number of demand (read+write) miss cycles 511system.cpu.dtb_walker_cache.demand_miss_latency::total 103895500 # number of demand (read+write) miss cycles 512system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 103895500 # number of overall miss cycles 513system.cpu.dtb_walker_cache.overall_miss_latency::total 103895500 # number of overall miss cycles 514system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21947 # number of ReadReq accesses(hits+misses) 515system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses) 516system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21947 # number of demand (read+write) accesses 517system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses 518system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21947 # number of overall (read+write) accesses 519system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses 520system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405340 # miss rate for ReadReq accesses 521system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405340 # miss rate for demand accesses 522system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses 523system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency 524system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency 525system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency 526system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 527system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 528system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 529system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked	464system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 465system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 466system.cpu.itb_walker_cache.writebacks::writebacks 826 # number of writebacks 467system.cpu.itb_walker_cache.writebacks::total 826 # number of writebacks 468system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4602 # number of ReadReq MSHR misses 469system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4602 # number of ReadReq MSHR misses 470system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4602 # number of demand (read+write) MSHR misses 471system.cpu.itb_walker_cache.demand_mshr_misses::total 4602 # number of demand (read+write) MSHR misses 472system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4602 # number of overall MSHR misses 473system.cpu.itb_walker_cache.overall_mshr_misses::total 4602 # number of overall MSHR misses 474system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37011000 # number of ReadReq MSHR miss cycles 475system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37011000 # number of ReadReq MSHR miss cycles 476system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37011000 # number of demand (read+write) MSHR miss cycles 477system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37011000 # number of demand (read+write) MSHR miss cycles 478system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37011000 # number of overall MSHR miss cycles 479system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37011000 # number of overall MSHR miss cycles 480system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376565 # mshr miss rate for ReadReq accesses 481system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for demand accesses 482system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376503 # mshr miss rate for overall accesses 483system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average ReadReq mshr miss latency 484system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency 485system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8042.372881 # average overall mshr miss latency 486system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 487system.cpu.dtb_walker_cache.replacements 7704 # number of replacements 488system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use 489system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks. 490system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks. 491system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks. 492system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit. 493system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.052403 # Average occupied blocks per requestor 494system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315775 # Average percentage of cache occupancy 495system.cpu.dtb_walker_cache.occ_percent::total 0.315775 # Average percentage of cache occupancy 496system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13051 # number of ReadReq hits 497system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits 498system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13051 # number of demand (read+write) hits 499system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits 500system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13051 # number of overall hits 501system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits 502system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8896 # number of ReadReq misses 503system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses 504system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8896 # number of demand (read+write) misses 505system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses 506system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8896 # number of overall misses 507system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses 508system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 103895500 # number of ReadReq miss cycles 509system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 103895500 # number of ReadReq miss cycles 510system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 103895500 # number of demand (read+write) miss cycles 511system.cpu.dtb_walker_cache.demand_miss_latency::total 103895500 # number of demand (read+write) miss cycles 512system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 103895500 # number of overall miss cycles 513system.cpu.dtb_walker_cache.overall_miss_latency::total 103895500 # number of overall miss cycles 514system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21947 # number of ReadReq accesses(hits+misses) 515system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses) 516system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21947 # number of demand (read+write) accesses 517system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses 518system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21947 # number of overall (read+write) accesses 519system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses 520system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405340 # miss rate for ReadReq accesses 521system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405340 # miss rate for demand accesses 522system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405340 # miss rate for overall accesses 523system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629 # average ReadReq miss latency 524system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency 525system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629 # average overall miss latency 526system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 527system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 528system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 529system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
530system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 531system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	530system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 531system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
532system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 533system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 534system.cpu.dtb_walker_cache.writebacks::writebacks 2985 # number of writebacks 535system.cpu.dtb_walker_cache.writebacks::total 2985 # number of writebacks 536system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8896 # number of ReadReq MSHR misses 537system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses 538system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8896 # number of demand (read+write) MSHR misses 539system.cpu.dtb_walker_cache.demand_mshr_misses::total 8896 # number of demand (read+write) MSHR misses 540system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8896 # number of overall MSHR misses 541system.cpu.dtb_walker_cache.overall_mshr_misses::total 8896 # number of overall MSHR misses 542system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77207000 # number of ReadReq MSHR miss cycles 543system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77207000 # number of ReadReq MSHR miss cycles 544system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77207000 # number of demand (read+write) MSHR miss cycles 545system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77207000 # number of demand (read+write) MSHR miss cycles 546system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77207000 # number of overall MSHR miss cycles 547system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77207000 # number of overall MSHR miss cycles 548system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for ReadReq accesses 549system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for demand accesses 550system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for overall accesses 551system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average ReadReq mshr miss latency 552system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency 553system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency 554system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 555system.cpu.dcache.replacements 1623424 # number of replacements 556system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use 557system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks. 558system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks. 559system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks. 560system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit. 561system.cpu.dcache.occ_blocks::cpu.data 511.997312 # Average occupied blocks per requestor 562system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy 563system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy 564system.cpu.dcache.ReadReq_hits::cpu.data 11977182 # number of ReadReq hits 565system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits 566system.cpu.dcache.WriteReq_hits::cpu.data 8032009 # number of WriteReq hits 567system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits 568system.cpu.dcache.demand_hits::cpu.data 20009191 # number of demand (read+write) hits 569system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits 570system.cpu.dcache.overall_hits::cpu.data 20009191 # number of overall hits 571system.cpu.dcache.overall_hits::total 20009191 # number of overall hits 572system.cpu.dcache.ReadReq_misses::cpu.data 1310824 # number of ReadReq misses 573system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses 574system.cpu.dcache.WriteReq_misses::cpu.data 315344 # number of WriteReq misses 575system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses 576system.cpu.dcache.demand_misses::cpu.data 1626168 # number of demand (read+write) misses 577system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses 578system.cpu.dcache.overall_misses::cpu.data 1626168 # number of overall misses 579system.cpu.dcache.overall_misses::total 1626168 # number of overall misses 580system.cpu.dcache.ReadReq_miss_latency::cpu.data 19851809000 # number of ReadReq miss cycles 581system.cpu.dcache.ReadReq_miss_latency::total 19851809000 # number of ReadReq miss cycles 582system.cpu.dcache.WriteReq_miss_latency::cpu.data 9514837000 # number of WriteReq miss cycles 583system.cpu.dcache.WriteReq_miss_latency::total 9514837000 # number of WriteReq miss cycles 584system.cpu.dcache.demand_miss_latency::cpu.data 29366646000 # number of demand (read+write) miss cycles 585system.cpu.dcache.demand_miss_latency::total 29366646000 # number of demand (read+write) miss cycles 586system.cpu.dcache.overall_miss_latency::cpu.data 29366646000 # number of overall miss cycles 587system.cpu.dcache.overall_miss_latency::total 29366646000 # number of overall miss cycles 588system.cpu.dcache.ReadReq_accesses::cpu.data 13288006 # number of ReadReq accesses(hits+misses) 589system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses) 590system.cpu.dcache.WriteReq_accesses::cpu.data 8347353 # number of WriteReq accesses(hits+misses) 591system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses) 592system.cpu.dcache.demand_accesses::cpu.data 21635359 # number of demand (read+write) accesses 593system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses 594system.cpu.dcache.overall_accesses::cpu.data 21635359 # number of overall (read+write) accesses 595system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses 596system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098647 # miss rate for ReadReq accesses 597system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037778 # miss rate for WriteReq accesses 598system.cpu.dcache.demand_miss_rate::cpu.data 0.075163 # miss rate for demand accesses 599system.cpu.dcache.overall_miss_rate::cpu.data 0.075163 # miss rate for overall accesses 600system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency 601system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency 602system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency 603system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency 604system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 605system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 606system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 607system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked	532system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 533system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 534system.cpu.dtb_walker_cache.writebacks::writebacks 2985 # number of writebacks 535system.cpu.dtb_walker_cache.writebacks::total 2985 # number of writebacks 536system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8896 # number of ReadReq MSHR misses 537system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses 538system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8896 # number of demand (read+write) MSHR misses 539system.cpu.dtb_walker_cache.demand_mshr_misses::total 8896 # number of demand (read+write) MSHR misses 540system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8896 # number of overall MSHR misses 541system.cpu.dtb_walker_cache.overall_mshr_misses::total 8896 # number of overall MSHR misses 542system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 77207000 # number of ReadReq MSHR miss cycles 543system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 77207000 # number of ReadReq MSHR miss cycles 544system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 77207000 # number of demand (read+write) MSHR miss cycles 545system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 77207000 # number of demand (read+write) MSHR miss cycles 546system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 77207000 # number of overall MSHR miss cycles 547system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 77207000 # number of overall MSHR miss cycles 548system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for ReadReq accesses 549system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for demand accesses 550system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.405340 # mshr miss rate for overall accesses 551system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average ReadReq mshr miss latency 552system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency 553system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8678.844424 # average overall mshr miss latency 554system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 555system.cpu.dcache.replacements 1623424 # number of replacements 556system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use 557system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks. 558system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks. 559system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks. 560system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit. 561system.cpu.dcache.occ_blocks::cpu.data 511.997312 # Average occupied blocks per requestor 562system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy 563system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy 564system.cpu.dcache.ReadReq_hits::cpu.data 11977182 # number of ReadReq hits 565system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits 566system.cpu.dcache.WriteReq_hits::cpu.data 8032009 # number of WriteReq hits 567system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits 568system.cpu.dcache.demand_hits::cpu.data 20009191 # number of demand (read+write) hits 569system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits 570system.cpu.dcache.overall_hits::cpu.data 20009191 # number of overall hits 571system.cpu.dcache.overall_hits::total 20009191 # number of overall hits 572system.cpu.dcache.ReadReq_misses::cpu.data 1310824 # number of ReadReq misses 573system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses 574system.cpu.dcache.WriteReq_misses::cpu.data 315344 # number of WriteReq misses 575system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses 576system.cpu.dcache.demand_misses::cpu.data 1626168 # number of demand (read+write) misses 577system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses 578system.cpu.dcache.overall_misses::cpu.data 1626168 # number of overall misses 579system.cpu.dcache.overall_misses::total 1626168 # number of overall misses 580system.cpu.dcache.ReadReq_miss_latency::cpu.data 19851809000 # number of ReadReq miss cycles 581system.cpu.dcache.ReadReq_miss_latency::total 19851809000 # number of ReadReq miss cycles 582system.cpu.dcache.WriteReq_miss_latency::cpu.data 9514837000 # number of WriteReq miss cycles 583system.cpu.dcache.WriteReq_miss_latency::total 9514837000 # number of WriteReq miss cycles 584system.cpu.dcache.demand_miss_latency::cpu.data 29366646000 # number of demand (read+write) miss cycles 585system.cpu.dcache.demand_miss_latency::total 29366646000 # number of demand (read+write) miss cycles 586system.cpu.dcache.overall_miss_latency::cpu.data 29366646000 # number of overall miss cycles 587system.cpu.dcache.overall_miss_latency::total 29366646000 # number of overall miss cycles 588system.cpu.dcache.ReadReq_accesses::cpu.data 13288006 # number of ReadReq accesses(hits+misses) 589system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses) 590system.cpu.dcache.WriteReq_accesses::cpu.data 8347353 # number of WriteReq accesses(hits+misses) 591system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses) 592system.cpu.dcache.demand_accesses::cpu.data 21635359 # number of demand (read+write) accesses 593system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses 594system.cpu.dcache.overall_accesses::cpu.data 21635359 # number of overall (read+write) accesses 595system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses 596system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098647 # miss rate for ReadReq accesses 597system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037778 # miss rate for WriteReq accesses 598system.cpu.dcache.demand_miss_rate::cpu.data 0.075163 # miss rate for demand accesses 599system.cpu.dcache.overall_miss_rate::cpu.data 0.075163 # miss rate for overall accesses 600system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649 # average ReadReq miss latency 601system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044 # average WriteReq miss latency 602system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency 603system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043 # average overall miss latency 604system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 605system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 606system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 607system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
608system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 609system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked	608system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 609system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
610system.cpu.dcache.fast_writes 0 # number of fast writes performed 611system.cpu.dcache.cache_copies 0 # number of cache copies performed 612system.cpu.dcache.writebacks::writebacks 1529951 # number of writebacks 613system.cpu.dcache.writebacks::total 1529951 # number of writebacks 614system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1310824 # number of ReadReq MSHR misses 615system.cpu.dcache.ReadReq_mshr_misses::total 1310824 # number of ReadReq MSHR misses 616system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315344 # number of WriteReq MSHR misses 617system.cpu.dcache.WriteReq_mshr_misses::total 315344 # number of WriteReq MSHR misses 618system.cpu.dcache.demand_mshr_misses::cpu.data 1626168 # number of demand (read+write) MSHR misses 619system.cpu.dcache.demand_mshr_misses::total 1626168 # number of demand (read+write) MSHR misses 620system.cpu.dcache.overall_mshr_misses::cpu.data 1626168 # number of overall MSHR misses 621system.cpu.dcache.overall_mshr_misses::total 1626168 # number of overall MSHR misses 622system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15919294500 # number of ReadReq MSHR miss cycles 623system.cpu.dcache.ReadReq_mshr_miss_latency::total 15919294500 # number of ReadReq MSHR miss cycles 624system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8568794500 # number of WriteReq MSHR miss cycles 625system.cpu.dcache.WriteReq_mshr_miss_latency::total 8568794500 # number of WriteReq MSHR miss cycles 626system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488089000 # number of demand (read+write) MSHR miss cycles 627system.cpu.dcache.demand_mshr_miss_latency::total 24488089000 # number of demand (read+write) MSHR miss cycles 628system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488089000 # number of overall MSHR miss cycles 629system.cpu.dcache.overall_mshr_miss_latency::total 24488089000 # number of overall MSHR miss cycles 630system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75925324500 # number of ReadReq MSHR uncacheable cycles 631system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75925324500 # number of ReadReq MSHR uncacheable cycles 632system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1379728500 # number of WriteReq MSHR uncacheable cycles 633system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379728500 # number of WriteReq MSHR uncacheable cycles 634system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77305053000 # number of overall MSHR uncacheable cycles 635system.cpu.dcache.overall_mshr_uncacheable_latency::total 77305053000 # number of overall MSHR uncacheable cycles 636system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098647 # mshr miss rate for ReadReq accesses 637system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037778 # mshr miss rate for WriteReq accesses 638system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for demand accesses 639system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for overall accesses 640system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227 # average ReadReq mshr miss latency 641system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747 # average WriteReq mshr miss latency 642system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency 643system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency 644system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 645system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 646system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 647system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 648 649---------- End Simulation Statistics ----------	610system.cpu.dcache.fast_writes 0 # number of fast writes performed 611system.cpu.dcache.cache_copies 0 # number of cache copies performed 612system.cpu.dcache.writebacks::writebacks 1529951 # number of writebacks 613system.cpu.dcache.writebacks::total 1529951 # number of writebacks 614system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1310824 # number of ReadReq MSHR misses 615system.cpu.dcache.ReadReq_mshr_misses::total 1310824 # number of ReadReq MSHR misses 616system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315344 # number of WriteReq MSHR misses 617system.cpu.dcache.WriteReq_mshr_misses::total 315344 # number of WriteReq MSHR misses 618system.cpu.dcache.demand_mshr_misses::cpu.data 1626168 # number of demand (read+write) MSHR misses 619system.cpu.dcache.demand_mshr_misses::total 1626168 # number of demand (read+write) MSHR misses 620system.cpu.dcache.overall_mshr_misses::cpu.data 1626168 # number of overall MSHR misses 621system.cpu.dcache.overall_mshr_misses::total 1626168 # number of overall MSHR misses 622system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15919294500 # number of ReadReq MSHR miss cycles 623system.cpu.dcache.ReadReq_mshr_miss_latency::total 15919294500 # number of ReadReq MSHR miss cycles 624system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8568794500 # number of WriteReq MSHR miss cycles 625system.cpu.dcache.WriteReq_mshr_miss_latency::total 8568794500 # number of WriteReq MSHR miss cycles 626system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488089000 # number of demand (read+write) MSHR miss cycles 627system.cpu.dcache.demand_mshr_miss_latency::total 24488089000 # number of demand (read+write) MSHR miss cycles 628system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488089000 # number of overall MSHR miss cycles 629system.cpu.dcache.overall_mshr_miss_latency::total 24488089000 # number of overall MSHR miss cycles 630system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75925324500 # number of ReadReq MSHR uncacheable cycles 631system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75925324500 # number of ReadReq MSHR uncacheable cycles 632system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1379728500 # number of WriteReq MSHR uncacheable cycles 633system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379728500 # number of WriteReq MSHR uncacheable cycles 634system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77305053000 # number of overall MSHR uncacheable cycles 635system.cpu.dcache.overall_mshr_uncacheable_latency::total 77305053000 # number of overall MSHR uncacheable cycles 636system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098647 # mshr miss rate for ReadReq accesses 637system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037778 # mshr miss rate for WriteReq accesses 638system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for demand accesses 639system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for overall accesses 640system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227 # average ReadReq mshr miss latency 641system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747 # average WriteReq mshr miss latency 642system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency 643system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency 644system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 645system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 646system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 647system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 648 649---------- End Simulation Statistics ----------