Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt

Deleted Added

sdiff udiff text old ( 10036:80e84beef3bb ) new ( 10063:9595c7a1d837 )

full compact

stats.txt (10036:80e84beef3bb)	stats.txt (10063:9595c7a1d837)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.196390 # Number of seconds simulated 4sim_ticks 5196390180000 # Number of ticks simulated 5final_tick 5196390180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 991078 # Simulator instruction rate (inst/s) 8host_op_rate 1910460 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40129605273 # Simulator tick rate (ticks/s) 10host_mem_usage 591204 # Number of bytes of host memory used 11host_seconds 129.49 # Real time elapsed on the host 12sim_insts 128334813 # Number of instructions simulated 13sim_ops 247385808 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 2883712 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 8989184 # Number of bytes read from this memory 21system.physmem.bytes_read::total 12697856 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8110912 # Number of bytes written to this memory 25system.physmem.bytes_written::total 8110912 # Number of bytes written to this memory 26system.physmem.num_reads::pc.south_bridge.ide 45058 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 140456 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 198404 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 126733 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 126733 # Number of write requests responded to by this memory 34system.physmem.bw_read::pc.south_bridge.ide 554945 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 158670 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 1729890 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2443592 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 158670 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 158670 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1560874 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1560874 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1560874 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::pc.south_bridge.ide 554945 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.inst 158670 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.data 1729890 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4004466 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 198404 # Number of read requests accepted 52system.physmem.writeReqs 126733 # Number of write requests accepted 53system.physmem.readBursts 198404 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 126733 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 12694144 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue 57system.physmem.bytesWritten 8109888 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 12697856 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 8110912 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 1616 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 12580 # Per bank write bursts 64system.physmem.perBankRdBursts::1 12146 # Per bank write bursts 65system.physmem.perBankRdBursts::2 12820 # Per bank write bursts 66system.physmem.perBankRdBursts::3 12639 # Per bank write bursts 67system.physmem.perBankRdBursts::4 12420 # Per bank write bursts 68system.physmem.perBankRdBursts::5 12033 # Per bank write bursts 69system.physmem.perBankRdBursts::6 12032 # Per bank write bursts 70system.physmem.perBankRdBursts::7 12154 # Per bank write bursts 71system.physmem.perBankRdBursts::8 12328 # Per bank write bursts 72system.physmem.perBankRdBursts::9 11842 # Per bank write bursts 73system.physmem.perBankRdBursts::10 12289 # Per bank write bursts 74system.physmem.perBankRdBursts::11 12385 # Per bank write bursts 75system.physmem.perBankRdBursts::12 12618 # Per bank write bursts 76system.physmem.perBankRdBursts::13 13039 # Per bank write bursts 77system.physmem.perBankRdBursts::14 12508 # Per bank write bursts 78system.physmem.perBankRdBursts::15 12513 # Per bank write bursts 79system.physmem.perBankWrBursts::0 8180 # Per bank write bursts 80system.physmem.perBankWrBursts::1 7837 # Per bank write bursts 81system.physmem.perBankWrBursts::2 8283 # Per bank write bursts 82system.physmem.perBankWrBursts::3 8150 # Per bank write bursts 83system.physmem.perBankWrBursts::4 7961 # Per bank write bursts 84system.physmem.perBankWrBursts::5 7589 # Per bank write bursts 85system.physmem.perBankWrBursts::6 7480 # Per bank write bursts 86system.physmem.perBankWrBursts::7 7728 # Per bank write bursts 87system.physmem.perBankWrBursts::8 7696 # Per bank write bursts 88system.physmem.perBankWrBursts::9 7447 # Per bank write bursts 89system.physmem.perBankWrBursts::10 7846 # Per bank write bursts 90system.physmem.perBankWrBursts::11 7788 # Per bank write bursts 91system.physmem.perBankWrBursts::12 8080 # Per bank write bursts 92system.physmem.perBankWrBursts::13 8539 # Per bank write bursts 93system.physmem.perBankWrBursts::14 8032 # Per bank write bursts 94system.physmem.perBankWrBursts::15 8081 # Per bank write bursts 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 7 # Number of times write queue was full causing retry 97system.physmem.totGap 5196390116500 # Total gap between requests 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) 104system.physmem.readPktSize::6 198404 # Read request sizes (log2) 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) 111system.physmem.writePktSize::6 126733 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 155323 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 13571 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 6905 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 2932 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 2598 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 2604 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 1783 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 1802 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 1789 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 826 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 797 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 790 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 755 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 733 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 725 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 712 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 712 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 711 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 52 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.wrQLenPdf::0 5072 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::1 5130 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::2 5143 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::3 5187 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::4 5411 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::5 5609 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::6 5671 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::7 5668 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 6394 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 6161 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 6233 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 6275 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 6715 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 6223 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::15 6456 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 6523 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 5238 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 5186 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 5154 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 5136 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 305 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 234 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 63 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 33 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 28 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 20 # What write queue length does an incoming req see 176system.physmem.bytesPerActivate::samples 53708 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::mean 387.265063 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::gmean 159.541838 # Bytes accessed per row activation 179system.physmem.bytesPerActivate::stdev 1283.636288 # Bytes accessed per row activation 180system.physmem.bytesPerActivate::64-67 22377 41.66% 41.66% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::128-131 8801 16.39% 58.05% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::192-195 5780 10.76% 68.81% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::256-259 3435 6.40% 75.21% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::320-323 2322 4.32% 79.53% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::384-387 1859 3.46% 82.99% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::448-451 1339 2.49% 85.49% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::512-515 1034 1.93% 87.41% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::576-579 806 1.50% 88.91% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::640-643 663 1.23% 90.15% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::704-707 546 1.02% 91.16% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::768-771 427 0.80% 91.96% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::832-835 325 0.61% 92.56% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::896-899 307 0.57% 93.14% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::960-963 277 0.52% 93.65% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1024-1027 550 1.02% 94.67% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1088-1091 185 0.34% 95.02% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1152-1155 190 0.35% 95.37% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1216-1219 112 0.21% 95.58% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1280-1283 109 0.20% 95.78% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1344-1347 125 0.23% 96.02% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1408-1411 422 0.79% 96.80% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1472-1475 149 0.28% 97.08% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1536-1539 87 0.16% 97.24% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1600-1603 55 0.10% 97.34% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1664-1667 85 0.16% 97.50% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1728-1731 52 0.10% 97.60% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1792-1795 36 0.07% 97.67% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1856-1859 25 0.05% 97.71% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1920-1923 24 0.04% 97.76% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::1984-1987 18 0.03% 97.79% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2048-2051 26 0.05% 97.84% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2112-2115 25 0.05% 97.89% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2176-2179 20 0.04% 97.92% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.95% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2304-2307 13 0.02% 97.97% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2368-2371 9 0.02% 97.99% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2432-2435 14 0.03% 98.02% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2496-2499 11 0.02% 98.04% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.06% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2624-2627 14 0.03% 98.08% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2688-2691 11 0.02% 98.10% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2752-2755 9 0.02% 98.12% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2816-2819 10 0.02% 98.14% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::2880-2883 13 0.02% 98.16% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.18% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.20% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3072-3075 26 0.05% 98.25% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3136-3139 12 0.02% 98.27% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3200-3203 9 0.02% 98.29% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3264-3267 19 0.04% 98.32% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3328-3331 10 0.02% 98.34% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3392-3395 9 0.02% 98.36% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3456-3459 12 0.02% 98.38% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.39% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3584-3587 12 0.02% 98.41% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3648-3651 15 0.03% 98.44% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3712-3715 10 0.02% 98.46% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3776-3779 20 0.04% 98.50% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3840-3843 13 0.02% 98.52% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::3904-3907 24 0.04% 98.57% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3968-3971 13 0.02% 98.59% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4032-4035 11 0.02% 98.61% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4096-4099 19 0.04% 98.65% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4160-4163 10 0.02% 98.67% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4224-4227 13 0.02% 98.69% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4288-4291 7 0.01% 98.70% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4352-4355 9 0.02% 98.72% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4416-4419 11 0.02% 98.74% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4480-4483 7 0.01% 98.75% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4544-4547 9 0.02% 98.77% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4608-4611 9 0.02% 98.79% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.79% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4736-4739 10 0.02% 98.81% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4800-4803 9 0.02% 98.83% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4864-4867 7 0.01% 98.84% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::4928-4931 9 0.02% 98.86% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::4992-4995 7 0.01% 98.87% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5056-5059 5 0.01% 98.88% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5120-5123 13 0.02% 98.91% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5184-5187 8 0.01% 98.92% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5248-5251 7 0.01% 98.93% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5312-5315 8 0.01% 98.95% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5376-5379 10 0.02% 98.97% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5440-5443 5 0.01% 98.98% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5504-5507 9 0.02% 98.99% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5568-5571 151 0.28% 99.27% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.28% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.28% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5824-5827 2 0.00% 99.28% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.28% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6208-6211 3 0.01% 99.29% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6272-6275 2 0.00% 99.29% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.29% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6528-6531 2 0.00% 99.30% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.31% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.31% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.31% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.32% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6912-6915 4 0.01% 99.33% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7040-7043 2 0.00% 99.33% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7168-7171 19 0.04% 99.37% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7232-7235 4 0.01% 99.37% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.38% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.38% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.38% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.39% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.39% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.40% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8192-8195 14 0.03% 99.42% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.43% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.43% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8512-8515 3 0.01% 99.44% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.44% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.44% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::9152-9155 2 0.00% 99.45% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.45% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.45% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.46% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9536-9539 2 0.00% 99.46% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.46% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.46% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.47% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.47% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.47% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::11136-11139 3 0.01% 99.48% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.48% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.49% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.49% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.49% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.49% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::12224-12227 4 0.01% 99.50% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.50% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.50% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.51% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.51% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.51% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.52% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.52% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::13248-13251 4 0.01% 99.53% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::13312-13315 6 0.01% 99.54% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.54% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::13760-13763 2 0.00% 99.54% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.55% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.55% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.55% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.56% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.56% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.56% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.56% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::14848-14851 3 0.01% 99.57% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::14912-14915 7 0.01% 99.58% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.59% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.59% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.60% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::15360-15363 32 0.06% 99.66% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.66% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::15872-15875 3 0.01% 99.66% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.66% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.67% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.67% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::16384-16387 178 0.33% 100.00% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::total 53708 # Bytes accessed per row activation 344system.physmem.totQLat 5080719250 # Total ticks spent queuing 345system.physmem.totMemAccLat 8752324250 # Total ticks spent from burst creation until serviced by the DRAM 346system.physmem.totBusLat 991730000 # Total ticks spent in databus transfers 347system.physmem.totBankLat 2679875000 # Total ticks spent accessing banks 348system.physmem.avgQLat 25615.44 # Average queueing delay per DRAM burst 349system.physmem.avgBankLat 13511.11 # Average bank access latency per DRAM burst 350system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 351system.physmem.avgMemAccLat 44126.55 # Average memory access latency per DRAM burst 352system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s 353system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s 354system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s 355system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s 356system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 357system.physmem.busUtil 0.03 # Data bus utilization in percentage 358system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 359system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 360system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing 361system.physmem.avgWrQLen 8.98 # Average write queue length when enqueuing 362system.physmem.readRowHits 173438 # Number of row buffer hits during reads 363system.physmem.writeRowHits 97917 # Number of row buffer hits during writes 364system.physmem.readRowHitRate 87.44 # Row buffer hit rate for reads 365system.physmem.writeRowHitRate 77.26 # Row buffer hit rate for writes 366system.physmem.avgGap 15982155.57 # Average gap between requests 367system.physmem.pageHitRate 83.47 # Row buffer hit rate, read and write combined 368system.physmem.prechargeAllPercent 0.27 # Percentage of time for which DRAM has all the banks in precharge state 369system.membus.throughput 4365247 # Throughput (bytes/s) 370system.membus.trans_dist::ReadReq 623514 # Transaction distribution 371system.membus.trans_dist::ReadResp 623514 # Transaction distribution 372system.membus.trans_dist::WriteReq 13775 # Transaction distribution 373system.membus.trans_dist::WriteResp 13775 # Transaction distribution 374system.membus.trans_dist::Writeback 126733 # Transaction distribution 375system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution 376system.membus.trans_dist::UpgradeResp 1634 # Transaction distribution 377system.membus.trans_dist::ReadExReq 159484 # Transaction distribution 378system.membus.trans_dist::ReadExResp 159484 # Transaction distribution 379system.membus.trans_dist::MessageReq 1655 # Transaction distribution 380system.membus.trans_dist::MessageResp 1655 # Transaction distribution 381system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) 382system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) 383system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) 384system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) 385system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391174 # Packet count per connected master and slave (bytes) 386system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581616 # Packet count per connected master and slave (bytes) 387system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139281 # Packet count per connected master and slave (bytes) 388system.membus.pkt_count_system.iocache.mem_side::total 139281 # Packet count per connected master and slave (bytes) 389system.membus.pkt_count::total 1724207 # Packet count per connected master and slave (bytes) 390system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) 391system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) 392system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) 393system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) 394system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14938368 # Cumulative packet size per connected master and slave (bytes) 395system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16605037 # Cumulative packet size per connected master and slave (bytes) 396system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5870400 # Cumulative packet size per connected master and slave (bytes) 397system.membus.tot_pkt_size_system.iocache.mem_side::total 5870400 # Cumulative packet size per connected master and slave (bytes) 398system.membus.tot_pkt_size::total 22482057 # Cumulative packet size per connected master and slave (bytes) 399system.membus.data_through_bus 22482057 # Total data (bytes) 400system.membus.snoop_data_through_bus 201472 # Total snoop data (bytes) 401system.membus.reqLayer0.occupancy 256796500 # Layer occupancy (ticks) 402system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 403system.membus.reqLayer1.occupancy 359316000 # Layer occupancy (ticks) 404system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 405system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) 406system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 407system.membus.reqLayer3.occupancy 1352149000 # Layer occupancy (ticks) 408system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 409system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) 410system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 411system.membus.respLayer2.occupancy 2612327754 # Layer occupancy (ticks) 412system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 413system.membus.respLayer4.occupancy 428873750 # Layer occupancy (ticks) 414system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 415system.iocache.tags.replacements 47501 # number of replacements 416system.iocache.tags.tagsinuse 0.113099 # Cycle average of tags in use 417system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 418system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. 419system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 420system.iocache.tags.warmup_cycle 5049776837000 # Cycle when the warmup percentage was hit. 421system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.113099 # Average occupied blocks per requestor 422system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007069 # Average percentage of cache occupancy 423system.iocache.tags.occ_percent::total 0.007069 # Average percentage of cache occupancy 424system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 425system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 426system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 427system.iocache.tags.tag_accesses 428004 # Number of tag accesses 428system.iocache.tags.data_accesses 428004 # Number of data accesses 429system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses 430system.iocache.ReadReq_misses::total 836 # number of ReadReq misses 431system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 432system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 433system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses 434system.iocache.demand_misses::total 47556 # number of demand (read+write) misses 435system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses 436system.iocache.overall_misses::total 47556 # number of overall misses 437system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144134686 # number of ReadReq miss cycles 438system.iocache.ReadReq_miss_latency::total 144134686 # number of ReadReq miss cycles 439system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12487439330 # number of WriteReq miss cycles 440system.iocache.WriteReq_miss_latency::total 12487439330 # number of WriteReq miss cycles 441system.iocache.demand_miss_latency::pc.south_bridge.ide 12631574016 # number of demand (read+write) miss cycles 442system.iocache.demand_miss_latency::total 12631574016 # number of demand (read+write) miss cycles 443system.iocache.overall_miss_latency::pc.south_bridge.ide 12631574016 # number of overall miss cycles 444system.iocache.overall_miss_latency::total 12631574016 # number of overall miss cycles 445system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) 446system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) 447system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 448system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 449system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses 450system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses 451system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses 452system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses 453system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 454system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 455system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 456system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 457system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 458system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 459system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 460system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 461system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 172409.911483 # average ReadReq miss latency 462system.iocache.ReadReq_avg_miss_latency::total 172409.911483 # average ReadReq miss latency 463system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267282.519906 # average WriteReq miss latency 464system.iocache.WriteReq_avg_miss_latency::total 267282.519906 # average WriteReq miss latency 465system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency 466system.iocache.demand_avg_miss_latency::total 265614.728236 # average overall miss latency 467system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency 468system.iocache.overall_avg_miss_latency::total 265614.728236 # average overall miss latency 469system.iocache.blocked_cycles::no_mshrs 216457 # number of cycles access was blocked 470system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 471system.iocache.blocked::no_mshrs 11594 # number of cycles access was blocked 472system.iocache.blocked::no_targets 0 # number of cycles access was blocked 473system.iocache.avg_blocked_cycles::no_mshrs 18.669743 # average number of cycles each access was blocked 474system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 475system.iocache.fast_writes 0 # number of fast writes performed 476system.iocache.cache_copies 0 # number of cache copies performed 477system.iocache.writebacks::writebacks 46667 # number of writebacks 478system.iocache.writebacks::total 46667 # number of writebacks 479system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses 480system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses 481system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 482system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 483system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses 484system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses 485system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses 486system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses 487system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100637686 # number of ReadReq MSHR miss cycles 488system.iocache.ReadReq_mshr_miss_latency::total 100637686 # number of ReadReq MSHR miss cycles 489system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 10056284830 # number of WriteReq MSHR miss cycles 490system.iocache.WriteReq_mshr_miss_latency::total 10056284830 # number of WriteReq MSHR miss cycles 491system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of demand (read+write) MSHR miss cycles 492system.iocache.demand_mshr_miss_latency::total 10156922516 # number of demand (read+write) MSHR miss cycles 493system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of overall MSHR miss cycles 494system.iocache.overall_mshr_miss_latency::total 10156922516 # number of overall MSHR miss cycles 495system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 496system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 497system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 498system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 499system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 500system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 501system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 502system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 503system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120380.007177 # average ReadReq mshr miss latency 504system.iocache.ReadReq_avg_mshr_miss_latency::total 120380.007177 # average ReadReq mshr miss latency 505system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215245.822560 # average WriteReq mshr miss latency 506system.iocache.WriteReq_avg_mshr_miss_latency::total 215245.822560 # average WriteReq mshr miss latency 507system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency 508system.iocache.demand_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency 509system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency 510system.iocache.overall_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency 511system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 512system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 513system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 514system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 515system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 516system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 517system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 518system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 519system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 520system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 521system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 522system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 523system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 524system.iobus.throughput 631264 # Throughput (bytes/s) 525system.iobus.trans_dist::ReadReq 230141 # Transaction distribution 526system.iobus.trans_dist::ReadResp 230141 # Transaction distribution 527system.iobus.trans_dist::WriteReq 57579 # Transaction distribution 528system.iobus.trans_dist::WriteResp 57579 # Transaction distribution 529system.iobus.trans_dist::MessageReq 1655 # Transaction distribution 530system.iobus.trans_dist::MessageResp 1655 # Transaction distribution 531system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 532system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 533system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 534system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 535system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 536system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 537system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 538system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 539system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) 540system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 541system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 542system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 543system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 544system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 545system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 546system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 547system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 548system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 549system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) 550system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) 551system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) 552system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) 553system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) 554system.iobus.pkt_count::total 578750 # Packet count per connected master and slave (bytes) 555system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 556system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 557system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 558system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 559system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 560system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 561system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 562system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 563system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 564system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 565system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 566system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 567system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 568system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 569system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 570system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 571system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 572system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 573system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) 574system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) 575system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) 576system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) 577system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) 578system.iobus.tot_pkt_size::total 3280296 # Cumulative packet size per connected master and slave (bytes) 579system.iobus.data_through_bus 3280296 # Total data (bytes) 580system.iobus.reqLayer0.occupancy 3948164 # Layer occupancy (ticks) 581system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 582system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 583system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 584system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 585system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 586system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 587system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 588system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 589system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 590system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 591system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 592system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) 593system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 594system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 595system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 596system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 597system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 598system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) 599system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 600system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 601system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 602system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 603system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 604system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 605system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 606system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks) 607system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 608system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 609system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 610system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 611system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 612system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 613system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 614system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 615system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 616system.iobus.reqLayer18.occupancy 424033266 # Layer occupancy (ticks) 617system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 618system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 619system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 620system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) 621system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 622system.iobus.respLayer1.occupancy 52989250 # Layer occupancy (ticks) 623system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 624system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) 625system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 626system.cpu_clk_domain.clock 500 # Clock period in ticks 627system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 628system.cpu.numCycles 10392780360 # number of cpu cycles simulated 629system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 630system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 631system.cpu.committedInsts 128334813 # Number of instructions committed 632system.cpu.committedOps 247385808 # Number of ops (including micro ops) committed 633system.cpu.num_int_alu_accesses 231978567 # Number of integer alu accesses 634system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 635system.cpu.num_func_calls 2299773 # number of times a function call or return occured 636system.cpu.num_conditional_control_insts 23169265 # number of instructions that are conditional controls 637system.cpu.num_int_insts 231978567 # number of integer instructions 638system.cpu.num_fp_insts 0 # number of float instructions 639system.cpu.num_int_register_reads 434513747 # number of times the integer registers were read 640system.cpu.num_int_register_writes 197852200 # number of times the integer registers were written 641system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 642system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 643system.cpu.num_cc_register_reads 132813019 # number of times the CC registers were read 644system.cpu.num_cc_register_writes 95534921 # number of times the CC registers were written 645system.cpu.num_mem_refs 22245363 # number of memory refs 646system.cpu.num_load_insts 13878746 # Number of load instructions 647system.cpu.num_store_insts 8366617 # Number of store instructions 648system.cpu.num_idle_cycles 9785238216.998117 # Number of idle cycles 649system.cpu.num_busy_cycles 607542143.001883 # Number of busy cycles 650system.cpu.not_idle_fraction 0.058458 # Percentage of non-idle cycles 651system.cpu.idle_fraction 0.941542 # Percentage of idle cycles	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.196390 # Number of seconds simulated 4sim_ticks 5196390180000 # Number of ticks simulated 5final_tick 5196390180000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 991078 # Simulator instruction rate (inst/s) 8host_op_rate 1910460 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40129605273 # Simulator tick rate (ticks/s) 10host_mem_usage 591204 # Number of bytes of host memory used 11host_seconds 129.49 # Real time elapsed on the host 12sim_insts 128334813 # Number of instructions simulated 13sim_ops 247385808 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 2883712 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 824512 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 8989184 # Number of bytes read from this memory 21system.physmem.bytes_read::total 12697856 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 824512 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 824512 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8110912 # Number of bytes written to this memory 25system.physmem.bytes_written::total 8110912 # Number of bytes written to this memory 26system.physmem.num_reads::pc.south_bridge.ide 45058 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 12883 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 140456 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 198404 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 126733 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 126733 # Number of write requests responded to by this memory 34system.physmem.bw_read::pc.south_bridge.ide 554945 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.inst 158670 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 1729890 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2443592 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 158670 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 158670 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1560874 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1560874 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1560874 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::pc.south_bridge.ide 554945 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.inst 158670 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.data 1729890 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4004466 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 198404 # Number of read requests accepted 52system.physmem.writeReqs 126733 # Number of write requests accepted 53system.physmem.readBursts 198404 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 126733 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 12694144 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue 57system.physmem.bytesWritten 8109888 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 12697856 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 8110912 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 1616 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 12580 # Per bank write bursts 64system.physmem.perBankRdBursts::1 12146 # Per bank write bursts 65system.physmem.perBankRdBursts::2 12820 # Per bank write bursts 66system.physmem.perBankRdBursts::3 12639 # Per bank write bursts 67system.physmem.perBankRdBursts::4 12420 # Per bank write bursts 68system.physmem.perBankRdBursts::5 12033 # Per bank write bursts 69system.physmem.perBankRdBursts::6 12032 # Per bank write bursts 70system.physmem.perBankRdBursts::7 12154 # Per bank write bursts 71system.physmem.perBankRdBursts::8 12328 # Per bank write bursts 72system.physmem.perBankRdBursts::9 11842 # Per bank write bursts 73system.physmem.perBankRdBursts::10 12289 # Per bank write bursts 74system.physmem.perBankRdBursts::11 12385 # Per bank write bursts 75system.physmem.perBankRdBursts::12 12618 # Per bank write bursts 76system.physmem.perBankRdBursts::13 13039 # Per bank write bursts 77system.physmem.perBankRdBursts::14 12508 # Per bank write bursts 78system.physmem.perBankRdBursts::15 12513 # Per bank write bursts 79system.physmem.perBankWrBursts::0 8180 # Per bank write bursts 80system.physmem.perBankWrBursts::1 7837 # Per bank write bursts 81system.physmem.perBankWrBursts::2 8283 # Per bank write bursts 82system.physmem.perBankWrBursts::3 8150 # Per bank write bursts 83system.physmem.perBankWrBursts::4 7961 # Per bank write bursts 84system.physmem.perBankWrBursts::5 7589 # Per bank write bursts 85system.physmem.perBankWrBursts::6 7480 # Per bank write bursts 86system.physmem.perBankWrBursts::7 7728 # Per bank write bursts 87system.physmem.perBankWrBursts::8 7696 # Per bank write bursts 88system.physmem.perBankWrBursts::9 7447 # Per bank write bursts 89system.physmem.perBankWrBursts::10 7846 # Per bank write bursts 90system.physmem.perBankWrBursts::11 7788 # Per bank write bursts 91system.physmem.perBankWrBursts::12 8080 # Per bank write bursts 92system.physmem.perBankWrBursts::13 8539 # Per bank write bursts 93system.physmem.perBankWrBursts::14 8032 # Per bank write bursts 94system.physmem.perBankWrBursts::15 8081 # Per bank write bursts 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 7 # Number of times write queue was full causing retry 97system.physmem.totGap 5196390116500 # Total gap between requests 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) 104system.physmem.readPktSize::6 198404 # Read request sizes (log2) 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) 111system.physmem.writePktSize::6 126733 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 155323 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 13571 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 6905 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 2932 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 2598 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 2604 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 1783 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 1802 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 1789 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 1294 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 826 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 797 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 790 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 755 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 733 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 725 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 712 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 712 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 711 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 52 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.wrQLenPdf::0 5072 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::1 5130 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::2 5143 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::3 5187 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::4 5411 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::5 5609 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::6 5671 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::7 5668 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 6394 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 6161 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 6233 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 6275 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 6715 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 6051 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 6223 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::15 6456 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 6523 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 5238 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 5186 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 5154 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 5136 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 305 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 234 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 63 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 43 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 33 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 28 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 26 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 24 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 23 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 20 # What write queue length does an incoming req see 176system.physmem.bytesPerActivate::samples 53708 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::mean 387.265063 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::gmean 159.541838 # Bytes accessed per row activation 179system.physmem.bytesPerActivate::stdev 1283.636288 # Bytes accessed per row activation 180system.physmem.bytesPerActivate::64-67 22377 41.66% 41.66% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::128-131 8801 16.39% 58.05% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::192-195 5780 10.76% 68.81% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::256-259 3435 6.40% 75.21% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::320-323 2322 4.32% 79.53% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::384-387 1859 3.46% 82.99% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::448-451 1339 2.49% 85.49% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::512-515 1034 1.93% 87.41% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::576-579 806 1.50% 88.91% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::640-643 663 1.23% 90.15% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::704-707 546 1.02% 91.16% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::768-771 427 0.80% 91.96% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::832-835 325 0.61% 92.56% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::896-899 307 0.57% 93.14% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::960-963 277 0.52% 93.65% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1024-1027 550 1.02% 94.67% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1088-1091 185 0.34% 95.02% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1152-1155 190 0.35% 95.37% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1216-1219 112 0.21% 95.58% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1280-1283 109 0.20% 95.78% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1344-1347 125 0.23% 96.02% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1408-1411 422 0.79% 96.80% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1472-1475 149 0.28% 97.08% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1536-1539 87 0.16% 97.24% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1600-1603 55 0.10% 97.34% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1664-1667 85 0.16% 97.50% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1728-1731 52 0.10% 97.60% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1792-1795 36 0.07% 97.67% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1856-1859 25 0.05% 97.71% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1920-1923 24 0.04% 97.76% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::1984-1987 18 0.03% 97.79% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2048-2051 26 0.05% 97.84% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2112-2115 25 0.05% 97.89% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2176-2179 20 0.04% 97.92% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2240-2243 14 0.03% 97.95% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2304-2307 13 0.02% 97.97% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2368-2371 9 0.02% 97.99% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2432-2435 14 0.03% 98.02% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2496-2499 11 0.02% 98.04% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2560-2563 11 0.02% 98.06% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2624-2627 14 0.03% 98.08% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2688-2691 11 0.02% 98.10% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2752-2755 9 0.02% 98.12% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2816-2819 10 0.02% 98.14% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::2880-2883 13 0.02% 98.16% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::2944-2947 10 0.02% 98.18% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3008-3011 8 0.01% 98.20% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3072-3075 26 0.05% 98.25% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3136-3139 12 0.02% 98.27% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3200-3203 9 0.02% 98.29% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3264-3267 19 0.04% 98.32% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3328-3331 10 0.02% 98.34% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3392-3395 9 0.02% 98.36% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3456-3459 12 0.02% 98.38% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3520-3523 7 0.01% 98.39% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3584-3587 12 0.02% 98.41% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3648-3651 15 0.03% 98.44% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3712-3715 10 0.02% 98.46% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3776-3779 20 0.04% 98.50% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3840-3843 13 0.02% 98.52% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::3904-3907 24 0.04% 98.57% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::3968-3971 13 0.02% 98.59% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4032-4035 11 0.02% 98.61% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4096-4099 19 0.04% 98.65% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4160-4163 10 0.02% 98.67% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4224-4227 13 0.02% 98.69% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4288-4291 7 0.01% 98.70% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4352-4355 9 0.02% 98.72% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4416-4419 11 0.02% 98.74% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4480-4483 7 0.01% 98.75% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4544-4547 9 0.02% 98.77% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4608-4611 9 0.02% 98.79% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4672-4675 4 0.01% 98.79% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4736-4739 10 0.02% 98.81% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4800-4803 9 0.02% 98.83% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4864-4867 7 0.01% 98.84% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::4928-4931 9 0.02% 98.86% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::4992-4995 7 0.01% 98.87% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5056-5059 5 0.01% 98.88% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5120-5123 13 0.02% 98.91% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5184-5187 8 0.01% 98.92% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5248-5251 7 0.01% 98.93% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5312-5315 8 0.01% 98.95% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5376-5379 10 0.02% 98.97% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5440-5443 5 0.01% 98.98% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5504-5507 9 0.02% 98.99% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5568-5571 151 0.28% 99.27% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5696-5699 1 0.00% 99.28% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5760-5763 1 0.00% 99.28% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5824-5827 2 0.00% 99.28% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6144-6147 1 0.00% 99.28% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6208-6211 3 0.01% 99.29% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6272-6275 2 0.00% 99.29% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6400-6403 1 0.00% 99.29% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6528-6531 2 0.00% 99.30% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6592-6595 4 0.01% 99.31% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6720-6723 1 0.00% 99.31% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6784-6787 1 0.00% 99.31% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6848-6851 5 0.01% 99.32% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6912-6915 4 0.01% 99.33% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7040-7043 2 0.00% 99.33% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7104-7107 1 0.00% 99.33% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7168-7171 19 0.04% 99.37% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7232-7235 4 0.01% 99.37% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7424-7427 1 0.00% 99.38% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7616-7619 2 0.00% 99.38% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7808-7811 1 0.00% 99.38% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7872-7875 4 0.01% 99.39% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::8064-8067 3 0.01% 99.39% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::8128-8131 2 0.00% 99.40% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::8192-8195 14 0.03% 99.42% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::8256-8259 2 0.00% 99.43% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.43% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::8512-8515 3 0.01% 99.44% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::8576-8579 1 0.00% 99.44% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::8768-8771 2 0.00% 99.44% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::9152-9155 2 0.00% 99.45% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::9216-9219 4 0.01% 99.45% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.45% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::9472-9475 1 0.00% 99.46% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::9536-9539 2 0.00% 99.46% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.46% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.46% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::10112-10115 1 0.00% 99.47% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::10176-10179 2 0.00% 99.47% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::10624-10627 1 0.00% 99.47% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::11136-11139 3 0.01% 99.48% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::11200-11203 1 0.00% 99.48% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::11264-11267 4 0.01% 99.49% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::11520-11523 1 0.00% 99.49% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::11904-11907 1 0.00% 99.49% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::12160-12163 1 0.00% 99.49% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::12224-12227 4 0.01% 99.50% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::12416-12419 2 0.00% 99.50% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::12480-12483 1 0.00% 99.50% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::12544-12547 2 0.00% 99.51% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::12608-12611 1 0.00% 99.51% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::12800-12803 1 0.00% 99.51% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::12864-12867 2 0.00% 99.52% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::13120-13123 1 0.00% 99.52% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::13248-13251 4 0.01% 99.53% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::13312-13315 6 0.01% 99.54% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::13632-13635 2 0.00% 99.54% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::13760-13763 2 0.00% 99.54% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::13824-13827 1 0.00% 99.55% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::13888-13891 2 0.00% 99.55% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.55% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::14208-14211 2 0.00% 99.56% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::14336-14339 1 0.00% 99.56% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::14400-14403 2 0.00% 99.56% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::14592-14595 2 0.00% 99.56% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::14848-14851 3 0.01% 99.57% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::14912-14915 7 0.01% 99.58% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::14976-14979 2 0.00% 99.59% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::15168-15171 2 0.00% 99.59% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::15232-15235 3 0.01% 99.60% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::15360-15363 32 0.06% 99.66% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::15680-15683 1 0.00% 99.66% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::15872-15875 3 0.01% 99.66% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.66% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::16064-16067 1 0.00% 99.67% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::16256-16259 1 0.00% 99.67% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::16384-16387 178 0.33% 100.00% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::total 53708 # Bytes accessed per row activation 344system.physmem.totQLat 5080719250 # Total ticks spent queuing 345system.physmem.totMemAccLat 8752324250 # Total ticks spent from burst creation until serviced by the DRAM 346system.physmem.totBusLat 991730000 # Total ticks spent in databus transfers 347system.physmem.totBankLat 2679875000 # Total ticks spent accessing banks 348system.physmem.avgQLat 25615.44 # Average queueing delay per DRAM burst 349system.physmem.avgBankLat 13511.11 # Average bank access latency per DRAM burst 350system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 351system.physmem.avgMemAccLat 44126.55 # Average memory access latency per DRAM burst 352system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s 353system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s 354system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s 355system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s 356system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 357system.physmem.busUtil 0.03 # Data bus utilization in percentage 358system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 359system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 360system.physmem.avgRdQLen 0.00 # Average read queue length when enqueuing 361system.physmem.avgWrQLen 8.98 # Average write queue length when enqueuing 362system.physmem.readRowHits 173438 # Number of row buffer hits during reads 363system.physmem.writeRowHits 97917 # Number of row buffer hits during writes 364system.physmem.readRowHitRate 87.44 # Row buffer hit rate for reads 365system.physmem.writeRowHitRate 77.26 # Row buffer hit rate for writes 366system.physmem.avgGap 15982155.57 # Average gap between requests 367system.physmem.pageHitRate 83.47 # Row buffer hit rate, read and write combined 368system.physmem.prechargeAllPercent 0.27 # Percentage of time for which DRAM has all the banks in precharge state 369system.membus.throughput 4365247 # Throughput (bytes/s) 370system.membus.trans_dist::ReadReq 623514 # Transaction distribution 371system.membus.trans_dist::ReadResp 623514 # Transaction distribution 372system.membus.trans_dist::WriteReq 13775 # Transaction distribution 373system.membus.trans_dist::WriteResp 13775 # Transaction distribution 374system.membus.trans_dist::Writeback 126733 # Transaction distribution 375system.membus.trans_dist::UpgradeReq 2150 # Transaction distribution 376system.membus.trans_dist::UpgradeResp 1634 # Transaction distribution 377system.membus.trans_dist::ReadExReq 159484 # Transaction distribution 378system.membus.trans_dist::ReadExResp 159484 # Transaction distribution 379system.membus.trans_dist::MessageReq 1655 # Transaction distribution 380system.membus.trans_dist::MessageResp 1655 # Transaction distribution 381system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3310 # Packet count per connected master and slave (bytes) 382system.membus.pkt_count_system.apicbridge.master::total 3310 # Packet count per connected master and slave (bytes) 383system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes) 384system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710114 # Packet count per connected master and slave (bytes) 385system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391174 # Packet count per connected master and slave (bytes) 386system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1581616 # Packet count per connected master and slave (bytes) 387system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139281 # Packet count per connected master and slave (bytes) 388system.membus.pkt_count_system.iocache.mem_side::total 139281 # Packet count per connected master and slave (bytes) 389system.membus.pkt_count::total 1724207 # Packet count per connected master and slave (bytes) 390system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6620 # Cumulative packet size per connected master and slave (bytes) 391system.membus.tot_pkt_size_system.apicbridge.master::total 6620 # Cumulative packet size per connected master and slave (bytes) 392system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes) 393system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420225 # Cumulative packet size per connected master and slave (bytes) 394system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14938368 # Cumulative packet size per connected master and slave (bytes) 395system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16605037 # Cumulative packet size per connected master and slave (bytes) 396system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5870400 # Cumulative packet size per connected master and slave (bytes) 397system.membus.tot_pkt_size_system.iocache.mem_side::total 5870400 # Cumulative packet size per connected master and slave (bytes) 398system.membus.tot_pkt_size::total 22482057 # Cumulative packet size per connected master and slave (bytes) 399system.membus.data_through_bus 22482057 # Total data (bytes) 400system.membus.snoop_data_through_bus 201472 # Total snoop data (bytes) 401system.membus.reqLayer0.occupancy 256796500 # Layer occupancy (ticks) 402system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 403system.membus.reqLayer1.occupancy 359316000 # Layer occupancy (ticks) 404system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 405system.membus.reqLayer2.occupancy 3310000 # Layer occupancy (ticks) 406system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 407system.membus.reqLayer3.occupancy 1352149000 # Layer occupancy (ticks) 408system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 409system.membus.respLayer0.occupancy 1655000 # Layer occupancy (ticks) 410system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 411system.membus.respLayer2.occupancy 2612327754 # Layer occupancy (ticks) 412system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 413system.membus.respLayer4.occupancy 428873750 # Layer occupancy (ticks) 414system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 415system.iocache.tags.replacements 47501 # number of replacements 416system.iocache.tags.tagsinuse 0.113099 # Cycle average of tags in use 417system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 418system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks. 419system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 420system.iocache.tags.warmup_cycle 5049776837000 # Cycle when the warmup percentage was hit. 421system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.113099 # Average occupied blocks per requestor 422system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007069 # Average percentage of cache occupancy 423system.iocache.tags.occ_percent::total 0.007069 # Average percentage of cache occupancy 424system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 425system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 426system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 427system.iocache.tags.tag_accesses 428004 # Number of tag accesses 428system.iocache.tags.data_accesses 428004 # Number of data accesses 429system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses 430system.iocache.ReadReq_misses::total 836 # number of ReadReq misses 431system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 432system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 433system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses 434system.iocache.demand_misses::total 47556 # number of demand (read+write) misses 435system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses 436system.iocache.overall_misses::total 47556 # number of overall misses 437system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144134686 # number of ReadReq miss cycles 438system.iocache.ReadReq_miss_latency::total 144134686 # number of ReadReq miss cycles 439system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12487439330 # number of WriteReq miss cycles 440system.iocache.WriteReq_miss_latency::total 12487439330 # number of WriteReq miss cycles 441system.iocache.demand_miss_latency::pc.south_bridge.ide 12631574016 # number of demand (read+write) miss cycles 442system.iocache.demand_miss_latency::total 12631574016 # number of demand (read+write) miss cycles 443system.iocache.overall_miss_latency::pc.south_bridge.ide 12631574016 # number of overall miss cycles 444system.iocache.overall_miss_latency::total 12631574016 # number of overall miss cycles 445system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses) 446system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses) 447system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 448system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 449system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses 450system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses 451system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses 452system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses 453system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 454system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 455system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 456system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 457system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 458system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 459system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 460system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 461system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 172409.911483 # average ReadReq miss latency 462system.iocache.ReadReq_avg_miss_latency::total 172409.911483 # average ReadReq miss latency 463system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 267282.519906 # average WriteReq miss latency 464system.iocache.WriteReq_avg_miss_latency::total 267282.519906 # average WriteReq miss latency 465system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency 466system.iocache.demand_avg_miss_latency::total 265614.728236 # average overall miss latency 467system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 265614.728236 # average overall miss latency 468system.iocache.overall_avg_miss_latency::total 265614.728236 # average overall miss latency 469system.iocache.blocked_cycles::no_mshrs 216457 # number of cycles access was blocked 470system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 471system.iocache.blocked::no_mshrs 11594 # number of cycles access was blocked 472system.iocache.blocked::no_targets 0 # number of cycles access was blocked 473system.iocache.avg_blocked_cycles::no_mshrs 18.669743 # average number of cycles each access was blocked 474system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 475system.iocache.fast_writes 0 # number of fast writes performed 476system.iocache.cache_copies 0 # number of cache copies performed 477system.iocache.writebacks::writebacks 46667 # number of writebacks 478system.iocache.writebacks::total 46667 # number of writebacks 479system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses 480system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses 481system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 482system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 483system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses 484system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses 485system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses 486system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses 487system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100637686 # number of ReadReq MSHR miss cycles 488system.iocache.ReadReq_mshr_miss_latency::total 100637686 # number of ReadReq MSHR miss cycles 489system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 10056284830 # number of WriteReq MSHR miss cycles 490system.iocache.WriteReq_mshr_miss_latency::total 10056284830 # number of WriteReq MSHR miss cycles 491system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of demand (read+write) MSHR miss cycles 492system.iocache.demand_mshr_miss_latency::total 10156922516 # number of demand (read+write) MSHR miss cycles 493system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 10156922516 # number of overall MSHR miss cycles 494system.iocache.overall_mshr_miss_latency::total 10156922516 # number of overall MSHR miss cycles 495system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 496system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 497system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 498system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 499system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 500system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 501system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 502system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 503system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 120380.007177 # average ReadReq mshr miss latency 504system.iocache.ReadReq_avg_mshr_miss_latency::total 120380.007177 # average ReadReq mshr miss latency 505system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 215245.822560 # average WriteReq mshr miss latency 506system.iocache.WriteReq_avg_mshr_miss_latency::total 215245.822560 # average WriteReq mshr miss latency 507system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency 508system.iocache.demand_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency 509system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 213578.150307 # average overall mshr miss latency 510system.iocache.overall_avg_mshr_miss_latency::total 213578.150307 # average overall mshr miss latency 511system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 512system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 513system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 514system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 515system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 516system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 517system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 518system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 519system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 520system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 521system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 522system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 523system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 524system.iobus.throughput 631264 # Throughput (bytes/s) 525system.iobus.trans_dist::ReadReq 230141 # Transaction distribution 526system.iobus.trans_dist::ReadResp 230141 # Transaction distribution 527system.iobus.trans_dist::WriteReq 57579 # Transaction distribution 528system.iobus.trans_dist::WriteResp 57579 # Transaction distribution 529system.iobus.trans_dist::MessageReq 1655 # Transaction distribution 530system.iobus.trans_dist::MessageResp 1655 # Transaction distribution 531system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 532system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 533system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 534system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 535system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 536system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 537system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 538system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 539system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) 540system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 541system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 542system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 543system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes) 544system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 545system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 546system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 547system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 548system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 549system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes) 550system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes) 551system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes) 552system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3310 # Packet count per connected master and slave (bytes) 553system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3310 # Packet count per connected master and slave (bytes) 554system.iobus.pkt_count::total 578750 # Packet count per connected master and slave (bytes) 555system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 556system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 557system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 558system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 559system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 560system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 561system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 562system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 563system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) 564system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 565system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 566system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 567system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) 568system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 569system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 570system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 571system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 572system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 573system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes) 574system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes) 575system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes) 576system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6620 # Cumulative packet size per connected master and slave (bytes) 577system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6620 # Cumulative packet size per connected master and slave (bytes) 578system.iobus.tot_pkt_size::total 3280296 # Cumulative packet size per connected master and slave (bytes) 579system.iobus.data_through_bus 3280296 # Total data (bytes) 580system.iobus.reqLayer0.occupancy 3948164 # Layer occupancy (ticks) 581system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 582system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 583system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 584system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 585system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 586system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks) 587system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 588system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 589system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 590system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 591system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 592system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks) 593system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 594system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 595system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 596system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 597system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 598system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) 599system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 600system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 601system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 602system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 603system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 604system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) 605system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) 606system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks) 607system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 608system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 609system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 610system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 611system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 612system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 613system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 614system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 615system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 616system.iobus.reqLayer18.occupancy 424033266 # Layer occupancy (ticks) 617system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 618system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) 619system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 620system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks) 621system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 622system.iobus.respLayer1.occupancy 52989250 # Layer occupancy (ticks) 623system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 624system.iobus.respLayer2.occupancy 1655000 # Layer occupancy (ticks) 625system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 626system.cpu_clk_domain.clock 500 # Clock period in ticks 627system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 628system.cpu.numCycles 10392780360 # number of cpu cycles simulated 629system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 630system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 631system.cpu.committedInsts 128334813 # Number of instructions committed 632system.cpu.committedOps 247385808 # Number of ops (including micro ops) committed 633system.cpu.num_int_alu_accesses 231978567 # Number of integer alu accesses 634system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 635system.cpu.num_func_calls 2299773 # number of times a function call or return occured 636system.cpu.num_conditional_control_insts 23169265 # number of instructions that are conditional controls 637system.cpu.num_int_insts 231978567 # number of integer instructions 638system.cpu.num_fp_insts 0 # number of float instructions 639system.cpu.num_int_register_reads 434513747 # number of times the integer registers were read 640system.cpu.num_int_register_writes 197852200 # number of times the integer registers were written 641system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 642system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 643system.cpu.num_cc_register_reads 132813019 # number of times the CC registers were read 644system.cpu.num_cc_register_writes 95534921 # number of times the CC registers were written 645system.cpu.num_mem_refs 22245363 # number of memory refs 646system.cpu.num_load_insts 13878746 # Number of load instructions 647system.cpu.num_store_insts 8366617 # Number of store instructions 648system.cpu.num_idle_cycles 9785238216.998117 # Number of idle cycles 649system.cpu.num_busy_cycles 607542143.001883 # Number of busy cycles 650system.cpu.not_idle_fraction 0.058458 # Percentage of non-idle cycles 651system.cpu.idle_fraction 0.941542 # Percentage of idle cycles
	652system.cpu.Branches 26307103 # Number of branches fetched
652system.cpu.kern.inst.arm 0 # number of arm instructions executed 653system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 654system.cpu.icache.tags.replacements 788090 # number of replacements 655system.cpu.icache.tags.tagsinuse 510.351939 # Cycle average of tags in use 656system.cpu.icache.tags.total_refs 144584753 # Total number of references to valid blocks. 657system.cpu.icache.tags.sampled_refs 788602 # Sample count of references to valid blocks. 658system.cpu.icache.tags.avg_refs 183.343122 # Average number of references to valid blocks. 659system.cpu.icache.tags.warmup_cycle 161436066250 # Cycle when the warmup percentage was hit. 660system.cpu.icache.tags.occ_blocks::cpu.inst 510.351939 # Average occupied blocks per requestor 661system.cpu.icache.tags.occ_percent::cpu.inst 0.996781 # Average percentage of cache occupancy 662system.cpu.icache.tags.occ_percent::total 0.996781 # Average percentage of cache occupancy 663system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 664system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 665system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id 666system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id 667system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 668system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 669system.cpu.icache.tags.tag_accesses 146161971 # Number of tag accesses 670system.cpu.icache.tags.data_accesses 146161971 # Number of data accesses 671system.cpu.icache.ReadReq_hits::cpu.inst 144584753 # number of ReadReq hits 672system.cpu.icache.ReadReq_hits::total 144584753 # number of ReadReq hits 673system.cpu.icache.demand_hits::cpu.inst 144584753 # number of demand (read+write) hits 674system.cpu.icache.demand_hits::total 144584753 # number of demand (read+write) hits 675system.cpu.icache.overall_hits::cpu.inst 144584753 # number of overall hits 676system.cpu.icache.overall_hits::total 144584753 # number of overall hits 677system.cpu.icache.ReadReq_misses::cpu.inst 788609 # number of ReadReq misses 678system.cpu.icache.ReadReq_misses::total 788609 # number of ReadReq misses 679system.cpu.icache.demand_misses::cpu.inst 788609 # number of demand (read+write) misses 680system.cpu.icache.demand_misses::total 788609 # number of demand (read+write) misses 681system.cpu.icache.overall_misses::cpu.inst 788609 # number of overall misses 682system.cpu.icache.overall_misses::total 788609 # number of overall misses 683system.cpu.icache.ReadReq_miss_latency::cpu.inst 11107362758 # number of ReadReq miss cycles 684system.cpu.icache.ReadReq_miss_latency::total 11107362758 # number of ReadReq miss cycles 685system.cpu.icache.demand_miss_latency::cpu.inst 11107362758 # number of demand (read+write) miss cycles 686system.cpu.icache.demand_miss_latency::total 11107362758 # number of demand (read+write) miss cycles 687system.cpu.icache.overall_miss_latency::cpu.inst 11107362758 # number of overall miss cycles 688system.cpu.icache.overall_miss_latency::total 11107362758 # number of overall miss cycles 689system.cpu.icache.ReadReq_accesses::cpu.inst 145373362 # number of ReadReq accesses(hits+misses) 690system.cpu.icache.ReadReq_accesses::total 145373362 # number of ReadReq accesses(hits+misses) 691system.cpu.icache.demand_accesses::cpu.inst 145373362 # number of demand (read+write) accesses 692system.cpu.icache.demand_accesses::total 145373362 # number of demand (read+write) accesses 693system.cpu.icache.overall_accesses::cpu.inst 145373362 # number of overall (read+write) accesses 694system.cpu.icache.overall_accesses::total 145373362 # number of overall (read+write) accesses 695system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005425 # miss rate for ReadReq accesses 696system.cpu.icache.ReadReq_miss_rate::total 0.005425 # miss rate for ReadReq accesses 697system.cpu.icache.demand_miss_rate::cpu.inst 0.005425 # miss rate for demand accesses 698system.cpu.icache.demand_miss_rate::total 0.005425 # miss rate for demand accesses 699system.cpu.icache.overall_miss_rate::cpu.inst 0.005425 # miss rate for overall accesses 700system.cpu.icache.overall_miss_rate::total 0.005425 # miss rate for overall accesses 701system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14084.752720 # average ReadReq miss latency 702system.cpu.icache.ReadReq_avg_miss_latency::total 14084.752720 # average ReadReq miss latency 703system.cpu.icache.demand_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency 704system.cpu.icache.demand_avg_miss_latency::total 14084.752720 # average overall miss latency 705system.cpu.icache.overall_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency 706system.cpu.icache.overall_avg_miss_latency::total 14084.752720 # average overall miss latency 707system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 708system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 709system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 710system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 711system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 712system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 713system.cpu.icache.fast_writes 0 # number of fast writes performed 714system.cpu.icache.cache_copies 0 # number of cache copies performed 715system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788609 # number of ReadReq MSHR misses 716system.cpu.icache.ReadReq_mshr_misses::total 788609 # number of ReadReq MSHR misses 717system.cpu.icache.demand_mshr_misses::cpu.inst 788609 # number of demand (read+write) MSHR misses 718system.cpu.icache.demand_mshr_misses::total 788609 # number of demand (read+write) MSHR misses 719system.cpu.icache.overall_mshr_misses::cpu.inst 788609 # number of overall MSHR misses 720system.cpu.icache.overall_mshr_misses::total 788609 # number of overall MSHR misses 721system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9525299242 # number of ReadReq MSHR miss cycles 722system.cpu.icache.ReadReq_mshr_miss_latency::total 9525299242 # number of ReadReq MSHR miss cycles 723system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9525299242 # number of demand (read+write) MSHR miss cycles 724system.cpu.icache.demand_mshr_miss_latency::total 9525299242 # number of demand (read+write) MSHR miss cycles 725system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9525299242 # number of overall MSHR miss cycles 726system.cpu.icache.overall_mshr_miss_latency::total 9525299242 # number of overall MSHR miss cycles 727system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for ReadReq accesses 728system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005425 # mshr miss rate for ReadReq accesses 729system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for demand accesses 730system.cpu.icache.demand_mshr_miss_rate::total 0.005425 # mshr miss rate for demand accesses 731system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for overall accesses 732system.cpu.icache.overall_mshr_miss_rate::total 0.005425 # mshr miss rate for overall accesses 733system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12078.608337 # average ReadReq mshr miss latency 734system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12078.608337 # average ReadReq mshr miss latency 735system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency 736system.cpu.icache.demand_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency 737system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency 738system.cpu.icache.overall_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency 739system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 740system.cpu.itb_walker_cache.tags.replacements 3741 # number of replacements 741system.cpu.itb_walker_cache.tags.tagsinuse 3.069761 # Cycle average of tags in use 742system.cpu.itb_walker_cache.tags.total_refs 7617 # Total number of references to valid blocks. 743system.cpu.itb_walker_cache.tags.sampled_refs 3752 # Sample count of references to valid blocks. 744system.cpu.itb_walker_cache.tags.avg_refs 2.030117 # Average number of references to valid blocks. 745system.cpu.itb_walker_cache.tags.warmup_cycle 5169682535000 # Cycle when the warmup percentage was hit. 746system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069761 # Average occupied blocks per requestor 747system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191860 # Average percentage of cache occupancy 748system.cpu.itb_walker_cache.tags.occ_percent::total 0.191860 # Average percentage of cache occupancy 749system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id 750system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 751system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 752system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 753system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 754system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id 755system.cpu.itb_walker_cache.tags.tag_accesses 29050 # Number of tag accesses 756system.cpu.itb_walker_cache.tags.data_accesses 29050 # Number of data accesses 757system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7617 # number of ReadReq hits 758system.cpu.itb_walker_cache.ReadReq_hits::total 7617 # number of ReadReq hits 759system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 760system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 761system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7619 # number of demand (read+write) hits 762system.cpu.itb_walker_cache.demand_hits::total 7619 # number of demand (read+write) hits 763system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7619 # number of overall hits 764system.cpu.itb_walker_cache.overall_hits::total 7619 # number of overall hits 765system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4604 # number of ReadReq misses 766system.cpu.itb_walker_cache.ReadReq_misses::total 4604 # number of ReadReq misses 767system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4604 # number of demand (read+write) misses 768system.cpu.itb_walker_cache.demand_misses::total 4604 # number of demand (read+write) misses 769system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4604 # number of overall misses 770system.cpu.itb_walker_cache.overall_misses::total 4604 # number of overall misses 771system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44886750 # number of ReadReq miss cycles 772system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44886750 # number of ReadReq miss cycles 773system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44886750 # number of demand (read+write) miss cycles 774system.cpu.itb_walker_cache.demand_miss_latency::total 44886750 # number of demand (read+write) miss cycles 775system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44886750 # number of overall miss cycles 776system.cpu.itb_walker_cache.overall_miss_latency::total 44886750 # number of overall miss cycles 777system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) 778system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) 779system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 780system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 781system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses 782system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses 783system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses 784system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses 785system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376729 # miss rate for ReadReq accesses 786system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376729 # miss rate for ReadReq accesses 787system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376667 # miss rate for demand accesses 788system.cpu.itb_walker_cache.demand_miss_rate::total 0.376667 # miss rate for demand accesses 789system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376667 # miss rate for overall accesses 790system.cpu.itb_walker_cache.overall_miss_rate::total 0.376667 # miss rate for overall accesses 791system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9749.511295 # average ReadReq miss latency 792system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9749.511295 # average ReadReq miss latency 793system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency 794system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9749.511295 # average overall miss latency 795system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency 796system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9749.511295 # average overall miss latency 797system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 798system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 799system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 800system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 801system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 802system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 803system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 804system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 805system.cpu.itb_walker_cache.writebacks::writebacks 621 # number of writebacks 806system.cpu.itb_walker_cache.writebacks::total 621 # number of writebacks 807system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4604 # number of ReadReq MSHR misses 808system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4604 # number of ReadReq MSHR misses 809system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4604 # number of demand (read+write) MSHR misses 810system.cpu.itb_walker_cache.demand_mshr_misses::total 4604 # number of demand (read+write) MSHR misses 811system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4604 # number of overall MSHR misses 812system.cpu.itb_walker_cache.overall_mshr_misses::total 4604 # number of overall MSHR misses 813system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35677750 # number of ReadReq MSHR miss cycles 814system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35677750 # number of ReadReq MSHR miss cycles 815system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35677750 # number of demand (read+write) MSHR miss cycles 816system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35677750 # number of demand (read+write) MSHR miss cycles 817system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35677750 # number of overall MSHR miss cycles 818system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35677750 # number of overall MSHR miss cycles 819system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376729 # mshr miss rate for ReadReq accesses 820system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376729 # mshr miss rate for ReadReq accesses 821system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for demand accesses 822system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376667 # mshr miss rate for demand accesses 823system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for overall accesses 824system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376667 # mshr miss rate for overall accesses 825system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average ReadReq mshr miss latency 826system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7749.294092 # average ReadReq mshr miss latency 827system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency 828system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency 829system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency 830system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency 831system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 832system.cpu.dtb_walker_cache.tags.replacements 7948 # number of replacements 833system.cpu.dtb_walker_cache.tags.tagsinuse 5.052475 # Cycle average of tags in use 834system.cpu.dtb_walker_cache.tags.total_refs 12793 # Total number of references to valid blocks. 835system.cpu.dtb_walker_cache.tags.sampled_refs 7961 # Sample count of references to valid blocks. 836system.cpu.dtb_walker_cache.tags.avg_refs 1.606959 # Average number of references to valid blocks. 837system.cpu.dtb_walker_cache.tags.warmup_cycle 5168018375000 # Cycle when the warmup percentage was hit. 838system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052475 # Average occupied blocks per requestor 839system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315780 # Average percentage of cache occupancy 840system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315780 # Average percentage of cache occupancy 841system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 842system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 843system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 844system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 845system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 846system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 847system.cpu.dtb_walker_cache.tags.tag_accesses 53026 # Number of tag accesses 848system.cpu.dtb_walker_cache.tags.data_accesses 53026 # Number of data accesses 849system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12806 # number of ReadReq hits 850system.cpu.dtb_walker_cache.ReadReq_hits::total 12806 # number of ReadReq hits 851system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12806 # number of demand (read+write) hits 852system.cpu.dtb_walker_cache.demand_hits::total 12806 # number of demand (read+write) hits 853system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12806 # number of overall hits 854system.cpu.dtb_walker_cache.overall_hits::total 12806 # number of overall hits 855system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9138 # number of ReadReq misses 856system.cpu.dtb_walker_cache.ReadReq_misses::total 9138 # number of ReadReq misses 857system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9138 # number of demand (read+write) misses 858system.cpu.dtb_walker_cache.demand_misses::total 9138 # number of demand (read+write) misses 859system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9138 # number of overall misses 860system.cpu.dtb_walker_cache.overall_misses::total 9138 # number of overall misses 861system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97347500 # number of ReadReq miss cycles 862system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97347500 # number of ReadReq miss cycles 863system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97347500 # number of demand (read+write) miss cycles 864system.cpu.dtb_walker_cache.demand_miss_latency::total 97347500 # number of demand (read+write) miss cycles 865system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97347500 # number of overall miss cycles 866system.cpu.dtb_walker_cache.overall_miss_latency::total 97347500 # number of overall miss cycles 867system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21944 # number of ReadReq accesses(hits+misses) 868system.cpu.dtb_walker_cache.ReadReq_accesses::total 21944 # number of ReadReq accesses(hits+misses) 869system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21944 # number of demand (read+write) accesses 870system.cpu.dtb_walker_cache.demand_accesses::total 21944 # number of demand (read+write) accesses 871system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21944 # number of overall (read+write) accesses 872system.cpu.dtb_walker_cache.overall_accesses::total 21944 # number of overall (read+write) accesses 873system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.416424 # miss rate for ReadReq accesses 874system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.416424 # miss rate for ReadReq accesses 875system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.416424 # miss rate for demand accesses 876system.cpu.dtb_walker_cache.demand_miss_rate::total 0.416424 # miss rate for demand accesses 877system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.416424 # miss rate for overall accesses 878system.cpu.dtb_walker_cache.overall_miss_rate::total 0.416424 # miss rate for overall accesses 879system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10653.042241 # average ReadReq miss latency 880system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10653.042241 # average ReadReq miss latency 881system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency 882system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10653.042241 # average overall miss latency 883system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency 884system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10653.042241 # average overall miss latency 885system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 886system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 887system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 888system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 889system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 890system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 891system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 892system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 893system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks 894system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks 895system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9138 # number of ReadReq MSHR misses 896system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9138 # number of ReadReq MSHR misses 897system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9138 # number of demand (read+write) MSHR misses 898system.cpu.dtb_walker_cache.demand_mshr_misses::total 9138 # number of demand (read+write) MSHR misses 899system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9138 # number of overall MSHR misses 900system.cpu.dtb_walker_cache.overall_mshr_misses::total 9138 # number of overall MSHR misses 901system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 79071000 # number of ReadReq MSHR miss cycles 902system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 79071000 # number of ReadReq MSHR miss cycles 903system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 79071000 # number of demand (read+write) MSHR miss cycles 904system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 79071000 # number of demand (read+write) MSHR miss cycles 905system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 79071000 # number of overall MSHR miss cycles 906system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 79071000 # number of overall MSHR miss cycles 907system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for ReadReq accesses 908system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.416424 # mshr miss rate for ReadReq accesses 909system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for demand accesses 910system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.416424 # mshr miss rate for demand accesses 911system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for overall accesses 912system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.416424 # mshr miss rate for overall accesses 913system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average ReadReq mshr miss latency 914system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8652.987525 # average ReadReq mshr miss latency 915system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average overall mshr miss latency 916system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8652.987525 # average overall mshr miss latency 917system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average overall mshr miss latency 918system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8652.987525 # average overall mshr miss latency 919system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 920system.cpu.dcache.tags.replacements 1621547 # number of replacements 921system.cpu.dcache.tags.tagsinuse 511.997026 # Cycle average of tags in use 922system.cpu.dcache.tags.total_refs 20035701 # Total number of references to valid blocks. 923system.cpu.dcache.tags.sampled_refs 1622059 # Sample count of references to valid blocks. 924system.cpu.dcache.tags.avg_refs 12.352017 # Average number of references to valid blocks. 925system.cpu.dcache.tags.warmup_cycle 50992250 # Cycle when the warmup percentage was hit. 926system.cpu.dcache.tags.occ_blocks::cpu.data 511.997026 # Average occupied blocks per requestor 927system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 928system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 929system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 930system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 931system.cpu.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 932system.cpu.dcache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 933system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 934system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 935system.cpu.dcache.tags.tag_accesses 88253354 # Number of tag accesses 936system.cpu.dcache.tags.data_accesses 88253354 # Number of data accesses 937system.cpu.dcache.ReadReq_hits::cpu.data 11993197 # number of ReadReq hits 938system.cpu.dcache.ReadReq_hits::total 11993197 # number of ReadReq hits 939system.cpu.dcache.WriteReq_hits::cpu.data 8040328 # number of WriteReq hits 940system.cpu.dcache.WriteReq_hits::total 8040328 # number of WriteReq hits 941system.cpu.dcache.demand_hits::cpu.data 20033525 # number of demand (read+write) hits 942system.cpu.dcache.demand_hits::total 20033525 # number of demand (read+write) hits 943system.cpu.dcache.overall_hits::cpu.data 20033525 # number of overall hits 944system.cpu.dcache.overall_hits::total 20033525 # number of overall hits 945system.cpu.dcache.ReadReq_misses::cpu.data 1308312 # number of ReadReq misses 946system.cpu.dcache.ReadReq_misses::total 1308312 # number of ReadReq misses 947system.cpu.dcache.WriteReq_misses::cpu.data 315974 # number of WriteReq misses 948system.cpu.dcache.WriteReq_misses::total 315974 # number of WriteReq misses 949system.cpu.dcache.demand_misses::cpu.data 1624286 # number of demand (read+write) misses 950system.cpu.dcache.demand_misses::total 1624286 # number of demand (read+write) misses 951system.cpu.dcache.overall_misses::cpu.data 1624286 # number of overall misses 952system.cpu.dcache.overall_misses::total 1624286 # number of overall misses 953system.cpu.dcache.ReadReq_miss_latency::cpu.data 18913909300 # number of ReadReq miss cycles 954system.cpu.dcache.ReadReq_miss_latency::total 18913909300 # number of ReadReq miss cycles 955system.cpu.dcache.WriteReq_miss_latency::cpu.data 11002078938 # number of WriteReq miss cycles 956system.cpu.dcache.WriteReq_miss_latency::total 11002078938 # number of WriteReq miss cycles 957system.cpu.dcache.demand_miss_latency::cpu.data 29915988238 # number of demand (read+write) miss cycles 958system.cpu.dcache.demand_miss_latency::total 29915988238 # number of demand (read+write) miss cycles 959system.cpu.dcache.overall_miss_latency::cpu.data 29915988238 # number of overall miss cycles 960system.cpu.dcache.overall_miss_latency::total 29915988238 # number of overall miss cycles 961system.cpu.dcache.ReadReq_accesses::cpu.data 13301509 # number of ReadReq accesses(hits+misses) 962system.cpu.dcache.ReadReq_accesses::total 13301509 # number of ReadReq accesses(hits+misses) 963system.cpu.dcache.WriteReq_accesses::cpu.data 8356302 # number of WriteReq accesses(hits+misses) 964system.cpu.dcache.WriteReq_accesses::total 8356302 # number of WriteReq accesses(hits+misses) 965system.cpu.dcache.demand_accesses::cpu.data 21657811 # number of demand (read+write) accesses 966system.cpu.dcache.demand_accesses::total 21657811 # number of demand (read+write) accesses 967system.cpu.dcache.overall_accesses::cpu.data 21657811 # number of overall (read+write) accesses 968system.cpu.dcache.overall_accesses::total 21657811 # number of overall (read+write) accesses 969system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098358 # miss rate for ReadReq accesses 970system.cpu.dcache.ReadReq_miss_rate::total 0.098358 # miss rate for ReadReq accesses 971system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses 972system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses 973system.cpu.dcache.demand_miss_rate::cpu.data 0.074998 # miss rate for demand accesses 974system.cpu.dcache.demand_miss_rate::total 0.074998 # miss rate for demand accesses 975system.cpu.dcache.overall_miss_rate::cpu.data 0.074998 # miss rate for overall accesses 976system.cpu.dcache.overall_miss_rate::total 0.074998 # miss rate for overall accesses 977system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14456.726912 # average ReadReq miss latency 978system.cpu.dcache.ReadReq_avg_miss_latency::total 14456.726912 # average ReadReq miss latency 979system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34819.570401 # average WriteReq miss latency 980system.cpu.dcache.WriteReq_avg_miss_latency::total 34819.570401 # average WriteReq miss latency 981system.cpu.dcache.demand_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency 982system.cpu.dcache.demand_avg_miss_latency::total 18417.931471 # average overall miss latency 983system.cpu.dcache.overall_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency 984system.cpu.dcache.overall_avg_miss_latency::total 18417.931471 # average overall miss latency 985system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 986system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 987system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 988system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 989system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 990system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 991system.cpu.dcache.fast_writes 0 # number of fast writes performed 992system.cpu.dcache.cache_copies 0 # number of cache copies performed 993system.cpu.dcache.writebacks::writebacks 1538973 # number of writebacks 994system.cpu.dcache.writebacks::total 1538973 # number of writebacks 995system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308312 # number of ReadReq MSHR misses 996system.cpu.dcache.ReadReq_mshr_misses::total 1308312 # number of ReadReq MSHR misses 997system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315974 # number of WriteReq MSHR misses 998system.cpu.dcache.WriteReq_mshr_misses::total 315974 # number of WriteReq MSHR misses 999system.cpu.dcache.demand_mshr_misses::cpu.data 1624286 # number of demand (read+write) MSHR misses 1000system.cpu.dcache.demand_mshr_misses::total 1624286 # number of demand (read+write) MSHR misses 1001system.cpu.dcache.overall_mshr_misses::cpu.data 1624286 # number of overall MSHR misses 1002system.cpu.dcache.overall_mshr_misses::total 1624286 # number of overall MSHR misses 1003system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16288101700 # number of ReadReq MSHR miss cycles 1004system.cpu.dcache.ReadReq_mshr_miss_latency::total 16288101700 # number of ReadReq MSHR miss cycles 1005system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10316379062 # number of WriteReq MSHR miss cycles 1006system.cpu.dcache.WriteReq_mshr_miss_latency::total 10316379062 # number of WriteReq MSHR miss cycles 1007system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26604480762 # number of demand (read+write) MSHR miss cycles 1008system.cpu.dcache.demand_mshr_miss_latency::total 26604480762 # number of demand (read+write) MSHR miss cycles 1009system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26604480762 # number of overall MSHR miss cycles 1010system.cpu.dcache.overall_mshr_miss_latency::total 26604480762 # number of overall MSHR miss cycles 1011system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214673000 # number of ReadReq MSHR uncacheable cycles 1012system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214673000 # number of ReadReq MSHR uncacheable cycles 1013system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537491500 # number of WriteReq MSHR uncacheable cycles 1014system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537491500 # number of WriteReq MSHR uncacheable cycles 1015system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752164500 # number of overall MSHR uncacheable cycles 1016system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752164500 # number of overall MSHR uncacheable cycles 1017system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098358 # mshr miss rate for ReadReq accesses 1018system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098358 # mshr miss rate for ReadReq accesses 1019system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037813 # mshr miss rate for WriteReq accesses 1020system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037813 # mshr miss rate for WriteReq accesses 1021system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for demand accesses 1022system.cpu.dcache.demand_mshr_miss_rate::total 0.074998 # mshr miss rate for demand accesses 1023system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for overall accesses 1024system.cpu.dcache.overall_mshr_miss_rate::total 0.074998 # mshr miss rate for overall accesses 1025system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12449.707486 # average ReadReq mshr miss latency 1026system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12449.707486 # average ReadReq mshr miss latency 1027system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32649.455531 # average WriteReq mshr miss latency 1028system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32649.455531 # average WriteReq mshr miss latency 1029system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency 1030system.cpu.dcache.demand_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency 1031system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency 1032system.cpu.dcache.overall_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency 1033system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1034system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1035system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1036system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1037system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1038system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1039system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1040system.cpu.toL2Bus.throughput 49185341 # Throughput (bytes/s) 1041system.cpu.toL2Bus.trans_dist::ReadReq 2692945 # Transaction distribution 1042system.cpu.toL2Bus.trans_dist::ReadResp 2692419 # Transaction distribution 1043system.cpu.toL2Bus.trans_dist::WriteReq 13775 # Transaction distribution 1044system.cpu.toL2Bus.trans_dist::WriteResp 13775 # Transaction distribution 1045system.cpu.toL2Bus.trans_dist::Writeback 1542700 # Transaction distribution 1046system.cpu.toL2Bus.trans_dist::UpgradeReq 2176 # Transaction distribution 1047system.cpu.toL2Bus.trans_dist::UpgradeResp 2176 # Transaction distribution 1048system.cpu.toL2Bus.trans_dist::ReadExReq 360518 # Transaction distribution 1049system.cpu.toL2Bus.trans_dist::ReadExResp 313820 # Transaction distribution 1050system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1577205 # Packet count per connected master and slave (bytes) 1051system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5977035 # Packet count per connected master and slave (bytes) 1052system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8133 # Packet count per connected master and slave (bytes) 1053system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18986 # Packet count per connected master and slave (bytes) 1054system.cpu.toL2Bus.pkt_count::total 7581359 # Packet count per connected master and slave (bytes) 1055system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50470144 # Cumulative packet size per connected master and slave (bytes) 1056system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203948077 # Cumulative packet size per connected master and slave (bytes) 1057system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 225856 # Cumulative packet size per connected master and slave (bytes) 1058system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 630272 # Cumulative packet size per connected master and slave (bytes) 1059system.cpu.toL2Bus.tot_pkt_size::total 255274349 # Cumulative packet size per connected master and slave (bytes) 1060system.cpu.toL2Bus.data_through_bus 255253101 # Total data (bytes) 1061system.cpu.toL2Bus.snoop_data_through_bus 333120 # Total snoop data (bytes) 1062system.cpu.toL2Bus.reqLayer0.occupancy 3831866500 # Layer occupancy (ticks) 1063system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1064system.cpu.toL2Bus.snoopLayer0.occupancy 498000 # Layer occupancy (ticks) 1065system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1066system.cpu.toL2Bus.respLayer0.occupancy 1185336258 # Layer occupancy (ticks) 1067system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1068system.cpu.toL2Bus.respLayer1.occupancy 3054054238 # Layer occupancy (ticks) 1069system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1070system.cpu.toL2Bus.respLayer2.occupancy 6906500 # Layer occupancy (ticks) 1071system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1072system.cpu.toL2Bus.respLayer3.occupancy 13707250 # Layer occupancy (ticks) 1073system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1074system.cpu.l2cache.tags.replacements 86910 # number of replacements 1075system.cpu.l2cache.tags.tagsinuse 64731.196890 # Cycle average of tags in use 1076system.cpu.l2cache.tags.total_refs 3488433 # Total number of references to valid blocks. 1077system.cpu.l2cache.tags.sampled_refs 151626 # Sample count of references to valid blocks. 1078system.cpu.l2cache.tags.avg_refs 23.006826 # Average number of references to valid blocks. 1079system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1080system.cpu.l2cache.tags.occ_blocks::writebacks 50120.476905 # Average occupied blocks per requestor 1081system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.033461 # Average occupied blocks per requestor 1082system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141258 # Average occupied blocks per requestor 1083system.cpu.l2cache.tags.occ_blocks::cpu.inst 3445.447212 # Average occupied blocks per requestor 1084system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.098054 # Average occupied blocks per requestor 1085system.cpu.l2cache.tags.occ_percent::writebacks 0.764778 # Average percentage of cache occupancy 1086system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000001 # Average percentage of cache occupancy 1087system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 1088system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052573 # Average percentage of cache occupancy 1089system.cpu.l2cache.tags.occ_percent::cpu.data 0.170366 # Average percentage of cache occupancy 1090system.cpu.l2cache.tags.occ_percent::total 0.987720 # Average percentage of cache occupancy 1091system.cpu.l2cache.tags.occ_task_id_blocks::1024 64716 # Occupied blocks per task id 1092system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 1093system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 1094system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2864 # Occupied blocks per task id 1095system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4951 # Occupied blocks per task id 1096system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56789 # Occupied blocks per task id 1097system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987488 # Percentage of cache occupancy per task id 1098system.cpu.l2cache.tags.tag_accesses 32180081 # Number of tag accesses 1099system.cpu.l2cache.tags.data_accesses 32180081 # Number of data accesses 1100system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6740 # number of ReadReq hits 1101system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2903 # number of ReadReq hits 1102system.cpu.l2cache.ReadReq_hits::cpu.inst 775712 # number of ReadReq hits 1103system.cpu.l2cache.ReadReq_hits::cpu.data 1279207 # number of ReadReq hits 1104system.cpu.l2cache.ReadReq_hits::total 2064562 # number of ReadReq hits 1105system.cpu.l2cache.Writeback_hits::writebacks 1542700 # number of Writeback hits 1106system.cpu.l2cache.Writeback_hits::total 1542700 # number of Writeback hits 1107system.cpu.l2cache.UpgradeReq_hits::cpu.data 304 # number of UpgradeReq hits 1108system.cpu.l2cache.UpgradeReq_hits::total 304 # number of UpgradeReq hits 1109system.cpu.l2cache.ReadExReq_hits::cpu.data 200752 # number of ReadExReq hits 1110system.cpu.l2cache.ReadExReq_hits::total 200752 # number of ReadExReq hits 1111system.cpu.l2cache.demand_hits::cpu.dtb.walker 6740 # number of demand (read+write) hits 1112system.cpu.l2cache.demand_hits::cpu.itb.walker 2903 # number of demand (read+write) hits 1113system.cpu.l2cache.demand_hits::cpu.inst 775712 # number of demand (read+write) hits 1114system.cpu.l2cache.demand_hits::cpu.data 1479959 # number of demand (read+write) hits 1115system.cpu.l2cache.demand_hits::total 2265314 # number of demand (read+write) hits 1116system.cpu.l2cache.overall_hits::cpu.dtb.walker 6740 # number of overall hits 1117system.cpu.l2cache.overall_hits::cpu.itb.walker 2903 # number of overall hits 1118system.cpu.l2cache.overall_hits::cpu.inst 775712 # number of overall hits 1119system.cpu.l2cache.overall_hits::cpu.data 1479959 # number of overall hits 1120system.cpu.l2cache.overall_hits::total 2265314 # number of overall hits 1121system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 1122system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 1123system.cpu.l2cache.ReadReq_misses::cpu.inst 12884 # number of ReadReq misses 1124system.cpu.l2cache.ReadReq_misses::cpu.data 28341 # number of ReadReq misses 1125system.cpu.l2cache.ReadReq_misses::total 41232 # number of ReadReq misses 1126system.cpu.l2cache.UpgradeReq_misses::cpu.data 1356 # number of UpgradeReq misses 1127system.cpu.l2cache.UpgradeReq_misses::total 1356 # number of UpgradeReq misses 1128system.cpu.l2cache.ReadExReq_misses::cpu.data 113042 # number of ReadExReq misses 1129system.cpu.l2cache.ReadExReq_misses::total 113042 # number of ReadExReq misses 1130system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 1131system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 1132system.cpu.l2cache.demand_misses::cpu.inst 12884 # number of demand (read+write) misses 1133system.cpu.l2cache.demand_misses::cpu.data 141383 # number of demand (read+write) misses 1134system.cpu.l2cache.demand_misses::total 154274 # number of demand (read+write) misses 1135system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 1136system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 1137system.cpu.l2cache.overall_misses::cpu.inst 12884 # number of overall misses 1138system.cpu.l2cache.overall_misses::cpu.data 141383 # number of overall misses 1139system.cpu.l2cache.overall_misses::total 154274 # number of overall misses 1140system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 136750 # number of ReadReq miss cycles 1141system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 347500 # number of ReadReq miss cycles 1142system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 979557242 # number of ReadReq miss cycles 1143system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2186954200 # number of ReadReq miss cycles 1144system.cpu.l2cache.ReadReq_miss_latency::total 3166995692 # number of ReadReq miss cycles 1145system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16260363 # number of UpgradeReq miss cycles 1146system.cpu.l2cache.UpgradeReq_miss_latency::total 16260363 # number of UpgradeReq miss cycles 1147system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7957275400 # number of ReadExReq miss cycles 1148system.cpu.l2cache.ReadExReq_miss_latency::total 7957275400 # number of ReadExReq miss cycles 1149system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 136750 # number of demand (read+write) miss cycles 1150system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 347500 # number of demand (read+write) miss cycles 1151system.cpu.l2cache.demand_miss_latency::cpu.inst 979557242 # number of demand (read+write) miss cycles 1152system.cpu.l2cache.demand_miss_latency::cpu.data 10144229600 # number of demand (read+write) miss cycles 1153system.cpu.l2cache.demand_miss_latency::total 11124271092 # number of demand (read+write) miss cycles 1154system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 136750 # number of overall miss cycles 1155system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 347500 # number of overall miss cycles 1156system.cpu.l2cache.overall_miss_latency::cpu.inst 979557242 # number of overall miss cycles 1157system.cpu.l2cache.overall_miss_latency::cpu.data 10144229600 # number of overall miss cycles 1158system.cpu.l2cache.overall_miss_latency::total 11124271092 # number of overall miss cycles 1159system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6742 # number of ReadReq accesses(hits+misses) 1160system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2908 # number of ReadReq accesses(hits+misses) 1161system.cpu.l2cache.ReadReq_accesses::cpu.inst 788596 # number of ReadReq accesses(hits+misses) 1162system.cpu.l2cache.ReadReq_accesses::cpu.data 1307548 # number of ReadReq accesses(hits+misses) 1163system.cpu.l2cache.ReadReq_accesses::total 2105794 # number of ReadReq accesses(hits+misses) 1164system.cpu.l2cache.Writeback_accesses::writebacks 1542700 # number of Writeback accesses(hits+misses) 1165system.cpu.l2cache.Writeback_accesses::total 1542700 # number of Writeback accesses(hits+misses) 1166system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1660 # number of UpgradeReq accesses(hits+misses) 1167system.cpu.l2cache.UpgradeReq_accesses::total 1660 # number of UpgradeReq accesses(hits+misses) 1168system.cpu.l2cache.ReadExReq_accesses::cpu.data 313794 # number of ReadExReq accesses(hits+misses) 1169system.cpu.l2cache.ReadExReq_accesses::total 313794 # number of ReadExReq accesses(hits+misses) 1170system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6742 # number of demand (read+write) accesses 1171system.cpu.l2cache.demand_accesses::cpu.itb.walker 2908 # number of demand (read+write) accesses 1172system.cpu.l2cache.demand_accesses::cpu.inst 788596 # number of demand (read+write) accesses 1173system.cpu.l2cache.demand_accesses::cpu.data 1621342 # number of demand (read+write) accesses 1174system.cpu.l2cache.demand_accesses::total 2419588 # number of demand (read+write) accesses 1175system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6742 # number of overall (read+write) accesses 1176system.cpu.l2cache.overall_accesses::cpu.itb.walker 2908 # number of overall (read+write) accesses 1177system.cpu.l2cache.overall_accesses::cpu.inst 788596 # number of overall (read+write) accesses 1178system.cpu.l2cache.overall_accesses::cpu.data 1621342 # number of overall (read+write) accesses 1179system.cpu.l2cache.overall_accesses::total 2419588 # number of overall (read+write) accesses 1180system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000297 # miss rate for ReadReq accesses 1181system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001719 # miss rate for ReadReq accesses 1182system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016338 # miss rate for ReadReq accesses 1183system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021675 # miss rate for ReadReq accesses 1184system.cpu.l2cache.ReadReq_miss_rate::total 0.019580 # miss rate for ReadReq accesses 1185system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.816867 # miss rate for UpgradeReq accesses 1186system.cpu.l2cache.UpgradeReq_miss_rate::total 0.816867 # miss rate for UpgradeReq accesses 1187system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360243 # miss rate for ReadExReq accesses 1188system.cpu.l2cache.ReadExReq_miss_rate::total 0.360243 # miss rate for ReadExReq accesses 1189system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000297 # miss rate for demand accesses 1190system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001719 # miss rate for demand accesses 1191system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016338 # miss rate for demand accesses 1192system.cpu.l2cache.demand_miss_rate::cpu.data 0.087201 # miss rate for demand accesses 1193system.cpu.l2cache.demand_miss_rate::total 0.063760 # miss rate for demand accesses 1194system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000297 # miss rate for overall accesses 1195system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001719 # miss rate for overall accesses 1196system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016338 # miss rate for overall accesses 1197system.cpu.l2cache.overall_miss_rate::cpu.data 0.087201 # miss rate for overall accesses 1198system.cpu.l2cache.overall_miss_rate::total 0.063760 # miss rate for overall accesses 1199system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68375 # average ReadReq miss latency 1200system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69500 # average ReadReq miss latency 1201system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76028.969419 # average ReadReq miss latency 1202system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77165.738682 # average ReadReq miss latency 1203system.cpu.l2cache.ReadReq_avg_miss_latency::total 76809.169868 # average ReadReq miss latency 1204system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11991.418142 # average UpgradeReq miss latency 1205system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11991.418142 # average UpgradeReq miss latency 1206system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70392.202898 # average ReadExReq miss latency 1207system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70392.202898 # average ReadExReq miss latency 1208system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68375 # average overall miss latency 1209system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69500 # average overall miss latency 1210system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76028.969419 # average overall miss latency 1211system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71749.995403 # average overall miss latency 1212system.cpu.l2cache.demand_avg_miss_latency::total 72107.231886 # average overall miss latency 1213system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68375 # average overall miss latency 1214system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69500 # average overall miss latency 1215system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76028.969419 # average overall miss latency 1216system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71749.995403 # average overall miss latency 1217system.cpu.l2cache.overall_avg_miss_latency::total 72107.231886 # average overall miss latency 1218system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1219system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1220system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1221system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1222system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1223system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1224system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1225system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1226system.cpu.l2cache.writebacks::writebacks 80066 # number of writebacks 1227system.cpu.l2cache.writebacks::total 80066 # number of writebacks 1228system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2 # number of ReadReq MSHR misses 1229system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 1230system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12884 # number of ReadReq MSHR misses 1231system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28341 # number of ReadReq MSHR misses 1232system.cpu.l2cache.ReadReq_mshr_misses::total 41232 # number of ReadReq MSHR misses 1233system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1356 # number of UpgradeReq MSHR misses 1234system.cpu.l2cache.UpgradeReq_mshr_misses::total 1356 # number of UpgradeReq MSHR misses 1235system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113042 # number of ReadExReq MSHR misses 1236system.cpu.l2cache.ReadExReq_mshr_misses::total 113042 # number of ReadExReq MSHR misses 1237system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2 # number of demand (read+write) MSHR misses 1238system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 1239system.cpu.l2cache.demand_mshr_misses::cpu.inst 12884 # number of demand (read+write) MSHR misses 1240system.cpu.l2cache.demand_mshr_misses::cpu.data 141383 # number of demand (read+write) MSHR misses 1241system.cpu.l2cache.demand_mshr_misses::total 154274 # number of demand (read+write) MSHR misses 1242system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2 # number of overall MSHR misses 1243system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 1244system.cpu.l2cache.overall_mshr_misses::cpu.inst 12884 # number of overall MSHR misses 1245system.cpu.l2cache.overall_mshr_misses::cpu.data 141383 # number of overall MSHR misses 1246system.cpu.l2cache.overall_mshr_misses::total 154274 # number of overall MSHR misses 1247system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 111250 # number of ReadReq MSHR miss cycles 1248system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 285000 # number of ReadReq MSHR miss cycles 1249system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 818022758 # number of ReadReq MSHR miss cycles 1250system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1831787800 # number of ReadReq MSHR miss cycles 1251system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2650206808 # number of ReadReq MSHR miss cycles 1252system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14478338 # number of UpgradeReq MSHR miss cycles 1253system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14478338 # number of UpgradeReq MSHR miss cycles 1254system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6543285600 # number of ReadExReq MSHR miss cycles 1255system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6543285600 # number of ReadExReq MSHR miss cycles 1256system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 111250 # number of demand (read+write) MSHR miss cycles 1257system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 285000 # number of demand (read+write) MSHR miss cycles 1258system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 818022758 # number of demand (read+write) MSHR miss cycles 1259system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8375073400 # number of demand (read+write) MSHR miss cycles 1260system.cpu.l2cache.demand_mshr_miss_latency::total 9193492408 # number of demand (read+write) MSHR miss cycles 1261system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 111250 # number of overall MSHR miss cycles 1262system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 285000 # number of overall MSHR miss cycles 1263system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 818022758 # number of overall MSHR miss cycles 1264system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8375073400 # number of overall MSHR miss cycles 1265system.cpu.l2cache.overall_mshr_miss_latency::total 9193492408 # number of overall MSHR miss cycles 1266system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655869500 # number of ReadReq MSHR uncacheable cycles 1267system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655869500 # number of ReadReq MSHR uncacheable cycles 1268system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370854000 # number of WriteReq MSHR uncacheable cycles 1269system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370854000 # number of WriteReq MSHR uncacheable cycles 1270system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026723500 # number of overall MSHR uncacheable cycles 1271system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026723500 # number of overall MSHR uncacheable cycles 1272system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for ReadReq accesses 1273system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for ReadReq accesses 1274system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for ReadReq accesses 1275system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021675 # mshr miss rate for ReadReq accesses 1276system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019580 # mshr miss rate for ReadReq accesses 1277system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.816867 # mshr miss rate for UpgradeReq accesses 1278system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.816867 # mshr miss rate for UpgradeReq accesses 1279system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360243 # mshr miss rate for ReadExReq accesses 1280system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360243 # mshr miss rate for ReadExReq accesses 1281system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for demand accesses 1282system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for demand accesses 1283system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for demand accesses 1284system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087201 # mshr miss rate for demand accesses 1285system.cpu.l2cache.demand_mshr_miss_rate::total 0.063760 # mshr miss rate for demand accesses 1286system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for overall accesses 1287system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for overall accesses 1288system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for overall accesses 1289system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087201 # mshr miss rate for overall accesses 1290system.cpu.l2cache.overall_mshr_miss_rate::total 0.063760 # mshr miss rate for overall accesses 1291system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average ReadReq mshr miss latency 1292system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57000 # average ReadReq mshr miss latency 1293system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63491.365880 # average ReadReq mshr miss latency 1294system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64633.844960 # average ReadReq mshr miss latency 1295system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64275.485254 # average ReadReq mshr miss latency 1296system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10677.240413 # average UpgradeReq mshr miss latency 1297system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10677.240413 # average UpgradeReq mshr miss latency 1298system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57883.668017 # average ReadExReq mshr miss latency 1299system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57883.668017 # average ReadExReq mshr miss latency 1300system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency 1301system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57000 # average overall mshr miss latency 1302system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63491.365880 # average overall mshr miss latency 1303system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59236.778113 # average overall mshr miss latency 1304system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59591.975369 # average overall mshr miss latency 1305system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency 1306system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57000 # average overall mshr miss latency 1307system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63491.365880 # average overall mshr miss latency 1308system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59236.778113 # average overall mshr miss latency 1309system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59591.975369 # average overall mshr miss latency 1310system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1311system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1312system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1313system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1314system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1315system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1316system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1317 1318---------- End Simulation Statistics ----------	653system.cpu.kern.inst.arm 0 # number of arm instructions executed 654system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 655system.cpu.icache.tags.replacements 788090 # number of replacements 656system.cpu.icache.tags.tagsinuse 510.351939 # Cycle average of tags in use 657system.cpu.icache.tags.total_refs 144584753 # Total number of references to valid blocks. 658system.cpu.icache.tags.sampled_refs 788602 # Sample count of references to valid blocks. 659system.cpu.icache.tags.avg_refs 183.343122 # Average number of references to valid blocks. 660system.cpu.icache.tags.warmup_cycle 161436066250 # Cycle when the warmup percentage was hit. 661system.cpu.icache.tags.occ_blocks::cpu.inst 510.351939 # Average occupied blocks per requestor 662system.cpu.icache.tags.occ_percent::cpu.inst 0.996781 # Average percentage of cache occupancy 663system.cpu.icache.tags.occ_percent::total 0.996781 # Average percentage of cache occupancy 664system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 665system.cpu.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 666system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id 667system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id 668system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 669system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 670system.cpu.icache.tags.tag_accesses 146161971 # Number of tag accesses 671system.cpu.icache.tags.data_accesses 146161971 # Number of data accesses 672system.cpu.icache.ReadReq_hits::cpu.inst 144584753 # number of ReadReq hits 673system.cpu.icache.ReadReq_hits::total 144584753 # number of ReadReq hits 674system.cpu.icache.demand_hits::cpu.inst 144584753 # number of demand (read+write) hits 675system.cpu.icache.demand_hits::total 144584753 # number of demand (read+write) hits 676system.cpu.icache.overall_hits::cpu.inst 144584753 # number of overall hits 677system.cpu.icache.overall_hits::total 144584753 # number of overall hits 678system.cpu.icache.ReadReq_misses::cpu.inst 788609 # number of ReadReq misses 679system.cpu.icache.ReadReq_misses::total 788609 # number of ReadReq misses 680system.cpu.icache.demand_misses::cpu.inst 788609 # number of demand (read+write) misses 681system.cpu.icache.demand_misses::total 788609 # number of demand (read+write) misses 682system.cpu.icache.overall_misses::cpu.inst 788609 # number of overall misses 683system.cpu.icache.overall_misses::total 788609 # number of overall misses 684system.cpu.icache.ReadReq_miss_latency::cpu.inst 11107362758 # number of ReadReq miss cycles 685system.cpu.icache.ReadReq_miss_latency::total 11107362758 # number of ReadReq miss cycles 686system.cpu.icache.demand_miss_latency::cpu.inst 11107362758 # number of demand (read+write) miss cycles 687system.cpu.icache.demand_miss_latency::total 11107362758 # number of demand (read+write) miss cycles 688system.cpu.icache.overall_miss_latency::cpu.inst 11107362758 # number of overall miss cycles 689system.cpu.icache.overall_miss_latency::total 11107362758 # number of overall miss cycles 690system.cpu.icache.ReadReq_accesses::cpu.inst 145373362 # number of ReadReq accesses(hits+misses) 691system.cpu.icache.ReadReq_accesses::total 145373362 # number of ReadReq accesses(hits+misses) 692system.cpu.icache.demand_accesses::cpu.inst 145373362 # number of demand (read+write) accesses 693system.cpu.icache.demand_accesses::total 145373362 # number of demand (read+write) accesses 694system.cpu.icache.overall_accesses::cpu.inst 145373362 # number of overall (read+write) accesses 695system.cpu.icache.overall_accesses::total 145373362 # number of overall (read+write) accesses 696system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005425 # miss rate for ReadReq accesses 697system.cpu.icache.ReadReq_miss_rate::total 0.005425 # miss rate for ReadReq accesses 698system.cpu.icache.demand_miss_rate::cpu.inst 0.005425 # miss rate for demand accesses 699system.cpu.icache.demand_miss_rate::total 0.005425 # miss rate for demand accesses 700system.cpu.icache.overall_miss_rate::cpu.inst 0.005425 # miss rate for overall accesses 701system.cpu.icache.overall_miss_rate::total 0.005425 # miss rate for overall accesses 702system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14084.752720 # average ReadReq miss latency 703system.cpu.icache.ReadReq_avg_miss_latency::total 14084.752720 # average ReadReq miss latency 704system.cpu.icache.demand_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency 705system.cpu.icache.demand_avg_miss_latency::total 14084.752720 # average overall miss latency 706system.cpu.icache.overall_avg_miss_latency::cpu.inst 14084.752720 # average overall miss latency 707system.cpu.icache.overall_avg_miss_latency::total 14084.752720 # average overall miss latency 708system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 709system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 710system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 711system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 712system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 713system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 714system.cpu.icache.fast_writes 0 # number of fast writes performed 715system.cpu.icache.cache_copies 0 # number of cache copies performed 716system.cpu.icache.ReadReq_mshr_misses::cpu.inst 788609 # number of ReadReq MSHR misses 717system.cpu.icache.ReadReq_mshr_misses::total 788609 # number of ReadReq MSHR misses 718system.cpu.icache.demand_mshr_misses::cpu.inst 788609 # number of demand (read+write) MSHR misses 719system.cpu.icache.demand_mshr_misses::total 788609 # number of demand (read+write) MSHR misses 720system.cpu.icache.overall_mshr_misses::cpu.inst 788609 # number of overall MSHR misses 721system.cpu.icache.overall_mshr_misses::total 788609 # number of overall MSHR misses 722system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9525299242 # number of ReadReq MSHR miss cycles 723system.cpu.icache.ReadReq_mshr_miss_latency::total 9525299242 # number of ReadReq MSHR miss cycles 724system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9525299242 # number of demand (read+write) MSHR miss cycles 725system.cpu.icache.demand_mshr_miss_latency::total 9525299242 # number of demand (read+write) MSHR miss cycles 726system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9525299242 # number of overall MSHR miss cycles 727system.cpu.icache.overall_mshr_miss_latency::total 9525299242 # number of overall MSHR miss cycles 728system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for ReadReq accesses 729system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005425 # mshr miss rate for ReadReq accesses 730system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for demand accesses 731system.cpu.icache.demand_mshr_miss_rate::total 0.005425 # mshr miss rate for demand accesses 732system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005425 # mshr miss rate for overall accesses 733system.cpu.icache.overall_mshr_miss_rate::total 0.005425 # mshr miss rate for overall accesses 734system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12078.608337 # average ReadReq mshr miss latency 735system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12078.608337 # average ReadReq mshr miss latency 736system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency 737system.cpu.icache.demand_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency 738system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12078.608337 # average overall mshr miss latency 739system.cpu.icache.overall_avg_mshr_miss_latency::total 12078.608337 # average overall mshr miss latency 740system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 741system.cpu.itb_walker_cache.tags.replacements 3741 # number of replacements 742system.cpu.itb_walker_cache.tags.tagsinuse 3.069761 # Cycle average of tags in use 743system.cpu.itb_walker_cache.tags.total_refs 7617 # Total number of references to valid blocks. 744system.cpu.itb_walker_cache.tags.sampled_refs 3752 # Sample count of references to valid blocks. 745system.cpu.itb_walker_cache.tags.avg_refs 2.030117 # Average number of references to valid blocks. 746system.cpu.itb_walker_cache.tags.warmup_cycle 5169682535000 # Cycle when the warmup percentage was hit. 747system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069761 # Average occupied blocks per requestor 748system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191860 # Average percentage of cache occupancy 749system.cpu.itb_walker_cache.tags.occ_percent::total 0.191860 # Average percentage of cache occupancy 750system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id 751system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 752system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 753system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 754system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 755system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id 756system.cpu.itb_walker_cache.tags.tag_accesses 29050 # Number of tag accesses 757system.cpu.itb_walker_cache.tags.data_accesses 29050 # Number of data accesses 758system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7617 # number of ReadReq hits 759system.cpu.itb_walker_cache.ReadReq_hits::total 7617 # number of ReadReq hits 760system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 761system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 762system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7619 # number of demand (read+write) hits 763system.cpu.itb_walker_cache.demand_hits::total 7619 # number of demand (read+write) hits 764system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7619 # number of overall hits 765system.cpu.itb_walker_cache.overall_hits::total 7619 # number of overall hits 766system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4604 # number of ReadReq misses 767system.cpu.itb_walker_cache.ReadReq_misses::total 4604 # number of ReadReq misses 768system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4604 # number of demand (read+write) misses 769system.cpu.itb_walker_cache.demand_misses::total 4604 # number of demand (read+write) misses 770system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4604 # number of overall misses 771system.cpu.itb_walker_cache.overall_misses::total 4604 # number of overall misses 772system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44886750 # number of ReadReq miss cycles 773system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44886750 # number of ReadReq miss cycles 774system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44886750 # number of demand (read+write) miss cycles 775system.cpu.itb_walker_cache.demand_miss_latency::total 44886750 # number of demand (read+write) miss cycles 776system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44886750 # number of overall miss cycles 777system.cpu.itb_walker_cache.overall_miss_latency::total 44886750 # number of overall miss cycles 778system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12221 # number of ReadReq accesses(hits+misses) 779system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) 780system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 781system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 782system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12223 # number of demand (read+write) accesses 783system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses 784system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12223 # number of overall (read+write) accesses 785system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses 786system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.376729 # miss rate for ReadReq accesses 787system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.376729 # miss rate for ReadReq accesses 788system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.376667 # miss rate for demand accesses 789system.cpu.itb_walker_cache.demand_miss_rate::total 0.376667 # miss rate for demand accesses 790system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.376667 # miss rate for overall accesses 791system.cpu.itb_walker_cache.overall_miss_rate::total 0.376667 # miss rate for overall accesses 792system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9749.511295 # average ReadReq miss latency 793system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9749.511295 # average ReadReq miss latency 794system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency 795system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9749.511295 # average overall miss latency 796system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9749.511295 # average overall miss latency 797system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9749.511295 # average overall miss latency 798system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 799system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 800system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 801system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 802system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 803system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 804system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 805system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 806system.cpu.itb_walker_cache.writebacks::writebacks 621 # number of writebacks 807system.cpu.itb_walker_cache.writebacks::total 621 # number of writebacks 808system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4604 # number of ReadReq MSHR misses 809system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4604 # number of ReadReq MSHR misses 810system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4604 # number of demand (read+write) MSHR misses 811system.cpu.itb_walker_cache.demand_mshr_misses::total 4604 # number of demand (read+write) MSHR misses 812system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4604 # number of overall MSHR misses 813system.cpu.itb_walker_cache.overall_mshr_misses::total 4604 # number of overall MSHR misses 814system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 35677750 # number of ReadReq MSHR miss cycles 815system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 35677750 # number of ReadReq MSHR miss cycles 816system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 35677750 # number of demand (read+write) MSHR miss cycles 817system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 35677750 # number of demand (read+write) MSHR miss cycles 818system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 35677750 # number of overall MSHR miss cycles 819system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 35677750 # number of overall MSHR miss cycles 820system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.376729 # mshr miss rate for ReadReq accesses 821system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.376729 # mshr miss rate for ReadReq accesses 822system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for demand accesses 823system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.376667 # mshr miss rate for demand accesses 824system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.376667 # mshr miss rate for overall accesses 825system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.376667 # mshr miss rate for overall accesses 826system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average ReadReq mshr miss latency 827system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7749.294092 # average ReadReq mshr miss latency 828system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency 829system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency 830system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7749.294092 # average overall mshr miss latency 831system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7749.294092 # average overall mshr miss latency 832system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 833system.cpu.dtb_walker_cache.tags.replacements 7948 # number of replacements 834system.cpu.dtb_walker_cache.tags.tagsinuse 5.052475 # Cycle average of tags in use 835system.cpu.dtb_walker_cache.tags.total_refs 12793 # Total number of references to valid blocks. 836system.cpu.dtb_walker_cache.tags.sampled_refs 7961 # Sample count of references to valid blocks. 837system.cpu.dtb_walker_cache.tags.avg_refs 1.606959 # Average number of references to valid blocks. 838system.cpu.dtb_walker_cache.tags.warmup_cycle 5168018375000 # Cycle when the warmup percentage was hit. 839system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052475 # Average occupied blocks per requestor 840system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315780 # Average percentage of cache occupancy 841system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315780 # Average percentage of cache occupancy 842system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 843system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 844system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 845system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 846system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 847system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 848system.cpu.dtb_walker_cache.tags.tag_accesses 53026 # Number of tag accesses 849system.cpu.dtb_walker_cache.tags.data_accesses 53026 # Number of data accesses 850system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12806 # number of ReadReq hits 851system.cpu.dtb_walker_cache.ReadReq_hits::total 12806 # number of ReadReq hits 852system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12806 # number of demand (read+write) hits 853system.cpu.dtb_walker_cache.demand_hits::total 12806 # number of demand (read+write) hits 854system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12806 # number of overall hits 855system.cpu.dtb_walker_cache.overall_hits::total 12806 # number of overall hits 856system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9138 # number of ReadReq misses 857system.cpu.dtb_walker_cache.ReadReq_misses::total 9138 # number of ReadReq misses 858system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9138 # number of demand (read+write) misses 859system.cpu.dtb_walker_cache.demand_misses::total 9138 # number of demand (read+write) misses 860system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9138 # number of overall misses 861system.cpu.dtb_walker_cache.overall_misses::total 9138 # number of overall misses 862system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 97347500 # number of ReadReq miss cycles 863system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 97347500 # number of ReadReq miss cycles 864system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 97347500 # number of demand (read+write) miss cycles 865system.cpu.dtb_walker_cache.demand_miss_latency::total 97347500 # number of demand (read+write) miss cycles 866system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 97347500 # number of overall miss cycles 867system.cpu.dtb_walker_cache.overall_miss_latency::total 97347500 # number of overall miss cycles 868system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21944 # number of ReadReq accesses(hits+misses) 869system.cpu.dtb_walker_cache.ReadReq_accesses::total 21944 # number of ReadReq accesses(hits+misses) 870system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21944 # number of demand (read+write) accesses 871system.cpu.dtb_walker_cache.demand_accesses::total 21944 # number of demand (read+write) accesses 872system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21944 # number of overall (read+write) accesses 873system.cpu.dtb_walker_cache.overall_accesses::total 21944 # number of overall (read+write) accesses 874system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.416424 # miss rate for ReadReq accesses 875system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.416424 # miss rate for ReadReq accesses 876system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.416424 # miss rate for demand accesses 877system.cpu.dtb_walker_cache.demand_miss_rate::total 0.416424 # miss rate for demand accesses 878system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.416424 # miss rate for overall accesses 879system.cpu.dtb_walker_cache.overall_miss_rate::total 0.416424 # miss rate for overall accesses 880system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10653.042241 # average ReadReq miss latency 881system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10653.042241 # average ReadReq miss latency 882system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency 883system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10653.042241 # average overall miss latency 884system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10653.042241 # average overall miss latency 885system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10653.042241 # average overall miss latency 886system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 887system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 888system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 889system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 890system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 891system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 893system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 894system.cpu.dtb_walker_cache.writebacks::writebacks 3106 # number of writebacks 895system.cpu.dtb_walker_cache.writebacks::total 3106 # number of writebacks 896system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9138 # number of ReadReq MSHR misses 897system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9138 # number of ReadReq MSHR misses 898system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9138 # number of demand (read+write) MSHR misses 899system.cpu.dtb_walker_cache.demand_mshr_misses::total 9138 # number of demand (read+write) MSHR misses 900system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9138 # number of overall MSHR misses 901system.cpu.dtb_walker_cache.overall_mshr_misses::total 9138 # number of overall MSHR misses 902system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 79071000 # number of ReadReq MSHR miss cycles 903system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 79071000 # number of ReadReq MSHR miss cycles 904system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 79071000 # number of demand (read+write) MSHR miss cycles 905system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 79071000 # number of demand (read+write) MSHR miss cycles 906system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 79071000 # number of overall MSHR miss cycles 907system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 79071000 # number of overall MSHR miss cycles 908system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for ReadReq accesses 909system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.416424 # mshr miss rate for ReadReq accesses 910system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for demand accesses 911system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.416424 # mshr miss rate for demand accesses 912system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.416424 # mshr miss rate for overall accesses 913system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.416424 # mshr miss rate for overall accesses 914system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average ReadReq mshr miss latency 915system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8652.987525 # average ReadReq mshr miss latency 916system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average overall mshr miss latency 917system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8652.987525 # average overall mshr miss latency 918system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8652.987525 # average overall mshr miss latency 919system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8652.987525 # average overall mshr miss latency 920system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 921system.cpu.dcache.tags.replacements 1621547 # number of replacements 922system.cpu.dcache.tags.tagsinuse 511.997026 # Cycle average of tags in use 923system.cpu.dcache.tags.total_refs 20035701 # Total number of references to valid blocks. 924system.cpu.dcache.tags.sampled_refs 1622059 # Sample count of references to valid blocks. 925system.cpu.dcache.tags.avg_refs 12.352017 # Average number of references to valid blocks. 926system.cpu.dcache.tags.warmup_cycle 50992250 # Cycle when the warmup percentage was hit. 927system.cpu.dcache.tags.occ_blocks::cpu.data 511.997026 # Average occupied blocks per requestor 928system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 929system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 930system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 931system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 932system.cpu.dcache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 933system.cpu.dcache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 934system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 935system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 936system.cpu.dcache.tags.tag_accesses 88253354 # Number of tag accesses 937system.cpu.dcache.tags.data_accesses 88253354 # Number of data accesses 938system.cpu.dcache.ReadReq_hits::cpu.data 11993197 # number of ReadReq hits 939system.cpu.dcache.ReadReq_hits::total 11993197 # number of ReadReq hits 940system.cpu.dcache.WriteReq_hits::cpu.data 8040328 # number of WriteReq hits 941system.cpu.dcache.WriteReq_hits::total 8040328 # number of WriteReq hits 942system.cpu.dcache.demand_hits::cpu.data 20033525 # number of demand (read+write) hits 943system.cpu.dcache.demand_hits::total 20033525 # number of demand (read+write) hits 944system.cpu.dcache.overall_hits::cpu.data 20033525 # number of overall hits 945system.cpu.dcache.overall_hits::total 20033525 # number of overall hits 946system.cpu.dcache.ReadReq_misses::cpu.data 1308312 # number of ReadReq misses 947system.cpu.dcache.ReadReq_misses::total 1308312 # number of ReadReq misses 948system.cpu.dcache.WriteReq_misses::cpu.data 315974 # number of WriteReq misses 949system.cpu.dcache.WriteReq_misses::total 315974 # number of WriteReq misses 950system.cpu.dcache.demand_misses::cpu.data 1624286 # number of demand (read+write) misses 951system.cpu.dcache.demand_misses::total 1624286 # number of demand (read+write) misses 952system.cpu.dcache.overall_misses::cpu.data 1624286 # number of overall misses 953system.cpu.dcache.overall_misses::total 1624286 # number of overall misses 954system.cpu.dcache.ReadReq_miss_latency::cpu.data 18913909300 # number of ReadReq miss cycles 955system.cpu.dcache.ReadReq_miss_latency::total 18913909300 # number of ReadReq miss cycles 956system.cpu.dcache.WriteReq_miss_latency::cpu.data 11002078938 # number of WriteReq miss cycles 957system.cpu.dcache.WriteReq_miss_latency::total 11002078938 # number of WriteReq miss cycles 958system.cpu.dcache.demand_miss_latency::cpu.data 29915988238 # number of demand (read+write) miss cycles 959system.cpu.dcache.demand_miss_latency::total 29915988238 # number of demand (read+write) miss cycles 960system.cpu.dcache.overall_miss_latency::cpu.data 29915988238 # number of overall miss cycles 961system.cpu.dcache.overall_miss_latency::total 29915988238 # number of overall miss cycles 962system.cpu.dcache.ReadReq_accesses::cpu.data 13301509 # number of ReadReq accesses(hits+misses) 963system.cpu.dcache.ReadReq_accesses::total 13301509 # number of ReadReq accesses(hits+misses) 964system.cpu.dcache.WriteReq_accesses::cpu.data 8356302 # number of WriteReq accesses(hits+misses) 965system.cpu.dcache.WriteReq_accesses::total 8356302 # number of WriteReq accesses(hits+misses) 966system.cpu.dcache.demand_accesses::cpu.data 21657811 # number of demand (read+write) accesses 967system.cpu.dcache.demand_accesses::total 21657811 # number of demand (read+write) accesses 968system.cpu.dcache.overall_accesses::cpu.data 21657811 # number of overall (read+write) accesses 969system.cpu.dcache.overall_accesses::total 21657811 # number of overall (read+write) accesses 970system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098358 # miss rate for ReadReq accesses 971system.cpu.dcache.ReadReq_miss_rate::total 0.098358 # miss rate for ReadReq accesses 972system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses 973system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses 974system.cpu.dcache.demand_miss_rate::cpu.data 0.074998 # miss rate for demand accesses 975system.cpu.dcache.demand_miss_rate::total 0.074998 # miss rate for demand accesses 976system.cpu.dcache.overall_miss_rate::cpu.data 0.074998 # miss rate for overall accesses 977system.cpu.dcache.overall_miss_rate::total 0.074998 # miss rate for overall accesses 978system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14456.726912 # average ReadReq miss latency 979system.cpu.dcache.ReadReq_avg_miss_latency::total 14456.726912 # average ReadReq miss latency 980system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34819.570401 # average WriteReq miss latency 981system.cpu.dcache.WriteReq_avg_miss_latency::total 34819.570401 # average WriteReq miss latency 982system.cpu.dcache.demand_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency 983system.cpu.dcache.demand_avg_miss_latency::total 18417.931471 # average overall miss latency 984system.cpu.dcache.overall_avg_miss_latency::cpu.data 18417.931471 # average overall miss latency 985system.cpu.dcache.overall_avg_miss_latency::total 18417.931471 # average overall miss latency 986system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 987system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 988system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 989system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 990system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 991system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 992system.cpu.dcache.fast_writes 0 # number of fast writes performed 993system.cpu.dcache.cache_copies 0 # number of cache copies performed 994system.cpu.dcache.writebacks::writebacks 1538973 # number of writebacks 995system.cpu.dcache.writebacks::total 1538973 # number of writebacks 996system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308312 # number of ReadReq MSHR misses 997system.cpu.dcache.ReadReq_mshr_misses::total 1308312 # number of ReadReq MSHR misses 998system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315974 # number of WriteReq MSHR misses 999system.cpu.dcache.WriteReq_mshr_misses::total 315974 # number of WriteReq MSHR misses 1000system.cpu.dcache.demand_mshr_misses::cpu.data 1624286 # number of demand (read+write) MSHR misses 1001system.cpu.dcache.demand_mshr_misses::total 1624286 # number of demand (read+write) MSHR misses 1002system.cpu.dcache.overall_mshr_misses::cpu.data 1624286 # number of overall MSHR misses 1003system.cpu.dcache.overall_mshr_misses::total 1624286 # number of overall MSHR misses 1004system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16288101700 # number of ReadReq MSHR miss cycles 1005system.cpu.dcache.ReadReq_mshr_miss_latency::total 16288101700 # number of ReadReq MSHR miss cycles 1006system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10316379062 # number of WriteReq MSHR miss cycles 1007system.cpu.dcache.WriteReq_mshr_miss_latency::total 10316379062 # number of WriteReq MSHR miss cycles 1008system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26604480762 # number of demand (read+write) MSHR miss cycles 1009system.cpu.dcache.demand_mshr_miss_latency::total 26604480762 # number of demand (read+write) MSHR miss cycles 1010system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26604480762 # number of overall MSHR miss cycles 1011system.cpu.dcache.overall_mshr_miss_latency::total 26604480762 # number of overall MSHR miss cycles 1012system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214673000 # number of ReadReq MSHR uncacheable cycles 1013system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214673000 # number of ReadReq MSHR uncacheable cycles 1014system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537491500 # number of WriteReq MSHR uncacheable cycles 1015system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537491500 # number of WriteReq MSHR uncacheable cycles 1016system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752164500 # number of overall MSHR uncacheable cycles 1017system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752164500 # number of overall MSHR uncacheable cycles 1018system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098358 # mshr miss rate for ReadReq accesses 1019system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098358 # mshr miss rate for ReadReq accesses 1020system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037813 # mshr miss rate for WriteReq accesses 1021system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037813 # mshr miss rate for WriteReq accesses 1022system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for demand accesses 1023system.cpu.dcache.demand_mshr_miss_rate::total 0.074998 # mshr miss rate for demand accesses 1024system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074998 # mshr miss rate for overall accesses 1025system.cpu.dcache.overall_mshr_miss_rate::total 0.074998 # mshr miss rate for overall accesses 1026system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12449.707486 # average ReadReq mshr miss latency 1027system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12449.707486 # average ReadReq mshr miss latency 1028system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32649.455531 # average WriteReq mshr miss latency 1029system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32649.455531 # average WriteReq mshr miss latency 1030system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency 1031system.cpu.dcache.demand_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency 1032system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16379.184923 # average overall mshr miss latency 1033system.cpu.dcache.overall_avg_mshr_miss_latency::total 16379.184923 # average overall mshr miss latency 1034system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1035system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1036system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1037system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1038system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1039system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1040system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1041system.cpu.toL2Bus.throughput 49185341 # Throughput (bytes/s) 1042system.cpu.toL2Bus.trans_dist::ReadReq 2692945 # Transaction distribution 1043system.cpu.toL2Bus.trans_dist::ReadResp 2692419 # Transaction distribution 1044system.cpu.toL2Bus.trans_dist::WriteReq 13775 # Transaction distribution 1045system.cpu.toL2Bus.trans_dist::WriteResp 13775 # Transaction distribution 1046system.cpu.toL2Bus.trans_dist::Writeback 1542700 # Transaction distribution 1047system.cpu.toL2Bus.trans_dist::UpgradeReq 2176 # Transaction distribution 1048system.cpu.toL2Bus.trans_dist::UpgradeResp 2176 # Transaction distribution 1049system.cpu.toL2Bus.trans_dist::ReadExReq 360518 # Transaction distribution 1050system.cpu.toL2Bus.trans_dist::ReadExResp 313820 # Transaction distribution 1051system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1577205 # Packet count per connected master and slave (bytes) 1052system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5977035 # Packet count per connected master and slave (bytes) 1053system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8133 # Packet count per connected master and slave (bytes) 1054system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18986 # Packet count per connected master and slave (bytes) 1055system.cpu.toL2Bus.pkt_count::total 7581359 # Packet count per connected master and slave (bytes) 1056system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50470144 # Cumulative packet size per connected master and slave (bytes) 1057system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203948077 # Cumulative packet size per connected master and slave (bytes) 1058system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 225856 # Cumulative packet size per connected master and slave (bytes) 1059system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 630272 # Cumulative packet size per connected master and slave (bytes) 1060system.cpu.toL2Bus.tot_pkt_size::total 255274349 # Cumulative packet size per connected master and slave (bytes) 1061system.cpu.toL2Bus.data_through_bus 255253101 # Total data (bytes) 1062system.cpu.toL2Bus.snoop_data_through_bus 333120 # Total snoop data (bytes) 1063system.cpu.toL2Bus.reqLayer0.occupancy 3831866500 # Layer occupancy (ticks) 1064system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1065system.cpu.toL2Bus.snoopLayer0.occupancy 498000 # Layer occupancy (ticks) 1066system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1067system.cpu.toL2Bus.respLayer0.occupancy 1185336258 # Layer occupancy (ticks) 1068system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1069system.cpu.toL2Bus.respLayer1.occupancy 3054054238 # Layer occupancy (ticks) 1070system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1071system.cpu.toL2Bus.respLayer2.occupancy 6906500 # Layer occupancy (ticks) 1072system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1073system.cpu.toL2Bus.respLayer3.occupancy 13707250 # Layer occupancy (ticks) 1074system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1075system.cpu.l2cache.tags.replacements 86910 # number of replacements 1076system.cpu.l2cache.tags.tagsinuse 64731.196890 # Cycle average of tags in use 1077system.cpu.l2cache.tags.total_refs 3488433 # Total number of references to valid blocks. 1078system.cpu.l2cache.tags.sampled_refs 151626 # Sample count of references to valid blocks. 1079system.cpu.l2cache.tags.avg_refs 23.006826 # Average number of references to valid blocks. 1080system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1081system.cpu.l2cache.tags.occ_blocks::writebacks 50120.476905 # Average occupied blocks per requestor 1082system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.033461 # Average occupied blocks per requestor 1083system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141258 # Average occupied blocks per requestor 1084system.cpu.l2cache.tags.occ_blocks::cpu.inst 3445.447212 # Average occupied blocks per requestor 1085system.cpu.l2cache.tags.occ_blocks::cpu.data 11165.098054 # Average occupied blocks per requestor 1086system.cpu.l2cache.tags.occ_percent::writebacks 0.764778 # Average percentage of cache occupancy 1087system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000001 # Average percentage of cache occupancy 1088system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 1089system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052573 # Average percentage of cache occupancy 1090system.cpu.l2cache.tags.occ_percent::cpu.data 0.170366 # Average percentage of cache occupancy 1091system.cpu.l2cache.tags.occ_percent::total 0.987720 # Average percentage of cache occupancy 1092system.cpu.l2cache.tags.occ_task_id_blocks::1024 64716 # Occupied blocks per task id 1093system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 1094system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 1095system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2864 # Occupied blocks per task id 1096system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4951 # Occupied blocks per task id 1097system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56789 # Occupied blocks per task id 1098system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987488 # Percentage of cache occupancy per task id 1099system.cpu.l2cache.tags.tag_accesses 32180081 # Number of tag accesses 1100system.cpu.l2cache.tags.data_accesses 32180081 # Number of data accesses 1101system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6740 # number of ReadReq hits 1102system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2903 # number of ReadReq hits 1103system.cpu.l2cache.ReadReq_hits::cpu.inst 775712 # number of ReadReq hits 1104system.cpu.l2cache.ReadReq_hits::cpu.data 1279207 # number of ReadReq hits 1105system.cpu.l2cache.ReadReq_hits::total 2064562 # number of ReadReq hits 1106system.cpu.l2cache.Writeback_hits::writebacks 1542700 # number of Writeback hits 1107system.cpu.l2cache.Writeback_hits::total 1542700 # number of Writeback hits 1108system.cpu.l2cache.UpgradeReq_hits::cpu.data 304 # number of UpgradeReq hits 1109system.cpu.l2cache.UpgradeReq_hits::total 304 # number of UpgradeReq hits 1110system.cpu.l2cache.ReadExReq_hits::cpu.data 200752 # number of ReadExReq hits 1111system.cpu.l2cache.ReadExReq_hits::total 200752 # number of ReadExReq hits 1112system.cpu.l2cache.demand_hits::cpu.dtb.walker 6740 # number of demand (read+write) hits 1113system.cpu.l2cache.demand_hits::cpu.itb.walker 2903 # number of demand (read+write) hits 1114system.cpu.l2cache.demand_hits::cpu.inst 775712 # number of demand (read+write) hits 1115system.cpu.l2cache.demand_hits::cpu.data 1479959 # number of demand (read+write) hits 1116system.cpu.l2cache.demand_hits::total 2265314 # number of demand (read+write) hits 1117system.cpu.l2cache.overall_hits::cpu.dtb.walker 6740 # number of overall hits 1118system.cpu.l2cache.overall_hits::cpu.itb.walker 2903 # number of overall hits 1119system.cpu.l2cache.overall_hits::cpu.inst 775712 # number of overall hits 1120system.cpu.l2cache.overall_hits::cpu.data 1479959 # number of overall hits 1121system.cpu.l2cache.overall_hits::total 2265314 # number of overall hits 1122system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 1123system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 1124system.cpu.l2cache.ReadReq_misses::cpu.inst 12884 # number of ReadReq misses 1125system.cpu.l2cache.ReadReq_misses::cpu.data 28341 # number of ReadReq misses 1126system.cpu.l2cache.ReadReq_misses::total 41232 # number of ReadReq misses 1127system.cpu.l2cache.UpgradeReq_misses::cpu.data 1356 # number of UpgradeReq misses 1128system.cpu.l2cache.UpgradeReq_misses::total 1356 # number of UpgradeReq misses 1129system.cpu.l2cache.ReadExReq_misses::cpu.data 113042 # number of ReadExReq misses 1130system.cpu.l2cache.ReadExReq_misses::total 113042 # number of ReadExReq misses 1131system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 1132system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 1133system.cpu.l2cache.demand_misses::cpu.inst 12884 # number of demand (read+write) misses 1134system.cpu.l2cache.demand_misses::cpu.data 141383 # number of demand (read+write) misses 1135system.cpu.l2cache.demand_misses::total 154274 # number of demand (read+write) misses 1136system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 1137system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 1138system.cpu.l2cache.overall_misses::cpu.inst 12884 # number of overall misses 1139system.cpu.l2cache.overall_misses::cpu.data 141383 # number of overall misses 1140system.cpu.l2cache.overall_misses::total 154274 # number of overall misses 1141system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 136750 # number of ReadReq miss cycles 1142system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 347500 # number of ReadReq miss cycles 1143system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 979557242 # number of ReadReq miss cycles 1144system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2186954200 # number of ReadReq miss cycles 1145system.cpu.l2cache.ReadReq_miss_latency::total 3166995692 # number of ReadReq miss cycles 1146system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16260363 # number of UpgradeReq miss cycles 1147system.cpu.l2cache.UpgradeReq_miss_latency::total 16260363 # number of UpgradeReq miss cycles 1148system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7957275400 # number of ReadExReq miss cycles 1149system.cpu.l2cache.ReadExReq_miss_latency::total 7957275400 # number of ReadExReq miss cycles 1150system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 136750 # number of demand (read+write) miss cycles 1151system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 347500 # number of demand (read+write) miss cycles 1152system.cpu.l2cache.demand_miss_latency::cpu.inst 979557242 # number of demand (read+write) miss cycles 1153system.cpu.l2cache.demand_miss_latency::cpu.data 10144229600 # number of demand (read+write) miss cycles 1154system.cpu.l2cache.demand_miss_latency::total 11124271092 # number of demand (read+write) miss cycles 1155system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 136750 # number of overall miss cycles 1156system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 347500 # number of overall miss cycles 1157system.cpu.l2cache.overall_miss_latency::cpu.inst 979557242 # number of overall miss cycles 1158system.cpu.l2cache.overall_miss_latency::cpu.data 10144229600 # number of overall miss cycles 1159system.cpu.l2cache.overall_miss_latency::total 11124271092 # number of overall miss cycles 1160system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6742 # number of ReadReq accesses(hits+misses) 1161system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2908 # number of ReadReq accesses(hits+misses) 1162system.cpu.l2cache.ReadReq_accesses::cpu.inst 788596 # number of ReadReq accesses(hits+misses) 1163system.cpu.l2cache.ReadReq_accesses::cpu.data 1307548 # number of ReadReq accesses(hits+misses) 1164system.cpu.l2cache.ReadReq_accesses::total 2105794 # number of ReadReq accesses(hits+misses) 1165system.cpu.l2cache.Writeback_accesses::writebacks 1542700 # number of Writeback accesses(hits+misses) 1166system.cpu.l2cache.Writeback_accesses::total 1542700 # number of Writeback accesses(hits+misses) 1167system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1660 # number of UpgradeReq accesses(hits+misses) 1168system.cpu.l2cache.UpgradeReq_accesses::total 1660 # number of UpgradeReq accesses(hits+misses) 1169system.cpu.l2cache.ReadExReq_accesses::cpu.data 313794 # number of ReadExReq accesses(hits+misses) 1170system.cpu.l2cache.ReadExReq_accesses::total 313794 # number of ReadExReq accesses(hits+misses) 1171system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6742 # number of demand (read+write) accesses 1172system.cpu.l2cache.demand_accesses::cpu.itb.walker 2908 # number of demand (read+write) accesses 1173system.cpu.l2cache.demand_accesses::cpu.inst 788596 # number of demand (read+write) accesses 1174system.cpu.l2cache.demand_accesses::cpu.data 1621342 # number of demand (read+write) accesses 1175system.cpu.l2cache.demand_accesses::total 2419588 # number of demand (read+write) accesses 1176system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6742 # number of overall (read+write) accesses 1177system.cpu.l2cache.overall_accesses::cpu.itb.walker 2908 # number of overall (read+write) accesses 1178system.cpu.l2cache.overall_accesses::cpu.inst 788596 # number of overall (read+write) accesses 1179system.cpu.l2cache.overall_accesses::cpu.data 1621342 # number of overall (read+write) accesses 1180system.cpu.l2cache.overall_accesses::total 2419588 # number of overall (read+write) accesses 1181system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000297 # miss rate for ReadReq accesses 1182system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001719 # miss rate for ReadReq accesses 1183system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016338 # miss rate for ReadReq accesses 1184system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021675 # miss rate for ReadReq accesses 1185system.cpu.l2cache.ReadReq_miss_rate::total 0.019580 # miss rate for ReadReq accesses 1186system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.816867 # miss rate for UpgradeReq accesses 1187system.cpu.l2cache.UpgradeReq_miss_rate::total 0.816867 # miss rate for UpgradeReq accesses 1188system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360243 # miss rate for ReadExReq accesses 1189system.cpu.l2cache.ReadExReq_miss_rate::total 0.360243 # miss rate for ReadExReq accesses 1190system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000297 # miss rate for demand accesses 1191system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001719 # miss rate for demand accesses 1192system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016338 # miss rate for demand accesses 1193system.cpu.l2cache.demand_miss_rate::cpu.data 0.087201 # miss rate for demand accesses 1194system.cpu.l2cache.demand_miss_rate::total 0.063760 # miss rate for demand accesses 1195system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000297 # miss rate for overall accesses 1196system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001719 # miss rate for overall accesses 1197system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016338 # miss rate for overall accesses 1198system.cpu.l2cache.overall_miss_rate::cpu.data 0.087201 # miss rate for overall accesses 1199system.cpu.l2cache.overall_miss_rate::total 0.063760 # miss rate for overall accesses 1200system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68375 # average ReadReq miss latency 1201system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69500 # average ReadReq miss latency 1202system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76028.969419 # average ReadReq miss latency 1203system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77165.738682 # average ReadReq miss latency 1204system.cpu.l2cache.ReadReq_avg_miss_latency::total 76809.169868 # average ReadReq miss latency 1205system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11991.418142 # average UpgradeReq miss latency 1206system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11991.418142 # average UpgradeReq miss latency 1207system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70392.202898 # average ReadExReq miss latency 1208system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70392.202898 # average ReadExReq miss latency 1209system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68375 # average overall miss latency 1210system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69500 # average overall miss latency 1211system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76028.969419 # average overall miss latency 1212system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71749.995403 # average overall miss latency 1213system.cpu.l2cache.demand_avg_miss_latency::total 72107.231886 # average overall miss latency 1214system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68375 # average overall miss latency 1215system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69500 # average overall miss latency 1216system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76028.969419 # average overall miss latency 1217system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71749.995403 # average overall miss latency 1218system.cpu.l2cache.overall_avg_miss_latency::total 72107.231886 # average overall miss latency 1219system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1220system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1221system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1222system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1223system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1224system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1225system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1226system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1227system.cpu.l2cache.writebacks::writebacks 80066 # number of writebacks 1228system.cpu.l2cache.writebacks::total 80066 # number of writebacks 1229system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 2 # number of ReadReq MSHR misses 1230system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 1231system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12884 # number of ReadReq MSHR misses 1232system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28341 # number of ReadReq MSHR misses 1233system.cpu.l2cache.ReadReq_mshr_misses::total 41232 # number of ReadReq MSHR misses 1234system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1356 # number of UpgradeReq MSHR misses 1235system.cpu.l2cache.UpgradeReq_mshr_misses::total 1356 # number of UpgradeReq MSHR misses 1236system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113042 # number of ReadExReq MSHR misses 1237system.cpu.l2cache.ReadExReq_mshr_misses::total 113042 # number of ReadExReq MSHR misses 1238system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 2 # number of demand (read+write) MSHR misses 1239system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 1240system.cpu.l2cache.demand_mshr_misses::cpu.inst 12884 # number of demand (read+write) MSHR misses 1241system.cpu.l2cache.demand_mshr_misses::cpu.data 141383 # number of demand (read+write) MSHR misses 1242system.cpu.l2cache.demand_mshr_misses::total 154274 # number of demand (read+write) MSHR misses 1243system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 2 # number of overall MSHR misses 1244system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 1245system.cpu.l2cache.overall_mshr_misses::cpu.inst 12884 # number of overall MSHR misses 1246system.cpu.l2cache.overall_mshr_misses::cpu.data 141383 # number of overall MSHR misses 1247system.cpu.l2cache.overall_mshr_misses::total 154274 # number of overall MSHR misses 1248system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 111250 # number of ReadReq MSHR miss cycles 1249system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 285000 # number of ReadReq MSHR miss cycles 1250system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 818022758 # number of ReadReq MSHR miss cycles 1251system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1831787800 # number of ReadReq MSHR miss cycles 1252system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2650206808 # number of ReadReq MSHR miss cycles 1253system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14478338 # number of UpgradeReq MSHR miss cycles 1254system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14478338 # number of UpgradeReq MSHR miss cycles 1255system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6543285600 # number of ReadExReq MSHR miss cycles 1256system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6543285600 # number of ReadExReq MSHR miss cycles 1257system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 111250 # number of demand (read+write) MSHR miss cycles 1258system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 285000 # number of demand (read+write) MSHR miss cycles 1259system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 818022758 # number of demand (read+write) MSHR miss cycles 1260system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8375073400 # number of demand (read+write) MSHR miss cycles 1261system.cpu.l2cache.demand_mshr_miss_latency::total 9193492408 # number of demand (read+write) MSHR miss cycles 1262system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 111250 # number of overall MSHR miss cycles 1263system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 285000 # number of overall MSHR miss cycles 1264system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 818022758 # number of overall MSHR miss cycles 1265system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8375073400 # number of overall MSHR miss cycles 1266system.cpu.l2cache.overall_mshr_miss_latency::total 9193492408 # number of overall MSHR miss cycles 1267system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655869500 # number of ReadReq MSHR uncacheable cycles 1268system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655869500 # number of ReadReq MSHR uncacheable cycles 1269system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370854000 # number of WriteReq MSHR uncacheable cycles 1270system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370854000 # number of WriteReq MSHR uncacheable cycles 1271system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026723500 # number of overall MSHR uncacheable cycles 1272system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026723500 # number of overall MSHR uncacheable cycles 1273system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for ReadReq accesses 1274system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for ReadReq accesses 1275system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for ReadReq accesses 1276system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021675 # mshr miss rate for ReadReq accesses 1277system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019580 # mshr miss rate for ReadReq accesses 1278system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.816867 # mshr miss rate for UpgradeReq accesses 1279system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.816867 # mshr miss rate for UpgradeReq accesses 1280system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360243 # mshr miss rate for ReadExReq accesses 1281system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360243 # mshr miss rate for ReadExReq accesses 1282system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for demand accesses 1283system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for demand accesses 1284system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for demand accesses 1285system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087201 # mshr miss rate for demand accesses 1286system.cpu.l2cache.demand_mshr_miss_rate::total 0.063760 # mshr miss rate for demand accesses 1287system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000297 # mshr miss rate for overall accesses 1288system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001719 # mshr miss rate for overall accesses 1289system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016338 # mshr miss rate for overall accesses 1290system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087201 # mshr miss rate for overall accesses 1291system.cpu.l2cache.overall_mshr_miss_rate::total 0.063760 # mshr miss rate for overall accesses 1292system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average ReadReq mshr miss latency 1293system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 57000 # average ReadReq mshr miss latency 1294system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63491.365880 # average ReadReq mshr miss latency 1295system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64633.844960 # average ReadReq mshr miss latency 1296system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64275.485254 # average ReadReq mshr miss latency 1297system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10677.240413 # average UpgradeReq mshr miss latency 1298system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10677.240413 # average UpgradeReq mshr miss latency 1299system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57883.668017 # average ReadExReq mshr miss latency 1300system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57883.668017 # average ReadExReq mshr miss latency 1301system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency 1302system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 57000 # average overall mshr miss latency 1303system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63491.365880 # average overall mshr miss latency 1304system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59236.778113 # average overall mshr miss latency 1305system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59591.975369 # average overall mshr miss latency 1306system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 55625 # average overall mshr miss latency 1307system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 57000 # average overall mshr miss latency 1308system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63491.365880 # average overall mshr miss latency 1309system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59236.778113 # average overall mshr miss latency 1310system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59591.975369 # average overall mshr miss latency 1311system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1312system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1313system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1314system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1315system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1316system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1317system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1318 1319---------- End Simulation Statistics ----------