1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.195162 # Number of seconds simulated
4sim_ticks 5195162021000 # Number of ticks simulated
5final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 434432 # Simulator instruction rate (inst/s)
8host_op_rate 837466 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 17594801878 # Simulator tick rate (ticks/s)
10host_mem_usage 611684 # Number of bytes of host memory used
11host_seconds 295.27 # Real time elapsed on the host
12sim_insts 128273373 # Number of instructions simulated
13sim_ops 247275988 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9012160 # Number of bytes read from this memory
19system.physmem.bytes_read::total 12697600 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 8123136 # Number of bytes written to this memory
23system.physmem.bytes_written::total 8123136 # Number of bytes written to this memory
24system.physmem.num_reads::pc.south_bridge.ide 44708 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.data 140815 # Number of read requests responded to by this memory
29system.physmem.num_reads::total 198400 # Number of read requests responded to by this memory
30system.physmem.num_writes::writebacks 126924 # Number of write requests responded to by this memory
31system.physmem.num_writes::total 126924 # Number of write requests responded to by this memory
32system.physmem.bw_read::pc.south_bridge.ide 550765 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.inst 158560 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.data 1734722 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::total 2444120 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_inst_read::cpu.inst 158560 # Instruction read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::total 158560 # Instruction read bandwidth from this memory (bytes/s)
40system.physmem.bw_write::writebacks 1563596 # Write bandwidth from this memory (bytes/s)
41system.physmem.bw_write::total 1563596 # Write bandwidth from this memory (bytes/s)
42system.physmem.bw_total::writebacks 1563596 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::pc.south_bridge.ide 550765 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.inst 158560 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.data 1734722 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.readReqs 198400 # Total number of read requests seen
50system.physmem.writeReqs 126924 # Total number of write requests seen
51system.physmem.cpureqs 326952 # Reqs generatd by CPU via cache - shady
52system.physmem.bytesRead 12697600 # Total number of bytes read from memory
53system.physmem.bytesWritten 8123136 # Total number of bytes written to memory
54system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize()
55system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize()
56system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q
57system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed
58system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::2 12234 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::6 12566 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::7 12719 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::8 12479 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::9 12349 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::10 12465 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::11 12500 # Track reads on a per bank basis
70system.physmem.perBankRdReqs::12 12468 # Track reads on a per bank basis
71system.physmem.perBankRdReqs::13 12050 # Track reads on a per bank basis
72system.physmem.perBankRdReqs::14 12371 # Track reads on a per bank basis
73system.physmem.perBankRdReqs::15 12574 # Track reads on a per bank basis
74system.physmem.perBankWrReqs::0 8012 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::1 7683 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::2 7790 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::3 8089 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::4 7865 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::5 7679 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::6 8084 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::7 8243 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::8 8069 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::9 7980 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::10 7953 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::11 7969 # Track writes on a per bank basis
86system.physmem.perBankWrReqs::12 7935 # Track writes on a per bank basis
87system.physmem.perBankWrReqs::13 7628 # Track writes on a per bank basis
88system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis
89system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis
90system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
91system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry
92system.physmem.totGap 5195161957500 # Total gap between requests
93system.physmem.readPktSize::0 0 # Categorize read packet sizes
94system.physmem.readPktSize::1 0 # Categorize read packet sizes
95system.physmem.readPktSize::2 0 # Categorize read packet sizes
96system.physmem.readPktSize::3 0 # Categorize read packet sizes
97system.physmem.readPktSize::4 0 # Categorize read packet sizes
98system.physmem.readPktSize::5 0 # Categorize read packet sizes
99system.physmem.readPktSize::6 198400 # Categorize read packet sizes
100system.physmem.writePktSize::0 0 # Categorize write packet sizes
101system.physmem.writePktSize::1 0 # Categorize write packet sizes
102system.physmem.writePktSize::2 0 # Categorize write packet sizes
103system.physmem.writePktSize::3 0 # Categorize write packet sizes
104system.physmem.writePktSize::4 0 # Categorize write packet sizes
105system.physmem.writePktSize::5 0 # Categorize write packet sizes
106system.physmem.writePktSize::6 126924 # Categorize write packet sizes
107system.physmem.rdQLenPdf::0 155109 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::1 8773 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::2 6640 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::3 3418 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::4 3389 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::5 2825 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::6 2250 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::7 2164 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::8 2085 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::9 2006 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::10 1319 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::11 1198 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::12 1104 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::13 1044 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::14 968 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::15 978 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::16 1114 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::17 1077 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::18 526 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::19 320 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
139system.physmem.wrQLenPdf::0 4196 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::1 4527 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::2 5315 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::4 5480 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::6 5513 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::7 5513 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::8 5514 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::12 5518 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::13 5518 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::14 5518 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::15 5518 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::16 5518 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::17 5518 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::18 5518 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::19 5518 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::23 1323 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::24 992 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::25 204 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::27 39 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::29 6 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
171system.physmem.totQLat 4118897499 # Total cycles spent in queuing delays
172system.physmem.totMemAccLat 7915241249 # Sum of mem lat for all requests
173system.physmem.totBusLat 991715000 # Total cycles spent in databus access
174system.physmem.totBankLat 2804628750 # Total cycles spent in bank access
175system.physmem.avgQLat 20766.54 # Average queueing delay per request
176system.physmem.avgBankLat 14140.30 # Average bank access latency per request
177system.physmem.avgBusLat 5000.00 # Average bus latency per request
178system.physmem.avgMemAccLat 39906.83 # Average memory access latency
179system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
180system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
181system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
182system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
184system.physmem.busUtil 0.03 # Data bus utilization in percentage
185system.physmem.avgRdQLen 0.00 # Average read queue length over time
186system.physmem.avgWrQLen 12.66 # Average write queue length over time
187system.physmem.readRowHits 175593 # Number of row buffer hits during reads
188system.physmem.writeRowHits 94810 # Number of row buffer hits during writes
189system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads
190system.physmem.writeRowHitRate 74.70 # Row buffer hit rate for writes
191system.physmem.avgGap 15969193.66 # Average gap between requests
192system.iocache.replacements 47509 # number of replacements
193system.iocache.tagsinuse 0.124742 # Cycle average of tags in use
194system.iocache.total_refs 0 # Total number of references to valid blocks.
195system.iocache.sampled_refs 47525 # Sample count of references to valid blocks.
196system.iocache.avg_refs 0 # Average number of references to valid blocks.
197system.iocache.warmup_cycle 5044527520000 # Cycle when the warmup percentage was hit.
198system.iocache.occ_blocks::pc.south_bridge.ide 0.124742 # Average occupied blocks per requestor
199system.iocache.occ_percent::pc.south_bridge.ide 0.007796 # Average percentage of cache occupancy
200system.iocache.occ_percent::total 0.007796 # Average percentage of cache occupancy
201system.iocache.ReadReq_misses::pc.south_bridge.ide 844 # number of ReadReq misses
202system.iocache.ReadReq_misses::total 844 # number of ReadReq misses
203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
205system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses
206system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
207system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses
208system.iocache.overall_misses::total 47564 # number of overall misses
209system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137986397 # number of ReadReq miss cycles
210system.iocache.ReadReq_miss_latency::total 137986397 # number of ReadReq miss cycles
211system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10732360679 # number of WriteReq miss cycles
212system.iocache.WriteReq_miss_latency::total 10732360679 # number of WriteReq miss cycles
213system.iocache.demand_miss_latency::pc.south_bridge.ide 10870347076 # number of demand (read+write) miss cycles
214system.iocache.demand_miss_latency::total 10870347076 # number of demand (read+write) miss cycles
215system.iocache.overall_miss_latency::pc.south_bridge.ide 10870347076 # number of overall miss cycles
216system.iocache.overall_miss_latency::total 10870347076 # number of overall miss cycles
217system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
218system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
219system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
220system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
221system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses
222system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses
223system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses
224system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses
225system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
226system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
227system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
228system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
229system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
230system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
231system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
232system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
233system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 163490.991706 # average ReadReq miss latency
234system.iocache.ReadReq_avg_miss_latency::total 163490.991706 # average ReadReq miss latency
235system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229716.624122 # average WriteReq miss latency
236system.iocache.WriteReq_avg_miss_latency::total 229716.624122 # average WriteReq miss latency
237system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228541.482550 # average overall miss latency
238system.iocache.demand_avg_miss_latency::total 228541.482550 # average overall miss latency
239system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228541.482550 # average overall miss latency
240system.iocache.overall_avg_miss_latency::total 228541.482550 # average overall miss latency
241system.iocache.blocked_cycles::no_mshrs 175903 # number of cycles access was blocked
242system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
243system.iocache.blocked::no_mshrs 16290 # number of cycles access was blocked
244system.iocache.blocked::no_targets 0 # number of cycles access was blocked
245system.iocache.avg_blocked_cycles::no_mshrs 10.798220 # average number of cycles each access was blocked
246system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
247system.iocache.fast_writes 0 # number of fast writes performed
248system.iocache.cache_copies 0 # number of cache copies performed
249system.iocache.writebacks::writebacks 46667 # number of writebacks
250system.iocache.writebacks::total 46667 # number of writebacks
251system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses
252system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses
253system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
254system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
255system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses
256system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses
257system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses
258system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses
259system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94077427 # number of ReadReq MSHR miss cycles
260system.iocache.ReadReq_mshr_miss_latency::total 94077427 # number of ReadReq MSHR miss cycles
261system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8301562585 # number of WriteReq MSHR miss cycles
262system.iocache.WriteReq_mshr_miss_latency::total 8301562585 # number of WriteReq MSHR miss cycles
263system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8395640012 # number of demand (read+write) MSHR miss cycles
264system.iocache.demand_mshr_miss_latency::total 8395640012 # number of demand (read+write) MSHR miss cycles
265system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8395640012 # number of overall MSHR miss cycles
266system.iocache.overall_mshr_miss_latency::total 8395640012 # number of overall MSHR miss cycles
267system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
268system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
269system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
270system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
271system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
272system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
273system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
274system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
275system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 111466.145735 # average ReadReq mshr miss latency
276system.iocache.ReadReq_avg_mshr_miss_latency::total 111466.145735 # average ReadReq mshr miss latency
277system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177687.555330 # average WriteReq mshr miss latency
278system.iocache.WriteReq_avg_mshr_miss_latency::total 177687.555330 # average WriteReq mshr miss latency
279system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176512.488689 # average overall mshr miss latency
280system.iocache.demand_avg_mshr_miss_latency::total 176512.488689 # average overall mshr miss latency
281system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176512.488689 # average overall mshr miss latency
282system.iocache.overall_avg_mshr_miss_latency::total 176512.488689 # average overall mshr miss latency
283system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
284system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
285system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
286system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
287system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
288system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
289system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
290system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
291system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
292system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
293system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
294system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
295system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
296system.cpu.numCycles 10390324042 # number of cpu cycles simulated
297system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
298system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
299system.cpu.committedInsts 128273373 # Number of instructions committed
300system.cpu.committedOps 247275988 # Number of ops (including micro ops) committed
301system.cpu.num_int_alu_accesses 232011695 # Number of integer alu accesses
302system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
303system.cpu.num_func_calls 0 # number of times a function call or return occured
304system.cpu.num_conditional_control_insts 23157364 # number of instructions that are conditional controls
305system.cpu.num_int_insts 232011695 # number of integer instructions
306system.cpu.num_fp_insts 0 # number of float instructions
307system.cpu.num_int_register_reads 567056109 # number of times the integer registers were read
308system.cpu.num_int_register_writes 293242196 # number of times the integer registers were written
309system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
310system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
311system.cpu.num_mem_refs 22232145 # number of memory refs
312system.cpu.num_load_insts 13871789 # Number of load instructions
313system.cpu.num_store_insts 8360356 # Number of store instructions
314system.cpu.num_idle_cycles 9789660715.998116 # Number of idle cycles
315system.cpu.num_busy_cycles 600663326.001884 # Number of busy cycles
316system.cpu.not_idle_fraction 0.057810 # Percentage of non-idle cycles
317system.cpu.idle_fraction 0.942190 # Percentage of idle cycles
318system.cpu.kern.inst.arm 0 # number of arm instructions executed
319system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
320system.cpu.icache.replacements 791527 # number of replacements
321system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use
322system.cpu.icache.total_refs 144497724 # Total number of references to valid blocks.
323system.cpu.icache.sampled_refs 792039 # Sample count of references to valid blocks.
324system.cpu.icache.avg_refs 182.437638 # Average number of references to valid blocks.
325system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit.
326system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor
327system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy
328system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy
329system.cpu.icache.ReadReq_hits::cpu.inst 144497724 # number of ReadReq hits
330system.cpu.icache.ReadReq_hits::total 144497724 # number of ReadReq hits
331system.cpu.icache.demand_hits::cpu.inst 144497724 # number of demand (read+write) hits
332system.cpu.icache.demand_hits::total 144497724 # number of demand (read+write) hits
333system.cpu.icache.overall_hits::cpu.inst 144497724 # number of overall hits
334system.cpu.icache.overall_hits::total 144497724 # number of overall hits
335system.cpu.icache.ReadReq_misses::cpu.inst 792046 # number of ReadReq misses
336system.cpu.icache.ReadReq_misses::total 792046 # number of ReadReq misses
337system.cpu.icache.demand_misses::cpu.inst 792046 # number of demand (read+write) misses
338system.cpu.icache.demand_misses::total 792046 # number of demand (read+write) misses
339system.cpu.icache.overall_misses::cpu.inst 792046 # number of overall misses
340system.cpu.icache.overall_misses::total 792046 # number of overall misses
341system.cpu.icache.ReadReq_miss_latency::cpu.inst 10958971500 # number of ReadReq miss cycles
342system.cpu.icache.ReadReq_miss_latency::total 10958971500 # number of ReadReq miss cycles
343system.cpu.icache.demand_miss_latency::cpu.inst 10958971500 # number of demand (read+write) miss cycles
344system.cpu.icache.demand_miss_latency::total 10958971500 # number of demand (read+write) miss cycles
345system.cpu.icache.overall_miss_latency::cpu.inst 10958971500 # number of overall miss cycles
346system.cpu.icache.overall_miss_latency::total 10958971500 # number of overall miss cycles
347system.cpu.icache.ReadReq_accesses::cpu.inst 145289770 # number of ReadReq accesses(hits+misses)
348system.cpu.icache.ReadReq_accesses::total 145289770 # number of ReadReq accesses(hits+misses)
349system.cpu.icache.demand_accesses::cpu.inst 145289770 # number of demand (read+write) accesses
350system.cpu.icache.demand_accesses::total 145289770 # number of demand (read+write) accesses
351system.cpu.icache.overall_accesses::cpu.inst 145289770 # number of overall (read+write) accesses
352system.cpu.icache.overall_accesses::total 145289770 # number of overall (read+write) accesses
353system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses
354system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses
355system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses
356system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses
357system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses
358system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses
359system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13836.281605 # average ReadReq miss latency
360system.cpu.icache.ReadReq_avg_miss_latency::total 13836.281605 # average ReadReq miss latency
361system.cpu.icache.demand_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency
362system.cpu.icache.demand_avg_miss_latency::total 13836.281605 # average overall miss latency
363system.cpu.icache.overall_avg_miss_latency::cpu.inst 13836.281605 # average overall miss latency
364system.cpu.icache.overall_avg_miss_latency::total 13836.281605 # average overall miss latency
365system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
366system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
367system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
368system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
369system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
370system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
371system.cpu.icache.fast_writes 0 # number of fast writes performed
372system.cpu.icache.cache_copies 0 # number of cache copies performed
373system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792046 # number of ReadReq MSHR misses
374system.cpu.icache.ReadReq_mshr_misses::total 792046 # number of ReadReq MSHR misses
375system.cpu.icache.demand_mshr_misses::cpu.inst 792046 # number of demand (read+write) MSHR misses
376system.cpu.icache.demand_mshr_misses::total 792046 # number of demand (read+write) MSHR misses
377system.cpu.icache.overall_mshr_misses::cpu.inst 792046 # number of overall MSHR misses
378system.cpu.icache.overall_mshr_misses::total 792046 # number of overall MSHR misses
379system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9374879500 # number of ReadReq MSHR miss cycles
380system.cpu.icache.ReadReq_mshr_miss_latency::total 9374879500 # number of ReadReq MSHR miss cycles
381system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9374879500 # number of demand (read+write) MSHR miss cycles
382system.cpu.icache.demand_mshr_miss_latency::total 9374879500 # number of demand (read+write) MSHR miss cycles
383system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9374879500 # number of overall MSHR miss cycles
384system.cpu.icache.overall_mshr_miss_latency::total 9374879500 # number of overall MSHR miss cycles
385system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses
386system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses
387system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses
388system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses
389system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for overall accesses
390system.cpu.icache.overall_mshr_miss_rate::total 0.005451 # mshr miss rate for overall accesses
391system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11836.281605 # average ReadReq mshr miss latency
392system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11836.281605 # average ReadReq mshr miss latency
393system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency
394system.cpu.icache.demand_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency
395system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11836.281605 # average overall mshr miss latency
396system.cpu.icache.overall_avg_mshr_miss_latency::total 11836.281605 # average overall mshr miss latency
397system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
398system.cpu.itb_walker_cache.replacements 3425 # number of replacements
399system.cpu.itb_walker_cache.tagsinuse 3.077880 # Cycle average of tags in use
400system.cpu.itb_walker_cache.total_refs 8006 # Total number of references to valid blocks.
401system.cpu.itb_walker_cache.sampled_refs 3437 # Sample count of references to valid blocks.
402system.cpu.itb_walker_cache.avg_refs 2.329357 # Average number of references to valid blocks.
403system.cpu.itb_walker_cache.warmup_cycle 5164120857000 # Cycle when the warmup percentage was hit.
404system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077880 # Average occupied blocks per requestor
405system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.192367 # Average percentage of cache occupancy
406system.cpu.itb_walker_cache.occ_percent::total 0.192367 # Average percentage of cache occupancy
407system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8004 # number of ReadReq hits
408system.cpu.itb_walker_cache.ReadReq_hits::total 8004 # number of ReadReq hits
409system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
410system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
411system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8006 # number of demand (read+write) hits
412system.cpu.itb_walker_cache.demand_hits::total 8006 # number of demand (read+write) hits
413system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8006 # number of overall hits
414system.cpu.itb_walker_cache.overall_hits::total 8006 # number of overall hits
415system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4287 # number of ReadReq misses
416system.cpu.itb_walker_cache.ReadReq_misses::total 4287 # number of ReadReq misses
417system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4287 # number of demand (read+write) misses
418system.cpu.itb_walker_cache.demand_misses::total 4287 # number of demand (read+write) misses
419system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4287 # number of overall misses
420system.cpu.itb_walker_cache.overall_misses::total 4287 # number of overall misses
421system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42274000 # number of ReadReq miss cycles
422system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42274000 # number of ReadReq miss cycles
423system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42274000 # number of demand (read+write) miss cycles
424system.cpu.itb_walker_cache.demand_miss_latency::total 42274000 # number of demand (read+write) miss cycles
425system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42274000 # number of overall miss cycles
426system.cpu.itb_walker_cache.overall_miss_latency::total 42274000 # number of overall miss cycles
427system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12291 # number of ReadReq accesses(hits+misses)
428system.cpu.itb_walker_cache.ReadReq_accesses::total 12291 # number of ReadReq accesses(hits+misses)
429system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
430system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
431system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12293 # number of demand (read+write) accesses
432system.cpu.itb_walker_cache.demand_accesses::total 12293 # number of demand (read+write) accesses
433system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12293 # number of overall (read+write) accesses
434system.cpu.itb_walker_cache.overall_accesses::total 12293 # number of overall (read+write) accesses
435system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.348792 # miss rate for ReadReq accesses
436system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.348792 # miss rate for ReadReq accesses
437system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.348735 # miss rate for demand accesses
438system.cpu.itb_walker_cache.demand_miss_rate::total 0.348735 # miss rate for demand accesses
439system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.348735 # miss rate for overall accesses
440system.cpu.itb_walker_cache.overall_miss_rate::total 0.348735 # miss rate for overall accesses
441system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9860.975041 # average ReadReq miss latency
442system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9860.975041 # average ReadReq miss latency
443system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency
444system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9860.975041 # average overall miss latency
445system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9860.975041 # average overall miss latency
446system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9860.975041 # average overall miss latency
447system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
448system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
449system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
450system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
451system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
452system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
453system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
454system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
455system.cpu.itb_walker_cache.writebacks::writebacks 641 # number of writebacks
456system.cpu.itb_walker_cache.writebacks::total 641 # number of writebacks
457system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4287 # number of ReadReq MSHR misses
458system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4287 # number of ReadReq MSHR misses
459system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4287 # number of demand (read+write) MSHR misses
460system.cpu.itb_walker_cache.demand_mshr_misses::total 4287 # number of demand (read+write) MSHR misses
461system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4287 # number of overall MSHR misses
462system.cpu.itb_walker_cache.overall_mshr_misses::total 4287 # number of overall MSHR misses
463system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33700000 # number of ReadReq MSHR miss cycles
464system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33700000 # number of ReadReq MSHR miss cycles
465system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33700000 # number of demand (read+write) MSHR miss cycles
466system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33700000 # number of demand (read+write) MSHR miss cycles
467system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33700000 # number of overall MSHR miss cycles
468system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33700000 # number of overall MSHR miss cycles
469system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.348792 # mshr miss rate for ReadReq accesses
470system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.348792 # mshr miss rate for ReadReq accesses
471system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for demand accesses
472system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.348735 # mshr miss rate for demand accesses
473system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.348735 # mshr miss rate for overall accesses
474system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.348735 # mshr miss rate for overall accesses
475system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average ReadReq mshr miss latency
476system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7860.975041 # average ReadReq mshr miss latency
477system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency
478system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency
479system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency
480system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency
481system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
482system.cpu.dtb_walker_cache.replacements 7539 # number of replacements
483system.cpu.dtb_walker_cache.tagsinuse 5.062514 # Cycle average of tags in use
484system.cpu.dtb_walker_cache.total_refs 13178 # Total number of references to valid blocks.
485system.cpu.dtb_walker_cache.sampled_refs 7553 # Sample count of references to valid blocks.
486system.cpu.dtb_walker_cache.avg_refs 1.744737 # Average number of references to valid blocks.
487system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit.
488system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062514 # Average occupied blocks per requestor
489system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy
490system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy
491system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13180 # number of ReadReq hits
492system.cpu.dtb_walker_cache.ReadReq_hits::total 13180 # number of ReadReq hits
493system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13180 # number of demand (read+write) hits
494system.cpu.dtb_walker_cache.demand_hits::total 13180 # number of demand (read+write) hits
495system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13180 # number of overall hits
496system.cpu.dtb_walker_cache.overall_hits::total 13180 # number of overall hits
497system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8726 # number of ReadReq misses
498system.cpu.dtb_walker_cache.ReadReq_misses::total 8726 # number of ReadReq misses
499system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8726 # number of demand (read+write) misses
500system.cpu.dtb_walker_cache.demand_misses::total 8726 # number of demand (read+write) misses
501system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8726 # number of overall misses
502system.cpu.dtb_walker_cache.overall_misses::total 8726 # number of overall misses
503system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92094500 # number of ReadReq miss cycles
504system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92094500 # number of ReadReq miss cycles
505system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92094500 # number of demand (read+write) miss cycles
506system.cpu.dtb_walker_cache.demand_miss_latency::total 92094500 # number of demand (read+write) miss cycles
507system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92094500 # number of overall miss cycles
508system.cpu.dtb_walker_cache.overall_miss_latency::total 92094500 # number of overall miss cycles
509system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21906 # number of ReadReq accesses(hits+misses)
510system.cpu.dtb_walker_cache.ReadReq_accesses::total 21906 # number of ReadReq accesses(hits+misses)
511system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21906 # number of demand (read+write) accesses
512system.cpu.dtb_walker_cache.demand_accesses::total 21906 # number of demand (read+write) accesses
513system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21906 # number of overall (read+write) accesses
514system.cpu.dtb_walker_cache.overall_accesses::total 21906 # number of overall (read+write) accesses
515system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398338 # miss rate for ReadReq accesses
516system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398338 # miss rate for ReadReq accesses
517system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398338 # miss rate for demand accesses
518system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398338 # miss rate for demand accesses
519system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398338 # miss rate for overall accesses
520system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398338 # miss rate for overall accesses
521system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10554.033922 # average ReadReq miss latency
522system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10554.033922 # average ReadReq miss latency
523system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency
524system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10554.033922 # average overall miss latency
525system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10554.033922 # average overall miss latency
526system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10554.033922 # average overall miss latency
527system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
528system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
529system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
530system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
531system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
532system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
533system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
534system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
535system.cpu.dtb_walker_cache.writebacks::writebacks 2713 # number of writebacks
536system.cpu.dtb_walker_cache.writebacks::total 2713 # number of writebacks
537system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8726 # number of ReadReq MSHR misses
538system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8726 # number of ReadReq MSHR misses
539system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8726 # number of demand (read+write) MSHR misses
540system.cpu.dtb_walker_cache.demand_mshr_misses::total 8726 # number of demand (read+write) MSHR misses
541system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8726 # number of overall MSHR misses
542system.cpu.dtb_walker_cache.overall_mshr_misses::total 8726 # number of overall MSHR misses
543system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74642500 # number of ReadReq MSHR miss cycles
544system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74642500 # number of ReadReq MSHR miss cycles
545system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74642500 # number of demand (read+write) MSHR miss cycles
546system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74642500 # number of demand (read+write) MSHR miss cycles
547system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74642500 # number of overall MSHR miss cycles
548system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74642500 # number of overall MSHR miss cycles
549system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for ReadReq accesses
550system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398338 # mshr miss rate for ReadReq accesses
551system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for demand accesses
552system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398338 # mshr miss rate for demand accesses
553system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398338 # mshr miss rate for overall accesses
554system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398338 # mshr miss rate for overall accesses
555system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average ReadReq mshr miss latency
556system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8554.033922 # average ReadReq mshr miss latency
557system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency
558system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency
559system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8554.033922 # average overall mshr miss latency
560system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8554.033922 # average overall mshr miss latency
561system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
562system.cpu.dcache.replacements 1618797 # number of replacements
563system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use
564system.cpu.dcache.total_refs 20025896 # Total number of references to valid blocks.
565system.cpu.dcache.sampled_refs 1619309 # Sample count of references to valid blocks.
566system.cpu.dcache.avg_refs 12.366939 # Average number of references to valid blocks.
567system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit.
568system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor
569system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
570system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
571system.cpu.dcache.ReadReq_hits::cpu.data 11988260 # number of ReadReq hits
572system.cpu.dcache.ReadReq_hits::total 11988260 # number of ReadReq hits
573system.cpu.dcache.WriteReq_hits::cpu.data 8035474 # number of WriteReq hits
574system.cpu.dcache.WriteReq_hits::total 8035474 # number of WriteReq hits
575system.cpu.dcache.demand_hits::cpu.data 20023734 # number of demand (read+write) hits
576system.cpu.dcache.demand_hits::total 20023734 # number of demand (read+write) hits
577system.cpu.dcache.overall_hits::cpu.data 20023734 # number of overall hits
578system.cpu.dcache.overall_hits::total 20023734 # number of overall hits
579system.cpu.dcache.ReadReq_misses::cpu.data 1306617 # number of ReadReq misses
580system.cpu.dcache.ReadReq_misses::total 1306617 # number of ReadReq misses
581system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses
582system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses
583system.cpu.dcache.demand_misses::cpu.data 1621505 # number of demand (read+write) misses
584system.cpu.dcache.demand_misses::total 1621505 # number of demand (read+write) misses
585system.cpu.dcache.overall_misses::cpu.data 1621505 # number of overall misses
586system.cpu.dcache.overall_misses::total 1621505 # number of overall misses
587system.cpu.dcache.ReadReq_miss_latency::cpu.data 18345510500 # number of ReadReq miss cycles
588system.cpu.dcache.ReadReq_miss_latency::total 18345510500 # number of ReadReq miss cycles
589system.cpu.dcache.WriteReq_miss_latency::cpu.data 8557598000 # number of WriteReq miss cycles
590system.cpu.dcache.WriteReq_miss_latency::total 8557598000 # number of WriteReq miss cycles
591system.cpu.dcache.demand_miss_latency::cpu.data 26903108500 # number of demand (read+write) miss cycles
592system.cpu.dcache.demand_miss_latency::total 26903108500 # number of demand (read+write) miss cycles
593system.cpu.dcache.overall_miss_latency::cpu.data 26903108500 # number of overall miss cycles
594system.cpu.dcache.overall_miss_latency::total 26903108500 # number of overall miss cycles
595system.cpu.dcache.ReadReq_accesses::cpu.data 13294877 # number of ReadReq accesses(hits+misses)
596system.cpu.dcache.ReadReq_accesses::total 13294877 # number of ReadReq accesses(hits+misses)
597system.cpu.dcache.WriteReq_accesses::cpu.data 8350362 # number of WriteReq accesses(hits+misses)
598system.cpu.dcache.WriteReq_accesses::total 8350362 # number of WriteReq accesses(hits+misses)
599system.cpu.dcache.demand_accesses::cpu.data 21645239 # number of demand (read+write) accesses
600system.cpu.dcache.demand_accesses::total 21645239 # number of demand (read+write) accesses
601system.cpu.dcache.overall_accesses::cpu.data 21645239 # number of overall (read+write) accesses
602system.cpu.dcache.overall_accesses::total 21645239 # number of overall (read+write) accesses
603system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098280 # miss rate for ReadReq accesses
604system.cpu.dcache.ReadReq_miss_rate::total 0.098280 # miss rate for ReadReq accesses
605system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037710 # miss rate for WriteReq accesses
606system.cpu.dcache.WriteReq_miss_rate::total 0.037710 # miss rate for WriteReq accesses
607system.cpu.dcache.demand_miss_rate::cpu.data 0.074913 # miss rate for demand accesses
608system.cpu.dcache.demand_miss_rate::total 0.074913 # miss rate for demand accesses
609system.cpu.dcache.overall_miss_rate::cpu.data 0.074913 # miss rate for overall accesses
610system.cpu.dcache.overall_miss_rate::total 0.074913 # miss rate for overall accesses
611system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14040.465186 # average ReadReq miss latency
612system.cpu.dcache.ReadReq_avg_miss_latency::total 14040.465186 # average ReadReq miss latency
613system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27176.640583 # average WriteReq miss latency
614system.cpu.dcache.WriteReq_avg_miss_latency::total 27176.640583 # average WriteReq miss latency
615system.cpu.dcache.demand_avg_miss_latency::cpu.data 16591.443443 # average overall miss latency
616system.cpu.dcache.demand_avg_miss_latency::total 16591.443443 # average overall miss latency
617system.cpu.dcache.overall_avg_miss_latency::cpu.data 16591.443443 # average overall miss latency
618system.cpu.dcache.overall_avg_miss_latency::total 16591.443443 # average overall miss latency
619system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
620system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
621system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
622system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
623system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
624system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
625system.cpu.dcache.fast_writes 0 # number of fast writes performed
626system.cpu.dcache.cache_copies 0 # number of cache copies performed
627system.cpu.dcache.writebacks::writebacks 1536058 # number of writebacks
628system.cpu.dcache.writebacks::total 1536058 # number of writebacks
629system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1306617 # number of ReadReq MSHR misses
630system.cpu.dcache.ReadReq_mshr_misses::total 1306617 # number of ReadReq MSHR misses
631system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses
632system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses
633system.cpu.dcache.demand_mshr_misses::cpu.data 1621505 # number of demand (read+write) MSHR misses
634system.cpu.dcache.demand_mshr_misses::total 1621505 # number of demand (read+write) MSHR misses
635system.cpu.dcache.overall_mshr_misses::cpu.data 1621505 # number of overall MSHR misses
636system.cpu.dcache.overall_mshr_misses::total 1621505 # number of overall MSHR misses
637system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15732276500 # number of ReadReq MSHR miss cycles
638system.cpu.dcache.ReadReq_mshr_miss_latency::total 15732276500 # number of ReadReq MSHR miss cycles
639system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7927822000 # number of WriteReq MSHR miss cycles
640system.cpu.dcache.WriteReq_mshr_miss_latency::total 7927822000 # number of WriteReq MSHR miss cycles
641system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23660098500 # number of demand (read+write) MSHR miss cycles
642system.cpu.dcache.demand_mshr_miss_latency::total 23660098500 # number of demand (read+write) MSHR miss cycles
643system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23660098500 # number of overall MSHR miss cycles
644system.cpu.dcache.overall_mshr_miss_latency::total 23660098500 # number of overall MSHR miss cycles
645system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94145949000 # number of ReadReq MSHR uncacheable cycles
646system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94145949000 # number of ReadReq MSHR uncacheable cycles
647system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467833000 # number of WriteReq MSHR uncacheable cycles
648system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467833000 # number of WriteReq MSHR uncacheable cycles
649system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96613782000 # number of overall MSHR uncacheable cycles
650system.cpu.dcache.overall_mshr_uncacheable_latency::total 96613782000 # number of overall MSHR uncacheable cycles
651system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098280 # mshr miss rate for ReadReq accesses
652system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098280 # mshr miss rate for ReadReq accesses
653system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037710 # mshr miss rate for WriteReq accesses
654system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037710 # mshr miss rate for WriteReq accesses
655system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074913 # mshr miss rate for demand accesses
656system.cpu.dcache.demand_mshr_miss_rate::total 0.074913 # mshr miss rate for demand accesses
657system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074913 # mshr miss rate for overall accesses
658system.cpu.dcache.overall_mshr_miss_rate::total 0.074913 # mshr miss rate for overall accesses
659system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12040.465186 # average ReadReq mshr miss latency
660system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12040.465186 # average ReadReq mshr miss latency
661system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25176.640583 # average WriteReq mshr miss latency
662system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25176.640583 # average WriteReq mshr miss latency
663system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency
664system.cpu.dcache.demand_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency
665system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14591.443443 # average overall mshr miss latency
666system.cpu.dcache.overall_avg_mshr_miss_latency::total 14591.443443 # average overall mshr miss latency
667system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
668system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
669system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
670system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
671system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
672system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
673system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
674system.cpu.l2cache.replacements 86864 # number of replacements
675system.cpu.l2cache.tagsinuse 64770.428854 # Cycle average of tags in use
676system.cpu.l2cache.total_refs 3484759 # Total number of references to valid blocks.
677system.cpu.l2cache.sampled_refs 151631 # Sample count of references to valid blocks.
678system.cpu.l2cache.avg_refs 22.981837 # Average number of references to valid blocks.
679system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
680system.cpu.l2cache.occ_blocks::writebacks 50336.272506 # Average occupied blocks per requestor
681system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.007172 # Average occupied blocks per requestor
682system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140365 # Average occupied blocks per requestor
683system.cpu.l2cache.occ_blocks::cpu.inst 3358.130752 # Average occupied blocks per requestor
684system.cpu.l2cache.occ_blocks::cpu.data 11075.878059 # Average occupied blocks per requestor
685system.cpu.l2cache.occ_percent::writebacks 0.768071 # Average percentage of cache occupancy
686system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
687system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
688system.cpu.l2cache.occ_percent::cpu.inst 0.051241 # Average percentage of cache occupancy
689system.cpu.l2cache.occ_percent::cpu.data 0.169004 # Average percentage of cache occupancy
690system.cpu.l2cache.occ_percent::total 0.988318 # Average percentage of cache occupancy
691system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6347 # number of ReadReq hits
692system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2754 # number of ReadReq hits
693system.cpu.l2cache.ReadReq_hits::cpu.inst 779161 # number of ReadReq hits
694system.cpu.l2cache.ReadReq_hits::cpu.data 1277476 # number of ReadReq hits
695system.cpu.l2cache.ReadReq_hits::total 2065738 # number of ReadReq hits
696system.cpu.l2cache.Writeback_hits::writebacks 1539412 # number of Writeback hits
697system.cpu.l2cache.Writeback_hits::total 1539412 # number of Writeback hits
698system.cpu.l2cache.UpgradeReq_hits::cpu.data 293 # number of UpgradeReq hits
699system.cpu.l2cache.UpgradeReq_hits::total 293 # number of UpgradeReq hits
700system.cpu.l2cache.ReadExReq_hits::cpu.data 199364 # number of ReadExReq hits
701system.cpu.l2cache.ReadExReq_hits::total 199364 # number of ReadExReq hits
702system.cpu.l2cache.demand_hits::cpu.dtb.walker 6347 # number of demand (read+write) hits
703system.cpu.l2cache.demand_hits::cpu.itb.walker 2754 # number of demand (read+write) hits
704system.cpu.l2cache.demand_hits::cpu.inst 779161 # number of demand (read+write) hits
705system.cpu.l2cache.demand_hits::cpu.data 1476840 # number of demand (read+write) hits
706system.cpu.l2cache.demand_hits::total 2265102 # number of demand (read+write) hits
707system.cpu.l2cache.overall_hits::cpu.dtb.walker 6347 # number of overall hits
708system.cpu.l2cache.overall_hits::cpu.itb.walker 2754 # number of overall hits
709system.cpu.l2cache.overall_hits::cpu.inst 779161 # number of overall hits
710system.cpu.l2cache.overall_hits::cpu.data 1476840 # number of overall hits
711system.cpu.l2cache.overall_hits::total 2265102 # number of overall hits
712system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
713system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
714system.cpu.l2cache.ReadReq_misses::cpu.inst 12872 # number of ReadReq misses
715system.cpu.l2cache.ReadReq_misses::cpu.data 28385 # number of ReadReq misses
716system.cpu.l2cache.ReadReq_misses::total 41263 # number of ReadReq misses
717system.cpu.l2cache.UpgradeReq_misses::cpu.data 1364 # number of UpgradeReq misses
718system.cpu.l2cache.UpgradeReq_misses::total 1364 # number of UpgradeReq misses
719system.cpu.l2cache.ReadExReq_misses::cpu.data 113358 # number of ReadExReq misses
720system.cpu.l2cache.ReadExReq_misses::total 113358 # number of ReadExReq misses
721system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
722system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
723system.cpu.l2cache.demand_misses::cpu.inst 12872 # number of demand (read+write) misses
724system.cpu.l2cache.demand_misses::cpu.data 141743 # number of demand (read+write) misses
725system.cpu.l2cache.demand_misses::total 154621 # number of demand (read+write) misses
726system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
727system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
728system.cpu.l2cache.overall_misses::cpu.inst 12872 # number of overall misses
729system.cpu.l2cache.overall_misses::cpu.data 141743 # number of overall misses
730system.cpu.l2cache.overall_misses::total 154621 # number of overall misses
731system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 68500 # number of ReadReq miss cycles
732system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles
733system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 791210500 # number of ReadReq miss cycles
734system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1650142000 # number of ReadReq miss cycles
735system.cpu.l2cache.ReadReq_miss_latency::total 2441766000 # number of ReadReq miss cycles
736system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16179000 # number of UpgradeReq miss cycles
737system.cpu.l2cache.UpgradeReq_miss_latency::total 16179000 # number of UpgradeReq miss cycles
738system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5584232500 # number of ReadExReq miss cycles
739system.cpu.l2cache.ReadExReq_miss_latency::total 5584232500 # number of ReadExReq miss cycles
740system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 68500 # number of demand (read+write) miss cycles
741system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles
742system.cpu.l2cache.demand_miss_latency::cpu.inst 791210500 # number of demand (read+write) miss cycles
743system.cpu.l2cache.demand_miss_latency::cpu.data 7234374500 # number of demand (read+write) miss cycles
744system.cpu.l2cache.demand_miss_latency::total 8025998500 # number of demand (read+write) miss cycles
745system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 68500 # number of overall miss cycles
746system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles
747system.cpu.l2cache.overall_miss_latency::cpu.inst 791210500 # number of overall miss cycles
748system.cpu.l2cache.overall_miss_latency::cpu.data 7234374500 # number of overall miss cycles
749system.cpu.l2cache.overall_miss_latency::total 8025998500 # number of overall miss cycles
750system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6348 # number of ReadReq accesses(hits+misses)
751system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2759 # number of ReadReq accesses(hits+misses)
752system.cpu.l2cache.ReadReq_accesses::cpu.inst 792033 # number of ReadReq accesses(hits+misses)
753system.cpu.l2cache.ReadReq_accesses::cpu.data 1305861 # number of ReadReq accesses(hits+misses)
754system.cpu.l2cache.ReadReq_accesses::total 2107001 # number of ReadReq accesses(hits+misses)
755system.cpu.l2cache.Writeback_accesses::writebacks 1539412 # number of Writeback accesses(hits+misses)
756system.cpu.l2cache.Writeback_accesses::total 1539412 # number of Writeback accesses(hits+misses)
757system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1657 # number of UpgradeReq accesses(hits+misses)
758system.cpu.l2cache.UpgradeReq_accesses::total 1657 # number of UpgradeReq accesses(hits+misses)
759system.cpu.l2cache.ReadExReq_accesses::cpu.data 312722 # number of ReadExReq accesses(hits+misses)
760system.cpu.l2cache.ReadExReq_accesses::total 312722 # number of ReadExReq accesses(hits+misses)
761system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6348 # number of demand (read+write) accesses
762system.cpu.l2cache.demand_accesses::cpu.itb.walker 2759 # number of demand (read+write) accesses
763system.cpu.l2cache.demand_accesses::cpu.inst 792033 # number of demand (read+write) accesses
764system.cpu.l2cache.demand_accesses::cpu.data 1618583 # number of demand (read+write) accesses
765system.cpu.l2cache.demand_accesses::total 2419723 # number of demand (read+write) accesses
766system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6348 # number of overall (read+write) accesses
767system.cpu.l2cache.overall_accesses::cpu.itb.walker 2759 # number of overall (read+write) accesses
768system.cpu.l2cache.overall_accesses::cpu.inst 792033 # number of overall (read+write) accesses
769system.cpu.l2cache.overall_accesses::cpu.data 1618583 # number of overall (read+write) accesses
770system.cpu.l2cache.overall_accesses::total 2419723 # number of overall (read+write) accesses
771system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000158 # miss rate for ReadReq accesses
772system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001812 # miss rate for ReadReq accesses
773system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016252 # miss rate for ReadReq accesses
774system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021737 # miss rate for ReadReq accesses
775system.cpu.l2cache.ReadReq_miss_rate::total 0.019584 # miss rate for ReadReq accesses
776system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823174 # miss rate for UpgradeReq accesses
777system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823174 # miss rate for UpgradeReq accesses
778system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.362488 # miss rate for ReadExReq accesses
779system.cpu.l2cache.ReadExReq_miss_rate::total 0.362488 # miss rate for ReadExReq accesses
780system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000158 # miss rate for demand accesses
781system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001812 # miss rate for demand accesses
782system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016252 # miss rate for demand accesses
783system.cpu.l2cache.demand_miss_rate::cpu.data 0.087572 # miss rate for demand accesses
784system.cpu.l2cache.demand_miss_rate::total 0.063900 # miss rate for demand accesses
785system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000158 # miss rate for overall accesses
786system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001812 # miss rate for overall accesses
787system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016252 # miss rate for overall accesses
788system.cpu.l2cache.overall_miss_rate::cpu.data 0.087572 # miss rate for overall accesses
789system.cpu.l2cache.overall_miss_rate::total 0.063900 # miss rate for overall accesses
790system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 68500 # average ReadReq miss latency
791system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency
792system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61467.565258 # average ReadReq miss latency
793system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58134.296283 # average ReadReq miss latency
794system.cpu.l2cache.ReadReq_avg_miss_latency::total 59175.677968 # average ReadReq miss latency
795system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11861.436950 # average UpgradeReq miss latency
796system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11861.436950 # average UpgradeReq miss latency
797system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49261.917994 # average ReadExReq miss latency
798system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49261.917994 # average ReadExReq miss latency
799system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency
800system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
801system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61467.565258 # average overall miss latency
802system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51038.672104 # average overall miss latency
803system.cpu.l2cache.demand_avg_miss_latency::total 51907.557835 # average overall miss latency
804system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 68500 # average overall miss latency
805system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
806system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61467.565258 # average overall miss latency
807system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51038.672104 # average overall miss latency
808system.cpu.l2cache.overall_avg_miss_latency::total 51907.557835 # average overall miss latency
809system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
810system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
811system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
812system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
813system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
814system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
815system.cpu.l2cache.fast_writes 0 # number of fast writes performed
816system.cpu.l2cache.cache_copies 0 # number of cache copies performed
817system.cpu.l2cache.writebacks::writebacks 80257 # number of writebacks
818system.cpu.l2cache.writebacks::total 80257 # number of writebacks
819system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses
820system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
821system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12872 # number of ReadReq MSHR misses
822system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28385 # number of ReadReq MSHR misses
823system.cpu.l2cache.ReadReq_mshr_misses::total 41263 # number of ReadReq MSHR misses
824system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1364 # number of UpgradeReq MSHR misses
825system.cpu.l2cache.UpgradeReq_mshr_misses::total 1364 # number of UpgradeReq MSHR misses
826system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113358 # number of ReadExReq MSHR misses
827system.cpu.l2cache.ReadExReq_mshr_misses::total 113358 # number of ReadExReq MSHR misses
828system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
829system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
830system.cpu.l2cache.demand_mshr_misses::cpu.inst 12872 # number of demand (read+write) MSHR misses
831system.cpu.l2cache.demand_mshr_misses::cpu.data 141743 # number of demand (read+write) MSHR misses
832system.cpu.l2cache.demand_mshr_misses::total 154621 # number of demand (read+write) MSHR misses
833system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
834system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
835system.cpu.l2cache.overall_mshr_misses::cpu.inst 12872 # number of overall MSHR misses
836system.cpu.l2cache.overall_mshr_misses::cpu.data 141743 # number of overall MSHR misses
837system.cpu.l2cache.overall_mshr_misses::total 154621 # number of overall MSHR misses
838system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 56251 # number of ReadReq MSHR miss cycles
839system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281255 # number of ReadReq MSHR miss cycles
840system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 631288357 # number of ReadReq MSHR miss cycles
841system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1297548953 # number of ReadReq MSHR miss cycles
842system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1929174816 # number of ReadReq MSHR miss cycles
843system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14616845 # number of UpgradeReq MSHR miss cycles
844system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14616845 # number of UpgradeReq MSHR miss cycles
845system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4191303025 # number of ReadExReq MSHR miss cycles
846system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4191303025 # number of ReadExReq MSHR miss cycles
847system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles
848system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles
849system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 631288357 # number of demand (read+write) MSHR miss cycles
850system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5488851978 # number of demand (read+write) MSHR miss cycles
851system.cpu.l2cache.demand_mshr_miss_latency::total 6120477841 # number of demand (read+write) MSHR miss cycles
852system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 56251 # number of overall MSHR miss cycles
853system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles
854system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 631288357 # number of overall MSHR miss cycles
855system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5488851978 # number of overall MSHR miss cycles
856system.cpu.l2cache.overall_mshr_miss_latency::total 6120477841 # number of overall MSHR miss cycles
857system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86591175500 # number of ReadReq MSHR uncacheable cycles
858system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86591175500 # number of ReadReq MSHR uncacheable cycles
859system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2305022500 # number of WriteReq MSHR uncacheable cycles
860system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2305022500 # number of WriteReq MSHR uncacheable cycles
861system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88896198000 # number of overall MSHR uncacheable cycles
862system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88896198000 # number of overall MSHR uncacheable cycles
863system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for ReadReq accesses
864system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for ReadReq accesses
865system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for ReadReq accesses
866system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021737 # mshr miss rate for ReadReq accesses
867system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019584 # mshr miss rate for ReadReq accesses
868system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823174 # mshr miss rate for UpgradeReq accesses
869system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823174 # mshr miss rate for UpgradeReq accesses
870system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.362488 # mshr miss rate for ReadExReq accesses
871system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.362488 # mshr miss rate for ReadExReq accesses
872system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for demand accesses
873system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for demand accesses
874system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for demand accesses
875system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for demand accesses
876system.cpu.l2cache.demand_mshr_miss_rate::total 0.063900 # mshr miss rate for demand accesses
877system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000158 # mshr miss rate for overall accesses
878system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001812 # mshr miss rate for overall accesses
879system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016252 # mshr miss rate for overall accesses
880system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087572 # mshr miss rate for overall accesses
881system.cpu.l2cache.overall_mshr_miss_rate::total 0.063900 # mshr miss rate for overall accesses
882system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average ReadReq mshr miss latency
883system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency
884system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49043.533017 # average ReadReq mshr miss latency
885system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45712.487335 # average ReadReq mshr miss latency
886system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46753.140004 # average ReadReq mshr miss latency
887system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10716.162023 # average UpgradeReq mshr miss latency
888system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10716.162023 # average UpgradeReq mshr miss latency
889system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36974.038224 # average ReadExReq mshr miss latency
890system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36974.038224 # average ReadExReq mshr miss latency
891system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
892system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
893system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency
894system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency
895system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency
896system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
897system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
898system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency
899system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency
900system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency
901system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
902system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
903system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
904system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
905system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
906system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
907system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
908
909---------- End Simulation Statistics ----------