1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.195162 # Number of seconds simulated
4sim_ticks 5195162021000 # Number of ticks simulated
5final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 973985 # Simulator instruction rate (inst/s)
8host_op_rate 1877578 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 39447094407 # Simulator tick rate (ticks/s)
10host_mem_usage 612564 # Number of bytes of host memory used
11host_seconds 131.70 # Real time elapsed on the host
12sim_insts 128273348 # Number of instructions simulated
13sim_ops 247275973 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 9012160 # Number of bytes read from this memory
19system.physmem.bytes_read::total 12697600 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory

--- 21 unchanged lines hidden (view full) ---

43system.physmem.bw_total::pc.south_bridge.ide 550765 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.inst 158560 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.data 1734722 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.readReqs 198400 # Total number of read requests seen
50system.physmem.writeReqs 126924 # Total number of write requests seen
51system.physmem.cpureqs 331611 # Reqs generatd by CPU via cache - shady
52system.physmem.bytesRead 12697600 # Total number of bytes read from memory
53system.physmem.bytesWritten 8123136 # Total number of bytes written to memory
54system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize()
55system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize()
56system.physmem.servicedByWrQ 58 # Number of read reqs serviced by write Q
57system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed
58system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis

--- 32 unchanged lines hidden (view full) ---

92system.physmem.totGap 5195161957500 # Total gap between requests
93system.physmem.readPktSize::0 0 # Categorize read packet sizes
94system.physmem.readPktSize::1 0 # Categorize read packet sizes
95system.physmem.readPktSize::2 0 # Categorize read packet sizes
96system.physmem.readPktSize::3 0 # Categorize read packet sizes
97system.physmem.readPktSize::4 0 # Categorize read packet sizes
98system.physmem.readPktSize::5 0 # Categorize read packet sizes
99system.physmem.readPktSize::6 198400 # Categorize read packet sizes
100system.physmem.readPktSize::7 0 # Categorize read packet sizes
101system.physmem.readPktSize::8 0 # Categorize read packet sizes
102system.physmem.writePktSize::0 0 # categorize write packet sizes
103system.physmem.writePktSize::1 0 # categorize write packet sizes
104system.physmem.writePktSize::2 0 # categorize write packet sizes
105system.physmem.writePktSize::3 0 # categorize write packet sizes
106system.physmem.writePktSize::4 0 # categorize write packet sizes
107system.physmem.writePktSize::5 0 # categorize write packet sizes
108system.physmem.writePktSize::6 127557 # categorize write packet sizes
109system.physmem.writePktSize::7 0 # categorize write packet sizes
110system.physmem.writePktSize::8 0 # categorize write packet sizes
111system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
112system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
113system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
114system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
115system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
116system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
117system.physmem.neitherpktsize::6 1624 # categorize neither packet sizes
118system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
119system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
120system.physmem.rdQLenPdf::0 155111 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::1 8768 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::2 6671 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::3 3417 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::4 3399 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::5 2809 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::6 2248 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::7 2166 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::8 2070 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::9 2020 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::10 1315 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::11 1213 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::12 1130 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::13 1043 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::14 954 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::15 972 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::16 1102 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::17 1082 # What read queue length does an incoming req see
138system.physmem.rdQLenPdf::18 505 # What read queue length does an incoming req see
139system.physmem.rdQLenPdf::19 310 # What read queue length does an incoming req see
140system.physmem.rdQLenPdf::20 37 # What read queue length does an incoming req see
141system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
142system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
143system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
144system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
145system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
146system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
147system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
148system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
149system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
150system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
151system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
152system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
153system.physmem.wrQLenPdf::0 4190 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::1 4518 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::2 5322 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::3 5432 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::4 5474 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::5 5502 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::7 5510 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::8 5511 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::9 5519 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::10 5518 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::11 5518 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::12 5518 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::13 5518 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::14 5518 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::15 5518 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::16 5518 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::17 5518 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::18 5518 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::19 5518 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::20 5518 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::21 5518 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::22 5518 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::23 1329 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::24 1001 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::25 197 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::26 87 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::27 45 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::28 17 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::30 9 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
186system.physmem.totQLat 4076582985 # Total cycles spent in queuing delays
187system.physmem.totMemAccLat 7872522985 # Sum of mem lat for all requests
188system.physmem.totBusLat 991710000 # Total cycles spent in databus access
189system.physmem.totBankLat 2804230000 # Total cycles spent in bank access
190system.physmem.avgQLat 20553.30 # Average queueing delay per request
191system.physmem.avgBankLat 14138.36 # Average bank access latency per request
192system.physmem.avgBusLat 5000.00 # Average bus latency per request
193system.physmem.avgMemAccLat 39691.66 # Average memory access latency
194system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
195system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
196system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
197system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
198system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
199system.physmem.busUtil 0.03 # Data bus utilization in percentage
200system.physmem.avgRdQLen 0.00 # Average read queue length over time
201system.physmem.avgWrQLen 12.66 # Average write queue length over time
202system.physmem.readRowHits 175587 # Number of row buffer hits during reads
203system.physmem.writeRowHits 94819 # Number of row buffer hits during writes
204system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads
205system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes
206system.physmem.avgGap 15969193.66 # Average gap between requests
207system.iocache.replacements 47509 # number of replacements
208system.iocache.tagsinuse 0.124742 # Cycle average of tags in use
209system.iocache.total_refs 0 # Total number of references to valid blocks.
210system.iocache.sampled_refs 47525 # Sample count of references to valid blocks.
211system.iocache.avg_refs 0 # Average number of references to valid blocks.
212system.iocache.warmup_cycle 5044527520000 # Cycle when the warmup percentage was hit.
213system.iocache.occ_blocks::pc.south_bridge.ide 0.124742 # Average occupied blocks per requestor

--- 4 unchanged lines hidden (view full) ---

218system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
219system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
220system.iocache.demand_misses::pc.south_bridge.ide 47564 # number of demand (read+write) misses
221system.iocache.demand_misses::total 47564 # number of demand (read+write) misses
222system.iocache.overall_misses::pc.south_bridge.ide 47564 # number of overall misses
223system.iocache.overall_misses::total 47564 # number of overall misses
224system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 139479932 # number of ReadReq miss cycles
225system.iocache.ReadReq_miss_latency::total 139479932 # number of ReadReq miss cycles
226system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10701739160 # number of WriteReq miss cycles
227system.iocache.WriteReq_miss_latency::total 10701739160 # number of WriteReq miss cycles
228system.iocache.demand_miss_latency::pc.south_bridge.ide 10841219092 # number of demand (read+write) miss cycles
229system.iocache.demand_miss_latency::total 10841219092 # number of demand (read+write) miss cycles
230system.iocache.overall_miss_latency::pc.south_bridge.ide 10841219092 # number of overall miss cycles
231system.iocache.overall_miss_latency::total 10841219092 # number of overall miss cycles
232system.iocache.ReadReq_accesses::pc.south_bridge.ide 844 # number of ReadReq accesses(hits+misses)
233system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses)
234system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
235system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
236system.iocache.demand_accesses::pc.south_bridge.ide 47564 # number of demand (read+write) accesses
237system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses
238system.iocache.overall_accesses::pc.south_bridge.ide 47564 # number of overall (read+write) accesses
239system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses
240system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
241system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
242system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
243system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
244system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
245system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
246system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
247system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
248system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 165260.582938 # average ReadReq miss latency
249system.iocache.ReadReq_avg_miss_latency::total 165260.582938 # average ReadReq miss latency
250system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229061.197774 # average WriteReq miss latency
251system.iocache.WriteReq_avg_miss_latency::total 229061.197774 # average WriteReq miss latency
252system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency
253system.iocache.demand_avg_miss_latency::total 227929.086957 # average overall miss latency
254system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 227929.086957 # average overall miss latency
255system.iocache.overall_avg_miss_latency::total 227929.086957 # average overall miss latency
256system.iocache.blocked_cycles::no_mshrs 173428 # number of cycles access was blocked
257system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
258system.iocache.blocked::no_mshrs 16211 # number of cycles access was blocked
259system.iocache.blocked::no_targets 0 # number of cycles access was blocked
260system.iocache.avg_blocked_cycles::no_mshrs 10.698168 # average number of cycles each access was blocked
261system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
262system.iocache.fast_writes 0 # number of fast writes performed
263system.iocache.cache_copies 0 # number of cache copies performed
264system.iocache.writebacks::writebacks 46667 # number of writebacks
265system.iocache.writebacks::total 46667 # number of writebacks
266system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 844 # number of ReadReq MSHR misses
267system.iocache.ReadReq_mshr_misses::total 844 # number of ReadReq MSHR misses
268system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
269system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
270system.iocache.demand_mshr_misses::pc.south_bridge.ide 47564 # number of demand (read+write) MSHR misses
271system.iocache.demand_mshr_misses::total 47564 # number of demand (read+write) MSHR misses
272system.iocache.overall_mshr_misses::pc.south_bridge.ide 47564 # number of overall MSHR misses
273system.iocache.overall_mshr_misses::total 47564 # number of overall MSHR misses
274system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 95570991 # number of ReadReq MSHR miss cycles
275system.iocache.ReadReq_mshr_miss_latency::total 95570991 # number of ReadReq MSHR miss cycles
276system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8270938224 # number of WriteReq MSHR miss cycles
277system.iocache.WriteReq_mshr_miss_latency::total 8270938224 # number of WriteReq MSHR miss cycles
278system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of demand (read+write) MSHR miss cycles
279system.iocache.demand_mshr_miss_latency::total 8366509215 # number of demand (read+write) MSHR miss cycles
280system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8366509215 # number of overall MSHR miss cycles
281system.iocache.overall_mshr_miss_latency::total 8366509215 # number of overall MSHR miss cycles
282system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
283system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
284system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
285system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
286system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
287system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
288system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
289system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
290system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 113235.771327 # average ReadReq mshr miss latency
291system.iocache.ReadReq_avg_mshr_miss_latency::total 113235.771327 # average ReadReq mshr miss latency
292system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177032.068151 # average WriteReq mshr miss latency
293system.iocache.WriteReq_avg_mshr_miss_latency::total 177032.068151 # average WriteReq mshr miss latency
294system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency
295system.iocache.demand_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency
296system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 175900.033954 # average overall mshr miss latency
297system.iocache.overall_avg_mshr_miss_latency::total 175900.033954 # average overall mshr miss latency
298system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
299system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
300system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
301system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
302system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
303system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
304system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
305system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
306system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
307system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
308system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
309system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
310system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
311system.cpu.numCycles 10390324042 # number of cpu cycles simulated
312system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
313system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
314system.cpu.committedInsts 128273348 # Number of instructions committed
315system.cpu.committedOps 247275973 # Number of ops (including micro ops) committed
316system.cpu.num_int_alu_accesses 232011682 # Number of integer alu accesses
317system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
318system.cpu.num_func_calls 0 # number of times a function call or return occured
319system.cpu.num_conditional_control_insts 23157367 # number of instructions that are conditional controls
320system.cpu.num_int_insts 232011682 # number of integer instructions
321system.cpu.num_fp_insts 0 # number of float instructions
322system.cpu.num_int_register_reads 567056120 # number of times the integer registers were read
323system.cpu.num_int_register_writes 293242224 # number of times the integer registers were written
324system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
325system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
326system.cpu.num_mem_refs 22232138 # number of memory refs
327system.cpu.num_load_insts 13871783 # Number of load instructions
328system.cpu.num_store_insts 8360355 # Number of store instructions
329system.cpu.num_idle_cycles 9789668776.998116 # Number of idle cycles
330system.cpu.num_busy_cycles 600655265.001884 # Number of busy cycles
331system.cpu.not_idle_fraction 0.057809 # Percentage of non-idle cycles
332system.cpu.idle_fraction 0.942191 # Percentage of idle cycles
333system.cpu.kern.inst.arm 0 # number of arm instructions executed
334system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
335system.cpu.icache.replacements 791521 # number of replacements
336system.cpu.icache.tagsinuse 510.376104 # Cycle average of tags in use
337system.cpu.icache.total_refs 144497694 # Total number of references to valid blocks.
338system.cpu.icache.sampled_refs 792033 # Sample count of references to valid blocks.
339system.cpu.icache.avg_refs 182.438982 # Average number of references to valid blocks.
340system.cpu.icache.warmup_cycle 159800886000 # Cycle when the warmup percentage was hit.
341system.cpu.icache.occ_blocks::cpu.inst 510.376104 # Average occupied blocks per requestor
342system.cpu.icache.occ_percent::cpu.inst 0.996828 # Average percentage of cache occupancy
343system.cpu.icache.occ_percent::total 0.996828 # Average percentage of cache occupancy
344system.cpu.icache.ReadReq_hits::cpu.inst 144497694 # number of ReadReq hits
345system.cpu.icache.ReadReq_hits::total 144497694 # number of ReadReq hits
346system.cpu.icache.demand_hits::cpu.inst 144497694 # number of demand (read+write) hits
347system.cpu.icache.demand_hits::total 144497694 # number of demand (read+write) hits
348system.cpu.icache.overall_hits::cpu.inst 144497694 # number of overall hits
349system.cpu.icache.overall_hits::total 144497694 # number of overall hits
350system.cpu.icache.ReadReq_misses::cpu.inst 792040 # number of ReadReq misses
351system.cpu.icache.ReadReq_misses::total 792040 # number of ReadReq misses
352system.cpu.icache.demand_misses::cpu.inst 792040 # number of demand (read+write) misses
353system.cpu.icache.demand_misses::total 792040 # number of demand (read+write) misses
354system.cpu.icache.overall_misses::cpu.inst 792040 # number of overall misses
355system.cpu.icache.overall_misses::total 792040 # number of overall misses
356system.cpu.icache.ReadReq_miss_latency::cpu.inst 10957638500 # number of ReadReq miss cycles
357system.cpu.icache.ReadReq_miss_latency::total 10957638500 # number of ReadReq miss cycles
358system.cpu.icache.demand_miss_latency::cpu.inst 10957638500 # number of demand (read+write) miss cycles
359system.cpu.icache.demand_miss_latency::total 10957638500 # number of demand (read+write) miss cycles
360system.cpu.icache.overall_miss_latency::cpu.inst 10957638500 # number of overall miss cycles
361system.cpu.icache.overall_miss_latency::total 10957638500 # number of overall miss cycles
362system.cpu.icache.ReadReq_accesses::cpu.inst 145289734 # number of ReadReq accesses(hits+misses)
363system.cpu.icache.ReadReq_accesses::total 145289734 # number of ReadReq accesses(hits+misses)
364system.cpu.icache.demand_accesses::cpu.inst 145289734 # number of demand (read+write) accesses
365system.cpu.icache.demand_accesses::total 145289734 # number of demand (read+write) accesses
366system.cpu.icache.overall_accesses::cpu.inst 145289734 # number of overall (read+write) accesses
367system.cpu.icache.overall_accesses::total 145289734 # number of overall (read+write) accesses
368system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005451 # miss rate for ReadReq accesses
369system.cpu.icache.ReadReq_miss_rate::total 0.005451 # miss rate for ReadReq accesses
370system.cpu.icache.demand_miss_rate::cpu.inst 0.005451 # miss rate for demand accesses
371system.cpu.icache.demand_miss_rate::total 0.005451 # miss rate for demand accesses
372system.cpu.icache.overall_miss_rate::cpu.inst 0.005451 # miss rate for overall accesses
373system.cpu.icache.overall_miss_rate::total 0.005451 # miss rate for overall accesses
374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13834.703424 # average ReadReq miss latency
375system.cpu.icache.ReadReq_avg_miss_latency::total 13834.703424 # average ReadReq miss latency
376system.cpu.icache.demand_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency
377system.cpu.icache.demand_avg_miss_latency::total 13834.703424 # average overall miss latency
378system.cpu.icache.overall_avg_miss_latency::cpu.inst 13834.703424 # average overall miss latency
379system.cpu.icache.overall_avg_miss_latency::total 13834.703424 # average overall miss latency
380system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
381system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
382system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
383system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
384system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
385system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
386system.cpu.icache.fast_writes 0 # number of fast writes performed
387system.cpu.icache.cache_copies 0 # number of cache copies performed
388system.cpu.icache.ReadReq_mshr_misses::cpu.inst 792040 # number of ReadReq MSHR misses
389system.cpu.icache.ReadReq_mshr_misses::total 792040 # number of ReadReq MSHR misses
390system.cpu.icache.demand_mshr_misses::cpu.inst 792040 # number of demand (read+write) MSHR misses
391system.cpu.icache.demand_mshr_misses::total 792040 # number of demand (read+write) MSHR misses
392system.cpu.icache.overall_mshr_misses::cpu.inst 792040 # number of overall MSHR misses
393system.cpu.icache.overall_mshr_misses::total 792040 # number of overall MSHR misses
394system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9373558500 # number of ReadReq MSHR miss cycles
395system.cpu.icache.ReadReq_mshr_miss_latency::total 9373558500 # number of ReadReq MSHR miss cycles
396system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9373558500 # number of demand (read+write) MSHR miss cycles
397system.cpu.icache.demand_mshr_miss_latency::total 9373558500 # number of demand (read+write) MSHR miss cycles
398system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9373558500 # number of overall MSHR miss cycles
399system.cpu.icache.overall_mshr_miss_latency::total 9373558500 # number of overall MSHR miss cycles
400system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for ReadReq accesses
401system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005451 # mshr miss rate for ReadReq accesses
402system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for demand accesses
403system.cpu.icache.demand_mshr_miss_rate::total 0.005451 # mshr miss rate for demand accesses
404system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005451 # mshr miss rate for overall accesses
405system.cpu.icache.overall_mshr_miss_rate::total 0.005451 # mshr miss rate for overall accesses
406system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11834.703424 # average ReadReq mshr miss latency
407system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11834.703424 # average ReadReq mshr miss latency
408system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11834.703424 # average overall mshr miss latency
409system.cpu.icache.demand_avg_mshr_miss_latency::total 11834.703424 # average overall mshr miss latency
410system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11834.703424 # average overall mshr miss latency
411system.cpu.icache.overall_avg_mshr_miss_latency::total 11834.703424 # average overall mshr miss latency
412system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
413system.cpu.itb_walker_cache.replacements 3425 # number of replacements
414system.cpu.itb_walker_cache.tagsinuse 3.077882 # Cycle average of tags in use
415system.cpu.itb_walker_cache.total_refs 8006 # Total number of references to valid blocks.
416system.cpu.itb_walker_cache.sampled_refs 3437 # Sample count of references to valid blocks.
417system.cpu.itb_walker_cache.avg_refs 2.329357 # Average number of references to valid blocks.
418system.cpu.itb_walker_cache.warmup_cycle 5164118674000 # Cycle when the warmup percentage was hit.
419system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.077882 # Average occupied blocks per requestor

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489system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.348735 # mshr miss rate for overall accesses
490system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average ReadReq mshr miss latency
491system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7860.975041 # average ReadReq mshr miss latency
492system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency
493system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency
494system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7860.975041 # average overall mshr miss latency
495system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7860.975041 # average overall mshr miss latency
496system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
497system.cpu.dtb_walker_cache.replacements 7538 # number of replacements
498system.cpu.dtb_walker_cache.tagsinuse 5.062515 # Cycle average of tags in use
499system.cpu.dtb_walker_cache.total_refs 13179 # Total number of references to valid blocks.
500system.cpu.dtb_walker_cache.sampled_refs 7552 # Sample count of references to valid blocks.
501system.cpu.dtb_walker_cache.avg_refs 1.745101 # Average number of references to valid blocks.
502system.cpu.dtb_walker_cache.warmup_cycle 5159123845000 # Cycle when the warmup percentage was hit.
503system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.062515 # Average occupied blocks per requestor
504system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.316407 # Average percentage of cache occupancy
505system.cpu.dtb_walker_cache.occ_percent::total 0.316407 # Average percentage of cache occupancy
506system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13181 # number of ReadReq hits
507system.cpu.dtb_walker_cache.ReadReq_hits::total 13181 # number of ReadReq hits
508system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13181 # number of demand (read+write) hits
509system.cpu.dtb_walker_cache.demand_hits::total 13181 # number of demand (read+write) hits
510system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13181 # number of overall hits
511system.cpu.dtb_walker_cache.overall_hits::total 13181 # number of overall hits
512system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8725 # number of ReadReq misses
513system.cpu.dtb_walker_cache.ReadReq_misses::total 8725 # number of ReadReq misses
514system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8725 # number of demand (read+write) misses
515system.cpu.dtb_walker_cache.demand_misses::total 8725 # number of demand (read+write) misses
516system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8725 # number of overall misses
517system.cpu.dtb_walker_cache.overall_misses::total 8725 # number of overall misses
518system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92081500 # number of ReadReq miss cycles
519system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92081500 # number of ReadReq miss cycles
520system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92081500 # number of demand (read+write) miss cycles
521system.cpu.dtb_walker_cache.demand_miss_latency::total 92081500 # number of demand (read+write) miss cycles
522system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92081500 # number of overall miss cycles
523system.cpu.dtb_walker_cache.overall_miss_latency::total 92081500 # number of overall miss cycles
524system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21906 # number of ReadReq accesses(hits+misses)
525system.cpu.dtb_walker_cache.ReadReq_accesses::total 21906 # number of ReadReq accesses(hits+misses)
526system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21906 # number of demand (read+write) accesses
527system.cpu.dtb_walker_cache.demand_accesses::total 21906 # number of demand (read+write) accesses
528system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21906 # number of overall (read+write) accesses
529system.cpu.dtb_walker_cache.overall_accesses::total 21906 # number of overall (read+write) accesses
530system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.398293 # miss rate for ReadReq accesses
531system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.398293 # miss rate for ReadReq accesses
532system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.398293 # miss rate for demand accesses
533system.cpu.dtb_walker_cache.demand_miss_rate::total 0.398293 # miss rate for demand accesses
534system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.398293 # miss rate for overall accesses
535system.cpu.dtb_walker_cache.overall_miss_rate::total 0.398293 # miss rate for overall accesses
536system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.753582 # average ReadReq miss latency
537system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.753582 # average ReadReq miss latency
538system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency
539system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.753582 # average overall miss latency
540system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.753582 # average overall miss latency
541system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.753582 # average overall miss latency
542system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
543system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
544system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
545system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
546system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
547system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
548system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
549system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
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551system.cpu.dtb_walker_cache.writebacks::total 2712 # number of writebacks
552system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8725 # number of ReadReq MSHR misses
553system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8725 # number of ReadReq MSHR misses
554system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8725 # number of demand (read+write) MSHR misses
555system.cpu.dtb_walker_cache.demand_mshr_misses::total 8725 # number of demand (read+write) MSHR misses
556system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8725 # number of overall MSHR misses
557system.cpu.dtb_walker_cache.overall_mshr_misses::total 8725 # number of overall MSHR misses
558system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74631500 # number of ReadReq MSHR miss cycles
559system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74631500 # number of ReadReq MSHR miss cycles
560system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74631500 # number of demand (read+write) MSHR miss cycles
561system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74631500 # number of demand (read+write) MSHR miss cycles
562system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74631500 # number of overall MSHR miss cycles
563system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74631500 # number of overall MSHR miss cycles
564system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for ReadReq accesses
565system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.398293 # mshr miss rate for ReadReq accesses
566system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for demand accesses
567system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.398293 # mshr miss rate for demand accesses
568system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.398293 # mshr miss rate for overall accesses
569system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.398293 # mshr miss rate for overall accesses
570system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average ReadReq mshr miss latency
571system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.753582 # average ReadReq mshr miss latency
572system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency
573system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency
574system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.753582 # average overall mshr miss latency
575system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.753582 # average overall mshr miss latency
576system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
577system.cpu.dcache.replacements 1618787 # number of replacements
578system.cpu.dcache.tagsinuse 511.997766 # Cycle average of tags in use
579system.cpu.dcache.total_refs 20025899 # Total number of references to valid blocks.
580system.cpu.dcache.sampled_refs 1619299 # Sample count of references to valid blocks.
581system.cpu.dcache.avg_refs 12.367017 # Average number of references to valid blocks.
582system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit.
583system.cpu.dcache.occ_blocks::cpu.data 511.997766 # Average occupied blocks per requestor
584system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
585system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
586system.cpu.dcache.ReadReq_hits::cpu.data 11988264 # number of ReadReq hits
587system.cpu.dcache.ReadReq_hits::total 11988264 # number of ReadReq hits
588system.cpu.dcache.WriteReq_hits::cpu.data 8035473 # number of WriteReq hits
589system.cpu.dcache.WriteReq_hits::total 8035473 # number of WriteReq hits
590system.cpu.dcache.demand_hits::cpu.data 20023737 # number of demand (read+write) hits
591system.cpu.dcache.demand_hits::total 20023737 # number of demand (read+write) hits
592system.cpu.dcache.overall_hits::cpu.data 20023737 # number of overall hits
593system.cpu.dcache.overall_hits::total 20023737 # number of overall hits
594system.cpu.dcache.ReadReq_misses::cpu.data 1306607 # number of ReadReq misses
595system.cpu.dcache.ReadReq_misses::total 1306607 # number of ReadReq misses
596system.cpu.dcache.WriteReq_misses::cpu.data 314888 # number of WriteReq misses
597system.cpu.dcache.WriteReq_misses::total 314888 # number of WriteReq misses
598system.cpu.dcache.demand_misses::cpu.data 1621495 # number of demand (read+write) misses
599system.cpu.dcache.demand_misses::total 1621495 # number of demand (read+write) misses
600system.cpu.dcache.overall_misses::cpu.data 1621495 # number of overall misses
601system.cpu.dcache.overall_misses::total 1621495 # number of overall misses
602system.cpu.dcache.ReadReq_miss_latency::cpu.data 18344083000 # number of ReadReq miss cycles
603system.cpu.dcache.ReadReq_miss_latency::total 18344083000 # number of ReadReq miss cycles
604system.cpu.dcache.WriteReq_miss_latency::cpu.data 8556368000 # number of WriteReq miss cycles
605system.cpu.dcache.WriteReq_miss_latency::total 8556368000 # number of WriteReq miss cycles
606system.cpu.dcache.demand_miss_latency::cpu.data 26900451000 # number of demand (read+write) miss cycles
607system.cpu.dcache.demand_miss_latency::total 26900451000 # number of demand (read+write) miss cycles
608system.cpu.dcache.overall_miss_latency::cpu.data 26900451000 # number of overall miss cycles
609system.cpu.dcache.overall_miss_latency::total 26900451000 # number of overall miss cycles
610system.cpu.dcache.ReadReq_accesses::cpu.data 13294871 # number of ReadReq accesses(hits+misses)
611system.cpu.dcache.ReadReq_accesses::total 13294871 # number of ReadReq accesses(hits+misses)
612system.cpu.dcache.WriteReq_accesses::cpu.data 8350361 # number of WriteReq accesses(hits+misses)
613system.cpu.dcache.WriteReq_accesses::total 8350361 # number of WriteReq accesses(hits+misses)
614system.cpu.dcache.demand_accesses::cpu.data 21645232 # number of demand (read+write) accesses
615system.cpu.dcache.demand_accesses::total 21645232 # number of demand (read+write) accesses
616system.cpu.dcache.overall_accesses::cpu.data 21645232 # number of overall (read+write) accesses
617system.cpu.dcache.overall_accesses::total 21645232 # number of overall (read+write) accesses
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620system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037710 # miss rate for WriteReq accesses
621system.cpu.dcache.WriteReq_miss_rate::total 0.037710 # miss rate for WriteReq accesses
622system.cpu.dcache.demand_miss_rate::cpu.data 0.074912 # miss rate for demand accesses
623system.cpu.dcache.demand_miss_rate::total 0.074912 # miss rate for demand accesses
624system.cpu.dcache.overall_miss_rate::cpu.data 0.074912 # miss rate for overall accesses
625system.cpu.dcache.overall_miss_rate::total 0.074912 # miss rate for overall accesses
626system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14039.480119 # average ReadReq miss latency
627system.cpu.dcache.ReadReq_avg_miss_latency::total 14039.480119 # average ReadReq miss latency
628system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27172.734433 # average WriteReq miss latency
629system.cpu.dcache.WriteReq_avg_miss_latency::total 27172.734433 # average WriteReq miss latency
630system.cpu.dcache.demand_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency
631system.cpu.dcache.demand_avg_miss_latency::total 16589.906845 # average overall miss latency
632system.cpu.dcache.overall_avg_miss_latency::cpu.data 16589.906845 # average overall miss latency
633system.cpu.dcache.overall_avg_miss_latency::total 16589.906845 # average overall miss latency
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639system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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642system.cpu.dcache.writebacks::writebacks 1536049 # number of writebacks
643system.cpu.dcache.writebacks::total 1536049 # number of writebacks
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645system.cpu.dcache.ReadReq_mshr_misses::total 1306607 # number of ReadReq MSHR misses
646system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314888 # number of WriteReq MSHR misses
647system.cpu.dcache.WriteReq_mshr_misses::total 314888 # number of WriteReq MSHR misses
648system.cpu.dcache.demand_mshr_misses::cpu.data 1621495 # number of demand (read+write) MSHR misses
649system.cpu.dcache.demand_mshr_misses::total 1621495 # number of demand (read+write) MSHR misses
650system.cpu.dcache.overall_mshr_misses::cpu.data 1621495 # number of overall MSHR misses
651system.cpu.dcache.overall_mshr_misses::total 1621495 # number of overall MSHR misses
652system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15730869000 # number of ReadReq MSHR miss cycles
653system.cpu.dcache.ReadReq_mshr_miss_latency::total 15730869000 # number of ReadReq MSHR miss cycles
654system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7926592000 # number of WriteReq MSHR miss cycles
655system.cpu.dcache.WriteReq_mshr_miss_latency::total 7926592000 # number of WriteReq MSHR miss cycles
656system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23657461000 # number of demand (read+write) MSHR miss cycles
657system.cpu.dcache.demand_mshr_miss_latency::total 23657461000 # number of demand (read+write) MSHR miss cycles
658system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23657461000 # number of overall MSHR miss cycles
659system.cpu.dcache.overall_mshr_miss_latency::total 23657461000 # number of overall MSHR miss cycles
660system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94145949000 # number of ReadReq MSHR uncacheable cycles
661system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94145949000 # number of ReadReq MSHR uncacheable cycles
662system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2467832500 # number of WriteReq MSHR uncacheable cycles
663system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2467832500 # number of WriteReq MSHR uncacheable cycles
664system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96613781500 # number of overall MSHR uncacheable cycles
665system.cpu.dcache.overall_mshr_uncacheable_latency::total 96613781500 # number of overall MSHR uncacheable cycles
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667system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098279 # mshr miss rate for ReadReq accesses
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669system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037710 # mshr miss rate for WriteReq accesses
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671system.cpu.dcache.demand_mshr_miss_rate::total 0.074912 # mshr miss rate for demand accesses
672system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074912 # mshr miss rate for overall accesses
673system.cpu.dcache.overall_mshr_miss_rate::total 0.074912 # mshr miss rate for overall accesses
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675system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.480119 # average ReadReq mshr miss latency
676system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25172.734433 # average WriteReq mshr miss latency
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679system.cpu.dcache.demand_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency
680system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14589.906845 # average overall mshr miss latency
681system.cpu.dcache.overall_avg_mshr_miss_latency::total 14589.906845 # average overall mshr miss latency
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683system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
684system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
685system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
686system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
687system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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689system.cpu.l2cache.replacements 86864 # number of replacements
690system.cpu.l2cache.tagsinuse 64770.429000 # Cycle average of tags in use
691system.cpu.l2cache.total_refs 3484731 # Total number of references to valid blocks.
692system.cpu.l2cache.sampled_refs 151631 # Sample count of references to valid blocks.
693system.cpu.l2cache.avg_refs 22.981653 # Average number of references to valid blocks.
694system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
695system.cpu.l2cache.occ_blocks::writebacks 50336.267441 # Average occupied blocks per requestor
696system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.007172 # Average occupied blocks per requestor
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698system.cpu.l2cache.occ_blocks::cpu.inst 3358.135857 # Average occupied blocks per requestor
699system.cpu.l2cache.occ_blocks::cpu.data 11075.878163 # Average occupied blocks per requestor
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--- 5 unchanged lines hidden (view full) ---

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821system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61370.066812 # average overall miss latency
822system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51021.352024 # average overall miss latency
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829system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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--- 13 unchanged lines hidden (view full) ---

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916system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
917system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
918system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
919system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
920system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
921system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
922system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
923
924---------- End Simulation Statistics ----------