1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.191816 # Number of seconds simulated
4sim_ticks 5191816279000 # Number of ticks simulated
5final_tick 5191816279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 631596 # Simulator instruction rate (inst/s)
8host_op_rate 1217489 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 25553396248 # Simulator tick rate (ticks/s)
10host_mem_usage 629228 # Number of bytes of host memory used
11host_seconds 203.18 # Real time elapsed on the host
12sim_insts 128324646 # Number of instructions simulated
13sim_ops 247363464 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2859648 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
16system.physmem.bytes_read::cpu.inst 823360 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9009408 # Number of bytes read from this memory
18system.physmem.bytes_read::total 12692736 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 823360 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 823360 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 8106432 # Number of bytes written to this memory
22system.physmem.bytes_written::total 8106432 # Number of bytes written to this memory
23system.physmem.num_reads::pc.south_bridge.ide 44682 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.inst 12865 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 140772 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 198324 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 126663 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 126663 # Number of write requests responded to by this memory
30system.physmem.bw_read::pc.south_bridge.ide 550799 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.inst 158588 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.data 1735309 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::total 2444758 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::cpu.inst 158588 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::total 158588 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_write::writebacks 1561387 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_write::total 1561387 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_total::writebacks 1561387 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::pc.south_bridge.ide 550799 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::cpu.inst 158588 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::cpu.data 1735309 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::total 4006145 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.readReqs 198324 # Total number of read requests seen
46system.physmem.writeReqs 126663 # Total number of write requests seen
47system.physmem.cpureqs 326610 # Reqs generatd by CPU via cache - shady
48system.physmem.bytesRead 12692736 # Total number of bytes read from memory
49system.physmem.bytesWritten 8106432 # Total number of bytes written to memory
50system.physmem.bytesConsumedRd 12692736 # bytesRead derated as per pkt->getSize()
51system.physmem.bytesConsumedWr 8106432 # bytesWritten derated as per pkt->getSize()
52system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q
53system.physmem.neitherReadNorWrite 1618 # Reqs where no action is needed
54system.physmem.perBankRdReqs::0 12615 # Track reads on a per bank basis
55system.physmem.perBankRdReqs::1 12250 # Track reads on a per bank basis
56system.physmem.perBankRdReqs::2 12267 # Track reads on a per bank basis
57system.physmem.perBankRdReqs::3 12575 # Track reads on a per bank basis
58system.physmem.perBankRdReqs::4 12362 # Track reads on a per bank basis
59system.physmem.perBankRdReqs::5 12187 # Track reads on a per bank basis
60system.physmem.perBankRdReqs::6 12619 # Track reads on a per bank basis
61system.physmem.perBankRdReqs::7 12562 # Track reads on a per bank basis
62system.physmem.perBankRdReqs::8 12247 # Track reads on a per bank basis
63system.physmem.perBankRdReqs::9 11965 # Track reads on a per bank basis
64system.physmem.perBankRdReqs::10 12423 # Track reads on a per bank basis
65system.physmem.perBankRdReqs::11 12610 # Track reads on a per bank basis
66system.physmem.perBankRdReqs::12 12268 # Track reads on a per bank basis
67system.physmem.perBankRdReqs::13 12172 # Track reads on a per bank basis
68system.physmem.perBankRdReqs::14 12546 # Track reads on a per bank basis
69system.physmem.perBankRdReqs::15 12576 # Track reads on a per bank basis
70system.physmem.perBankWrReqs::0 8002 # Track writes on a per bank basis
71system.physmem.perBankWrReqs::1 7779 # Track writes on a per bank basis
72system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis
73system.physmem.perBankWrReqs::3 8120 # Track writes on a per bank basis
74system.physmem.perBankWrReqs::4 7982 # Track writes on a per bank basis
75system.physmem.perBankWrReqs::5 7804 # Track writes on a per bank basis
76system.physmem.perBankWrReqs::6 8130 # Track writes on a per bank basis
77system.physmem.perBankWrReqs::7 8156 # Track writes on a per bank basis
78system.physmem.perBankWrReqs::8 7749 # Track writes on a per bank basis
79system.physmem.perBankWrReqs::9 7475 # Track writes on a per bank basis
80system.physmem.perBankWrReqs::10 7958 # Track writes on a per bank basis
81system.physmem.perBankWrReqs::11 8068 # Track writes on a per bank basis
82system.physmem.perBankWrReqs::12 7819 # Track writes on a per bank basis
83system.physmem.perBankWrReqs::13 7741 # Track writes on a per bank basis
84system.physmem.perBankWrReqs::14 7995 # Track writes on a per bank basis
85system.physmem.perBankWrReqs::15 8083 # Track writes on a per bank basis
86system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
87system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry
88system.physmem.totGap 5191816215500 # Total gap between requests
89system.physmem.readPktSize::0 0 # Categorize read packet sizes
90system.physmem.readPktSize::1 0 # Categorize read packet sizes
91system.physmem.readPktSize::2 0 # Categorize read packet sizes
92system.physmem.readPktSize::3 0 # Categorize read packet sizes
93system.physmem.readPktSize::4 0 # Categorize read packet sizes
94system.physmem.readPktSize::5 0 # Categorize read packet sizes
95system.physmem.readPktSize::6 198324 # Categorize read packet sizes
96system.physmem.writePktSize::0 0 # Categorize write packet sizes
97system.physmem.writePktSize::1 0 # Categorize write packet sizes
98system.physmem.writePktSize::2 0 # Categorize write packet sizes
99system.physmem.writePktSize::3 0 # Categorize write packet sizes
100system.physmem.writePktSize::4 0 # Categorize write packet sizes
101system.physmem.writePktSize::5 0 # Categorize write packet sizes
102system.physmem.writePktSize::6 126663 # Categorize write packet sizes
103system.physmem.rdQLenPdf::0 155046 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::1 8732 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::2 6675 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::3 3414 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::4 3394 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::5 2806 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::6 2216 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::7 2153 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::8 2094 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::9 2013 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::10 1298 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::11 1183 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::12 1113 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::13 1034 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::14 959 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::15 975 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::16 1125 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::17 1097 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::18 541 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::19 344 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::20 32 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
135system.physmem.wrQLenPdf::0 4186 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::1 4510 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::2 5285 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::3 5419 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::4 5454 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::5 5493 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::6 5497 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::7 5499 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::8 5502 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::9 5507 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::10 5507 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::11 5507 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::12 5507 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::13 5507 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::14 5507 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::15 5507 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::16 5507 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::17 5507 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::18 5507 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::19 5507 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::20 5507 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::21 5507 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::22 5507 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::23 1322 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::24 998 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::25 222 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::26 88 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::27 53 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::28 14 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
167system.physmem.totQLat 4084993999 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 7884046499 # Sum of mem lat for all requests
169system.physmem.totBusLat 991220000 # Total cycles spent in databus access
170system.physmem.totBankLat 2807832500 # Total cycles spent in bank access
171system.physmem.avgQLat 20605.89 # Average queueing delay per request
172system.physmem.avgBankLat 14163.52 # Average bank access latency per request
173system.physmem.avgBusLat 5000.00 # Average bus latency per request
174system.physmem.avgMemAccLat 39769.41 # Average memory access latency
175system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
176system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
177system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
178system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
179system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
180system.physmem.busUtil 0.03 # Data bus utilization in percentage
181system.physmem.avgRdQLen 0.00 # Average read queue length over time
182system.physmem.avgWrQLen 8.79 # Average write queue length over time
183system.physmem.readRowHits 175346 # Number of row buffer hits during reads
184system.physmem.writeRowHits 94626 # Number of row buffer hits during writes
185system.physmem.readRowHitRate 88.45 # Row buffer hit rate for reads
186system.physmem.writeRowHitRate 74.71 # Row buffer hit rate for writes
187system.physmem.avgGap 15975458.14 # Average gap between requests
188system.iocache.replacements 47501 # number of replacements
189system.iocache.tagsinuse 0.114811 # Cycle average of tags in use
190system.iocache.total_refs 0 # Total number of references to valid blocks.
191system.iocache.sampled_refs 47517 # Sample count of references to valid blocks.
192system.iocache.avg_refs 0 # Average number of references to valid blocks.
193system.iocache.warmup_cycle 5044702860000 # Cycle when the warmup percentage was hit.
194system.iocache.occ_blocks::pc.south_bridge.ide 0.114811 # Average occupied blocks per requestor
195system.iocache.occ_percent::pc.south_bridge.ide 0.007176 # Average percentage of cache occupancy
196system.iocache.occ_percent::total 0.007176 # Average percentage of cache occupancy
197system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses
198system.iocache.ReadReq_misses::total 836 # number of ReadReq misses
199system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
200system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
201system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses
202system.iocache.demand_misses::total 47556 # number of demand (read+write) misses
203system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses
204system.iocache.overall_misses::total 47556 # number of overall misses
205system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 136123397 # number of ReadReq miss cycles
206system.iocache.ReadReq_miss_latency::total 136123397 # number of ReadReq miss cycles
207system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10718582907 # number of WriteReq miss cycles
208system.iocache.WriteReq_miss_latency::total 10718582907 # number of WriteReq miss cycles
209system.iocache.demand_miss_latency::pc.south_bridge.ide 10854706304 # number of demand (read+write) miss cycles
210system.iocache.demand_miss_latency::total 10854706304 # number of demand (read+write) miss cycles
211system.iocache.overall_miss_latency::pc.south_bridge.ide 10854706304 # number of overall miss cycles
212system.iocache.overall_miss_latency::total 10854706304 # number of overall miss cycles
213system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses)
214system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses)
215system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
216system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
217system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses
218system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses
219system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses
220system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses
221system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
222system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
223system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
224system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
225system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
226system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
227system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
228system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
229system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162827.029904 # average ReadReq miss latency
230system.iocache.ReadReq_avg_miss_latency::total 162827.029904 # average ReadReq miss latency
231system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 229421.723181 # average WriteReq miss latency
232system.iocache.WriteReq_avg_miss_latency::total 229421.723181 # average WriteReq miss latency
233system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 228251.036757 # average overall miss latency
234system.iocache.demand_avg_miss_latency::total 228251.036757 # average overall miss latency
235system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 228251.036757 # average overall miss latency
236system.iocache.overall_avg_miss_latency::total 228251.036757 # average overall miss latency
237system.iocache.blocked_cycles::no_mshrs 175533 # number of cycles access was blocked
238system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
239system.iocache.blocked::no_mshrs 16256 # number of cycles access was blocked
240system.iocache.blocked::no_targets 0 # number of cycles access was blocked
241system.iocache.avg_blocked_cycles::no_mshrs 10.798044 # average number of cycles each access was blocked
242system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
243system.iocache.fast_writes 0 # number of fast writes performed
244system.iocache.cache_copies 0 # number of cache copies performed
245system.iocache.writebacks::writebacks 46667 # number of writebacks
246system.iocache.writebacks::total 46667 # number of writebacks
247system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses
248system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses
249system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
250system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
251system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses
252system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses
253system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses
254system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses
255system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92629177 # number of ReadReq MSHR miss cycles
256system.iocache.ReadReq_mshr_miss_latency::total 92629177 # number of ReadReq MSHR miss cycles
257system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8287786786 # number of WriteReq MSHR miss cycles
258system.iocache.WriteReq_mshr_miss_latency::total 8287786786 # number of WriteReq MSHR miss cycles
259system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8380415963 # number of demand (read+write) MSHR miss cycles
260system.iocache.demand_mshr_miss_latency::total 8380415963 # number of demand (read+write) MSHR miss cycles
261system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8380415963 # number of overall MSHR miss cycles
262system.iocache.overall_mshr_miss_latency::total 8380415963 # number of overall MSHR miss cycles
263system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
264system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
265system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
266system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
267system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
268system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
269system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
270system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
271system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110800.450957 # average ReadReq mshr miss latency
272system.iocache.ReadReq_avg_mshr_miss_latency::total 110800.450957 # average ReadReq mshr miss latency
273system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 177392.696618 # average WriteReq mshr miss latency
274system.iocache.WriteReq_avg_mshr_miss_latency::total 177392.696618 # average WriteReq mshr miss latency
275system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 176222.053221 # average overall mshr miss latency
276system.iocache.demand_avg_mshr_miss_latency::total 176222.053221 # average overall mshr miss latency
277system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 176222.053221 # average overall mshr miss latency
278system.iocache.overall_avg_mshr_miss_latency::total 176222.053221 # average overall mshr miss latency
279system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
280system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
281system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
282system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
283system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
284system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
285system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
286system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
287system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
288system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
289system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
290system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
291system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
292system.cpu.numCycles 10383632558 # number of cpu cycles simulated
293system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
294system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
295system.cpu.committedInsts 128324646 # Number of instructions committed
296system.cpu.committedOps 247363464 # Number of ops (including micro ops) committed
297system.cpu.num_int_alu_accesses 232097683 # Number of integer alu accesses
298system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
299system.cpu.num_func_calls 0 # number of times a function call or return occured
300system.cpu.num_conditional_control_insts 23165556 # number of instructions that are conditional controls
301system.cpu.num_int_insts 232097683 # number of integer instructions
302system.cpu.num_fp_insts 0 # number of float instructions
303system.cpu.num_int_register_reads 567280399 # number of times the integer registers were read
304system.cpu.num_int_register_writes 293347970 # number of times the integer registers were written
305system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
306system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
307system.cpu.num_mem_refs 22249385 # number of memory refs
308system.cpu.num_load_insts 13880834 # Number of load instructions
309system.cpu.num_store_insts 8368551 # Number of store instructions
310system.cpu.num_idle_cycles 9782435662.998116 # Number of idle cycles
311system.cpu.num_busy_cycles 601196895.001884 # Number of busy cycles
312system.cpu.not_idle_fraction 0.057899 # Percentage of non-idle cycles
313system.cpu.idle_fraction 0.942101 # Percentage of idle cycles
314system.cpu.kern.inst.arm 0 # number of arm instructions executed
315system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
316system.cpu.icache.replacements 795387 # number of replacements
317system.cpu.icache.tagsinuse 510.410338 # Cycle average of tags in use
318system.cpu.icache.total_refs 144562130 # Total number of references to valid blocks.
319system.cpu.icache.sampled_refs 795899 # Sample count of references to valid blocks.
320system.cpu.icache.avg_refs 181.633763 # Average number of references to valid blocks.
321system.cpu.icache.warmup_cycle 160005789000 # Cycle when the warmup percentage was hit.
322system.cpu.icache.occ_blocks::cpu.inst 510.410338 # Average occupied blocks per requestor
323system.cpu.icache.occ_percent::cpu.inst 0.996895 # Average percentage of cache occupancy
324system.cpu.icache.occ_percent::total 0.996895 # Average percentage of cache occupancy
325system.cpu.icache.ReadReq_hits::cpu.inst 144562130 # number of ReadReq hits
326system.cpu.icache.ReadReq_hits::total 144562130 # number of ReadReq hits
327system.cpu.icache.demand_hits::cpu.inst 144562130 # number of demand (read+write) hits
328system.cpu.icache.demand_hits::total 144562130 # number of demand (read+write) hits
329system.cpu.icache.overall_hits::cpu.inst 144562130 # number of overall hits
330system.cpu.icache.overall_hits::total 144562130 # number of overall hits
331system.cpu.icache.ReadReq_misses::cpu.inst 795906 # number of ReadReq misses
332system.cpu.icache.ReadReq_misses::total 795906 # number of ReadReq misses
333system.cpu.icache.demand_misses::cpu.inst 795906 # number of demand (read+write) misses
334system.cpu.icache.demand_misses::total 795906 # number of demand (read+write) misses
335system.cpu.icache.overall_misses::cpu.inst 795906 # number of overall misses
336system.cpu.icache.overall_misses::total 795906 # number of overall misses
337system.cpu.icache.ReadReq_miss_latency::cpu.inst 11017856500 # number of ReadReq miss cycles
338system.cpu.icache.ReadReq_miss_latency::total 11017856500 # number of ReadReq miss cycles
339system.cpu.icache.demand_miss_latency::cpu.inst 11017856500 # number of demand (read+write) miss cycles
340system.cpu.icache.demand_miss_latency::total 11017856500 # number of demand (read+write) miss cycles
341system.cpu.icache.overall_miss_latency::cpu.inst 11017856500 # number of overall miss cycles
342system.cpu.icache.overall_miss_latency::total 11017856500 # number of overall miss cycles
343system.cpu.icache.ReadReq_accesses::cpu.inst 145358036 # number of ReadReq accesses(hits+misses)
344system.cpu.icache.ReadReq_accesses::total 145358036 # number of ReadReq accesses(hits+misses)
345system.cpu.icache.demand_accesses::cpu.inst 145358036 # number of demand (read+write) accesses
346system.cpu.icache.demand_accesses::total 145358036 # number of demand (read+write) accesses
347system.cpu.icache.overall_accesses::cpu.inst 145358036 # number of overall (read+write) accesses
348system.cpu.icache.overall_accesses::total 145358036 # number of overall (read+write) accesses
349system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005475 # miss rate for ReadReq accesses
350system.cpu.icache.ReadReq_miss_rate::total 0.005475 # miss rate for ReadReq accesses
351system.cpu.icache.demand_miss_rate::cpu.inst 0.005475 # miss rate for demand accesses
352system.cpu.icache.demand_miss_rate::total 0.005475 # miss rate for demand accesses
353system.cpu.icache.overall_miss_rate::cpu.inst 0.005475 # miss rate for overall accesses
354system.cpu.icache.overall_miss_rate::total 0.005475 # miss rate for overall accesses
355system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13843.163012 # average ReadReq miss latency
356system.cpu.icache.ReadReq_avg_miss_latency::total 13843.163012 # average ReadReq miss latency
357system.cpu.icache.demand_avg_miss_latency::cpu.inst 13843.163012 # average overall miss latency
358system.cpu.icache.demand_avg_miss_latency::total 13843.163012 # average overall miss latency
359system.cpu.icache.overall_avg_miss_latency::cpu.inst 13843.163012 # average overall miss latency
360system.cpu.icache.overall_avg_miss_latency::total 13843.163012 # average overall miss latency
361system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
362system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
363system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
364system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
365system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
366system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
367system.cpu.icache.fast_writes 0 # number of fast writes performed
368system.cpu.icache.cache_copies 0 # number of cache copies performed
369system.cpu.icache.ReadReq_mshr_misses::cpu.inst 795906 # number of ReadReq MSHR misses
370system.cpu.icache.ReadReq_mshr_misses::total 795906 # number of ReadReq MSHR misses
371system.cpu.icache.demand_mshr_misses::cpu.inst 795906 # number of demand (read+write) MSHR misses
372system.cpu.icache.demand_mshr_misses::total 795906 # number of demand (read+write) MSHR misses
373system.cpu.icache.overall_mshr_misses::cpu.inst 795906 # number of overall MSHR misses
374system.cpu.icache.overall_mshr_misses::total 795906 # number of overall MSHR misses
375system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9426044500 # number of ReadReq MSHR miss cycles
376system.cpu.icache.ReadReq_mshr_miss_latency::total 9426044500 # number of ReadReq MSHR miss cycles
377system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9426044500 # number of demand (read+write) MSHR miss cycles
378system.cpu.icache.demand_mshr_miss_latency::total 9426044500 # number of demand (read+write) MSHR miss cycles
379system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9426044500 # number of overall MSHR miss cycles
380system.cpu.icache.overall_mshr_miss_latency::total 9426044500 # number of overall MSHR miss cycles
381system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for ReadReq accesses
382system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005475 # mshr miss rate for ReadReq accesses
383system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for demand accesses
384system.cpu.icache.demand_mshr_miss_rate::total 0.005475 # mshr miss rate for demand accesses
385system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005475 # mshr miss rate for overall accesses
386system.cpu.icache.overall_mshr_miss_rate::total 0.005475 # mshr miss rate for overall accesses
387system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11843.163012 # average ReadReq mshr miss latency
388system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11843.163012 # average ReadReq mshr miss latency
389system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11843.163012 # average overall mshr miss latency
390system.cpu.icache.demand_avg_mshr_miss_latency::total 11843.163012 # average overall mshr miss latency
391system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11843.163012 # average overall mshr miss latency
392system.cpu.icache.overall_avg_mshr_miss_latency::total 11843.163012 # average overall mshr miss latency
393system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
394system.cpu.itb_walker_cache.replacements 3694 # number of replacements
395system.cpu.itb_walker_cache.tagsinuse 3.067610 # Cycle average of tags in use
396system.cpu.itb_walker_cache.total_refs 7642 # Total number of references to valid blocks.
397system.cpu.itb_walker_cache.sampled_refs 3706 # Sample count of references to valid blocks.
398system.cpu.itb_walker_cache.avg_refs 2.062062 # Average number of references to valid blocks.
399system.cpu.itb_walker_cache.warmup_cycle 5165748244000 # Cycle when the warmup percentage was hit.
400system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.067610 # Average occupied blocks per requestor
401system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.191726 # Average percentage of cache occupancy
402system.cpu.itb_walker_cache.occ_percent::total 0.191726 # Average percentage of cache occupancy
403system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7663 # number of ReadReq hits
404system.cpu.itb_walker_cache.ReadReq_hits::total 7663 # number of ReadReq hits
405system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
406system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
407system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7665 # number of demand (read+write) hits
408system.cpu.itb_walker_cache.demand_hits::total 7665 # number of demand (read+write) hits
409system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7665 # number of overall hits
410system.cpu.itb_walker_cache.overall_hits::total 7665 # number of overall hits
411system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4553 # number of ReadReq misses
412system.cpu.itb_walker_cache.ReadReq_misses::total 4553 # number of ReadReq misses
413system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4553 # number of demand (read+write) misses
414system.cpu.itb_walker_cache.demand_misses::total 4553 # number of demand (read+write) misses
415system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4553 # number of overall misses
416system.cpu.itb_walker_cache.overall_misses::total 4553 # number of overall misses
417system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 46128000 # number of ReadReq miss cycles
418system.cpu.itb_walker_cache.ReadReq_miss_latency::total 46128000 # number of ReadReq miss cycles
419system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 46128000 # number of demand (read+write) miss cycles
420system.cpu.itb_walker_cache.demand_miss_latency::total 46128000 # number of demand (read+write) miss cycles
421system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 46128000 # number of overall miss cycles
422system.cpu.itb_walker_cache.overall_miss_latency::total 46128000 # number of overall miss cycles
423system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12216 # number of ReadReq accesses(hits+misses)
424system.cpu.itb_walker_cache.ReadReq_accesses::total 12216 # number of ReadReq accesses(hits+misses)
425system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
426system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
427system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12218 # number of demand (read+write) accesses
428system.cpu.itb_walker_cache.demand_accesses::total 12218 # number of demand (read+write) accesses
429system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12218 # number of overall (read+write) accesses
430system.cpu.itb_walker_cache.overall_accesses::total 12218 # number of overall (read+write) accesses
431system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.372708 # miss rate for ReadReq accesses
432system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.372708 # miss rate for ReadReq accesses
433system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.372647 # miss rate for demand accesses
434system.cpu.itb_walker_cache.demand_miss_rate::total 0.372647 # miss rate for demand accesses
435system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.372647 # miss rate for overall accesses
436system.cpu.itb_walker_cache.overall_miss_rate::total 0.372647 # miss rate for overall accesses
437system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10131.341972 # average ReadReq miss latency
438system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10131.341972 # average ReadReq miss latency
439system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10131.341972 # average overall miss latency
440system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10131.341972 # average overall miss latency
441system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10131.341972 # average overall miss latency
442system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10131.341972 # average overall miss latency
443system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
444system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
445system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
446system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
447system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
448system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
449system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
450system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
451system.cpu.itb_walker_cache.writebacks::writebacks 782 # number of writebacks
452system.cpu.itb_walker_cache.writebacks::total 782 # number of writebacks
453system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4553 # number of ReadReq MSHR misses
454system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4553 # number of ReadReq MSHR misses
455system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4553 # number of demand (read+write) MSHR misses
456system.cpu.itb_walker_cache.demand_mshr_misses::total 4553 # number of demand (read+write) MSHR misses
457system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4553 # number of overall MSHR misses
458system.cpu.itb_walker_cache.overall_mshr_misses::total 4553 # number of overall MSHR misses
459system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 37022000 # number of ReadReq MSHR miss cycles
460system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 37022000 # number of ReadReq MSHR miss cycles
461system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 37022000 # number of demand (read+write) MSHR miss cycles
462system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 37022000 # number of demand (read+write) MSHR miss cycles
463system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 37022000 # number of overall MSHR miss cycles
464system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 37022000 # number of overall MSHR miss cycles
465system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.372708 # mshr miss rate for ReadReq accesses
466system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.372708 # mshr miss rate for ReadReq accesses
467system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.372647 # mshr miss rate for demand accesses
468system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.372647 # mshr miss rate for demand accesses
469system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.372647 # mshr miss rate for overall accesses
470system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.372647 # mshr miss rate for overall accesses
471system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average ReadReq mshr miss latency
472system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8131.341972 # average ReadReq mshr miss latency
473system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average overall mshr miss latency
474system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8131.341972 # average overall mshr miss latency
475system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8131.341972 # average overall mshr miss latency
476system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8131.341972 # average overall mshr miss latency
477system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
478system.cpu.dtb_walker_cache.replacements 8348 # number of replacements
479system.cpu.dtb_walker_cache.tagsinuse 5.050573 # Cycle average of tags in use
480system.cpu.dtb_walker_cache.total_refs 12635 # Total number of references to valid blocks.
481system.cpu.dtb_walker_cache.sampled_refs 8361 # Sample count of references to valid blocks.
482system.cpu.dtb_walker_cache.avg_refs 1.511183 # Average number of references to valid blocks.
483system.cpu.dtb_walker_cache.warmup_cycle 5162441732000 # Cycle when the warmup percentage was hit.
484system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.050573 # Average occupied blocks per requestor
485system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.315661 # Average percentage of cache occupancy
486system.cpu.dtb_walker_cache.occ_percent::total 0.315661 # Average percentage of cache occupancy
487system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12638 # number of ReadReq hits
488system.cpu.dtb_walker_cache.ReadReq_hits::total 12638 # number of ReadReq hits
489system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12638 # number of demand (read+write) hits
490system.cpu.dtb_walker_cache.demand_hits::total 12638 # number of demand (read+write) hits
491system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12638 # number of overall hits
492system.cpu.dtb_walker_cache.overall_hits::total 12638 # number of overall hits
493system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9544 # number of ReadReq misses
494system.cpu.dtb_walker_cache.ReadReq_misses::total 9544 # number of ReadReq misses
495system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9544 # number of demand (read+write) misses
496system.cpu.dtb_walker_cache.demand_misses::total 9544 # number of demand (read+write) misses
497system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9544 # number of overall misses
498system.cpu.dtb_walker_cache.overall_misses::total 9544 # number of overall misses
499system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 102265000 # number of ReadReq miss cycles
500system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 102265000 # number of ReadReq miss cycles
501system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 102265000 # number of demand (read+write) miss cycles
502system.cpu.dtb_walker_cache.demand_miss_latency::total 102265000 # number of demand (read+write) miss cycles
503system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 102265000 # number of overall miss cycles
504system.cpu.dtb_walker_cache.overall_miss_latency::total 102265000 # number of overall miss cycles
505system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22182 # number of ReadReq accesses(hits+misses)
506system.cpu.dtb_walker_cache.ReadReq_accesses::total 22182 # number of ReadReq accesses(hits+misses)
507system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22182 # number of demand (read+write) accesses
508system.cpu.dtb_walker_cache.demand_accesses::total 22182 # number of demand (read+write) accesses
509system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22182 # number of overall (read+write) accesses
510system.cpu.dtb_walker_cache.overall_accesses::total 22182 # number of overall (read+write) accesses
511system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.430259 # miss rate for ReadReq accesses
512system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.430259 # miss rate for ReadReq accesses
513system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.430259 # miss rate for demand accesses
514system.cpu.dtb_walker_cache.demand_miss_rate::total 0.430259 # miss rate for demand accesses
515system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.430259 # miss rate for overall accesses
516system.cpu.dtb_walker_cache.overall_miss_rate::total 0.430259 # miss rate for overall accesses
517system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10715.108969 # average ReadReq miss latency
518system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10715.108969 # average ReadReq miss latency
519system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10715.108969 # average overall miss latency
520system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10715.108969 # average overall miss latency
521system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10715.108969 # average overall miss latency
522system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10715.108969 # average overall miss latency
523system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
524system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
525system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
526system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
527system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
528system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
529system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
530system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
531system.cpu.dtb_walker_cache.writebacks::writebacks 3309 # number of writebacks
532system.cpu.dtb_walker_cache.writebacks::total 3309 # number of writebacks
533system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 9544 # number of ReadReq MSHR misses
534system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 9544 # number of ReadReq MSHR misses
535system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 9544 # number of demand (read+write) MSHR misses
536system.cpu.dtb_walker_cache.demand_mshr_misses::total 9544 # number of demand (read+write) MSHR misses
537system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 9544 # number of overall MSHR misses
538system.cpu.dtb_walker_cache.overall_mshr_misses::total 9544 # number of overall MSHR misses
539system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 83177000 # number of ReadReq MSHR miss cycles
540system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 83177000 # number of ReadReq MSHR miss cycles
541system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 83177000 # number of demand (read+write) MSHR miss cycles
542system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 83177000 # number of demand (read+write) MSHR miss cycles
543system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 83177000 # number of overall MSHR miss cycles
544system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 83177000 # number of overall MSHR miss cycles
545system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for ReadReq accesses
546system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.430259 # mshr miss rate for ReadReq accesses
547system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for demand accesses
548system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.430259 # mshr miss rate for demand accesses
549system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.430259 # mshr miss rate for overall accesses
550system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.430259 # mshr miss rate for overall accesses
551system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # average ReadReq mshr miss latency
552system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8715.108969 # average ReadReq mshr miss latency
553system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # average overall mshr miss latency
554system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8715.108969 # average overall mshr miss latency
555system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8715.108969 # average overall mshr miss latency
556system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8715.108969 # average overall mshr miss latency
557system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
558system.cpu.dcache.replacements 1620219 # number of replacements
559system.cpu.dcache.tagsinuse 511.997551 # Cycle average of tags in use
560system.cpu.dcache.total_refs 20041204 # Total number of references to valid blocks.
561system.cpu.dcache.sampled_refs 1620731 # Sample count of references to valid blocks.
562system.cpu.dcache.avg_refs 12.365534 # Average number of references to valid blocks.
563system.cpu.dcache.warmup_cycle 39012000 # Cycle when the warmup percentage was hit.
564system.cpu.dcache.occ_blocks::cpu.data 511.997551 # Average occupied blocks per requestor
565system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy
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568system.cpu.dcache.ReadReq_hits::total 11996661 # number of ReadReq hits
569system.cpu.dcache.WriteReq_hits::cpu.data 8042358 # number of WriteReq hits
570system.cpu.dcache.WriteReq_hits::total 8042358 # number of WriteReq hits
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572system.cpu.dcache.demand_hits::total 20039019 # number of demand (read+write) hits
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574system.cpu.dcache.overall_hits::total 20039019 # number of overall hits
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576system.cpu.dcache.ReadReq_misses::total 1307017 # number of ReadReq misses
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578system.cpu.dcache.WriteReq_misses::total 315944 # number of WriteReq misses
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580system.cpu.dcache.demand_misses::total 1622961 # number of demand (read+write) misses
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582system.cpu.dcache.overall_misses::total 1622961 # number of overall misses
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586system.cpu.dcache.WriteReq_miss_latency::total 8568992000 # number of WriteReq miss cycles
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588system.cpu.dcache.demand_miss_latency::total 26907467500 # number of demand (read+write) miss cycles
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590system.cpu.dcache.overall_miss_latency::total 26907467500 # number of overall miss cycles
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592system.cpu.dcache.ReadReq_accesses::total 13303678 # number of ReadReq accesses(hits+misses)
593system.cpu.dcache.WriteReq_accesses::cpu.data 8358302 # number of WriteReq accesses(hits+misses)
594system.cpu.dcache.WriteReq_accesses::total 8358302 # number of WriteReq accesses(hits+misses)
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596system.cpu.dcache.demand_accesses::total 21661980 # number of demand (read+write) accesses
597system.cpu.dcache.overall_accesses::cpu.data 21661980 # number of overall (read+write) accesses
598system.cpu.dcache.overall_accesses::total 21661980 # number of overall (read+write) accesses
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600system.cpu.dcache.ReadReq_miss_rate::total 0.098245 # miss rate for ReadReq accesses
601system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037800 # miss rate for WriteReq accesses
602system.cpu.dcache.WriteReq_miss_rate::total 0.037800 # miss rate for WriteReq accesses
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605system.cpu.dcache.overall_miss_rate::cpu.data 0.074922 # miss rate for overall accesses
606system.cpu.dcache.overall_miss_rate::total 0.074922 # miss rate for overall accesses
607system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14030.785751 # average ReadReq miss latency
608system.cpu.dcache.ReadReq_avg_miss_latency::total 14030.785751 # average ReadReq miss latency
609system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27121.869698 # average WriteReq miss latency
610system.cpu.dcache.WriteReq_avg_miss_latency::total 27121.869698 # average WriteReq miss latency
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612system.cpu.dcache.demand_avg_miss_latency::total 16579.244665 # average overall miss latency
613system.cpu.dcache.overall_avg_miss_latency::cpu.data 16579.244665 # average overall miss latency
614system.cpu.dcache.overall_avg_miss_latency::total 16579.244665 # average overall miss latency
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616system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
617system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
618system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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620system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
621system.cpu.dcache.fast_writes 0 # number of fast writes performed
622system.cpu.dcache.cache_copies 0 # number of cache copies performed
623system.cpu.dcache.writebacks::writebacks 1537528 # number of writebacks
624system.cpu.dcache.writebacks::total 1537528 # number of writebacks
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626system.cpu.dcache.ReadReq_mshr_misses::total 1307017 # number of ReadReq MSHR misses
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628system.cpu.dcache.WriteReq_mshr_misses::total 315944 # number of WriteReq MSHR misses
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630system.cpu.dcache.demand_mshr_misses::total 1622961 # number of demand (read+write) MSHR misses
631system.cpu.dcache.overall_mshr_misses::cpu.data 1622961 # number of overall MSHR misses
632system.cpu.dcache.overall_mshr_misses::total 1622961 # number of overall MSHR misses
633system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15724441500 # number of ReadReq MSHR miss cycles
634system.cpu.dcache.ReadReq_mshr_miss_latency::total 15724441500 # number of ReadReq MSHR miss cycles
635system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7937104000 # number of WriteReq MSHR miss cycles
636system.cpu.dcache.WriteReq_mshr_miss_latency::total 7937104000 # number of WriteReq MSHR miss cycles
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638system.cpu.dcache.demand_mshr_miss_latency::total 23661545500 # number of demand (read+write) MSHR miss cycles
639system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23661545500 # number of overall MSHR miss cycles
640system.cpu.dcache.overall_mshr_miss_latency::total 23661545500 # number of overall MSHR miss cycles
641system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94200592000 # number of ReadReq MSHR uncacheable cycles
642system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94200592000 # number of ReadReq MSHR uncacheable cycles
643system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2523051000 # number of WriteReq MSHR uncacheable cycles
644system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2523051000 # number of WriteReq MSHR uncacheable cycles
645system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96723643000 # number of overall MSHR uncacheable cycles
646system.cpu.dcache.overall_mshr_uncacheable_latency::total 96723643000 # number of overall MSHR uncacheable cycles
647system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098245 # mshr miss rate for ReadReq accesses
648system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098245 # mshr miss rate for ReadReq accesses
649system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037800 # mshr miss rate for WriteReq accesses
650system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037800 # mshr miss rate for WriteReq accesses
651system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074922 # mshr miss rate for demand accesses
652system.cpu.dcache.demand_mshr_miss_rate::total 0.074922 # mshr miss rate for demand accesses
653system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074922 # mshr miss rate for overall accesses
654system.cpu.dcache.overall_mshr_miss_rate::total 0.074922 # mshr miss rate for overall accesses
655system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12030.785751 # average ReadReq mshr miss latency
656system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12030.785751 # average ReadReq mshr miss latency
657system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25121.869698 # average WriteReq mshr miss latency
658system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25121.869698 # average WriteReq mshr miss latency
659system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14579.244665 # average overall mshr miss latency
660system.cpu.dcache.demand_avg_mshr_miss_latency::total 14579.244665 # average overall mshr miss latency
661system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14579.244665 # average overall mshr miss latency
662system.cpu.dcache.overall_avg_mshr_miss_latency::total 14579.244665 # average overall mshr miss latency
663system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
664system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
665system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
666system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
667system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
668system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
669system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
670system.cpu.l2cache.replacements 86848 # number of replacements
671system.cpu.l2cache.tagsinuse 64773.888762 # Cycle average of tags in use
672system.cpu.l2cache.total_refs 3493567 # Total number of references to valid blocks.
673system.cpu.l2cache.sampled_refs 151551 # Sample count of references to valid blocks.
674system.cpu.l2cache.avg_refs 23.052088 # Average number of references to valid blocks.
675system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
676system.cpu.l2cache.occ_blocks::writebacks 50389.259334 # Average occupied blocks per requestor
677system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.140563 # Average occupied blocks per requestor
678system.cpu.l2cache.occ_blocks::cpu.inst 3365.987776 # Average occupied blocks per requestor
679system.cpu.l2cache.occ_blocks::cpu.data 11018.501089 # Average occupied blocks per requestor
680system.cpu.l2cache.occ_percent::writebacks 0.768879 # Average percentage of cache occupancy
681system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
682system.cpu.l2cache.occ_percent::cpu.inst 0.051361 # Average percentage of cache occupancy
683system.cpu.l2cache.occ_percent::cpu.data 0.168129 # Average percentage of cache occupancy
684system.cpu.l2cache.occ_percent::total 0.988371 # Average percentage of cache occupancy
685system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7121 # number of ReadReq hits
686system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3064 # number of ReadReq hits
687system.cpu.l2cache.ReadReq_hits::cpu.inst 783027 # number of ReadReq hits
688system.cpu.l2cache.ReadReq_hits::cpu.data 1277919 # number of ReadReq hits
689system.cpu.l2cache.ReadReq_hits::total 2071131 # number of ReadReq hits
690system.cpu.l2cache.Writeback_hits::writebacks 1541619 # number of Writeback hits
691system.cpu.l2cache.Writeback_hits::total 1541619 # number of Writeback hits
692system.cpu.l2cache.UpgradeReq_hits::cpu.data 322 # number of UpgradeReq hits
693system.cpu.l2cache.UpgradeReq_hits::total 322 # number of UpgradeReq hits
694system.cpu.l2cache.ReadExReq_hits::cpu.data 200393 # number of ReadExReq hits
695system.cpu.l2cache.ReadExReq_hits::total 200393 # number of ReadExReq hits
696system.cpu.l2cache.demand_hits::cpu.dtb.walker 7121 # number of demand (read+write) hits
697system.cpu.l2cache.demand_hits::cpu.itb.walker 3064 # number of demand (read+write) hits
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701system.cpu.l2cache.overall_hits::cpu.dtb.walker 7121 # number of overall hits
702system.cpu.l2cache.overall_hits::cpu.itb.walker 3064 # number of overall hits
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706system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
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711system.cpu.l2cache.UpgradeReq_misses::total 1357 # number of UpgradeReq misses
712system.cpu.l2cache.ReadExReq_misses::cpu.data 113361 # number of ReadExReq misses
713system.cpu.l2cache.ReadExReq_misses::total 113361 # number of ReadExReq misses
714system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
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718system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
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720system.cpu.l2cache.overall_misses::cpu.data 141700 # number of overall misses
721system.cpu.l2cache.overall_misses::total 154571 # number of overall misses
722system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 345000 # number of ReadReq miss cycles
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725system.cpu.l2cache.ReadReq_miss_latency::total 2437674500 # number of ReadReq miss cycles
726system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16426500 # number of UpgradeReq miss cycles
727system.cpu.l2cache.UpgradeReq_miss_latency::total 16426500 # number of UpgradeReq miss cycles
728system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5582026000 # number of ReadExReq miss cycles
729system.cpu.l2cache.ReadExReq_miss_latency::total 5582026000 # number of ReadExReq miss cycles
730system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 345000 # number of demand (read+write) miss cycles
731system.cpu.l2cache.demand_miss_latency::cpu.inst 799855500 # number of demand (read+write) miss cycles
732system.cpu.l2cache.demand_miss_latency::cpu.data 7219500000 # number of demand (read+write) miss cycles
733system.cpu.l2cache.demand_miss_latency::total 8019700500 # number of demand (read+write) miss cycles
734system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 345000 # number of overall miss cycles
735system.cpu.l2cache.overall_miss_latency::cpu.inst 799855500 # number of overall miss cycles
736system.cpu.l2cache.overall_miss_latency::cpu.data 7219500000 # number of overall miss cycles
737system.cpu.l2cache.overall_miss_latency::total 8019700500 # number of overall miss cycles
738system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7121 # number of ReadReq accesses(hits+misses)
739system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3069 # number of ReadReq accesses(hits+misses)
740system.cpu.l2cache.ReadReq_accesses::cpu.inst 795893 # number of ReadReq accesses(hits+misses)
741system.cpu.l2cache.ReadReq_accesses::cpu.data 1306258 # number of ReadReq accesses(hits+misses)
742system.cpu.l2cache.ReadReq_accesses::total 2112341 # number of ReadReq accesses(hits+misses)
743system.cpu.l2cache.Writeback_accesses::writebacks 1541619 # number of Writeback accesses(hits+misses)
744system.cpu.l2cache.Writeback_accesses::total 1541619 # number of Writeback accesses(hits+misses)
745system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1679 # number of UpgradeReq accesses(hits+misses)
746system.cpu.l2cache.UpgradeReq_accesses::total 1679 # number of UpgradeReq accesses(hits+misses)
747system.cpu.l2cache.ReadExReq_accesses::cpu.data 313754 # number of ReadExReq accesses(hits+misses)
748system.cpu.l2cache.ReadExReq_accesses::total 313754 # number of ReadExReq accesses(hits+misses)
749system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7121 # number of demand (read+write) accesses
750system.cpu.l2cache.demand_accesses::cpu.itb.walker 3069 # number of demand (read+write) accesses
751system.cpu.l2cache.demand_accesses::cpu.inst 795893 # number of demand (read+write) accesses
752system.cpu.l2cache.demand_accesses::cpu.data 1620012 # number of demand (read+write) accesses
753system.cpu.l2cache.demand_accesses::total 2426095 # number of demand (read+write) accesses
754system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7121 # number of overall (read+write) accesses
755system.cpu.l2cache.overall_accesses::cpu.itb.walker 3069 # number of overall (read+write) accesses
756system.cpu.l2cache.overall_accesses::cpu.inst 795893 # number of overall (read+write) accesses
757system.cpu.l2cache.overall_accesses::cpu.data 1620012 # number of overall (read+write) accesses
758system.cpu.l2cache.overall_accesses::total 2426095 # number of overall (read+write) accesses
759system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001629 # miss rate for ReadReq accesses
760system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016165 # miss rate for ReadReq accesses
761system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021695 # miss rate for ReadReq accesses
762system.cpu.l2cache.ReadReq_miss_rate::total 0.019509 # miss rate for ReadReq accesses
763system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.808219 # miss rate for UpgradeReq accesses
764system.cpu.l2cache.UpgradeReq_miss_rate::total 0.808219 # miss rate for UpgradeReq accesses
765system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361305 # miss rate for ReadExReq accesses
766system.cpu.l2cache.ReadExReq_miss_rate::total 0.361305 # miss rate for ReadExReq accesses
767system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001629 # miss rate for demand accesses
768system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016165 # miss rate for demand accesses
769system.cpu.l2cache.demand_miss_rate::cpu.data 0.087468 # miss rate for demand accesses
770system.cpu.l2cache.demand_miss_rate::total 0.063712 # miss rate for demand accesses
771system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001629 # miss rate for overall accesses
772system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016165 # miss rate for overall accesses
773system.cpu.l2cache.overall_miss_rate::cpu.data 0.087468 # miss rate for overall accesses
774system.cpu.l2cache.overall_miss_rate::total 0.063712 # miss rate for overall accesses
775system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 69000 # average ReadReq miss latency
776system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 62168.156381 # average ReadReq miss latency
777system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57781.643671 # average ReadReq miss latency
778system.cpu.l2cache.ReadReq_avg_miss_latency::total 59152.499393 # average ReadReq miss latency
779system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12105.011054 # average UpgradeReq miss latency
780system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12105.011054 # average UpgradeReq miss latency
781system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49241.149955 # average ReadExReq miss latency
782system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49241.149955 # average ReadExReq miss latency
783system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
784system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 62168.156381 # average overall miss latency
785system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50949.188426 # average overall miss latency
786system.cpu.l2cache.demand_avg_miss_latency::total 51883.603651 # average overall miss latency
787system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 69000 # average overall miss latency
788system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 62168.156381 # average overall miss latency
789system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50949.188426 # average overall miss latency
790system.cpu.l2cache.overall_avg_miss_latency::total 51883.603651 # average overall miss latency
791system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
792system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
793system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
794system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
795system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
796system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
797system.cpu.l2cache.fast_writes 0 # number of fast writes performed
798system.cpu.l2cache.cache_copies 0 # number of cache copies performed
799system.cpu.l2cache.writebacks::writebacks 79996 # number of writebacks
800system.cpu.l2cache.writebacks::total 79996 # number of writebacks
801system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
802system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12866 # number of ReadReq MSHR misses
803system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28339 # number of ReadReq MSHR misses
804system.cpu.l2cache.ReadReq_mshr_misses::total 41210 # number of ReadReq MSHR misses
805system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1357 # number of UpgradeReq MSHR misses
806system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses
807system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113361 # number of ReadExReq MSHR misses
808system.cpu.l2cache.ReadExReq_mshr_misses::total 113361 # number of ReadExReq MSHR misses
809system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
810system.cpu.l2cache.demand_mshr_misses::cpu.inst 12866 # number of demand (read+write) MSHR misses
811system.cpu.l2cache.demand_mshr_misses::cpu.data 141700 # number of demand (read+write) MSHR misses
812system.cpu.l2cache.demand_mshr_misses::total 154571 # number of demand (read+write) MSHR misses
813system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
814system.cpu.l2cache.overall_mshr_misses::cpu.inst 12866 # number of overall MSHR misses
815system.cpu.l2cache.overall_mshr_misses::cpu.data 141700 # number of overall MSHR misses
816system.cpu.l2cache.overall_mshr_misses::total 154571 # number of overall MSHR misses
817system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281255 # number of ReadReq MSHR miss cycles
818system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 639995855 # number of ReadReq MSHR miss cycles
819system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1285411156 # number of ReadReq MSHR miss cycles
820system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1925688266 # number of ReadReq MSHR miss cycles
821system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14543837 # number of UpgradeReq MSHR miss cycles
822system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14543837 # number of UpgradeReq MSHR miss cycles
823system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4189000523 # number of ReadExReq MSHR miss cycles
824system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4189000523 # number of ReadExReq MSHR miss cycles
825system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281255 # number of demand (read+write) MSHR miss cycles
826system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 639995855 # number of demand (read+write) MSHR miss cycles
827system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5474411679 # number of demand (read+write) MSHR miss cycles
828system.cpu.l2cache.demand_mshr_miss_latency::total 6114688789 # number of demand (read+write) MSHR miss cycles
829system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281255 # number of overall MSHR miss cycles
830system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 639995855 # number of overall MSHR miss cycles
831system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5474411679 # number of overall MSHR miss cycles
832system.cpu.l2cache.overall_mshr_miss_latency::total 6114688789 # number of overall MSHR miss cycles
833system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86642607500 # number of ReadReq MSHR uncacheable cycles
834system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86642607500 # number of ReadReq MSHR uncacheable cycles
835system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2357207000 # number of WriteReq MSHR uncacheable cycles
836system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2357207000 # number of WriteReq MSHR uncacheable cycles
837system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88999814500 # number of overall MSHR uncacheable cycles
838system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88999814500 # number of overall MSHR uncacheable cycles
839system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001629 # mshr miss rate for ReadReq accesses
840system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016165 # mshr miss rate for ReadReq accesses
841system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021695 # mshr miss rate for ReadReq accesses
842system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019509 # mshr miss rate for ReadReq accesses
843system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808219 # mshr miss rate for UpgradeReq accesses
844system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808219 # mshr miss rate for UpgradeReq accesses
845system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361305 # mshr miss rate for ReadExReq accesses
846system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361305 # mshr miss rate for ReadExReq accesses
847system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001629 # mshr miss rate for demand accesses
848system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016165 # mshr miss rate for demand accesses
849system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087468 # mshr miss rate for demand accesses
850system.cpu.l2cache.demand_mshr_miss_rate::total 0.063712 # mshr miss rate for demand accesses
851system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001629 # mshr miss rate for overall accesses
852system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016165 # mshr miss rate for overall accesses
853system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087468 # mshr miss rate for overall accesses
854system.cpu.l2cache.overall_mshr_miss_rate::total 0.063712 # mshr miss rate for overall accesses
855system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency
856system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49743.187859 # average ReadReq mshr miss latency
857system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45358.380889 # average ReadReq mshr miss latency
858system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46728.664547 # average ReadReq mshr miss latency
859system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10717.639646 # average UpgradeReq mshr miss latency
860system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10717.639646 # average UpgradeReq mshr miss latency
861system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36952.748503 # average ReadExReq mshr miss latency
862system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36952.748503 # average ReadExReq mshr miss latency
863system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
864system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49743.187859 # average overall mshr miss latency
865system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38633.815660 # average overall mshr miss latency
866system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39559.094455 # average overall mshr miss latency
867system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
868system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49743.187859 # average overall mshr miss latency
869system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38633.815660 # average overall mshr miss latency
870system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39559.094455 # average overall mshr miss latency
871system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
872system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
873system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
874system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
875system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
876system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
877system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
878
879---------- End Simulation Statistics ----------