1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.200396 # Number of seconds simulated
4sim_ticks 5200396150000 # Number of ticks simulated
5final_tick 5200396150000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 778841 # Simulator instruction rate (inst/s)
8host_op_rate 1501355 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 31560622919 # Simulator tick rate (ticks/s)
10host_mem_usage 627712 # Number of bytes of host memory used
11host_seconds 164.77 # Real time elapsed on the host
12sim_insts 128333376 # Number of instructions simulated
13sim_ops 247385531 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::pc.south_bridge.ide 2886336 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 825216 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 8967296 # Number of bytes read from this memory
21system.physmem.bytes_read::total 12679232 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 825216 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 825216 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 8106560 # Number of bytes written to this memory
25system.physmem.bytes_written::total 8106560 # Number of bytes written to this memory
26system.physmem.num_reads::pc.south_bridge.ide 45099 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.inst 12894 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.data 140114 # Number of read requests responded to by this memory
31system.physmem.num_reads::total 198113 # Number of read requests responded to by this memory
32system.physmem.num_writes::writebacks 126665 # Number of write requests responded to by this memory
33system.physmem.num_writes::total 126665 # Number of write requests responded to by this memory
34system.physmem.bw_read::pc.south_bridge.ide 555022 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.inst 158683 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.data 1724349 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::total 2438128 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_inst_read::cpu.inst 158683 # Instruction read bandwidth from this memory (bytes/s)
41system.physmem.bw_inst_read::total 158683 # Instruction read bandwidth from this memory (bytes/s)
42system.physmem.bw_write::writebacks 1558835 # Write bandwidth from this memory (bytes/s)
43system.physmem.bw_write::total 1558835 # Write bandwidth from this memory (bytes/s)
44system.physmem.bw_total::writebacks 1558835 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::pc.south_bridge.ide 555022 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
47system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::cpu.inst 158683 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.data 1724349 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::total 3996963 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.readReqs 198113 # Number of read requests accepted
52system.physmem.writeReqs 126665 # Number of write requests accepted
53system.physmem.readBursts 198113 # Number of DRAM read bursts, including those serviced by the write queue
54system.physmem.writeBursts 126665 # Number of DRAM write bursts, including those merged in the write queue
55system.physmem.bytesReadDRAM 12670976 # Total number of bytes read from DRAM
56system.physmem.bytesReadWrQ 8256 # Total number of bytes read from write queue
57system.physmem.bytesWritten 8105536 # Total number of bytes written to DRAM
58system.physmem.bytesReadSys 12679232 # Total read bytes from the system interface side
59system.physmem.bytesWrittenSys 8106560 # Total written bytes from the system interface side
60system.physmem.servicedByWrQ 129 # Number of DRAM read bursts serviced by the write queue
61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
62system.physmem.neitherReadNorWriteReqs 1623 # Number of requests that are neither read nor write
63system.physmem.perBankRdBursts::0 12177 # Per bank write bursts
64system.physmem.perBankRdBursts::1 12548 # Per bank write bursts
65system.physmem.perBankRdBursts::2 13053 # Per bank write bursts
66system.physmem.perBankRdBursts::3 12620 # Per bank write bursts
67system.physmem.perBankRdBursts::4 12592 # Per bank write bursts
68system.physmem.perBankRdBursts::5 12288 # Per bank write bursts
69system.physmem.perBankRdBursts::6 11961 # Per bank write bursts
70system.physmem.perBankRdBursts::7 12236 # Per bank write bursts
71system.physmem.perBankRdBursts::8 11972 # Per bank write bursts
72system.physmem.perBankRdBursts::9 11957 # Per bank write bursts
73system.physmem.perBankRdBursts::10 12338 # Per bank write bursts
74system.physmem.perBankRdBursts::11 12177 # Per bank write bursts
75system.physmem.perBankRdBursts::12 12807 # Per bank write bursts
76system.physmem.perBankRdBursts::13 12813 # Per bank write bursts
77system.physmem.perBankRdBursts::14 12433 # Per bank write bursts
78system.physmem.perBankRdBursts::15 12012 # Per bank write bursts
79system.physmem.perBankWrBursts::0 7757 # Per bank write bursts
80system.physmem.perBankWrBursts::1 8145 # Per bank write bursts
81system.physmem.perBankWrBursts::2 8603 # Per bank write bursts
82system.physmem.perBankWrBursts::3 8164 # Per bank write bursts
83system.physmem.perBankWrBursts::4 8201 # Per bank write bursts
84system.physmem.perBankWrBursts::5 7973 # Per bank write bursts
85system.physmem.perBankWrBursts::6 7511 # Per bank write bursts
86system.physmem.perBankWrBursts::7 7789 # Per bank write bursts
87system.physmem.perBankWrBursts::8 7356 # Per bank write bursts
88system.physmem.perBankWrBursts::9 7523 # Per bank write bursts
89system.physmem.perBankWrBursts::10 7874 # Per bank write bursts
90system.physmem.perBankWrBursts::11 7684 # Per bank write bursts
91system.physmem.perBankWrBursts::12 8313 # Per bank write bursts
92system.physmem.perBankWrBursts::13 8300 # Per bank write bursts
93system.physmem.perBankWrBursts::14 7968 # Per bank write bursts
94system.physmem.perBankWrBursts::15 7488 # Per bank write bursts
95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
96system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
97system.physmem.totGap 5200396086500 # Total gap between requests
98system.physmem.readPktSize::0 0 # Read request sizes (log2)
99system.physmem.readPktSize::1 0 # Read request sizes (log2)
100system.physmem.readPktSize::2 0 # Read request sizes (log2)
101system.physmem.readPktSize::3 0 # Read request sizes (log2)
102system.physmem.readPktSize::4 0 # Read request sizes (log2)
103system.physmem.readPktSize::5 0 # Read request sizes (log2)
104system.physmem.readPktSize::6 198113 # Read request sizes (log2)
105system.physmem.writePktSize::0 0 # Write request sizes (log2)
106system.physmem.writePktSize::1 0 # Write request sizes (log2)
107system.physmem.writePktSize::2 0 # Write request sizes (log2)
108system.physmem.writePktSize::3 0 # Write request sizes (log2)
109system.physmem.writePktSize::4 0 # Write request sizes (log2)
110system.physmem.writePktSize::5 0 # Write request sizes (log2)
111system.physmem.writePktSize::6 126665 # Write request sizes (log2)
112system.physmem.rdQLenPdf::0 153621 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::1 2695 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::2 4322 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::3 2990 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::4 3543 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::5 4544 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::6 4208 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::7 3990 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::8 3280 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::9 2652 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::10 2195 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::11 1870 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::12 1376 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::13 1254 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::14 1133 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::15 1028 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::16 1144 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::17 834 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::18 668 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::19 612 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::20 25 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see

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151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::15 1639 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::16 1812 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::17 5075 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::18 5119 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::20 5183 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::21 5335 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::22 5509 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::23 5794 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::24 5985 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::25 6651 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::26 6946 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::27 6999 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::28 7260 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::29 7338 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::30 7801 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::31 7668 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::32 7468 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::33 2018 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::34 1858 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::35 2408 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::36 2636 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::37 2551 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::38 2242 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::39 1885 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::40 1536 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::41 1298 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::42 897 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::43 721 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::44 585 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::45 277 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::46 223 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::47 173 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::51 72 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::53 44 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::55 21 # What write queue length does an incoming req see
200system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see
201system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see
202system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see
203system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see
204system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see
205system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see
206system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see
207system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
208system.physmem.bytesPerActivate::samples 59433 # Bytes accessed per row activation
209system.physmem.bytesPerActivate::mean 349.577642 # Bytes accessed per row activation
210system.physmem.bytesPerActivate::gmean 202.117781 # Bytes accessed per row activation
211system.physmem.bytesPerActivate::stdev 357.932182 # Bytes accessed per row activation
212system.physmem.bytesPerActivate::0-127 20505 34.50% 34.50% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::128-255 13774 23.18% 57.68% # Bytes accessed per row activation
214system.physmem.bytesPerActivate::256-383 5765 9.70% 67.38% # Bytes accessed per row activation
215system.physmem.bytesPerActivate::384-511 3461 5.82% 73.20% # Bytes accessed per row activation
216system.physmem.bytesPerActivate::512-639 2240 3.77% 76.97% # Bytes accessed per row activation
217system.physmem.bytesPerActivate::640-767 1591 2.68% 79.65% # Bytes accessed per row activation
218system.physmem.bytesPerActivate::768-895 1115 1.88% 81.52% # Bytes accessed per row activation
219system.physmem.bytesPerActivate::896-1023 921 1.55% 83.07% # Bytes accessed per row activation
220system.physmem.bytesPerActivate::1024-1151 10061 16.93% 100.00% # Bytes accessed per row activation
221system.physmem.bytesPerActivate::total 59433 # Bytes accessed per row activation
222system.physmem.rdPerTurnAround::samples 6976 # Reads before turning the bus around for writes
223system.physmem.rdPerTurnAround::mean 28.380447 # Reads before turning the bus around for writes
224system.physmem.rdPerTurnAround::stdev 572.057676 # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::0-2047 6975 99.99% 99.99% # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::total 6976 # Reads before turning the bus around for writes
228system.physmem.wrPerTurnAround::samples 6976 # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::mean 18.154960 # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::gmean 17.623474 # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::stdev 5.583584 # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::16-17 4785 68.59% 68.59% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::18-19 1454 20.84% 89.44% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::20-21 33 0.47% 89.91% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::22-23 125 1.79% 91.70% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::24-25 57 0.82% 92.52% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::26-27 47 0.67% 93.19% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::28-29 75 1.08% 94.27% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::30-31 59 0.85% 95.11% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::32-33 41 0.59% 95.70% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::34-35 19 0.27% 95.97% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::36-37 30 0.43% 96.40% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::38-39 56 0.80% 97.20% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::40-41 145 2.08% 99.28% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::42-43 17 0.24% 99.53% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::44-45 4 0.06% 99.58% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::46-47 11 0.16% 99.74% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::48-49 3 0.04% 99.78% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::50-51 3 0.04% 99.83% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::52-53 2 0.03% 99.86% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::54-55 2 0.03% 99.89% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::56-57 1 0.01% 99.90% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::58-59 1 0.01% 99.91% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::60-61 2 0.03% 99.94% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::62-63 3 0.04% 99.99% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::68-69 1 0.01% 100.00% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::total 6976 # Writes before turning the bus around for reads
258system.physmem.totQLat 5514862500 # Total ticks spent queuing
259system.physmem.totMemAccLat 9227062500 # Total ticks spent from burst creation until serviced by the DRAM
260system.physmem.totBusLat 989920000 # Total ticks spent in databus transfers
261system.physmem.avgQLat 27855.09 # Average queueing delay per DRAM burst
262system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
263system.physmem.avgMemAccLat 46605.09 # Average memory access latency per DRAM burst
264system.physmem.avgRdBW 2.44 # Average DRAM read bandwidth in MiByte/s
265system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MiByte/s
266system.physmem.avgRdBWSys 2.44 # Average system read bandwidth in MiByte/s
267system.physmem.avgWrBWSys 1.56 # Average system write bandwidth in MiByte/s
268system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
269system.physmem.busUtil 0.03 # Data bus utilization in percentage
270system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
271system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
272system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
273system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing
274system.physmem.readRowHits 166366 # Number of row buffer hits during reads
275system.physmem.writeRowHits 98833 # Number of row buffer hits during writes
276system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads
277system.physmem.writeRowHitRate 78.03 # Row buffer hit rate for writes
278system.physmem.avgGap 16012156.26 # Average gap between requests
279system.physmem.pageHitRate 81.69 # Row buffer hit rate, read and write combined
280system.physmem.memoryStateTime::IDLE 4979189621500 # Time in different power states
281system.physmem.memoryStateTime::REF 173652440000 # Time in different power states
282system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
283system.physmem.memoryStateTime::ACT 47553973500 # Time in different power states
284system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
285system.membus.throughput 4356964 # Throughput (bytes/s)
286system.membus.trans_dist::ReadReq 623381 # Transaction distribution
287system.membus.trans_dist::ReadResp 623381 # Transaction distribution
288system.membus.trans_dist::WriteReq 13777 # Transaction distribution
289system.membus.trans_dist::WriteResp 13777 # Transaction distribution
290system.membus.trans_dist::Writeback 126665 # Transaction distribution
291system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution
292system.membus.trans_dist::UpgradeResp 1641 # Transaction distribution
293system.membus.trans_dist::ReadExReq 159285 # Transaction distribution
294system.membus.trans_dist::ReadExResp 159285 # Transaction distribution
295system.membus.trans_dist::MessageReq 1656 # Transaction distribution
296system.membus.trans_dist::MessageResp 1656 # Transaction distribution
297system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3312 # Packet count per connected master and slave (bytes)
298system.membus.pkt_count_system.apicbridge.master::total 3312 # Packet count per connected master and slave (bytes)
299system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes)
300system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710118 # Packet count per connected master and slave (bytes)
301system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 390454 # Packet count per connected master and slave (bytes)
302system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1580900 # Packet count per connected master and slave (bytes)
303system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139322 # Packet count per connected master and slave (bytes)
304system.membus.pkt_count_system.iocache.mem_side::total 139322 # Packet count per connected master and slave (bytes)
305system.membus.pkt_count::total 1723534 # Packet count per connected master and slave (bytes)
306system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6624 # Cumulative packet size per connected master and slave (bytes)
307system.membus.tot_pkt_size_system.apicbridge.master::total 6624 # Cumulative packet size per connected master and slave (bytes)
308system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes)
309system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420233 # Cumulative packet size per connected master and slave (bytes)
310system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14912768 # Cumulative packet size per connected master and slave (bytes)
311system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16579445 # Cumulative packet size per connected master and slave (bytes)
312system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5873024 # Cumulative packet size per connected master and slave (bytes)
313system.membus.tot_pkt_size_system.iocache.mem_side::total 5873024 # Cumulative packet size per connected master and slave (bytes)
314system.membus.tot_pkt_size::total 22459093 # Cumulative packet size per connected master and slave (bytes)
315system.membus.data_through_bus 22459093 # Total data (bytes)
316system.membus.snoop_data_through_bus 198848 # Total snoop data (bytes)
317system.membus.reqLayer0.occupancy 256797000 # Layer occupancy (ticks)
318system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
319system.membus.reqLayer1.occupancy 359321500 # Layer occupancy (ticks)
320system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
321system.membus.reqLayer2.occupancy 3312000 # Layer occupancy (ticks)
322system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
323system.membus.reqLayer3.occupancy 1351243000 # Layer occupancy (ticks)
324system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
325system.membus.respLayer0.occupancy 1656000 # Layer occupancy (ticks)
326system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
327system.membus.respLayer2.occupancy 2609486505 # Layer occupancy (ticks)
328system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
329system.membus.respLayer4.occupancy 429020250 # Layer occupancy (ticks)
330system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
331system.iocache.tags.replacements 47501 # number of replacements
332system.iocache.tags.tagsinuse 0.128246 # Cycle average of tags in use
333system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
334system.iocache.tags.sampled_refs 47517 # Sample count of references to valid blocks.
335system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
336system.iocache.tags.warmup_cycle 5049779388000 # Cycle when the warmup percentage was hit.
337system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.128246 # Average occupied blocks per requestor
338system.iocache.tags.occ_percent::pc.south_bridge.ide 0.008015 # Average percentage of cache occupancy
339system.iocache.tags.occ_percent::total 0.008015 # Average percentage of cache occupancy
340system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
341system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
342system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
343system.iocache.tags.tag_accesses 428004 # Number of tag accesses
344system.iocache.tags.data_accesses 428004 # Number of data accesses
345system.iocache.ReadReq_misses::pc.south_bridge.ide 836 # number of ReadReq misses
346system.iocache.ReadReq_misses::total 836 # number of ReadReq misses
347system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
348system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
349system.iocache.demand_misses::pc.south_bridge.ide 47556 # number of demand (read+write) misses
350system.iocache.demand_misses::total 47556 # number of demand (read+write) misses
351system.iocache.overall_misses::pc.south_bridge.ide 47556 # number of overall misses
352system.iocache.overall_misses::total 47556 # number of overall misses
353system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 140309686 # number of ReadReq miss cycles
354system.iocache.ReadReq_miss_latency::total 140309686 # number of ReadReq miss cycles
355system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 12229393602 # number of WriteReq miss cycles
356system.iocache.WriteReq_miss_latency::total 12229393602 # number of WriteReq miss cycles
357system.iocache.demand_miss_latency::pc.south_bridge.ide 12369703288 # number of demand (read+write) miss cycles
358system.iocache.demand_miss_latency::total 12369703288 # number of demand (read+write) miss cycles
359system.iocache.overall_miss_latency::pc.south_bridge.ide 12369703288 # number of overall miss cycles
360system.iocache.overall_miss_latency::total 12369703288 # number of overall miss cycles
361system.iocache.ReadReq_accesses::pc.south_bridge.ide 836 # number of ReadReq accesses(hits+misses)
362system.iocache.ReadReq_accesses::total 836 # number of ReadReq accesses(hits+misses)
363system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
364system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
365system.iocache.demand_accesses::pc.south_bridge.ide 47556 # number of demand (read+write) accesses
366system.iocache.demand_accesses::total 47556 # number of demand (read+write) accesses
367system.iocache.overall_accesses::pc.south_bridge.ide 47556 # number of overall (read+write) accesses
368system.iocache.overall_accesses::total 47556 # number of overall (read+write) accesses
369system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
370system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
371system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
372system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
373system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
374system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
375system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
376system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
377system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167834.552632 # average ReadReq miss latency
378system.iocache.ReadReq_avg_miss_latency::total 167834.552632 # average ReadReq miss latency
379system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 261759.280865 # average WriteReq miss latency
380system.iocache.WriteReq_avg_miss_latency::total 261759.280865 # average WriteReq miss latency
381system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 260108.152242 # average overall miss latency
382system.iocache.demand_avg_miss_latency::total 260108.152242 # average overall miss latency
383system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 260108.152242 # average overall miss latency
384system.iocache.overall_avg_miss_latency::total 260108.152242 # average overall miss latency
385system.iocache.blocked_cycles::no_mshrs 207651 # number of cycles access was blocked
386system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
387system.iocache.blocked::no_mshrs 17427 # number of cycles access was blocked
388system.iocache.blocked::no_targets 0 # number of cycles access was blocked
389system.iocache.avg_blocked_cycles::no_mshrs 11.915476 # average number of cycles each access was blocked
390system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
391system.iocache.fast_writes 0 # number of fast writes performed
392system.iocache.cache_copies 0 # number of cache copies performed
393system.iocache.writebacks::writebacks 46667 # number of writebacks
394system.iocache.writebacks::total 46667 # number of writebacks
395system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 836 # number of ReadReq MSHR misses
396system.iocache.ReadReq_mshr_misses::total 836 # number of ReadReq MSHR misses
397system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
398system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
399system.iocache.demand_mshr_misses::pc.south_bridge.ide 47556 # number of demand (read+write) MSHR misses
400system.iocache.demand_mshr_misses::total 47556 # number of demand (read+write) MSHR misses
401system.iocache.overall_mshr_misses::pc.south_bridge.ide 47556 # number of overall MSHR misses
402system.iocache.overall_mshr_misses::total 47556 # number of overall MSHR misses
403system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96812686 # number of ReadReq MSHR miss cycles
404system.iocache.ReadReq_mshr_miss_latency::total 96812686 # number of ReadReq MSHR miss cycles
405system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 9797946102 # number of WriteReq MSHR miss cycles
406system.iocache.WriteReq_mshr_miss_latency::total 9797946102 # number of WriteReq MSHR miss cycles
407system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 9894758788 # number of demand (read+write) MSHR miss cycles
408system.iocache.demand_mshr_miss_latency::total 9894758788 # number of demand (read+write) MSHR miss cycles
409system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 9894758788 # number of overall MSHR miss cycles
410system.iocache.overall_mshr_miss_latency::total 9894758788 # number of overall MSHR miss cycles
411system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
412system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
413system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
414system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
415system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
416system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
417system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
418system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
419system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115804.648325 # average ReadReq mshr miss latency
420system.iocache.ReadReq_avg_mshr_miss_latency::total 115804.648325 # average ReadReq mshr miss latency
421system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 209716.312115 # average WriteReq mshr miss latency
422system.iocache.WriteReq_avg_mshr_miss_latency::total 209716.312115 # average WriteReq mshr miss latency
423system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155 # average overall mshr miss latency
424system.iocache.demand_avg_mshr_miss_latency::total 208065.413155 # average overall mshr miss latency
425system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 208065.413155 # average overall mshr miss latency
426system.iocache.overall_avg_mshr_miss_latency::total 208065.413155 # average overall mshr miss latency
427system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
428system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
429system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
430system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
431system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
432system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
433system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
434system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
435system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
436system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
437system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
438system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
439system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
440system.iobus.throughput 630779 # Throughput (bytes/s)
441system.iobus.trans_dist::ReadReq 230141 # Transaction distribution
442system.iobus.trans_dist::ReadResp 230141 # Transaction distribution
443system.iobus.trans_dist::WriteReq 57579 # Transaction distribution
444system.iobus.trans_dist::WriteResp 57579 # Transaction distribution
445system.iobus.trans_dist::MessageReq 1656 # Transaction distribution
446system.iobus.trans_dist::MessageResp 1656 # Transaction distribution
447system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
448system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
449system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
450system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)

--- 7 unchanged lines hidden (view full) ---

458system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
459system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
460system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
461system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
462system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
463system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
464system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
465system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes)
466system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95112 # Packet count per connected master and slave (bytes)
467system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95112 # Packet count per connected master and slave (bytes)
468system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3312 # Packet count per connected master and slave (bytes)
469system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3312 # Packet count per connected master and slave (bytes)
470system.iobus.pkt_count::total 578752 # Packet count per connected master and slave (bytes)
471system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
472system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
473system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
474system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
475system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
476system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
477system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
478system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
479system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
480system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
481system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
482system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
483system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
484system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
485system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
486system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
487system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
488system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
489system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes)
490system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027232 # Cumulative packet size per connected master and slave (bytes)
491system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027232 # Cumulative packet size per connected master and slave (bytes)
492system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6624 # Cumulative packet size per connected master and slave (bytes)
493system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6624 # Cumulative packet size per connected master and slave (bytes)
494system.iobus.tot_pkt_size::total 3280300 # Cumulative packet size per connected master and slave (bytes)
495system.iobus.data_through_bus 3280300 # Total data (bytes)
496system.iobus.reqLayer0.occupancy 3954900 # Layer occupancy (ticks)
497system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
498system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
499system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
500system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
501system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
502system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks)
503system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
504system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)

--- 19 unchanged lines hidden (view full) ---

524system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
525system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
526system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
527system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
528system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
529system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
530system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
531system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
532system.iobus.reqLayer18.occupancy 424640038 # Layer occupancy (ticks)
533system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
534system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
535system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
536system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks)
537system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
538system.iobus.respLayer1.occupancy 53686750 # Layer occupancy (ticks)
539system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
540system.iobus.respLayer2.occupancy 1656000 # Layer occupancy (ticks)
541system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
542system.cpu_clk_domain.clock 500 # Clock period in ticks
543system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
544system.cpu.numCycles 10400792300 # number of cpu cycles simulated
545system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
546system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
547system.cpu.committedInsts 128333376 # Number of instructions committed
548system.cpu.committedOps 247385531 # Number of ops (including micro ops) committed
549system.cpu.num_int_alu_accesses 231978349 # Number of integer alu accesses
550system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
551system.cpu.num_func_calls 2299991 # number of times a function call or return occured
552system.cpu.num_conditional_control_insts 23168967 # number of instructions that are conditional controls
553system.cpu.num_int_insts 231978349 # number of integer instructions
554system.cpu.num_fp_insts 0 # number of float instructions
555system.cpu.num_int_register_reads 434511356 # number of times the integer registers were read
556system.cpu.num_int_register_writes 197852349 # number of times the integer registers were written
557system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
558system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
559system.cpu.num_cc_register_reads 132811982 # number of times the CC registers were read
560system.cpu.num_cc_register_writes 95533715 # number of times the CC registers were written
561system.cpu.num_mem_refs 22244872 # number of memory refs
562system.cpu.num_load_insts 13879055 # Number of load instructions
563system.cpu.num_store_insts 8365817 # Number of store instructions
564system.cpu.num_idle_cycles 9793794512.998117 # Number of idle cycles
565system.cpu.num_busy_cycles 606997787.001883 # Number of busy cycles
566system.cpu.not_idle_fraction 0.058361 # Percentage of non-idle cycles
567system.cpu.idle_fraction 0.941639 # Percentage of idle cycles
568system.cpu.Branches 26307123 # Number of branches fetched
569system.cpu.op_class::No_OpClass 174810 0.07% 0.07% # Class of executed instruction
570system.cpu.op_class::IntAlu 224704553 90.83% 90.90% # Class of executed instruction
571system.cpu.op_class::IntMult 139755 0.06% 90.96% # Class of executed instruction
572system.cpu.op_class::IntDiv 123089 0.05% 91.01% # Class of executed instruction
573system.cpu.op_class::FloatAdd 0 0.00% 91.01% # Class of executed instruction
574system.cpu.op_class::FloatCmp 0 0.00% 91.01% # Class of executed instruction
575system.cpu.op_class::FloatCvt 0 0.00% 91.01% # Class of executed instruction
576system.cpu.op_class::FloatMult 0 0.00% 91.01% # Class of executed instruction
577system.cpu.op_class::FloatDiv 0 0.00% 91.01% # Class of executed instruction
578system.cpu.op_class::FloatSqrt 0 0.00% 91.01% # Class of executed instruction
579system.cpu.op_class::SimdAdd 0 0.00% 91.01% # Class of executed instruction
580system.cpu.op_class::SimdAddAcc 0 0.00% 91.01% # Class of executed instruction
581system.cpu.op_class::SimdAlu 0 0.00% 91.01% # Class of executed instruction
582system.cpu.op_class::SimdCmp 0 0.00% 91.01% # Class of executed instruction
583system.cpu.op_class::SimdCvt 0 0.00% 91.01% # Class of executed instruction
584system.cpu.op_class::SimdMisc 0 0.00% 91.01% # Class of executed instruction
585system.cpu.op_class::SimdMult 0 0.00% 91.01% # Class of executed instruction
586system.cpu.op_class::SimdMultAcc 0 0.00% 91.01% # Class of executed instruction
587system.cpu.op_class::SimdShift 0 0.00% 91.01% # Class of executed instruction
588system.cpu.op_class::SimdShiftAcc 0 0.00% 91.01% # Class of executed instruction
589system.cpu.op_class::SimdSqrt 0 0.00% 91.01% # Class of executed instruction
590system.cpu.op_class::SimdFloatAdd 0 0.00% 91.01% # Class of executed instruction
591system.cpu.op_class::SimdFloatAlu 0 0.00% 91.01% # Class of executed instruction
592system.cpu.op_class::SimdFloatCmp 0 0.00% 91.01% # Class of executed instruction
593system.cpu.op_class::SimdFloatCvt 0 0.00% 91.01% # Class of executed instruction
594system.cpu.op_class::SimdFloatDiv 0 0.00% 91.01% # Class of executed instruction
595system.cpu.op_class::SimdFloatMisc 0 0.00% 91.01% # Class of executed instruction
596system.cpu.op_class::SimdFloatMult 0 0.00% 91.01% # Class of executed instruction
597system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.01% # Class of executed instruction
598system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.01% # Class of executed instruction
599system.cpu.op_class::MemRead 13879055 5.61% 96.62% # Class of executed instruction
600system.cpu.op_class::MemWrite 8365817 3.38% 100.00% # Class of executed instruction
601system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
602system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
603system.cpu.op_class::total 247387079 # Class of executed instruction
604system.cpu.kern.inst.arm 0 # number of arm instructions executed
605system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
606system.cpu.icache.tags.replacements 791030 # number of replacements
607system.cpu.icache.tags.tagsinuse 510.352813 # Cycle average of tags in use
608system.cpu.icache.tags.total_refs 144579864 # Total number of references to valid blocks.
609system.cpu.icache.tags.sampled_refs 791542 # Sample count of references to valid blocks.
610system.cpu.icache.tags.avg_refs 182.655960 # Average number of references to valid blocks.
611system.cpu.icache.tags.warmup_cycle 161437750250 # Cycle when the warmup percentage was hit.
612system.cpu.icache.tags.occ_blocks::cpu.inst 510.352813 # Average occupied blocks per requestor
613system.cpu.icache.tags.occ_percent::cpu.inst 0.996783 # Average percentage of cache occupancy
614system.cpu.icache.tags.occ_percent::total 0.996783 # Average percentage of cache occupancy
615system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
616system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
617system.cpu.icache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id
618system.cpu.icache.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id
619system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id
620system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
621system.cpu.icache.tags.tag_accesses 146162962 # Number of tag accesses
622system.cpu.icache.tags.data_accesses 146162962 # Number of data accesses
623system.cpu.icache.ReadReq_hits::cpu.inst 144579864 # number of ReadReq hits
624system.cpu.icache.ReadReq_hits::total 144579864 # number of ReadReq hits
625system.cpu.icache.demand_hits::cpu.inst 144579864 # number of demand (read+write) hits
626system.cpu.icache.demand_hits::total 144579864 # number of demand (read+write) hits
627system.cpu.icache.overall_hits::cpu.inst 144579864 # number of overall hits
628system.cpu.icache.overall_hits::total 144579864 # number of overall hits
629system.cpu.icache.ReadReq_misses::cpu.inst 791549 # number of ReadReq misses
630system.cpu.icache.ReadReq_misses::total 791549 # number of ReadReq misses
631system.cpu.icache.demand_misses::cpu.inst 791549 # number of demand (read+write) misses
632system.cpu.icache.demand_misses::total 791549 # number of demand (read+write) misses
633system.cpu.icache.overall_misses::cpu.inst 791549 # number of overall misses
634system.cpu.icache.overall_misses::total 791549 # number of overall misses
635system.cpu.icache.ReadReq_miss_latency::cpu.inst 11108553755 # number of ReadReq miss cycles
636system.cpu.icache.ReadReq_miss_latency::total 11108553755 # number of ReadReq miss cycles
637system.cpu.icache.demand_miss_latency::cpu.inst 11108553755 # number of demand (read+write) miss cycles
638system.cpu.icache.demand_miss_latency::total 11108553755 # number of demand (read+write) miss cycles
639system.cpu.icache.overall_miss_latency::cpu.inst 11108553755 # number of overall miss cycles
640system.cpu.icache.overall_miss_latency::total 11108553755 # number of overall miss cycles
641system.cpu.icache.ReadReq_accesses::cpu.inst 145371413 # number of ReadReq accesses(hits+misses)
642system.cpu.icache.ReadReq_accesses::total 145371413 # number of ReadReq accesses(hits+misses)
643system.cpu.icache.demand_accesses::cpu.inst 145371413 # number of demand (read+write) accesses
644system.cpu.icache.demand_accesses::total 145371413 # number of demand (read+write) accesses
645system.cpu.icache.overall_accesses::cpu.inst 145371413 # number of overall (read+write) accesses
646system.cpu.icache.overall_accesses::total 145371413 # number of overall (read+write) accesses
647system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005445 # miss rate for ReadReq accesses
648system.cpu.icache.ReadReq_miss_rate::total 0.005445 # miss rate for ReadReq accesses
649system.cpu.icache.demand_miss_rate::cpu.inst 0.005445 # miss rate for demand accesses
650system.cpu.icache.demand_miss_rate::total 0.005445 # miss rate for demand accesses
651system.cpu.icache.overall_miss_rate::cpu.inst 0.005445 # miss rate for overall accesses
652system.cpu.icache.overall_miss_rate::total 0.005445 # miss rate for overall accesses
653system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14033.943262 # average ReadReq miss latency
654system.cpu.icache.ReadReq_avg_miss_latency::total 14033.943262 # average ReadReq miss latency
655system.cpu.icache.demand_avg_miss_latency::cpu.inst 14033.943262 # average overall miss latency
656system.cpu.icache.demand_avg_miss_latency::total 14033.943262 # average overall miss latency
657system.cpu.icache.overall_avg_miss_latency::cpu.inst 14033.943262 # average overall miss latency
658system.cpu.icache.overall_avg_miss_latency::total 14033.943262 # average overall miss latency
659system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
660system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
661system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
662system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
663system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
664system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
665system.cpu.icache.fast_writes 0 # number of fast writes performed
666system.cpu.icache.cache_copies 0 # number of cache copies performed
667system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791549 # number of ReadReq MSHR misses
668system.cpu.icache.ReadReq_mshr_misses::total 791549 # number of ReadReq MSHR misses
669system.cpu.icache.demand_mshr_misses::cpu.inst 791549 # number of demand (read+write) MSHR misses
670system.cpu.icache.demand_mshr_misses::total 791549 # number of demand (read+write) MSHR misses
671system.cpu.icache.overall_mshr_misses::cpu.inst 791549 # number of overall MSHR misses
672system.cpu.icache.overall_mshr_misses::total 791549 # number of overall MSHR misses
673system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9520697745 # number of ReadReq MSHR miss cycles
674system.cpu.icache.ReadReq_mshr_miss_latency::total 9520697745 # number of ReadReq MSHR miss cycles
675system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9520697745 # number of demand (read+write) MSHR miss cycles
676system.cpu.icache.demand_mshr_miss_latency::total 9520697745 # number of demand (read+write) MSHR miss cycles
677system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9520697745 # number of overall MSHR miss cycles
678system.cpu.icache.overall_mshr_miss_latency::total 9520697745 # number of overall MSHR miss cycles
679system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for ReadReq accesses
680system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005445 # mshr miss rate for ReadReq accesses
681system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for demand accesses
682system.cpu.icache.demand_mshr_miss_rate::total 0.005445 # mshr miss rate for demand accesses
683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005445 # mshr miss rate for overall accesses
684system.cpu.icache.overall_mshr_miss_rate::total 0.005445 # mshr miss rate for overall accesses
685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12027.932251 # average ReadReq mshr miss latency
686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12027.932251 # average ReadReq mshr miss latency
687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12027.932251 # average overall mshr miss latency
688system.cpu.icache.demand_avg_mshr_miss_latency::total 12027.932251 # average overall mshr miss latency
689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12027.932251 # average overall mshr miss latency
690system.cpu.icache.overall_avg_mshr_miss_latency::total 12027.932251 # average overall mshr miss latency
691system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
692system.cpu.itb_walker_cache.tags.replacements 3407 # number of replacements
693system.cpu.itb_walker_cache.tags.tagsinuse 3.079507 # Cycle average of tags in use
694system.cpu.itb_walker_cache.tags.total_refs 7935 # Total number of references to valid blocks.
695system.cpu.itb_walker_cache.tags.sampled_refs 3418 # Sample count of references to valid blocks.
696system.cpu.itb_walker_cache.tags.avg_refs 2.321533 # Average number of references to valid blocks.
697system.cpu.itb_walker_cache.tags.warmup_cycle 5169623666000 # Cycle when the warmup percentage was hit.
698system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.079507 # Average occupied blocks per requestor
699system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.192469 # Average percentage of cache occupancy
700system.cpu.itb_walker_cache.tags.occ_percent::total 0.192469 # Average percentage of cache occupancy
701system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id
702system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
703system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
704system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
705system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
706system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id
707system.cpu.itb_walker_cache.tags.tag_accesses 28718 # Number of tag accesses
708system.cpu.itb_walker_cache.tags.data_accesses 28718 # Number of data accesses
709system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7937 # number of ReadReq hits
710system.cpu.itb_walker_cache.ReadReq_hits::total 7937 # number of ReadReq hits
711system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
712system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
713system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7939 # number of demand (read+write) hits
714system.cpu.itb_walker_cache.demand_hits::total 7939 # number of demand (read+write) hits
715system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7939 # number of overall hits
716system.cpu.itb_walker_cache.overall_hits::total 7939 # number of overall hits
717system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4280 # number of ReadReq misses
718system.cpu.itb_walker_cache.ReadReq_misses::total 4280 # number of ReadReq misses
719system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4280 # number of demand (read+write) misses
720system.cpu.itb_walker_cache.demand_misses::total 4280 # number of demand (read+write) misses
721system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4280 # number of overall misses
722system.cpu.itb_walker_cache.overall_misses::total 4280 # number of overall misses
723system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42457500 # number of ReadReq miss cycles
724system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42457500 # number of ReadReq miss cycles
725system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42457500 # number of demand (read+write) miss cycles
726system.cpu.itb_walker_cache.demand_miss_latency::total 42457500 # number of demand (read+write) miss cycles
727system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42457500 # number of overall miss cycles
728system.cpu.itb_walker_cache.overall_miss_latency::total 42457500 # number of overall miss cycles
729system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12217 # number of ReadReq accesses(hits+misses)
730system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses)
731system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
732system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
733system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12219 # number of demand (read+write) accesses
734system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses
735system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12219 # number of overall (read+write) accesses
736system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses
737system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.350332 # miss rate for ReadReq accesses
738system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.350332 # miss rate for ReadReq accesses
739system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.350274 # miss rate for demand accesses
740system.cpu.itb_walker_cache.demand_miss_rate::total 0.350274 # miss rate for demand accesses
741system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.350274 # miss rate for overall accesses
742system.cpu.itb_walker_cache.overall_miss_rate::total 0.350274 # miss rate for overall accesses
743system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9919.976636 # average ReadReq miss latency
744system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9919.976636 # average ReadReq miss latency
745system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9919.976636 # average overall miss latency
746system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9919.976636 # average overall miss latency
747system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9919.976636 # average overall miss latency
748system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9919.976636 # average overall miss latency
749system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
750system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
751system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
752system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
753system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
754system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
755system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
756system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
757system.cpu.itb_walker_cache.writebacks::writebacks 704 # number of writebacks
758system.cpu.itb_walker_cache.writebacks::total 704 # number of writebacks
759system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4280 # number of ReadReq MSHR misses
760system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4280 # number of ReadReq MSHR misses
761system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4280 # number of demand (read+write) MSHR misses
762system.cpu.itb_walker_cache.demand_mshr_misses::total 4280 # number of demand (read+write) MSHR misses
763system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4280 # number of overall MSHR misses
764system.cpu.itb_walker_cache.overall_mshr_misses::total 4280 # number of overall MSHR misses
765system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33895500 # number of ReadReq MSHR miss cycles
766system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33895500 # number of ReadReq MSHR miss cycles
767system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33895500 # number of demand (read+write) MSHR miss cycles
768system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33895500 # number of demand (read+write) MSHR miss cycles
769system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33895500 # number of overall MSHR miss cycles
770system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33895500 # number of overall MSHR miss cycles
771system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.350332 # mshr miss rate for ReadReq accesses
772system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.350332 # mshr miss rate for ReadReq accesses
773system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.350274 # mshr miss rate for demand accesses
774system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.350274 # mshr miss rate for demand accesses
775system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.350274 # mshr miss rate for overall accesses
776system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.350274 # mshr miss rate for overall accesses
777system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average ReadReq mshr miss latency
778system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7919.509346 # average ReadReq mshr miss latency
779system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average overall mshr miss latency
780system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7919.509346 # average overall mshr miss latency
781system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7919.509346 # average overall mshr miss latency
782system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7919.509346 # average overall mshr miss latency
783system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
784system.cpu.dtb_walker_cache.tags.replacements 7502 # number of replacements
785system.cpu.dtb_walker_cache.tags.tagsinuse 5.061351 # Cycle average of tags in use
786system.cpu.dtb_walker_cache.tags.total_refs 13282 # Total number of references to valid blocks.
787system.cpu.dtb_walker_cache.tags.sampled_refs 7516 # Sample count of references to valid blocks.
788system.cpu.dtb_walker_cache.tags.avg_refs 1.767163 # Average number of references to valid blocks.
789system.cpu.dtb_walker_cache.tags.warmup_cycle 5167976228000 # Cycle when the warmup percentage was hit.
790system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.061351 # Average occupied blocks per requestor
791system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.316334 # Average percentage of cache occupancy
792system.cpu.dtb_walker_cache.tags.occ_percent::total 0.316334 # Average percentage of cache occupancy
793system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id
794system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id
795system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id
796system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
797system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
798system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id
799system.cpu.dtb_walker_cache.tags.tag_accesses 52668 # Number of tag accesses
800system.cpu.dtb_walker_cache.tags.data_accesses 52668 # Number of data accesses
801system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13284 # number of ReadReq hits
802system.cpu.dtb_walker_cache.ReadReq_hits::total 13284 # number of ReadReq hits
803system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13284 # number of demand (read+write) hits
804system.cpu.dtb_walker_cache.demand_hits::total 13284 # number of demand (read+write) hits
805system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13284 # number of overall hits
806system.cpu.dtb_walker_cache.overall_hits::total 13284 # number of overall hits
807system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8700 # number of ReadReq misses
808system.cpu.dtb_walker_cache.ReadReq_misses::total 8700 # number of ReadReq misses
809system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8700 # number of demand (read+write) misses
810system.cpu.dtb_walker_cache.demand_misses::total 8700 # number of demand (read+write) misses
811system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8700 # number of overall misses
812system.cpu.dtb_walker_cache.overall_misses::total 8700 # number of overall misses
813system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92345000 # number of ReadReq miss cycles
814system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92345000 # number of ReadReq miss cycles
815system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92345000 # number of demand (read+write) miss cycles
816system.cpu.dtb_walker_cache.demand_miss_latency::total 92345000 # number of demand (read+write) miss cycles
817system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92345000 # number of overall miss cycles
818system.cpu.dtb_walker_cache.overall_miss_latency::total 92345000 # number of overall miss cycles
819system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21984 # number of ReadReq accesses(hits+misses)
820system.cpu.dtb_walker_cache.ReadReq_accesses::total 21984 # number of ReadReq accesses(hits+misses)
821system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21984 # number of demand (read+write) accesses
822system.cpu.dtb_walker_cache.demand_accesses::total 21984 # number of demand (read+write) accesses
823system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21984 # number of overall (read+write) accesses
824system.cpu.dtb_walker_cache.overall_accesses::total 21984 # number of overall (read+write) accesses
825system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395742 # miss rate for ReadReq accesses
826system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395742 # miss rate for ReadReq accesses
827system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395742 # miss rate for demand accesses
828system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395742 # miss rate for demand accesses
829system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395742 # miss rate for overall accesses
830system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395742 # miss rate for overall accesses
831system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10614.367816 # average ReadReq miss latency
832system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10614.367816 # average ReadReq miss latency
833system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10614.367816 # average overall miss latency
834system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10614.367816 # average overall miss latency
835system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10614.367816 # average overall miss latency
836system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10614.367816 # average overall miss latency
837system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
838system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
839system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
840system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
841system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
842system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
843system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
844system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
845system.cpu.dtb_walker_cache.writebacks::writebacks 3054 # number of writebacks
846system.cpu.dtb_walker_cache.writebacks::total 3054 # number of writebacks
847system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8700 # number of ReadReq MSHR misses
848system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8700 # number of ReadReq MSHR misses
849system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8700 # number of demand (read+write) MSHR misses
850system.cpu.dtb_walker_cache.demand_mshr_misses::total 8700 # number of demand (read+write) MSHR misses
851system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8700 # number of overall MSHR misses
852system.cpu.dtb_walker_cache.overall_mshr_misses::total 8700 # number of overall MSHR misses
853system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74944500 # number of ReadReq MSHR miss cycles
854system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74944500 # number of ReadReq MSHR miss cycles
855system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74944500 # number of demand (read+write) MSHR miss cycles
856system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74944500 # number of demand (read+write) MSHR miss cycles
857system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74944500 # number of overall MSHR miss cycles
858system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74944500 # number of overall MSHR miss cycles
859system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for ReadReq accesses
860system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395742 # mshr miss rate for ReadReq accesses
861system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for demand accesses
862system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395742 # mshr miss rate for demand accesses
863system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395742 # mshr miss rate for overall accesses
864system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395742 # mshr miss rate for overall accesses
865system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average ReadReq mshr miss latency
866system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8614.310345 # average ReadReq mshr miss latency
867system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average overall mshr miss latency
868system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8614.310345 # average overall mshr miss latency
869system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8614.310345 # average overall mshr miss latency
870system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8614.310345 # average overall mshr miss latency
871system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
872system.cpu.dcache.tags.replacements 1620643 # number of replacements
873system.cpu.dcache.tags.tagsinuse 511.997078 # Cycle average of tags in use
874system.cpu.dcache.tags.total_refs 20036158 # Total number of references to valid blocks.
875system.cpu.dcache.tags.sampled_refs 1621155 # Sample count of references to valid blocks.
876system.cpu.dcache.tags.avg_refs 12.359187 # Average number of references to valid blocks.
877system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit.
878system.cpu.dcache.tags.occ_blocks::cpu.data 511.997078 # Average occupied blocks per requestor
879system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
880system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
881system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
882system.cpu.dcache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id
883system.cpu.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id
884system.cpu.dcache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
885system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
886system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
887system.cpu.dcache.tags.tag_accesses 88250512 # Number of tag accesses
888system.cpu.dcache.tags.data_accesses 88250512 # Number of data accesses
889system.cpu.dcache.ReadReq_hits::cpu.data 11993410 # number of ReadReq hits
890system.cpu.dcache.ReadReq_hits::total 11993410 # number of ReadReq hits
891system.cpu.dcache.WriteReq_hits::cpu.data 8040535 # number of WriteReq hits
892system.cpu.dcache.WriteReq_hits::total 8040535 # number of WriteReq hits
893system.cpu.dcache.demand_hits::cpu.data 20033945 # number of demand (read+write) hits
894system.cpu.dcache.demand_hits::total 20033945 # number of demand (read+write) hits
895system.cpu.dcache.overall_hits::cpu.data 20033945 # number of overall hits
896system.cpu.dcache.overall_hits::total 20033945 # number of overall hits
897system.cpu.dcache.ReadReq_misses::cpu.data 1308416 # number of ReadReq misses
898system.cpu.dcache.ReadReq_misses::total 1308416 # number of ReadReq misses
899system.cpu.dcache.WriteReq_misses::cpu.data 314973 # number of WriteReq misses
900system.cpu.dcache.WriteReq_misses::total 314973 # number of WriteReq misses
901system.cpu.dcache.demand_misses::cpu.data 1623389 # number of demand (read+write) misses
902system.cpu.dcache.demand_misses::total 1623389 # number of demand (read+write) misses
903system.cpu.dcache.overall_misses::cpu.data 1623389 # number of overall misses
904system.cpu.dcache.overall_misses::total 1623389 # number of overall misses
905system.cpu.dcache.ReadReq_miss_latency::cpu.data 18840132304 # number of ReadReq miss cycles
906system.cpu.dcache.ReadReq_miss_latency::total 18840132304 # number of ReadReq miss cycles
907system.cpu.dcache.WriteReq_miss_latency::cpu.data 10814294936 # number of WriteReq miss cycles
908system.cpu.dcache.WriteReq_miss_latency::total 10814294936 # number of WriteReq miss cycles
909system.cpu.dcache.demand_miss_latency::cpu.data 29654427240 # number of demand (read+write) miss cycles
910system.cpu.dcache.demand_miss_latency::total 29654427240 # number of demand (read+write) miss cycles
911system.cpu.dcache.overall_miss_latency::cpu.data 29654427240 # number of overall miss cycles
912system.cpu.dcache.overall_miss_latency::total 29654427240 # number of overall miss cycles
913system.cpu.dcache.ReadReq_accesses::cpu.data 13301826 # number of ReadReq accesses(hits+misses)
914system.cpu.dcache.ReadReq_accesses::total 13301826 # number of ReadReq accesses(hits+misses)
915system.cpu.dcache.WriteReq_accesses::cpu.data 8355508 # number of WriteReq accesses(hits+misses)
916system.cpu.dcache.WriteReq_accesses::total 8355508 # number of WriteReq accesses(hits+misses)
917system.cpu.dcache.demand_accesses::cpu.data 21657334 # number of demand (read+write) accesses
918system.cpu.dcache.demand_accesses::total 21657334 # number of demand (read+write) accesses
919system.cpu.dcache.overall_accesses::cpu.data 21657334 # number of overall (read+write) accesses
920system.cpu.dcache.overall_accesses::total 21657334 # number of overall (read+write) accesses
921system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098364 # miss rate for ReadReq accesses
922system.cpu.dcache.ReadReq_miss_rate::total 0.098364 # miss rate for ReadReq accesses
923system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037696 # miss rate for WriteReq accesses
924system.cpu.dcache.WriteReq_miss_rate::total 0.037696 # miss rate for WriteReq accesses
925system.cpu.dcache.demand_miss_rate::cpu.data 0.074958 # miss rate for demand accesses
926system.cpu.dcache.demand_miss_rate::total 0.074958 # miss rate for demand accesses
927system.cpu.dcache.overall_miss_rate::cpu.data 0.074958 # miss rate for overall accesses
928system.cpu.dcache.overall_miss_rate::total 0.074958 # miss rate for overall accesses
929system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14399.191315 # average ReadReq miss latency
930system.cpu.dcache.ReadReq_avg_miss_latency::total 14399.191315 # average ReadReq miss latency
931system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34334.037952 # average WriteReq miss latency
932system.cpu.dcache.WriteReq_avg_miss_latency::total 34334.037952 # average WriteReq miss latency
933system.cpu.dcache.demand_avg_miss_latency::cpu.data 18266.987912 # average overall miss latency
934system.cpu.dcache.demand_avg_miss_latency::total 18266.987912 # average overall miss latency
935system.cpu.dcache.overall_avg_miss_latency::cpu.data 18266.987912 # average overall miss latency
936system.cpu.dcache.overall_avg_miss_latency::total 18266.987912 # average overall miss latency
937system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
938system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
939system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
940system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
941system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
942system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
943system.cpu.dcache.fast_writes 0 # number of fast writes performed
944system.cpu.dcache.cache_copies 0 # number of cache copies performed
945system.cpu.dcache.writebacks::writebacks 1537613 # number of writebacks
946system.cpu.dcache.writebacks::total 1537613 # number of writebacks
947system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1308416 # number of ReadReq MSHR misses
948system.cpu.dcache.ReadReq_mshr_misses::total 1308416 # number of ReadReq MSHR misses
949system.cpu.dcache.WriteReq_mshr_misses::cpu.data 314973 # number of WriteReq MSHR misses
950system.cpu.dcache.WriteReq_mshr_misses::total 314973 # number of WriteReq MSHR misses
951system.cpu.dcache.demand_mshr_misses::cpu.data 1623389 # number of demand (read+write) MSHR misses
952system.cpu.dcache.demand_mshr_misses::total 1623389 # number of demand (read+write) MSHR misses
953system.cpu.dcache.overall_mshr_misses::cpu.data 1623389 # number of overall MSHR misses
954system.cpu.dcache.overall_mshr_misses::total 1623389 # number of overall MSHR misses
955system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16214330696 # number of ReadReq MSHR miss cycles
956system.cpu.dcache.ReadReq_mshr_miss_latency::total 16214330696 # number of ReadReq MSHR miss cycles
957system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10132215064 # number of WriteReq MSHR miss cycles
958system.cpu.dcache.WriteReq_mshr_miss_latency::total 10132215064 # number of WriteReq MSHR miss cycles
959system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26346545760 # number of demand (read+write) MSHR miss cycles
960system.cpu.dcache.demand_mshr_miss_latency::total 26346545760 # number of demand (read+write) MSHR miss cycles
961system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26346545760 # number of overall MSHR miss cycles
962system.cpu.dcache.overall_mshr_miss_latency::total 26346545760 # number of overall MSHR miss cycles
963system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672500 # number of ReadReq MSHR uncacheable cycles
964system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672500 # number of ReadReq MSHR uncacheable cycles
965system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537738000 # number of WriteReq MSHR uncacheable cycles
966system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537738000 # number of WriteReq MSHR uncacheable cycles
967system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96752410500 # number of overall MSHR uncacheable cycles
968system.cpu.dcache.overall_mshr_uncacheable_latency::total 96752410500 # number of overall MSHR uncacheable cycles
969system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098364 # mshr miss rate for ReadReq accesses
970system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098364 # mshr miss rate for ReadReq accesses
971system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037696 # mshr miss rate for WriteReq accesses
972system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037696 # mshr miss rate for WriteReq accesses
973system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074958 # mshr miss rate for demand accesses
974system.cpu.dcache.demand_mshr_miss_rate::total 0.074958 # mshr miss rate for demand accesses
975system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074958 # mshr miss rate for overall accesses
976system.cpu.dcache.overall_mshr_miss_rate::total 0.074958 # mshr miss rate for overall accesses
977system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12392.335997 # average ReadReq mshr miss latency
978system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12392.335997 # average ReadReq mshr miss latency
979system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32168.519410 # average WriteReq mshr miss latency
980system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32168.519410 # average WriteReq mshr miss latency
981system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16229.348456 # average overall mshr miss latency
982system.cpu.dcache.demand_avg_mshr_miss_latency::total 16229.348456 # average overall mshr miss latency
983system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16229.348456 # average overall mshr miss latency
984system.cpu.dcache.overall_avg_mshr_miss_latency::total 16229.348456 # average overall mshr miss latency
985system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
986system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
987system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
988system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
989system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
990system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
991system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
992system.cpu.toL2Bus.throughput 49146383 # Throughput (bytes/s)
993system.cpu.toL2Bus.trans_dist::ReadReq 2695227 # Transaction distribution
994system.cpu.toL2Bus.trans_dist::ReadResp 2694701 # Transaction distribution
995system.cpu.toL2Bus.trans_dist::WriteReq 13777 # Transaction distribution
996system.cpu.toL2Bus.trans_dist::WriteResp 13777 # Transaction distribution
997system.cpu.toL2Bus.trans_dist::Writeback 1541371 # Transaction distribution
998system.cpu.toL2Bus.trans_dist::UpgradeReq 2213 # Transaction distribution
999system.cpu.toL2Bus.trans_dist::UpgradeResp 2213 # Transaction distribution
1000system.cpu.toL2Bus.trans_dist::ReadExReq 359480 # Transaction distribution
1001system.cpu.toL2Bus.trans_dist::ReadExResp 312780 # Transaction distribution
1002system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1583085 # Packet count per connected master and slave (bytes)
1003system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5973901 # Packet count per connected master and slave (bytes)
1004system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7764 # Packet count per connected master and slave (bytes)
1005system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18139 # Packet count per connected master and slave (bytes)
1006system.cpu.toL2Bus.pkt_count::total 7582889 # Packet count per connected master and slave (bytes)
1007system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50658304 # Cumulative packet size per connected master and slave (bytes)
1008system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 203802165 # Cumulative packet size per connected master and slave (bytes)
1009system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 222976 # Cumulative packet size per connected master and slave (bytes)
1010system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 604096 # Cumulative packet size per connected master and slave (bytes)
1011system.cpu.toL2Bus.tot_pkt_size::total 255287541 # Cumulative packet size per connected master and slave (bytes)
1012system.cpu.toL2Bus.data_through_bus 255266421 # Total data (bytes)
1013system.cpu.toL2Bus.snoop_data_through_bus 314240 # Total snoop data (bytes)
1014system.cpu.toL2Bus.reqLayer0.occupancy 3830515500 # Layer occupancy (ticks)
1015system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
1016system.cpu.toL2Bus.snoopLayer0.occupancy 495000 # Layer occupancy (ticks)
1017system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1018system.cpu.toL2Bus.respLayer0.occupancy 1189702505 # Layer occupancy (ticks)
1019system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1020system.cpu.toL2Bus.respLayer1.occupancy 3051756740 # Layer occupancy (ticks)
1021system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
1022system.cpu.toL2Bus.respLayer2.occupancy 6421000 # Layer occupancy (ticks)
1023system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
1024system.cpu.toL2Bus.respLayer3.occupancy 13050250 # Layer occupancy (ticks)
1025system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
1026system.cpu.l2cache.tags.replacements 86651 # number of replacements
1027system.cpu.l2cache.tags.tagsinuse 64733.611120 # Cycle average of tags in use
1028system.cpu.l2cache.tags.total_refs 3487942 # Total number of references to valid blocks.
1029system.cpu.l2cache.tags.sampled_refs 151340 # Sample count of references to valid blocks.
1030system.cpu.l2cache.tags.avg_refs 23.047060 # Average number of references to valid blocks.
1031system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
1032system.cpu.l2cache.tags.occ_blocks::writebacks 50209.763854 # Average occupied blocks per requestor
1033system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.027833 # Average occupied blocks per requestor
1034system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141473 # Average occupied blocks per requestor
1035system.cpu.l2cache.tags.occ_blocks::cpu.inst 3434.458363 # Average occupied blocks per requestor
1036system.cpu.l2cache.tags.occ_blocks::cpu.data 11089.219598 # Average occupied blocks per requestor
1037system.cpu.l2cache.tags.occ_percent::writebacks 0.766140 # Average percentage of cache occupancy
1038system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
1039system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
1040system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052406 # Average percentage of cache occupancy
1041system.cpu.l2cache.tags.occ_percent::cpu.data 0.169208 # Average percentage of cache occupancy
1042system.cpu.l2cache.tags.occ_percent::total 0.987757 # Average percentage of cache occupancy
1043system.cpu.l2cache.tags.occ_task_id_blocks::1024 64689 # Occupied blocks per task id
1044system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
1045system.cpu.l2cache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
1046system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2880 # Occupied blocks per task id
1047system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4787 # Occupied blocks per task id
1048system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56896 # Occupied blocks per task id
1049system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987076 # Percentage of cache occupancy per task id
1050system.cpu.l2cache.tags.tag_accesses 32180689 # Number of tag accesses
1051system.cpu.l2cache.tags.data_accesses 32180689 # Number of data accesses
1052system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6384 # number of ReadReq hits
1053system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2775 # number of ReadReq hits
1054system.cpu.l2cache.ReadReq_hits::cpu.inst 778641 # number of ReadReq hits
1055system.cpu.l2cache.ReadReq_hits::cpu.data 1279470 # number of ReadReq hits
1056system.cpu.l2cache.ReadReq_hits::total 2067270 # number of ReadReq hits
1057system.cpu.l2cache.Writeback_hits::writebacks 1541371 # number of Writeback hits
1058system.cpu.l2cache.Writeback_hits::total 1541371 # number of Writeback hits
1059system.cpu.l2cache.UpgradeReq_hits::cpu.data 305 # number of UpgradeReq hits
1060system.cpu.l2cache.UpgradeReq_hits::total 305 # number of UpgradeReq hits
1061system.cpu.l2cache.ReadExReq_hits::cpu.data 199944 # number of ReadExReq hits
1062system.cpu.l2cache.ReadExReq_hits::total 199944 # number of ReadExReq hits
1063system.cpu.l2cache.demand_hits::cpu.dtb.walker 6384 # number of demand (read+write) hits
1064system.cpu.l2cache.demand_hits::cpu.itb.walker 2775 # number of demand (read+write) hits
1065system.cpu.l2cache.demand_hits::cpu.inst 778641 # number of demand (read+write) hits
1066system.cpu.l2cache.demand_hits::cpu.data 1479414 # number of demand (read+write) hits
1067system.cpu.l2cache.demand_hits::total 2267214 # number of demand (read+write) hits
1068system.cpu.l2cache.overall_hits::cpu.dtb.walker 6384 # number of overall hits
1069system.cpu.l2cache.overall_hits::cpu.itb.walker 2775 # number of overall hits
1070system.cpu.l2cache.overall_hits::cpu.inst 778641 # number of overall hits
1071system.cpu.l2cache.overall_hits::cpu.data 1479414 # number of overall hits
1072system.cpu.l2cache.overall_hits::total 2267214 # number of overall hits
1073system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
1074system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
1075system.cpu.l2cache.ReadReq_misses::cpu.inst 12895 # number of ReadReq misses
1076system.cpu.l2cache.ReadReq_misses::cpu.data 28198 # number of ReadReq misses
1077system.cpu.l2cache.ReadReq_misses::total 41099 # number of ReadReq misses
1078system.cpu.l2cache.UpgradeReq_misses::cpu.data 1394 # number of UpgradeReq misses
1079system.cpu.l2cache.UpgradeReq_misses::total 1394 # number of UpgradeReq misses
1080system.cpu.l2cache.ReadExReq_misses::cpu.data 112812 # number of ReadExReq misses
1081system.cpu.l2cache.ReadExReq_misses::total 112812 # number of ReadExReq misses
1082system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
1083system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
1084system.cpu.l2cache.demand_misses::cpu.inst 12895 # number of demand (read+write) misses
1085system.cpu.l2cache.demand_misses::cpu.data 141010 # number of demand (read+write) misses
1086system.cpu.l2cache.demand_misses::total 153911 # number of demand (read+write) misses
1087system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
1088system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
1089system.cpu.l2cache.overall_misses::cpu.inst 12895 # number of overall misses
1090system.cpu.l2cache.overall_misses::cpu.data 141010 # number of overall misses
1091system.cpu.l2cache.overall_misses::total 153911 # number of overall misses
1092system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles
1093system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 365000 # number of ReadReq miss cycles
1094system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 942725495 # number of ReadReq miss cycles
1095system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2110465196 # number of ReadReq miss cycles
1096system.cpu.l2cache.ReadReq_miss_latency::total 3053644941 # number of ReadReq miss cycles
1097system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16120870 # number of UpgradeReq miss cycles
1098system.cpu.l2cache.UpgradeReq_miss_latency::total 16120870 # number of UpgradeReq miss cycles
1099system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7781341940 # number of ReadExReq miss cycles
1100system.cpu.l2cache.ReadExReq_miss_latency::total 7781341940 # number of ReadExReq miss cycles
1101system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles
1102system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 365000 # number of demand (read+write) miss cycles
1103system.cpu.l2cache.demand_miss_latency::cpu.inst 942725495 # number of demand (read+write) miss cycles
1104system.cpu.l2cache.demand_miss_latency::cpu.data 9891807136 # number of demand (read+write) miss cycles
1105system.cpu.l2cache.demand_miss_latency::total 10834986881 # number of demand (read+write) miss cycles
1106system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles
1107system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 365000 # number of overall miss cycles
1108system.cpu.l2cache.overall_miss_latency::cpu.inst 942725495 # number of overall miss cycles
1109system.cpu.l2cache.overall_miss_latency::cpu.data 9891807136 # number of overall miss cycles
1110system.cpu.l2cache.overall_miss_latency::total 10834986881 # number of overall miss cycles
1111system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6385 # number of ReadReq accesses(hits+misses)
1112system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2780 # number of ReadReq accesses(hits+misses)
1113system.cpu.l2cache.ReadReq_accesses::cpu.inst 791536 # number of ReadReq accesses(hits+misses)
1114system.cpu.l2cache.ReadReq_accesses::cpu.data 1307668 # number of ReadReq accesses(hits+misses)
1115system.cpu.l2cache.ReadReq_accesses::total 2108369 # number of ReadReq accesses(hits+misses)
1116system.cpu.l2cache.Writeback_accesses::writebacks 1541371 # number of Writeback accesses(hits+misses)
1117system.cpu.l2cache.Writeback_accesses::total 1541371 # number of Writeback accesses(hits+misses)
1118system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1699 # number of UpgradeReq accesses(hits+misses)
1119system.cpu.l2cache.UpgradeReq_accesses::total 1699 # number of UpgradeReq accesses(hits+misses)
1120system.cpu.l2cache.ReadExReq_accesses::cpu.data 312756 # number of ReadExReq accesses(hits+misses)
1121system.cpu.l2cache.ReadExReq_accesses::total 312756 # number of ReadExReq accesses(hits+misses)
1122system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6385 # number of demand (read+write) accesses
1123system.cpu.l2cache.demand_accesses::cpu.itb.walker 2780 # number of demand (read+write) accesses
1124system.cpu.l2cache.demand_accesses::cpu.inst 791536 # number of demand (read+write) accesses
1125system.cpu.l2cache.demand_accesses::cpu.data 1620424 # number of demand (read+write) accesses
1126system.cpu.l2cache.demand_accesses::total 2421125 # number of demand (read+write) accesses
1127system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6385 # number of overall (read+write) accesses
1128system.cpu.l2cache.overall_accesses::cpu.itb.walker 2780 # number of overall (read+write) accesses
1129system.cpu.l2cache.overall_accesses::cpu.inst 791536 # number of overall (read+write) accesses
1130system.cpu.l2cache.overall_accesses::cpu.data 1620424 # number of overall (read+write) accesses
1131system.cpu.l2cache.overall_accesses::total 2421125 # number of overall (read+write) accesses
1132system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000157 # miss rate for ReadReq accesses
1133system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001799 # miss rate for ReadReq accesses
1134system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016291 # miss rate for ReadReq accesses
1135system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021564 # miss rate for ReadReq accesses
1136system.cpu.l2cache.ReadReq_miss_rate::total 0.019493 # miss rate for ReadReq accesses
1137system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.820483 # miss rate for UpgradeReq accesses
1138system.cpu.l2cache.UpgradeReq_miss_rate::total 0.820483 # miss rate for UpgradeReq accesses
1139system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360703 # miss rate for ReadExReq accesses
1140system.cpu.l2cache.ReadExReq_miss_rate::total 0.360703 # miss rate for ReadExReq accesses
1141system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000157 # miss rate for demand accesses
1142system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001799 # miss rate for demand accesses
1143system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016291 # miss rate for demand accesses
1144system.cpu.l2cache.demand_miss_rate::cpu.data 0.087020 # miss rate for demand accesses
1145system.cpu.l2cache.demand_miss_rate::total 0.063570 # miss rate for demand accesses
1146system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000157 # miss rate for overall accesses
1147system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001799 # miss rate for overall accesses
1148system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016291 # miss rate for overall accesses
1149system.cpu.l2cache.overall_miss_rate::cpu.data 0.087020 # miss rate for overall accesses
1150system.cpu.l2cache.overall_miss_rate::total 0.063570 # miss rate for overall accesses
1151system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency
1152system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 73000 # average ReadReq miss latency
1153system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73107.832105 # average ReadReq miss latency
1154system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74844.499468 # average ReadReq miss latency
1155system.cpu.l2cache.ReadReq_avg_miss_latency::total 74299.738217 # average ReadReq miss latency
1156system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11564.469154 # average UpgradeReq miss latency
1157system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11564.469154 # average UpgradeReq miss latency
1158system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68976.189944 # average ReadExReq miss latency
1159system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68976.189944 # average ReadExReq miss latency
1160system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
1161system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency
1162system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73107.832105 # average overall miss latency
1163system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70149.685384 # average overall miss latency
1164system.cpu.l2cache.demand_avg_miss_latency::total 70397.742078 # average overall miss latency
1165system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
1166system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 73000 # average overall miss latency
1167system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73107.832105 # average overall miss latency
1168system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70149.685384 # average overall miss latency
1169system.cpu.l2cache.overall_avg_miss_latency::total 70397.742078 # average overall miss latency
1170system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1171system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1172system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1173system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1174system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1175system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1176system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1177system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1178system.cpu.l2cache.writebacks::writebacks 79998 # number of writebacks
1179system.cpu.l2cache.writebacks::total 79998 # number of writebacks
1180system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses
1181system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
1182system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12895 # number of ReadReq MSHR misses
1183system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28198 # number of ReadReq MSHR misses
1184system.cpu.l2cache.ReadReq_mshr_misses::total 41099 # number of ReadReq MSHR misses
1185system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1394 # number of UpgradeReq MSHR misses
1186system.cpu.l2cache.UpgradeReq_mshr_misses::total 1394 # number of UpgradeReq MSHR misses
1187system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 112812 # number of ReadExReq MSHR misses
1188system.cpu.l2cache.ReadExReq_mshr_misses::total 112812 # number of ReadExReq MSHR misses
1189system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
1190system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
1191system.cpu.l2cache.demand_mshr_misses::cpu.inst 12895 # number of demand (read+write) MSHR misses
1192system.cpu.l2cache.demand_mshr_misses::cpu.data 141010 # number of demand (read+write) MSHR misses
1193system.cpu.l2cache.demand_mshr_misses::total 153911 # number of demand (read+write) MSHR misses
1194system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
1195system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
1196system.cpu.l2cache.overall_mshr_misses::cpu.inst 12895 # number of overall MSHR misses
1197system.cpu.l2cache.overall_mshr_misses::cpu.data 141010 # number of overall MSHR misses
1198system.cpu.l2cache.overall_mshr_misses::total 153911 # number of overall MSHR misses
1199system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles
1200system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 301500 # number of ReadReq MSHR miss cycles
1201system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 781175005 # number of ReadReq MSHR miss cycles
1202system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1757280304 # number of ReadReq MSHR miss cycles
1203system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2538833059 # number of ReadReq MSHR miss cycles
1204system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14868876 # number of UpgradeReq MSHR miss cycles
1205system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14868876 # number of UpgradeReq MSHR miss cycles
1206system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6370597060 # number of ReadExReq MSHR miss cycles
1207system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6370597060 # number of ReadExReq MSHR miss cycles
1208system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
1209system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 301500 # number of demand (read+write) MSHR miss cycles
1210system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 781175005 # number of demand (read+write) MSHR miss cycles
1211system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8127877364 # number of demand (read+write) MSHR miss cycles
1212system.cpu.l2cache.demand_mshr_miss_latency::total 8909430119 # number of demand (read+write) MSHR miss cycles
1213system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles
1214system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 301500 # number of overall MSHR miss cycles
1215system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 781175005 # number of overall MSHR miss cycles
1216system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8127877364 # number of overall MSHR miss cycles
1217system.cpu.l2cache.overall_mshr_miss_latency::total 8909430119 # number of overall MSHR miss cycles
1218system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655869000 # number of ReadReq MSHR uncacheable cycles
1219system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655869000 # number of ReadReq MSHR uncacheable cycles
1220system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2371075000 # number of WriteReq MSHR uncacheable cycles
1221system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2371075000 # number of WriteReq MSHR uncacheable cycles
1222system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026944000 # number of overall MSHR uncacheable cycles
1223system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026944000 # number of overall MSHR uncacheable cycles
1224system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses
1225system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for ReadReq accesses
1226system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for ReadReq accesses
1227system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021564 # mshr miss rate for ReadReq accesses
1228system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019493 # mshr miss rate for ReadReq accesses
1229system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.820483 # mshr miss rate for UpgradeReq accesses
1230system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.820483 # mshr miss rate for UpgradeReq accesses
1231system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360703 # mshr miss rate for ReadExReq accesses
1232system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360703 # mshr miss rate for ReadExReq accesses
1233system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses
1234system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for demand accesses
1235system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for demand accesses
1236system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087020 # mshr miss rate for demand accesses
1237system.cpu.l2cache.demand_mshr_miss_rate::total 0.063570 # mshr miss rate for demand accesses
1238system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses
1239system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001799 # mshr miss rate for overall accesses
1240system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016291 # mshr miss rate for overall accesses
1241system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087020 # mshr miss rate for overall accesses
1242system.cpu.l2cache.overall_mshr_miss_rate::total 0.063570 # mshr miss rate for overall accesses
1243system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
1244system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 60300 # average ReadReq mshr miss latency
1245system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60579.682435 # average ReadReq mshr miss latency
1246system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62319.324207 # average ReadReq mshr miss latency
1247system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61773.596900 # average ReadReq mshr miss latency
1248system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10666.338594 # average UpgradeReq mshr miss latency
1249system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10666.338594 # average UpgradeReq mshr miss latency
1250system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56470.916746 # average ReadExReq mshr miss latency
1251system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56470.916746 # average ReadExReq mshr miss latency
1252system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
1253system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
1254system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60579.682435 # average overall mshr miss latency
1255system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57640.432338 # average overall mshr miss latency
1256system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57886.896447 # average overall mshr miss latency
1257system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
1258system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 60300 # average overall mshr miss latency
1259system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60579.682435 # average overall mshr miss latency
1260system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57640.432338 # average overall mshr miss latency
1261system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57886.896447 # average overall mshr miss latency
1262system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
1263system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
1264system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
1265system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
1266system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
1267system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
1268system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1269
1270---------- End Simulation Statistics ----------