11c11
< children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
---
> children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table
14c14
< clock=1
---
> clock=1000
55c55
< clock=1
---
> clock=1000
65c65
< clock=1
---
> clock=1000
75c75
< children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer
---
> children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache l2cache toL2Bus tracer
106c106
< clock=1
---
> clock=500
108a109
> hit_latency=2
110d110
< latency=1000
116a117
> response_latency=2
120c121
< tgts_per_mshr=8
---
> tgts_per_mshr=20
125c126
< mem_side=system.toL2Bus.slave[1]
---
> mem_side=system.cpu.toL2Bus.slave[1]
135c136
< clock=1
---
> clock=500
144c145
< clock=1
---
> clock=500
147,148c148,149
< is_top_level=false
< latency=1000
---
> hit_latency=2
> is_top_level=true
154a156
> response_latency=2
163c165
< mem_side=system.toL2Bus.slave[3]
---
> mem_side=system.cpu.toL2Bus.slave[3]
170c172
< clock=1
---
> clock=500
172a175
> hit_latency=2
174d176
< latency=1000
180a183
> response_latency=2
184c187
< tgts_per_mshr=8
---
> tgts_per_mshr=20
189c192
< mem_side=system.toL2Bus.slave[0]
---
> mem_side=system.cpu.toL2Bus.slave[0]
193c196
< clock=1
---
> clock=500
210c213
< clock=1
---
> clock=500
219c222
< clock=1
---
> clock=500
222,223c225,226
< is_top_level=false
< latency=1000
---
> hit_latency=2
> is_top_level=true
229a233
> response_latency=2
238c242
< mem_side=system.toL2Bus.slave[2]
---
> mem_side=system.cpu.toL2Bus.slave[2]
239a244,280
> [system.cpu.l2cache]
> type=BaseCache
> addr_ranges=0:18446744073709551615
> assoc=8
> block_size=64
> clock=500
> forward_snoops=true
> hash_delay=1
> hit_latency=20
> is_top_level=false
> max_miss_count=0
> mshrs=20
> prefetch_on_access=false
> prefetcher=Null
> prioritizeRequests=false
> repl=Null
> response_latency=20
> size=4194304
> subblock_size=0
> system=system
> tgts_per_mshr=12
> trace_addr=0
> two_queue=false
> write_buffers=8
> cpu_side=system.cpu.toL2Bus.master[0]
> mem_side=system.membus.slave[3]
>
> [system.cpu.toL2Bus]
> type=CoherentBus
> block_size=64
> clock=500
> header_cycles=1
> use_default_range=false
> width=32
> master=system.cpu.l2cache.cpu_side
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
>
622c663
< clock=1
---
> clock=1000
625,626c666,667
< is_top_level=false
< latency=50000
---
> hit_latency=50
> is_top_level=true
632a674
> response_latency=50
643,668d684
< [system.l2c]
< type=BaseCache
< addr_ranges=0:18446744073709551615
< assoc=8
< block_size=64
< clock=1
< forward_snoops=true
< hash_delay=1
< is_top_level=false
< latency=10000
< max_miss_count=0
< mshrs=92
< prefetch_on_access=false
< prefetcher=Null
< prioritizeRequests=false
< repl=Null
< size=4194304
< subblock_size=0
< system=system
< tgts_per_mshr=16
< trace_addr=0
< two_queue=false
< write_buffers=8
< cpu_side=system.toL2Bus.master[0]
< mem_side=system.membus.slave[3]
<
679c695
< slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master
---
> slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
683c699
< clock=1
---
> clock=1000
706c722
< clock=1
---
> clock=1000
724c740
< clock=1
---
> clock=1000
748c764
< clock=1
---
> clock=1000
765c781
< clock=1
---
> clock=1000
782c798
< clock=1
---
> clock=1000
799c815
< clock=1
---
> clock=1000
816c832
< clock=1
---
> clock=1000
834c850
< clock=1
---
> clock=1000
857c873
< clock=1
---
> clock=1000
870c886
< clock=1
---
> clock=1000
917c933
< clock=1
---
> clock=1000
1052c1068
< clock=1
---
> clock=1000
1064c1080
< clock=1
---
> clock=1000
1083c1099
< clock=1
---
> clock=1000
1098c1114
< clock=1
---
> clock=1000
1113c1129
< clock=1
---
> clock=1000
1125c1141
< clock=1
---
> clock=1000
1133,1134c1149,1152
< type=SimpleMemory
< clock=1
---
> type=SimpleDRAM
> addr_mapping=openmap
> banks_per_rank=8
> clock=1000
1136d1153
< file=
1138,1139c1155,1156
< latency=30000
< latency_var=0
---
> lines_per_rowbuffer=64
> mem_sched_policy=fcfs
1140a1158
> page_policy=open
1141a1160,1170
> ranks_per_channel=2
> read_buffer_size=32
> tBURST=4000
> tCL=14000
> tRCD=14000
> tREFI=7800000
> tRFC=300000
> tRP=14000
> tWTR=1000
> write_buffer_size=32
> write_thresh_perc=70
1166,1175d1194
< [system.toL2Bus]
< type=CoherentBus
< block_size=64
< clock=1000
< header_cycles=1
< use_default_range=false
< width=8
< master=system.l2c.cpu_side
< slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
<