| stats.txt (9924:31ef410b6843) | stats.txt (9962:7aef35367a21) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112126 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112126 # Number of seconds simulated |
| 4sim_ticks 5112126311000 # Number of ticks simulated 5final_tick 5112126311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 5112126264500 # Number of ticks simulated 5final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1595516 # Simulator instruction rate (inst/s) 8host_op_rate 3266720 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 40796695114 # Simulator tick rate (ticks/s) 10host_mem_usage 587608 # Number of bytes of host memory used 11host_seconds 125.31 # Real time elapsed on the host | 7host_inst_rate 1904189 # Simulator instruction rate (inst/s) 8host_op_rate 3898708 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48689346278 # Simulator tick rate (ticks/s) 10host_mem_usage 587596 # Number of bytes of host memory used 11host_seconds 104.99 # Real time elapsed on the host |
| 12sim_insts 199929810 # Number of instructions simulated | 12sim_insts 199929810 # Number of instructions simulated |
| 13sim_ops 409343980 # Number of ops (including micro ops) simulated | 13sim_ops 409343850 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory --- 7 unchanged lines hidden (view full) --- 29system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s) | 14system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory --- 7 unchanged lines hidden (view full) --- 29system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::total 2715826 # Total read bandwidth from this memory (bytes/s) | 37system.physmem.bw_read::total 2715827 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s) | 38system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller 50system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 51system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 52system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 53system.physmem.bytesRead 0 # Total number of bytes read from memory 54system.physmem.bytesWritten 0 # Total number of bytes written to memory 55system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 56system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 57system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 58system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 59system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 75system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 91system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 92system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 93system.physmem.totGap 0 # Total gap between requests 94system.physmem.readPktSize::0 0 # Categorize read packet sizes 95system.physmem.readPktSize::1 0 # Categorize read packet sizes 96system.physmem.readPktSize::2 0 # Categorize read packet sizes 97system.physmem.readPktSize::3 0 # Categorize read packet sizes 98system.physmem.readPktSize::4 0 # Categorize read packet sizes 99system.physmem.readPktSize::5 0 # Categorize read packet sizes 100system.physmem.readPktSize::6 0 # Categorize read packet sizes 101system.physmem.writePktSize::0 0 # Categorize write packet sizes 102system.physmem.writePktSize::1 0 # Categorize write packet sizes 103system.physmem.writePktSize::2 0 # Categorize write packet sizes 104system.physmem.writePktSize::3 0 # Categorize write packet sizes 105system.physmem.writePktSize::4 0 # Categorize write packet sizes 106system.physmem.writePktSize::5 0 # Categorize write packet sizes 107system.physmem.writePktSize::6 0 # Categorize write packet sizes 108system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 172system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation 173system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation 174system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation 175system.physmem.totQLat 0 # Total cycles spent in queuing delays 176system.physmem.totMemAccLat 0 # Sum of mem lat for all requests 177system.physmem.totBusLat 0 # Total cycles spent in databus access 178system.physmem.totBankLat 0 # Total cycles spent in bank access 179system.physmem.avgQLat nan # Average queueing delay per request 180system.physmem.avgBankLat nan # Average bank access latency per request 181system.physmem.avgBusLat nan # Average bus latency per request 182system.physmem.avgMemAccLat nan # Average memory access latency 183system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 184system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 185system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 186system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 187system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 188system.physmem.busUtil 0.00 # Data bus utilization in percentage 189system.physmem.avgRdQLen 0.00 # Average read queue length over time 190system.physmem.avgWrQLen 0.00 # Average write queue length over time 191system.physmem.readRowHits 0 # Number of row buffer hits during reads 192system.physmem.writeRowHits 0 # Number of row buffer hits during writes 193system.physmem.readRowHitRate nan # Row buffer hit rate for reads 194system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 195system.physmem.avgGap nan # Average gap between requests | |
| 196system.membus.throughput 9634332 # Throughput (bytes/s) 197system.membus.data_through_bus 49251923 # Total data (bytes) 198system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 199system.iocache.tags.replacements 47569 # number of replacements 200system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use 201system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 202system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 203system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. --- 45 unchanged lines hidden (view full) --- 249system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 250system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 251system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 252system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 253system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 254system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 255system.iobus.throughput 2555207 # Throughput (bytes/s) 256system.iobus.data_through_bus 13062542 # Total data (bytes) | 49system.membus.throughput 9634332 # Throughput (bytes/s) 50system.membus.data_through_bus 49251923 # Total data (bytes) 51system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 52system.iocache.tags.replacements 47569 # number of replacements 53system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use 54system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 55system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 56system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. --- 45 unchanged lines hidden (view full) --- 102system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 103system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 104system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 105system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 106system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 107system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 108system.iobus.throughput 2555207 # Throughput (bytes/s) 109system.iobus.data_through_bus 13062542 # Total data (bytes) |
| 257system.cpu.numCycles 10224252644 # number of cpu cycles simulated | 110system.cpu.numCycles 10224252551 # number of cpu cycles simulated |
| 258system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 259system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 260system.cpu.committedInsts 199929810 # Number of instructions committed | 111system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 112system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 113system.cpu.committedInsts 199929810 # Number of instructions committed |
| 261system.cpu.committedOps 409343980 # Number of ops (including micro ops) committed 262system.cpu.num_int_alu_accesses 374364740 # Number of integer alu accesses | 114system.cpu.committedOps 409343850 # Number of ops (including micro ops) committed 115system.cpu.num_int_alu_accesses 374364636 # Number of integer alu accesses |
| 263system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 264system.cpu.num_func_calls 2307717 # number of times a function call or return occured | 116system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 117system.cpu.num_func_calls 2307717 # number of times a function call or return occured |
| 265system.cpu.num_conditional_control_insts 39976354 # number of instructions that are conditional controls 266system.cpu.num_int_insts 374364740 # number of integer instructions | 118system.cpu.num_conditional_control_insts 39976328 # number of instructions that are conditional controls 119system.cpu.num_int_insts 374364636 # number of integer instructions |
| 267system.cpu.num_fp_insts 0 # number of float instructions | 120system.cpu.num_fp_insts 0 # number of float instructions |
| 268system.cpu.num_int_register_reads 682285995 # number of times the integer registers were read 269system.cpu.num_int_register_writes 323369548 # number of times the integer registers were written | 121system.cpu.num_int_register_reads 682285475 # number of times the integer registers were read 122system.cpu.num_int_register_writes 323369236 # number of times the integer registers were written |
| 270system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 271system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 123system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 124system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 272system.cpu.num_cc_register_reads 233715170 # number of times the CC registers were read 273system.cpu.num_cc_register_writes 157233581 # number of times the CC registers were written | 125system.cpu.num_cc_register_reads 233715040 # number of times the CC registers were read 126system.cpu.num_cc_register_writes 157233555 # number of times the CC registers were written |
| 274system.cpu.num_mem_refs 35660913 # number of memory refs 275system.cpu.num_load_insts 27238816 # Number of load instructions 276system.cpu.num_store_insts 8422097 # Number of store instructions | 127system.cpu.num_mem_refs 35660913 # number of memory refs 128system.cpu.num_load_insts 27238816 # Number of load instructions 129system.cpu.num_store_insts 8422097 # Number of store instructions |
| 277system.cpu.num_idle_cycles 9770516880.735765 # Number of idle cycles 278system.cpu.num_busy_cycles 453735763.264236 # Number of busy cycles | 130system.cpu.num_idle_cycles 9770516920.735764 # Number of idle cycles 131system.cpu.num_busy_cycles 453735630.264235 # Number of busy cycles |
| 279system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles 280system.cpu.idle_fraction 0.955622 # Percentage of idle cycles 281system.cpu.kern.inst.arm 0 # number of arm instructions executed 282system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 132system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles 133system.cpu.idle_fraction 0.955622 # Percentage of idle cycles 134system.cpu.kern.inst.arm 0 # number of arm instructions executed 135system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 283system.cpu.icache.tags.replacements 790541 # number of replacements | 136system.cpu.icache.tags.replacements 790558 # number of replacements |
| 284system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use | 137system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use |
| 285system.cpu.icache.tags.total_refs 243525798 # Total number of references to valid blocks. 286system.cpu.icache.tags.sampled_refs 791053 # Sample count of references to valid blocks. 287system.cpu.icache.tags.avg_refs 307.850167 # Average number of references to valid blocks. | 138system.cpu.icache.tags.total_refs 243525778 # Total number of references to valid blocks. 139system.cpu.icache.tags.sampled_refs 791070 # Sample count of references to valid blocks. 140system.cpu.icache.tags.avg_refs 307.843526 # Average number of references to valid blocks. |
| 288system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. 289system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor 290system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy 291system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy | 141system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. 142system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor 143system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy 144system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy |
| 292system.cpu.icache.ReadReq_hits::cpu.inst 243525798 # number of ReadReq hits 293system.cpu.icache.ReadReq_hits::total 243525798 # number of ReadReq hits 294system.cpu.icache.demand_hits::cpu.inst 243525798 # number of demand (read+write) hits 295system.cpu.icache.demand_hits::total 243525798 # number of demand (read+write) hits 296system.cpu.icache.overall_hits::cpu.inst 243525798 # number of overall hits 297system.cpu.icache.overall_hits::total 243525798 # number of overall hits 298system.cpu.icache.ReadReq_misses::cpu.inst 791060 # number of ReadReq misses 299system.cpu.icache.ReadReq_misses::total 791060 # number of ReadReq misses 300system.cpu.icache.demand_misses::cpu.inst 791060 # number of demand (read+write) misses 301system.cpu.icache.demand_misses::total 791060 # number of demand (read+write) misses 302system.cpu.icache.overall_misses::cpu.inst 791060 # number of overall misses 303system.cpu.icache.overall_misses::total 791060 # number of overall misses 304system.cpu.icache.ReadReq_accesses::cpu.inst 244316858 # number of ReadReq accesses(hits+misses) 305system.cpu.icache.ReadReq_accesses::total 244316858 # number of ReadReq accesses(hits+misses) 306system.cpu.icache.demand_accesses::cpu.inst 244316858 # number of demand (read+write) accesses 307system.cpu.icache.demand_accesses::total 244316858 # number of demand (read+write) accesses 308system.cpu.icache.overall_accesses::cpu.inst 244316858 # number of overall (read+write) accesses 309system.cpu.icache.overall_accesses::total 244316858 # number of overall (read+write) accesses | 145system.cpu.icache.ReadReq_hits::cpu.inst 243525778 # number of ReadReq hits 146system.cpu.icache.ReadReq_hits::total 243525778 # number of ReadReq hits 147system.cpu.icache.demand_hits::cpu.inst 243525778 # number of demand (read+write) hits 148system.cpu.icache.demand_hits::total 243525778 # number of demand (read+write) hits 149system.cpu.icache.overall_hits::cpu.inst 243525778 # number of overall hits 150system.cpu.icache.overall_hits::total 243525778 # number of overall hits 151system.cpu.icache.ReadReq_misses::cpu.inst 791077 # number of ReadReq misses 152system.cpu.icache.ReadReq_misses::total 791077 # number of ReadReq misses 153system.cpu.icache.demand_misses::cpu.inst 791077 # number of demand (read+write) misses 154system.cpu.icache.demand_misses::total 791077 # number of demand (read+write) misses 155system.cpu.icache.overall_misses::cpu.inst 791077 # number of overall misses 156system.cpu.icache.overall_misses::total 791077 # number of overall misses 157system.cpu.icache.ReadReq_accesses::cpu.inst 244316855 # number of ReadReq accesses(hits+misses) 158system.cpu.icache.ReadReq_accesses::total 244316855 # number of ReadReq accesses(hits+misses) 159system.cpu.icache.demand_accesses::cpu.inst 244316855 # number of demand (read+write) accesses 160system.cpu.icache.demand_accesses::total 244316855 # number of demand (read+write) accesses 161system.cpu.icache.overall_accesses::cpu.inst 244316855 # number of overall (read+write) accesses 162system.cpu.icache.overall_accesses::total 244316855 # number of overall (read+write) accesses |
| 310system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 311system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 312system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 313system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 314system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 315system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 316system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 317system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 318system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 319system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 320system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 321system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 322system.cpu.icache.fast_writes 0 # number of fast writes performed 323system.cpu.icache.cache_copies 0 # number of cache copies performed 324system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 325system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements | 163system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 164system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 165system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 166system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 167system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 168system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 169system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 175system.cpu.icache.fast_writes 0 # number of fast writes performed 176system.cpu.icache.cache_copies 0 # number of cache copies performed 177system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 178system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements |
| 326system.cpu.itb_walker_cache.tags.tagsinuse 3.026300 # Cycle average of tags in use | 179system.cpu.itb_walker_cache.tags.tagsinuse 3.026303 # Cycle average of tags in use |
| 327system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 328system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 329system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. | 180system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 181system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 182system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. |
| 330system.cpu.itb_walker_cache.tags.warmup_cycle 5102118322000 # Cycle when the warmup percentage was hit. 331system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026300 # Average occupied blocks per requestor | 183system.cpu.itb_walker_cache.tags.warmup_cycle 5102116468000 # Cycle when the warmup percentage was hit. 184system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026303 # Average occupied blocks per requestor |
| 332system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy 333system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy 334system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 335system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 336system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 337system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 338system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits 339system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits --- 26 unchanged lines hidden (view full) --- 366system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 369system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 370system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 371system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 372system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 373system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements | 185system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy 186system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy 187system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 188system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 189system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 190system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 191system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits 192system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits --- 26 unchanged lines hidden (view full) --- 219system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 220system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 221system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 222system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 223system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 224system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 225system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 226system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements |
| 374system.cpu.dtb_walker_cache.tags.tagsinuse 5.014180 # Cycle average of tags in use | 227system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use |
| 375system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks. 376system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. 377system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks. | 228system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks. 229system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. 230system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks. |
| 378system.cpu.dtb_walker_cache.tags.warmup_cycle 5100463009500 # Cycle when the warmup percentage was hit. 379system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014180 # Average occupied blocks per requestor | 231system.cpu.dtb_walker_cache.tags.warmup_cycle 5100462243000 # Cycle when the warmup percentage was hit. 232system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor |
| 380system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 381system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 382system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits 383system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits 384system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits 385system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits 386system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits 387system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits --- 21 unchanged lines hidden (view full) --- 409system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 410system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 411system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 412system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 413system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 414system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks 415system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks 416system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 233system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 234system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 235system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits 236system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits 237system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits 238system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits 239system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits 240system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits --- 21 unchanged lines hidden (view full) --- 262system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 263system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 264system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 265system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 266system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 267system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks 268system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks 269system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 417system.cpu.dcache.tags.replacements 1622093 # number of replacements | 270system.cpu.dcache.tags.replacements 1622097 # number of replacements |
| 418system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use | 271system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use |
| 419system.cpu.dcache.tags.total_refs 20175183 # Total number of references to valid blocks. 420system.cpu.dcache.tags.sampled_refs 1622605 # Sample count of references to valid blocks. 421system.cpu.dcache.tags.avg_refs 12.433823 # Average number of references to valid blocks. | 272system.cpu.dcache.tags.total_refs 20175179 # Total number of references to valid blocks. 273system.cpu.dcache.tags.sampled_refs 1622609 # Sample count of references to valid blocks. 274system.cpu.dcache.tags.avg_refs 12.433790 # Average number of references to valid blocks. |
| 422system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 423system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 424system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 425system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy | 275system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 276system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 277system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 278system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy |
| 426system.cpu.dcache.ReadReq_hits::cpu.data 12077542 # number of ReadReq hits 427system.cpu.dcache.ReadReq_hits::total 12077542 # number of ReadReq hits 428system.cpu.dcache.WriteReq_hits::cpu.data 8095371 # number of WriteReq hits 429system.cpu.dcache.WriteReq_hits::total 8095371 # number of WriteReq hits 430system.cpu.dcache.demand_hits::cpu.data 20172913 # number of demand (read+write) hits 431system.cpu.dcache.demand_hits::total 20172913 # number of demand (read+write) hits 432system.cpu.dcache.overall_hits::cpu.data 20172913 # number of overall hits 433system.cpu.dcache.overall_hits::total 20172913 # number of overall hits 434system.cpu.dcache.ReadReq_misses::cpu.data 1308419 # number of ReadReq misses 435system.cpu.dcache.ReadReq_misses::total 1308419 # number of ReadReq misses 436system.cpu.dcache.WriteReq_misses::cpu.data 316472 # number of WriteReq misses 437system.cpu.dcache.WriteReq_misses::total 316472 # number of WriteReq misses 438system.cpu.dcache.demand_misses::cpu.data 1624891 # number of demand (read+write) misses 439system.cpu.dcache.demand_misses::total 1624891 # number of demand (read+write) misses 440system.cpu.dcache.overall_misses::cpu.data 1624891 # number of overall misses 441system.cpu.dcache.overall_misses::total 1624891 # number of overall misses | 279system.cpu.dcache.ReadReq_hits::cpu.data 12077531 # number of ReadReq hits 280system.cpu.dcache.ReadReq_hits::total 12077531 # number of ReadReq hits 281system.cpu.dcache.WriteReq_hits::cpu.data 8095378 # number of WriteReq hits 282system.cpu.dcache.WriteReq_hits::total 8095378 # number of WriteReq hits 283system.cpu.dcache.demand_hits::cpu.data 20172909 # number of demand (read+write) hits 284system.cpu.dcache.demand_hits::total 20172909 # number of demand (read+write) hits 285system.cpu.dcache.overall_hits::cpu.data 20172909 # number of overall hits 286system.cpu.dcache.overall_hits::total 20172909 # number of overall hits 287system.cpu.dcache.ReadReq_misses::cpu.data 1308430 # number of ReadReq misses 288system.cpu.dcache.ReadReq_misses::total 1308430 # number of ReadReq misses 289system.cpu.dcache.WriteReq_misses::cpu.data 316465 # number of WriteReq misses 290system.cpu.dcache.WriteReq_misses::total 316465 # number of WriteReq misses 291system.cpu.dcache.demand_misses::cpu.data 1624895 # number of demand (read+write) misses 292system.cpu.dcache.demand_misses::total 1624895 # number of demand (read+write) misses 293system.cpu.dcache.overall_misses::cpu.data 1624895 # number of overall misses 294system.cpu.dcache.overall_misses::total 1624895 # number of overall misses |
| 442system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses) 443system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses) 444system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses) 445system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses) 446system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses 447system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses 448system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses 449system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses 450system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses 451system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses | 295system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses) 296system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses) 297system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses) 298system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses) 299system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses 300system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses 301system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses 302system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses 303system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses 304system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses |
| 452system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses 453system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses | 305system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses 306system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses |
| 454system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses 455system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses 456system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses 457system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses 458system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 459system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 460system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 461system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 462system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 463system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 464system.cpu.dcache.fast_writes 0 # number of fast writes performed 465system.cpu.dcache.cache_copies 0 # number of cache copies performed | 307system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses 308system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses 309system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses 310system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses 311system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 312system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 313system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 314system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 315system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 316system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 317system.cpu.dcache.fast_writes 0 # number of fast writes performed 318system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 466system.cpu.dcache.writebacks::writebacks 1535822 # number of writebacks 467system.cpu.dcache.writebacks::total 1535822 # number of writebacks | 319system.cpu.dcache.writebacks::writebacks 1535825 # number of writebacks 320system.cpu.dcache.writebacks::total 1535825 # number of writebacks |
| 468system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 321system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 469system.cpu.toL2Bus.throughput 54624920 # Throughput (bytes/s) 470system.cpu.toL2Bus.data_through_bus 279224019 # Total data (bytes) | 322system.cpu.toL2Bus.throughput 54625221 # Throughput (bytes/s) 323system.cpu.toL2Bus.data_through_bus 279225555 # Total data (bytes) |
| 471system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) 472system.cpu.l2cache.tags.replacements 105999 # number of replacements | 324system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) 325system.cpu.l2cache.tags.replacements 105999 # number of replacements |
| 473system.cpu.l2cache.tags.tagsinuse 64822.033663 # Cycle average of tags in use 474system.cpu.l2cache.tags.total_refs 3456588 # Total number of references to valid blocks. | 326system.cpu.l2cache.tags.tagsinuse 64822.034013 # Cycle average of tags in use 327system.cpu.l2cache.tags.total_refs 3456623 # Total number of references to valid blocks. |
| 475system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks. | 328system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks. |
| 476system.cpu.l2cache.tags.avg_refs 20.317692 # Average number of references to valid blocks. | 329system.cpu.l2cache.tags.avg_refs 20.317898 # Average number of references to valid blocks. |
| 477system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 330system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 478system.cpu.l2cache.tags.occ_blocks::writebacks 51908.841728 # Average occupied blocks per requestor | 331system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839094 # Average occupied blocks per requestor |
| 479system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor 480system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor | 332system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor 333system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor |
| 481system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.538603 # Average occupied blocks per requestor 482system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.518599 # Average occupied blocks per requestor | 334system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.539598 # Average occupied blocks per requestor 335system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.520587 # Average occupied blocks per requestor |
| 483system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy 484system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 485system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 486system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 487system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy 488system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy 489system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits 490system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits | 336system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy 337system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 338system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 339system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 340system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy 341system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy 342system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits 343system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits |
| 491system.cpu.l2cache.ReadReq_hits::cpu.inst 777722 # number of ReadReq hits 492system.cpu.l2cache.ReadReq_hits::cpu.data 1275543 # number of ReadReq hits 493system.cpu.l2cache.ReadReq_hits::total 2062571 # number of ReadReq hits 494system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits 495system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits | 344system.cpu.l2cache.ReadReq_hits::cpu.inst 777739 # number of ReadReq hits 345system.cpu.l2cache.ReadReq_hits::cpu.data 1275554 # number of ReadReq hits 346system.cpu.l2cache.ReadReq_hits::total 2062599 # number of ReadReq hits 347system.cpu.l2cache.Writeback_hits::writebacks 1538784 # number of Writeback hits 348system.cpu.l2cache.Writeback_hits::total 1538784 # number of Writeback hits |
| 496system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 497system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits | 349system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 350system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits |
| 498system.cpu.l2cache.ReadExReq_hits::cpu.data 179739 # number of ReadExReq hits 499system.cpu.l2cache.ReadExReq_hits::total 179739 # number of ReadExReq hits | 351system.cpu.l2cache.ReadExReq_hits::cpu.data 179732 # number of ReadExReq hits 352system.cpu.l2cache.ReadExReq_hits::total 179732 # number of ReadExReq hits |
| 500system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits 501system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits | 353system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits 354system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits |
| 502system.cpu.l2cache.demand_hits::cpu.inst 777722 # number of demand (read+write) hits 503system.cpu.l2cache.demand_hits::cpu.data 1455282 # number of demand (read+write) hits 504system.cpu.l2cache.demand_hits::total 2242310 # number of demand (read+write) hits | 355system.cpu.l2cache.demand_hits::cpu.inst 777739 # number of demand (read+write) hits 356system.cpu.l2cache.demand_hits::cpu.data 1455286 # number of demand (read+write) hits 357system.cpu.l2cache.demand_hits::total 2242331 # number of demand (read+write) hits |
| 505system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits 506system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits | 358system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits 359system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits |
| 507system.cpu.l2cache.overall_hits::cpu.inst 777722 # number of overall hits 508system.cpu.l2cache.overall_hits::cpu.data 1455282 # number of overall hits 509system.cpu.l2cache.overall_hits::total 2242310 # number of overall hits | 360system.cpu.l2cache.overall_hits::cpu.inst 777739 # number of overall hits 361system.cpu.l2cache.overall_hits::cpu.data 1455286 # number of overall hits 362system.cpu.l2cache.overall_hits::total 2242331 # number of overall hits |
| 510system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 511system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 512system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 513system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 514system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses 515system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses 516system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses 517system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses --- 5 unchanged lines hidden (view full) --- 523system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses 524system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 525system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 526system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 527system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses 528system.cpu.l2cache.overall_misses::total 180035 # number of overall misses 529system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses) 530system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) | 363system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 364system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 365system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 366system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 367system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses 368system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses 369system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses 370system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses --- 5 unchanged lines hidden (view full) --- 376system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses 377system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 378system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 379system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 380system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses 381system.cpu.l2cache.overall_misses::total 180035 # number of overall misses 382system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses) 383system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) |
| 531system.cpu.l2cache.ReadReq_accesses::cpu.inst 791047 # number of ReadReq accesses(hits+misses) 532system.cpu.l2cache.ReadReq_accesses::cpu.data 1307789 # number of ReadReq accesses(hits+misses) 533system.cpu.l2cache.ReadReq_accesses::total 2108148 # number of ReadReq accesses(hits+misses) 534system.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses) 535system.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses) | 384system.cpu.l2cache.ReadReq_accesses::cpu.inst 791064 # number of ReadReq accesses(hits+misses) 385system.cpu.l2cache.ReadReq_accesses::cpu.data 1307800 # number of ReadReq accesses(hits+misses) 386system.cpu.l2cache.ReadReq_accesses::total 2108176 # number of ReadReq accesses(hits+misses) 387system.cpu.l2cache.Writeback_accesses::writebacks 1538784 # number of Writeback accesses(hits+misses) 388system.cpu.l2cache.Writeback_accesses::total 1538784 # number of Writeback accesses(hits+misses) |
| 536system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) 537system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) | 389system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) 390system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) |
| 538system.cpu.l2cache.ReadExReq_accesses::cpu.data 314197 # number of ReadExReq accesses(hits+misses) 539system.cpu.l2cache.ReadExReq_accesses::total 314197 # number of ReadExReq accesses(hits+misses) | 391system.cpu.l2cache.ReadExReq_accesses::cpu.data 314190 # number of ReadExReq accesses(hits+misses) 392system.cpu.l2cache.ReadExReq_accesses::total 314190 # number of ReadExReq accesses(hits+misses) |
| 540system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses 541system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses | 393system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses 394system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses |
| 542system.cpu.l2cache.demand_accesses::cpu.inst 791047 # number of demand (read+write) accesses 543system.cpu.l2cache.demand_accesses::cpu.data 1621986 # number of demand (read+write) accesses 544system.cpu.l2cache.demand_accesses::total 2422345 # number of demand (read+write) accesses | 395system.cpu.l2cache.demand_accesses::cpu.inst 791064 # number of demand (read+write) accesses 396system.cpu.l2cache.demand_accesses::cpu.data 1621990 # number of demand (read+write) accesses 397system.cpu.l2cache.demand_accesses::total 2422366 # number of demand (read+write) accesses |
| 545system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses 546system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses | 398system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses 399system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses |
| 547system.cpu.l2cache.overall_accesses::cpu.inst 791047 # number of overall (read+write) accesses 548system.cpu.l2cache.overall_accesses::cpu.data 1621986 # number of overall (read+write) accesses 549system.cpu.l2cache.overall_accesses::total 2422345 # number of overall (read+write) accesses | 400system.cpu.l2cache.overall_accesses::cpu.inst 791064 # number of overall (read+write) accesses 401system.cpu.l2cache.overall_accesses::cpu.data 1621990 # number of overall (read+write) accesses 402system.cpu.l2cache.overall_accesses::total 2422366 # number of overall (read+write) accesses |
| 550system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses 551system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses | 403system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses 404system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses |
| 552system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses | 405system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses |
| 553system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses 554system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses 555system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses 556system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses | 406system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses 407system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses 408system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses 409system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses |
| 557system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427942 # miss rate for ReadExReq accesses 558system.cpu.l2cache.ReadExReq_miss_rate::total 0.427942 # miss rate for ReadExReq accesses | 410system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427951 # miss rate for ReadExReq accesses 411system.cpu.l2cache.ReadExReq_miss_rate::total 0.427951 # miss rate for ReadExReq accesses |
| 559system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses 560system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses | 412system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses 413system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses |
| 561system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses 562system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses 563system.cpu.l2cache.demand_miss_rate::total 0.074323 # miss rate for demand accesses | 414system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses 415system.cpu.l2cache.demand_miss_rate::cpu.data 0.102777 # miss rate for demand accesses 416system.cpu.l2cache.demand_miss_rate::total 0.074322 # miss rate for demand accesses |
| 564system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses 565system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses | 417system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses 418system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses |
| 566system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses 567system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses 568system.cpu.l2cache.overall_miss_rate::total 0.074323 # miss rate for overall accesses | 419system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses 420system.cpu.l2cache.overall_miss_rate::cpu.data 0.102777 # miss rate for overall accesses 421system.cpu.l2cache.overall_miss_rate::total 0.074322 # miss rate for overall accesses |
| 569system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 570system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 571system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 572system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 573system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 574system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 575system.cpu.l2cache.fast_writes 0 # number of fast writes performed 576system.cpu.l2cache.cache_copies 0 # number of cache copies performed 577system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks 578system.cpu.l2cache.writebacks::total 98156 # number of writebacks 579system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 580 581---------- End Simulation Statistics ---------- | 422system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 423system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 424system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 425system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 426system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 427system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 428system.cpu.l2cache.fast_writes 0 # number of fast writes performed 429system.cpu.l2cache.cache_copies 0 # number of cache copies performed 430system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks 431system.cpu.l2cache.writebacks::total 98156 # number of writebacks 432system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 433 434---------- End Simulation Statistics ---------- |