Cross Reference: /gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 5.112102 # Number of seconds simulated
4sim_ticks 5112102211000 # Number of ticks simulated
5final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 5.112126 # Number of seconds simulated
4sim_ticks 5112126311000 # Number of ticks simulated
5final_tick 5112126311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 856407 # Simulator instruction rate (inst/s)
8host_op_rate 1753461 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 21900233108 # Simulator tick rate (ticks/s)
10host_mem_usage 584104 # Number of bytes of host memory used
11host_seconds 233.43 # Real time elapsed on the host
12sim_insts 199908396 # Number of instructions simulated
13sim_ops 409304707 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory

7host_inst_rate 1020096 # Simulator instruction rate (inst/s)
8host_op_rate 2088583 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 26083435490 # Simulator tick rate (ticks/s)
10host_mem_usage 587152 # Number of bytes of host memory used
11host_seconds 195.99 # Real time elapsed on the host
12sim_insts 199929810 # Number of instructions simulated
13sim_ops 409343980 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory

16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu.data 10605120 # Number of bytes read from this memory
19system.physmem.bytes_read::total 13879360 # Number of bytes read from this memory

18system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory
19system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory

20system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory

22system.physmem.bytes_written::writebacks 9264512 # Number of bytes written to this memory
23system.physmem.bytes_written::total 9264512 # Number of bytes written to this memory
24system.physmem.num_reads::pc.south_bridge.ide 37829 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory

22system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory
23system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory
24system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory

26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
27system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory

28system.physmem.num_reads::cpu.data 165705 # Number of read requests responded to by this memory
29system.physmem.num_reads::total 216865 # Number of read requests responded to by this memory
30system.physmem.num_writes::writebacks 144758 # Number of write requests responded to by this memory
31system.physmem.num_writes::total 144758 # Number of write requests responded to by this memory
32system.physmem.bw_read::pc.south_bridge.ide 473593 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)

28system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory
29system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory
30system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory
31system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory
32system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)

34system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s)

36system.physmem.bw_read::cpu.data 2074513 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::total 2715000 # Total read bandwidth from this memory (bytes/s)

36system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::total 2715826 # Total read bandwidth from this memory (bytes/s)

38system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s)
39system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s)

40system.physmem.bw_write::writebacks 1812270 # Write bandwidth from this memory (bytes/s)
41system.physmem.bw_write::total 1812270 # Write bandwidth from this memory (bytes/s)
42system.physmem.bw_total::writebacks 1812270 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::pc.south_bridge.ide 473593 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)

40system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s)
41system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s)
42system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)

45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
46system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s)

47system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s)

47system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s)

49system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller
50system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
51system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
52system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
53system.physmem.bytesRead 0 # Total number of bytes read from memory
54system.physmem.bytesWritten 0 # Total number of bytes written to memory
55system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize()
56system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()

--- 131 unchanged lines hidden (view full) ---

188system.physmem.busUtil 0.00 # Data bus utilization in percentage
189system.physmem.avgRdQLen 0.00 # Average read queue length over time
190system.physmem.avgWrQLen 0.00 # Average write queue length over time
191system.physmem.readRowHits 0 # Number of row buffer hits during reads
192system.physmem.writeRowHits 0 # Number of row buffer hits during writes
193system.physmem.readRowHitRate nan # Row buffer hit rate for reads
194system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
195system.physmem.avgGap nan # Average gap between requests

196system.membus.throughput 9632725 # Throughput (bytes/s)
197system.membus.data_through_bus 49243475 # Total data (bytes)

196system.membus.throughput 9634332 # Throughput (bytes/s)
197system.membus.data_through_bus 49251923 # Total data (bytes)

198system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
199system.iocache.tags.replacements 47569 # number of replacements

200system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use

200system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use

201system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
202system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
203system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.

204system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit.
205system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor

204system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit.
205system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor

206system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
207system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
208system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
209system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
210system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
211system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
212system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
213system.iocache.demand_misses::total 47624 # number of demand (read+write) misses

--- 33 unchanged lines hidden (view full) ---

247system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
248system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
249system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
250system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
251system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
252system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
253system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
254system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.

255system.iobus.throughput 2555194 # Throughput (bytes/s)
256system.iobus.data_through_bus 13062414 # Total data (bytes)
257system.cpu.numCycles 10224204444 # number of cpu cycles simulated

255system.iobus.throughput 2555207 # Throughput (bytes/s)
256system.iobus.data_through_bus 13062542 # Total data (bytes)
257system.cpu.numCycles 10224252644 # number of cpu cycles simulated

258system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
259system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

260system.cpu.committedInsts 199908396 # Number of instructions committed
261system.cpu.committedOps 409304707 # Number of ops (including micro ops) committed
262system.cpu.num_int_alu_accesses 374467605 # Number of integer alu accesses

260system.cpu.committedInsts 199929810 # Number of instructions committed
261system.cpu.committedOps 409343980 # Number of ops (including micro ops) committed
262system.cpu.num_int_alu_accesses 374506599 # Number of integer alu accesses

263system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses

264system.cpu.num_func_calls 2307395 # number of times a function call or return occured
265system.cpu.num_conditional_control_insts 39972475 # number of instructions that are conditional controls
266system.cpu.num_int_insts 374467605 # number of integer instructions

264system.cpu.num_func_calls 2307717 # number of times a function call or return occured
265system.cpu.num_conditional_control_insts 39976354 # number of instructions that are conditional controls
266system.cpu.num_int_insts 374506599 # number of integer instructions

267system.cpu.num_fp_insts 0 # number of float instructions

268system.cpu.num_int_register_reads 915905592 # number of times the integer registers were read
269system.cpu.num_int_register_writes 480549431 # number of times the integer registers were written

268system.cpu.num_int_register_reads 916001165 # number of times the integer registers were read
269system.cpu.num_int_register_writes 480603129 # number of times the integer registers were written

270system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
271system.cpu.num_fp_register_writes 0 # number of times the floating registers were written

272system.cpu.num_mem_refs 35655576 # number of memory refs
273system.cpu.num_load_insts 27235236 # Number of load instructions
274system.cpu.num_store_insts 8420340 # Number of store instructions
275system.cpu.num_idle_cycles 9770516372.735863 # Number of idle cycles
276system.cpu.num_busy_cycles 453688071.264138 # Number of busy cycles
277system.cpu.not_idle_fraction 0.044374 # Percentage of non-idle cycles
278system.cpu.idle_fraction 0.955626 # Percentage of idle cycles

272system.cpu.num_mem_refs 35660913 # number of memory refs
273system.cpu.num_load_insts 27238816 # Number of load instructions
274system.cpu.num_store_insts 8422097 # Number of store instructions
275system.cpu.num_idle_cycles 9770516880.735765 # Number of idle cycles
276system.cpu.num_busy_cycles 453735763.264236 # Number of busy cycles
277system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
278system.cpu.idle_fraction 0.955622 # Percentage of idle cycles

279system.cpu.kern.inst.arm 0 # number of arm instructions executed
280system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed

281system.cpu.icache.tags.replacements 790522 # number of replacements
282system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use
283system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks.
284system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks.
285system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks.
286system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
287system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
288system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
289system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy
290system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits
291system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits
292system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits
293system.cpu.icache.demand_hits::total 243495984 # number of demand (read+write) hits
294system.cpu.icache.overall_hits::cpu.inst 243495984 # number of overall hits
295system.cpu.icache.overall_hits::total 243495984 # number of overall hits
296system.cpu.icache.ReadReq_misses::cpu.inst 791041 # number of ReadReq misses
297system.cpu.icache.ReadReq_misses::total 791041 # number of ReadReq misses
298system.cpu.icache.demand_misses::cpu.inst 791041 # number of demand (read+write) misses
299system.cpu.icache.demand_misses::total 791041 # number of demand (read+write) misses
300system.cpu.icache.overall_misses::cpu.inst 791041 # number of overall misses
301system.cpu.icache.overall_misses::total 791041 # number of overall misses
302system.cpu.icache.ReadReq_accesses::cpu.inst 244287025 # number of ReadReq accesses(hits+misses)
303system.cpu.icache.ReadReq_accesses::total 244287025 # number of ReadReq accesses(hits+misses)
304system.cpu.icache.demand_accesses::cpu.inst 244287025 # number of demand (read+write) accesses
305system.cpu.icache.demand_accesses::total 244287025 # number of demand (read+write) accesses
306system.cpu.icache.overall_accesses::cpu.inst 244287025 # number of overall (read+write) accesses
307system.cpu.icache.overall_accesses::total 244287025 # number of overall (read+write) accesses

281system.cpu.icache.tags.replacements 790541 # number of replacements
282system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
283system.cpu.icache.tags.total_refs 243525798 # Total number of references to valid blocks.
284system.cpu.icache.tags.sampled_refs 791053 # Sample count of references to valid blocks.
285system.cpu.icache.tags.avg_refs 307.850167 # Average number of references to valid blocks.
286system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
287system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
288system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
289system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy
290system.cpu.icache.ReadReq_hits::cpu.inst 243525798 # number of ReadReq hits
291system.cpu.icache.ReadReq_hits::total 243525798 # number of ReadReq hits
292system.cpu.icache.demand_hits::cpu.inst 243525798 # number of demand (read+write) hits
293system.cpu.icache.demand_hits::total 243525798 # number of demand (read+write) hits
294system.cpu.icache.overall_hits::cpu.inst 243525798 # number of overall hits
295system.cpu.icache.overall_hits::total 243525798 # number of overall hits
296system.cpu.icache.ReadReq_misses::cpu.inst 791060 # number of ReadReq misses
297system.cpu.icache.ReadReq_misses::total 791060 # number of ReadReq misses
298system.cpu.icache.demand_misses::cpu.inst 791060 # number of demand (read+write) misses
299system.cpu.icache.demand_misses::total 791060 # number of demand (read+write) misses
300system.cpu.icache.overall_misses::cpu.inst 791060 # number of overall misses
301system.cpu.icache.overall_misses::total 791060 # number of overall misses
302system.cpu.icache.ReadReq_accesses::cpu.inst 244316858 # number of ReadReq accesses(hits+misses)
303system.cpu.icache.ReadReq_accesses::total 244316858 # number of ReadReq accesses(hits+misses)
304system.cpu.icache.demand_accesses::cpu.inst 244316858 # number of demand (read+write) accesses
305system.cpu.icache.demand_accesses::total 244316858 # number of demand (read+write) accesses
306system.cpu.icache.overall_accesses::cpu.inst 244316858 # number of overall (read+write) accesses
307system.cpu.icache.overall_accesses::total 244316858 # number of overall (read+write) accesses

308system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
309system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
310system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
311system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses
312system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses
313system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses
314system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
315system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
316system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
317system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
318system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
319system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
320system.cpu.icache.fast_writes 0 # number of fast writes performed
321system.cpu.icache.cache_copies 0 # number of cache copies performed
322system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
323system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements

324system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use

324system.cpu.itb_walker_cache.tags.tagsinuse 3.026300 # Cycle average of tags in use

325system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks.
326system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks.
327system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks.

328system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit.
329system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor
330system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy
331system.cpu.itb_walker_cache.tags.occ_percent::total 0.189143 # Average percentage of cache occupancy

328system.cpu.itb_walker_cache.tags.warmup_cycle 5102118322000 # Cycle when the warmup percentage was hit.
329system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026300 # Average occupied blocks per requestor
330system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy
331system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy

332system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits
333system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits
334system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
335system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
336system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits
337system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits
338system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits
339system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits

--- 24 unchanged lines hidden (view full) ---

364system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
365system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
366system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
367system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
368system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks
369system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
370system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
371system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements

372system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use
373system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks.

372system.cpu.dtb_walker_cache.tags.tagsinuse 5.014180 # Cycle average of tags in use
373system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks.

374system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks.

375system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks.
376system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit.
377system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor

375system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks.
376system.cpu.dtb_walker_cache.tags.warmup_cycle 5100463009500 # Cycle when the warmup percentage was hit.
377system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014180 # Average occupied blocks per requestor

378system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy
379system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy

380system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12956 # number of ReadReq hits
381system.cpu.dtb_walker_cache.ReadReq_hits::total 12956 # number of ReadReq hits
382system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12956 # number of demand (read+write) hits
383system.cpu.dtb_walker_cache.demand_hits::total 12956 # number of demand (read+write) hits
384system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12956 # number of overall hits
385system.cpu.dtb_walker_cache.overall_hits::total 12956 # number of overall hits
386system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8822 # number of ReadReq misses
387system.cpu.dtb_walker_cache.ReadReq_misses::total 8822 # number of ReadReq misses
388system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8822 # number of demand (read+write) misses
389system.cpu.dtb_walker_cache.demand_misses::total 8822 # number of demand (read+write) misses
390system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8822 # number of overall misses
391system.cpu.dtb_walker_cache.overall_misses::total 8822 # number of overall misses
392system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21778 # number of ReadReq accesses(hits+misses)
393system.cpu.dtb_walker_cache.ReadReq_accesses::total 21778 # number of ReadReq accesses(hits+misses)
394system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21778 # number of demand (read+write) accesses
395system.cpu.dtb_walker_cache.demand_accesses::total 21778 # number of demand (read+write) accesses
396system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21778 # number of overall (read+write) accesses
397system.cpu.dtb_walker_cache.overall_accesses::total 21778 # number of overall (read+write) accesses
398system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405088 # miss rate for ReadReq accesses
399system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405088 # miss rate for ReadReq accesses
400system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405088 # miss rate for demand accesses
401system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405088 # miss rate for demand accesses
402system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405088 # miss rate for overall accesses
403system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405088 # miss rate for overall accesses

380system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits
381system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits
382system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits
383system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits
384system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits
385system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits
386system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses
387system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses
388system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses
389system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses
390system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses
391system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses
392system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses)
393system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses)
394system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses
395system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses
396system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses
397system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses
398system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses
399system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses
400system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses
401system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses
402system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses
403system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses

404system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
405system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
406system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
407system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
408system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
409system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
410system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
411system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed

412system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks
413system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks

412system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks
413system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks

414system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate

415system.cpu.dcache.tags.replacements 1622027 # number of replacements

415system.cpu.dcache.tags.replacements 1622093 # number of replacements

416system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use

417system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks.
418system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks.
419system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks.

417system.cpu.dcache.tags.total_refs 20175183 # Total number of references to valid blocks.
418system.cpu.dcache.tags.sampled_refs 1622605 # Sample count of references to valid blocks.
419system.cpu.dcache.tags.avg_refs 12.433823 # Average number of references to valid blocks.

420system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
421system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor
422system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
423system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy

424system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits
425system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits
426system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits
427system.cpu.dcache.WriteReq_hits::total 8093747 # number of WriteReq hits
428system.cpu.dcache.demand_hits::cpu.data 20167772 # number of demand (read+write) hits
429system.cpu.dcache.demand_hits::total 20167772 # number of demand (read+write) hits
430system.cpu.dcache.overall_hits::cpu.data 20167772 # number of overall hits
431system.cpu.dcache.overall_hits::total 20167772 # number of overall hits
432system.cpu.dcache.ReadReq_misses::cpu.data 1308420 # number of ReadReq misses
433system.cpu.dcache.ReadReq_misses::total 1308420 # number of ReadReq misses
434system.cpu.dcache.WriteReq_misses::cpu.data 316403 # number of WriteReq misses
435system.cpu.dcache.WriteReq_misses::total 316403 # number of WriteReq misses
436system.cpu.dcache.demand_misses::cpu.data 1624823 # number of demand (read+write) misses
437system.cpu.dcache.demand_misses::total 1624823 # number of demand (read+write) misses
438system.cpu.dcache.overall_misses::cpu.data 1624823 # number of overall misses
439system.cpu.dcache.overall_misses::total 1624823 # number of overall misses
440system.cpu.dcache.ReadReq_accesses::cpu.data 13382445 # number of ReadReq accesses(hits+misses)
441system.cpu.dcache.ReadReq_accesses::total 13382445 # number of ReadReq accesses(hits+misses)
442system.cpu.dcache.WriteReq_accesses::cpu.data 8410150 # number of WriteReq accesses(hits+misses)
443system.cpu.dcache.WriteReq_accesses::total 8410150 # number of WriteReq accesses(hits+misses)
444system.cpu.dcache.demand_accesses::cpu.data 21792595 # number of demand (read+write) accesses
445system.cpu.dcache.demand_accesses::total 21792595 # number of demand (read+write) accesses
446system.cpu.dcache.overall_accesses::cpu.data 21792595 # number of overall (read+write) accesses
447system.cpu.dcache.overall_accesses::total 21792595 # number of overall (read+write) accesses
448system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097771 # miss rate for ReadReq accesses
449system.cpu.dcache.ReadReq_miss_rate::total 0.097771 # miss rate for ReadReq accesses

424system.cpu.dcache.ReadReq_hits::cpu.data 12077542 # number of ReadReq hits
425system.cpu.dcache.ReadReq_hits::total 12077542 # number of ReadReq hits
426system.cpu.dcache.WriteReq_hits::cpu.data 8095371 # number of WriteReq hits
427system.cpu.dcache.WriteReq_hits::total 8095371 # number of WriteReq hits
428system.cpu.dcache.demand_hits::cpu.data 20172913 # number of demand (read+write) hits
429system.cpu.dcache.demand_hits::total 20172913 # number of demand (read+write) hits
430system.cpu.dcache.overall_hits::cpu.data 20172913 # number of overall hits
431system.cpu.dcache.overall_hits::total 20172913 # number of overall hits
432system.cpu.dcache.ReadReq_misses::cpu.data 1308419 # number of ReadReq misses
433system.cpu.dcache.ReadReq_misses::total 1308419 # number of ReadReq misses
434system.cpu.dcache.WriteReq_misses::cpu.data 316472 # number of WriteReq misses
435system.cpu.dcache.WriteReq_misses::total 316472 # number of WriteReq misses
436system.cpu.dcache.demand_misses::cpu.data 1624891 # number of demand (read+write) misses
437system.cpu.dcache.demand_misses::total 1624891 # number of demand (read+write) misses
438system.cpu.dcache.overall_misses::cpu.data 1624891 # number of overall misses
439system.cpu.dcache.overall_misses::total 1624891 # number of overall misses
440system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses)
441system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses)
442system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses)
443system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses)
444system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses
445system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses
446system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses
447system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses
448system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses
449system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses

450system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses
451system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses

452system.cpu.dcache.demand_miss_rate::cpu.data 0.074558 # miss rate for demand accesses
453system.cpu.dcache.demand_miss_rate::total 0.074558 # miss rate for demand accesses
454system.cpu.dcache.overall_miss_rate::cpu.data 0.074558 # miss rate for overall accesses
455system.cpu.dcache.overall_miss_rate::total 0.074558 # miss rate for overall accesses

452system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses
453system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses
454system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses
455system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses

456system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
457system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
458system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
459system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
460system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
461system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
462system.cpu.dcache.fast_writes 0 # number of fast writes performed
463system.cpu.dcache.cache_copies 0 # number of cache copies performed

464system.cpu.dcache.writebacks::writebacks 1535756 # number of writebacks
465system.cpu.dcache.writebacks::total 1535756 # number of writebacks

464system.cpu.dcache.writebacks::writebacks 1535822 # number of writebacks
465system.cpu.dcache.writebacks::total 1535822 # number of writebacks

466system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

467system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s)
468system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes)

467system.cpu.toL2Bus.throughput 54624920 # Throughput (bytes/s)
468system.cpu.toL2Bus.data_through_bus 279224019 # Total data (bytes)

469system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes)

470system.cpu.l2cache.tags.replacements 105931 # number of replacements
471system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use
472system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks.
473system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks.
474system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks.

470system.cpu.l2cache.tags.replacements 105999 # number of replacements
471system.cpu.l2cache.tags.tagsinuse 64822.033663 # Cycle average of tags in use
472system.cpu.l2cache.tags.total_refs 3456588 # Total number of references to valid blocks.
473system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks.
474system.cpu.l2cache.tags.avg_refs 20.317692 # Average number of references to valid blocks.

475system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

476system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor
477system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor
478system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor
479system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor
480system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor
481system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy

476system.cpu.l2cache.tags.occ_blocks::writebacks 51908.841728 # Average occupied blocks per requestor
477system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
478system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor
479system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.538603 # Average occupied blocks per requestor
480system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.518599 # Average occupied blocks per requestor
481system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy

482system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
483system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
484system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy

485system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy
486system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy
487system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits

485system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy
486system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy
487system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits

488system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits

489system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits
490system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits
491system.cpu.l2cache.ReadReq_hits::total 2062551 # number of ReadReq hits
492system.cpu.l2cache.Writeback_hits::writebacks 1538695 # number of Writeback hits
493system.cpu.l2cache.Writeback_hits::total 1538695 # number of Writeback hits

489system.cpu.l2cache.ReadReq_hits::cpu.inst 777722 # number of ReadReq hits
490system.cpu.l2cache.ReadReq_hits::cpu.data 1275543 # number of ReadReq hits
491system.cpu.l2cache.ReadReq_hits::total 2062571 # number of ReadReq hits
492system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits
493system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits

494system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
495system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits

496system.cpu.l2cache.ReadExReq_hits::cpu.data 179738 # number of ReadExReq hits
497system.cpu.l2cache.ReadExReq_hits::total 179738 # number of ReadExReq hits
498system.cpu.l2cache.demand_hits::cpu.dtb.walker 6502 # number of demand (read+write) hits

496system.cpu.l2cache.ReadExReq_hits::cpu.data 179739 # number of ReadExReq hits
497system.cpu.l2cache.ReadExReq_hits::total 179739 # number of ReadExReq hits
498system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits

499system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits

500system.cpu.l2cache.demand_hits::cpu.inst 777703 # number of demand (read+write) hits

500system.cpu.l2cache.demand_hits::cpu.inst 777722 # number of demand (read+write) hits

501system.cpu.l2cache.demand_hits::cpu.data 1455282 # number of demand (read+write) hits

502system.cpu.l2cache.demand_hits::total 2242289 # number of demand (read+write) hits
503system.cpu.l2cache.overall_hits::cpu.dtb.walker 6502 # number of overall hits

502system.cpu.l2cache.demand_hits::total 2242310 # number of demand (read+write) hits
503system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits

504system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits

505system.cpu.l2cache.overall_hits::cpu.inst 777703 # number of overall hits

505system.cpu.l2cache.overall_hits::cpu.inst 777722 # number of overall hits

506system.cpu.l2cache.overall_hits::cpu.data 1455282 # number of overall hits

507system.cpu.l2cache.overall_hits::total 2242289 # number of overall hits
508system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses

507system.cpu.l2cache.overall_hits::total 2242310 # number of overall hits
508system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses

509system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
510system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses
511system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses

512system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses
513system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses
514system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses
515system.cpu.l2cache.ReadExReq_misses::cpu.data 134392 # number of ReadExReq misses
516system.cpu.l2cache.ReadExReq_misses::total 134392 # number of ReadExReq misses
517system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses

512system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses
513system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses
514system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses
515system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses
516system.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses
517system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses

518system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
519system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses

520system.cpu.l2cache.demand_misses::cpu.data 166638 # number of demand (read+write) misses
521system.cpu.l2cache.demand_misses::total 179970 # number of demand (read+write) misses
522system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses

520system.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses
521system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses
522system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses

523system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
524system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses

525system.cpu.l2cache.overall_misses::cpu.data 166638 # number of overall misses
526system.cpu.l2cache.overall_misses::total 179970 # number of overall misses
527system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6504 # number of ReadReq accesses(hits+misses)

525system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses
526system.cpu.l2cache.overall_misses::total 180035 # number of overall misses
527system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses)

528system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)

529system.cpu.l2cache.ReadReq_accesses::cpu.inst 791028 # number of ReadReq accesses(hits+misses)
530system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses)
531system.cpu.l2cache.ReadReq_accesses::total 2108129 # number of ReadReq accesses(hits+misses)
532system.cpu.l2cache.Writeback_accesses::writebacks 1538695 # number of Writeback accesses(hits+misses)
533system.cpu.l2cache.Writeback_accesses::total 1538695 # number of Writeback accesses(hits+misses)
534system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
535system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
536system.cpu.l2cache.ReadExReq_accesses::cpu.data 314130 # number of ReadExReq accesses(hits+misses)
537system.cpu.l2cache.ReadExReq_accesses::total 314130 # number of ReadExReq accesses(hits+misses)
538system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6504 # number of demand (read+write) accesses

529system.cpu.l2cache.ReadReq_accesses::cpu.inst 791047 # number of ReadReq accesses(hits+misses)
530system.cpu.l2cache.ReadReq_accesses::cpu.data 1307789 # number of ReadReq accesses(hits+misses)
531system.cpu.l2cache.ReadReq_accesses::total 2108148 # number of ReadReq accesses(hits+misses)
532system.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses)
533system.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses)
534system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses)
535system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
536system.cpu.l2cache.ReadExReq_accesses::cpu.data 314197 # number of ReadExReq accesses(hits+misses)
537system.cpu.l2cache.ReadExReq_accesses::total 314197 # number of ReadExReq accesses(hits+misses)
538system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses

539system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses

540system.cpu.l2cache.demand_accesses::cpu.inst 791028 # number of demand (read+write) accesses
541system.cpu.l2cache.demand_accesses::cpu.data 1621920 # number of demand (read+write) accesses
542system.cpu.l2cache.demand_accesses::total 2422259 # number of demand (read+write) accesses
543system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6504 # number of overall (read+write) accesses

540system.cpu.l2cache.demand_accesses::cpu.inst 791047 # number of demand (read+write) accesses
541system.cpu.l2cache.demand_accesses::cpu.data 1621986 # number of demand (read+write) accesses
542system.cpu.l2cache.demand_accesses::total 2422345 # number of demand (read+write) accesses
543system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses

544system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses

545system.cpu.l2cache.overall_accesses::cpu.inst 791028 # number of overall (read+write) accesses
546system.cpu.l2cache.overall_accesses::cpu.data 1621920 # number of overall (read+write) accesses
547system.cpu.l2cache.overall_accesses::total 2422259 # number of overall (read+write) accesses
548system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses

545system.cpu.l2cache.overall_accesses::cpu.inst 791047 # number of overall (read+write) accesses
546system.cpu.l2cache.overall_accesses::cpu.data 1621986 # number of overall (read+write) accesses
547system.cpu.l2cache.overall_accesses::total 2422345 # number of overall (read+write) accesses
548system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses

549system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
550system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses
551system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses

552system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses
553system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses
554system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses
555system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427823 # miss rate for ReadExReq accesses
556system.cpu.l2cache.ReadExReq_miss_rate::total 0.427823 # miss rate for ReadExReq accesses
557system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses

552system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses
553system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses
554system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses
555system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427942 # miss rate for ReadExReq accesses
556system.cpu.l2cache.ReadExReq_miss_rate::total 0.427942 # miss rate for ReadExReq accesses
557system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses

558system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
559system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses

560system.cpu.l2cache.demand_miss_rate::cpu.data 0.102741 # miss rate for demand accesses
561system.cpu.l2cache.demand_miss_rate::total 0.074298 # miss rate for demand accesses
562system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses

560system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses
561system.cpu.l2cache.demand_miss_rate::total 0.074323 # miss rate for demand accesses
562system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses

563system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
564system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses

565system.cpu.l2cache.overall_miss_rate::cpu.data 0.102741 # miss rate for overall accesses
566system.cpu.l2cache.overall_miss_rate::total 0.074298 # miss rate for overall accesses

565system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses
566system.cpu.l2cache.overall_miss_rate::total 0.074323 # miss rate for overall accesses

567system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
568system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
569system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
570system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
571system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
572system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
573system.cpu.l2cache.fast_writes 0 # number of fast writes performed
574system.cpu.l2cache.cache_copies 0 # number of cache copies performed

575system.cpu.l2cache.writebacks::writebacks 98091 # number of writebacks
576system.cpu.l2cache.writebacks::total 98091 # number of writebacks

575system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks
576system.cpu.l2cache.writebacks::total 98156 # number of writebacks