| stats.txt (9625:47591444a7c5) | stats.txt (9672:4a4294822ec5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112100 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112100 # Number of seconds simulated |
| 4sim_ticks 5112099860500 # Number of ticks simulated 5final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 5112099861500 # Number of ticks simulated 5final_tick 5112099861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1028107 # Simulator instruction rate (inst/s) 8host_op_rate 2105009 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26291327617 # Simulator tick rate (ticks/s) 10host_mem_usage 628192 # Number of bytes of host memory used 11host_seconds 194.44 # Real time elapsed on the host | 7host_inst_rate 1058684 # Simulator instruction rate (inst/s) 8host_op_rate 2167614 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27073251373 # Simulator tick rate (ticks/s) 10host_mem_usage 628224 # Number of bytes of host memory used 11host_seconds 188.82 # Real time elapsed on the host |
| 12sim_insts 199905607 # Number of instructions simulated | 12sim_insts 199905607 # Number of instructions simulated |
| 13sim_ops 409299132 # Number of ops (including micro ops) simulated | 13sim_ops 409299164 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory --- 167 unchanged lines hidden (view full) --- 189system.physmem.readRowHitRate nan # Row buffer hit rate for reads 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 191system.physmem.avgGap nan # Average gap between requests 192system.iocache.replacements 47568 # number of replacements 193system.iocache.tagsinuse 0.042441 # Cycle average of tags in use 194system.iocache.total_refs 0 # Total number of references to valid blocks. 195system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. 196system.iocache.avg_refs 0 # Average number of references to valid blocks. | 14system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory --- 167 unchanged lines hidden (view full) --- 189system.physmem.readRowHitRate nan # Row buffer hit rate for reads 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 191system.physmem.avgGap nan # Average gap between requests 192system.iocache.replacements 47568 # number of replacements 193system.iocache.tagsinuse 0.042441 # Cycle average of tags in use 194system.iocache.total_refs 0 # Total number of references to valid blocks. 195system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. 196system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 197system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit. | 197system.iocache.warmup_cycle 4994822604059 # Cycle when the warmup percentage was hit. |
| 198system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor 199system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 200system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy 201system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses 202system.iocache.ReadReq_misses::total 903 # number of ReadReq misses 203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 205system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses --- 34 unchanged lines hidden (view full) --- 240system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 241system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 242system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 243system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 244system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 245system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 246system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 247system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 198system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor 199system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 200system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy 201system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses 202system.iocache.ReadReq_misses::total 903 # number of ReadReq misses 203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 205system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses --- 34 unchanged lines hidden (view full) --- 240system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 241system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 242system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 243system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 244system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 245system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 246system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 247system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 248system.cpu.numCycles 10224199744 # number of cpu cycles simulated | 248system.cpu.numCycles 10224199746 # number of cpu cycles simulated |
| 249system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 250system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 251system.cpu.committedInsts 199905607 # Number of instructions committed | 249system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 250system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 251system.cpu.committedInsts 199905607 # Number of instructions committed |
| 252system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed 253system.cpu.num_int_alu_accesses 374462045 # Number of integer alu accesses | 252system.cpu.committedOps 409299164 # Number of ops (including micro ops) committed 253system.cpu.num_int_alu_accesses 374462077 # Number of integer alu accesses |
| 254system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 255system.cpu.num_func_calls 0 # number of times a function call or return occured | 254system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 255system.cpu.num_func_calls 0 # number of times a function call or return occured |
| 256system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls 257system.cpu.num_int_insts 374462045 # number of integer instructions | 256system.cpu.num_conditional_control_insts 39972120 # number of instructions that are conditional controls 257system.cpu.num_int_insts 374462077 # number of integer instructions |
| 258system.cpu.num_fp_insts 0 # number of float instructions | 258system.cpu.num_fp_insts 0 # number of float instructions |
| 259system.cpu.num_int_register_reads 915890298 # number of times the integer registers were read 260system.cpu.num_int_register_writes 480542887 # number of times the integer registers were written | 259system.cpu.num_int_register_reads 915890450 # number of times the integer registers were read 260system.cpu.num_int_register_writes 480542967 # number of times the integer registers were written |
| 261system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 262system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 263system.cpu.num_mem_refs 35654170 # number of memory refs 264system.cpu.num_load_insts 27234345 # Number of load instructions 265system.cpu.num_store_insts 8419825 # Number of store instructions | 261system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 262system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 263system.cpu.num_mem_refs 35654170 # number of memory refs 264system.cpu.num_load_insts 27234345 # Number of load instructions 265system.cpu.num_store_insts 8419825 # Number of store instructions |
| 266system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles 267system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles | 266system.cpu.num_idle_cycles 9770518373.401503 # Number of idle cycles 267system.cpu.num_busy_cycles 453681372.598497 # Number of busy cycles |
| 268system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles 269system.cpu.idle_fraction 0.955627 # Percentage of idle cycles 270system.cpu.kern.inst.arm 0 # number of arm instructions executed 271system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 272system.cpu.icache.replacements 790584 # number of replacements 273system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use | 268system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles 269system.cpu.idle_fraction 0.955627 # Percentage of idle cycles 270system.cpu.kern.inst.arm 0 # number of arm instructions executed 271system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 272system.cpu.icache.replacements 790584 # number of replacements 273system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use |
| 274system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks. | 274system.cpu.icache.total_refs 243492011 # Total number of references to valid blocks. |
| 275system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks. | 275system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks. |
| 276system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks. 277system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. | 276system.cpu.icache.avg_refs 307.790725 # Average number of references to valid blocks. 277system.cpu.icache.warmup_cycle 148824779500 # Cycle when the warmup percentage was hit. |
| 278system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor 279system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy 280system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy | 278system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor 279system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy 280system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy |
| 281system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits 282system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits 283system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits 284system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits 285system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits 286system.cpu.icache.overall_hits::total 243492014 # number of overall hits | 281system.cpu.icache.ReadReq_hits::cpu.inst 243492011 # number of ReadReq hits 282system.cpu.icache.ReadReq_hits::total 243492011 # number of ReadReq hits 283system.cpu.icache.demand_hits::cpu.inst 243492011 # number of demand (read+write) hits 284system.cpu.icache.demand_hits::total 243492011 # number of demand (read+write) hits 285system.cpu.icache.overall_hits::cpu.inst 243492011 # number of overall hits 286system.cpu.icache.overall_hits::total 243492011 # number of overall hits |
| 287system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses 288system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses 289system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses 290system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses 291system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses 292system.cpu.icache.overall_misses::total 791103 # number of overall misses | 287system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses 288system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses 289system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses 290system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses 291system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses 292system.cpu.icache.overall_misses::total 791103 # number of overall misses |
| 293system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses) 294system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses) 295system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses 296system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses 297system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses 298system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses | 293system.cpu.icache.ReadReq_accesses::cpu.inst 244283114 # number of ReadReq accesses(hits+misses) 294system.cpu.icache.ReadReq_accesses::total 244283114 # number of ReadReq accesses(hits+misses) 295system.cpu.icache.demand_accesses::cpu.inst 244283114 # number of demand (read+write) accesses 296system.cpu.icache.demand_accesses::total 244283114 # number of demand (read+write) accesses 297system.cpu.icache.overall_accesses::cpu.inst 244283114 # number of overall (read+write) accesses 298system.cpu.icache.overall_accesses::total 244283114 # number of overall (read+write) accesses |
| 299system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 300system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 301system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 302system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 303system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 304system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 305system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 306system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked --- 4 unchanged lines hidden (view full) --- 311system.cpu.icache.fast_writes 0 # number of fast writes performed 312system.cpu.icache.cache_copies 0 # number of cache copies performed 313system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 314system.cpu.itb_walker_cache.replacements 3477 # number of replacements 315system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cycle average of tags in use 316system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks. 317system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks. 318system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks. | 299system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 300system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 301system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 302system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 303system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 304system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 305system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 306system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked --- 4 unchanged lines hidden (view full) --- 311system.cpu.icache.fast_writes 0 # number of fast writes performed 312system.cpu.icache.cache_copies 0 # number of cache copies performed 313system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 314system.cpu.itb_walker_cache.replacements 3477 # number of replacements 315system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cycle average of tags in use 316system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks. 317system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks. 318system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks. |
| 319system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit. | 319system.cpu.itb_walker_cache.warmup_cycle 5102064746500 # Cycle when the warmup percentage was hit. |
| 320system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor 321system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy 322system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy 323system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 324system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 325system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 326system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 327system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits --- 31 unchanged lines hidden (view full) --- 359system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 360system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 361system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 362system.cpu.dtb_walker_cache.replacements 7629 # number of replacements 363system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cycle average of tags in use 364system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks. 365system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks. 366system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks. | 320system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor 321system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy 322system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy 323system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 324system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 325system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 326system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 327system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits --- 31 unchanged lines hidden (view full) --- 359system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 360system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 361system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 362system.cpu.dtb_walker_cache.replacements 7629 # number of replacements 363system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cycle average of tags in use 364system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks. 365system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks. 366system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks. |
| 367system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit. | 367system.cpu.dtb_walker_cache.warmup_cycle 5100425402500 # Cycle when the warmup percentage was hit. |
| 368system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor 369system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy 370system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy 371system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12955 # number of ReadReq hits 372system.cpu.dtb_walker_cache.ReadReq_hits::total 12955 # number of ReadReq hits 373system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12955 # number of demand (read+write) hits 374system.cpu.dtb_walker_cache.demand_hits::total 12955 # number of demand (read+write) hits 375system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12955 # number of overall hits --- 22 unchanged lines hidden (view full) --- 398system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 401system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 402system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 403system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks 404system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks 405system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 368system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor 369system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy 370system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy 371system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12955 # number of ReadReq hits 372system.cpu.dtb_walker_cache.ReadReq_hits::total 12955 # number of ReadReq hits 373system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12955 # number of demand (read+write) hits 374system.cpu.dtb_walker_cache.demand_hits::total 12955 # number of demand (read+write) hits 375system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12955 # number of overall hits --- 22 unchanged lines hidden (view full) --- 398system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 401system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 402system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 403system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks 404system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks 405system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 406system.cpu.dcache.replacements 1621965 # number of replacements | 406system.cpu.dcache.replacements 1621960 # number of replacements |
| 407system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use | 407system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use |
| 408system.cpu.dcache.total_refs 20168700 # Total number of references to valid blocks. 409system.cpu.dcache.sampled_refs 1622477 # Sample count of references to valid blocks. 410system.cpu.dcache.avg_refs 12.430808 # Average number of references to valid blocks. 411system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. | 408system.cpu.dcache.total_refs 20168705 # Total number of references to valid blocks. 409system.cpu.dcache.sampled_refs 1622472 # Sample count of references to valid blocks. 410system.cpu.dcache.avg_refs 12.430849 # Average number of references to valid blocks. 411system.cpu.dcache.warmup_cycle 7550500 # Cycle when the warmup percentage was hit. |
| 412system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor 413system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 414system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy | 412system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor 413system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 414system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy |
| 415system.cpu.dcache.ReadReq_hits::cpu.data 12073043 # number of ReadReq hits 416system.cpu.dcache.ReadReq_hits::total 12073043 # number of ReadReq hits 417system.cpu.dcache.WriteReq_hits::cpu.data 8093389 # number of WriteReq hits 418system.cpu.dcache.WriteReq_hits::total 8093389 # number of WriteReq hits 419system.cpu.dcache.demand_hits::cpu.data 20166432 # number of demand (read+write) hits 420system.cpu.dcache.demand_hits::total 20166432 # number of demand (read+write) hits 421system.cpu.dcache.overall_hits::cpu.data 20166432 # number of overall hits 422system.cpu.dcache.overall_hits::total 20166432 # number of overall hits 423system.cpu.dcache.ReadReq_misses::cpu.data 1308511 # number of ReadReq misses 424system.cpu.dcache.ReadReq_misses::total 1308511 # number of ReadReq misses 425system.cpu.dcache.WriteReq_misses::cpu.data 316250 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 316250 # number of WriteReq misses 427system.cpu.dcache.demand_misses::cpu.data 1624761 # number of demand (read+write) misses 428system.cpu.dcache.demand_misses::total 1624761 # number of demand (read+write) misses 429system.cpu.dcache.overall_misses::cpu.data 1624761 # number of overall misses 430system.cpu.dcache.overall_misses::total 1624761 # number of overall misses | 415system.cpu.dcache.ReadReq_hits::cpu.data 12073184 # number of ReadReq hits 416system.cpu.dcache.ReadReq_hits::total 12073184 # number of ReadReq hits 417system.cpu.dcache.WriteReq_hits::cpu.data 8093253 # number of WriteReq hits 418system.cpu.dcache.WriteReq_hits::total 8093253 # number of WriteReq hits 419system.cpu.dcache.demand_hits::cpu.data 20166437 # number of demand (read+write) hits 420system.cpu.dcache.demand_hits::total 20166437 # number of demand (read+write) hits 421system.cpu.dcache.overall_hits::cpu.data 20166437 # number of overall hits 422system.cpu.dcache.overall_hits::total 20166437 # number of overall hits 423system.cpu.dcache.ReadReq_misses::cpu.data 1308370 # number of ReadReq misses 424system.cpu.dcache.ReadReq_misses::total 1308370 # number of ReadReq misses 425system.cpu.dcache.WriteReq_misses::cpu.data 316386 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 316386 # number of WriteReq misses 427system.cpu.dcache.demand_misses::cpu.data 1624756 # number of demand (read+write) misses 428system.cpu.dcache.demand_misses::total 1624756 # number of demand (read+write) misses 429system.cpu.dcache.overall_misses::cpu.data 1624756 # number of overall misses 430system.cpu.dcache.overall_misses::total 1624756 # number of overall misses |
| 431system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses) 432system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses) 433system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses) 434system.cpu.dcache.WriteReq_accesses::total 8409639 # number of WriteReq accesses(hits+misses) 435system.cpu.dcache.demand_accesses::cpu.data 21791193 # number of demand (read+write) accesses 436system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses 437system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses 438system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses | 431system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses) 432system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses) 433system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses) 434system.cpu.dcache.WriteReq_accesses::total 8409639 # number of WriteReq accesses(hits+misses) 435system.cpu.dcache.demand_accesses::cpu.data 21791193 # number of demand (read+write) accesses 436system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses 437system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses 438system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses |
| 439system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097785 # miss rate for ReadReq accesses 440system.cpu.dcache.ReadReq_miss_rate::total 0.097785 # miss rate for ReadReq accesses 441system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037606 # miss rate for WriteReq accesses 442system.cpu.dcache.WriteReq_miss_rate::total 0.037606 # miss rate for WriteReq accesses | 439system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097774 # miss rate for ReadReq accesses 440system.cpu.dcache.ReadReq_miss_rate::total 0.097774 # miss rate for ReadReq accesses 441system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses 442system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses |
| 443system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses 444system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses 445system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses 446system.cpu.dcache.overall_miss_rate::total 0.074560 # miss rate for overall accesses 447system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 448system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 449system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 451system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 453system.cpu.dcache.fast_writes 0 # number of fast writes performed 454system.cpu.dcache.cache_copies 0 # number of cache copies performed | 443system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses 444system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses 445system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses 446system.cpu.dcache.overall_miss_rate::total 0.074560 # miss rate for overall accesses 447system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 448system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 449system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 451system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 453system.cpu.dcache.fast_writes 0 # number of fast writes performed 454system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 455system.cpu.dcache.writebacks::writebacks 1535695 # number of writebacks 456system.cpu.dcache.writebacks::total 1535695 # number of writebacks | 455system.cpu.dcache.writebacks::writebacks 1535700 # number of writebacks 456system.cpu.dcache.writebacks::total 1535700 # number of writebacks |
| 457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 458system.cpu.l2cache.replacements 105930 # number of replacements | 457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 458system.cpu.l2cache.replacements 105930 # number of replacements |
| 459system.cpu.l2cache.tagsinuse 64821.868749 # Cycle average of tags in use 460system.cpu.l2cache.total_refs 3456653 # Total number of references to valid blocks. | 459system.cpu.l2cache.tagsinuse 64819.953894 # Cycle average of tags in use 460system.cpu.l2cache.total_refs 3456507 # Total number of references to valid blocks. |
| 461system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks. | 461system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks. |
| 462system.cpu.l2cache.avg_refs 20.326318 # Average number of references to valid blocks. | 462system.cpu.l2cache.avg_refs 20.325460 # Average number of references to valid blocks. |
| 463system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 463system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 464system.cpu.l2cache.occ_blocks::writebacks 51906.789291 # Average occupied blocks per requestor | 464system.cpu.l2cache.occ_blocks::writebacks 51906.788142 # Average occupied blocks per requestor |
| 465system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor 466system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor | 465system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor 466system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor |
| 467system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor 468system.cpu.l2cache.occ_blocks::cpu.data 10424.349245 # Average occupied blocks per requestor | 467system.cpu.l2cache.occ_blocks::cpu.inst 2490.593014 # Average occupied blocks per requestor 468system.cpu.l2cache.occ_blocks::cpu.data 10422.435538 # Average occupied blocks per requestor |
| 469system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy 470system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 471system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 472system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy | 469system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy 470system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 471system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 472system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy |
| 473system.cpu.l2cache.occ_percent::cpu.data 0.159063 # Average percentage of cache occupancy 474system.cpu.l2cache.occ_percent::total 0.989103 # Average percentage of cache occupancy | 473system.cpu.l2cache.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy 474system.cpu.l2cache.occ_percent::total 0.989074 # Average percentage of cache occupancy |
| 475system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits 476system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits 477system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits | 475system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits 476system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits 477system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits |
| 478system.cpu.l2cache.ReadReq_hits::cpu.data 1275631 # number of ReadReq hits 479system.cpu.l2cache.ReadReq_hits::total 2062699 # number of ReadReq hits 480system.cpu.l2cache.Writeback_hits::writebacks 1538634 # number of Writeback hits 481system.cpu.l2cache.Writeback_hits::total 1538634 # number of Writeback hits | 478system.cpu.l2cache.ReadReq_hits::cpu.data 1275492 # number of ReadReq hits 479system.cpu.l2cache.ReadReq_hits::total 2062560 # number of ReadReq hits 480system.cpu.l2cache.Writeback_hits::writebacks 1538639 # number of Writeback hits 481system.cpu.l2cache.Writeback_hits::total 1538639 # number of Writeback hits |
| 482system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 483system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits | 482system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 483system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits |
| 484system.cpu.l2cache.ReadExReq_hits::cpu.data 179586 # number of ReadExReq hits 485system.cpu.l2cache.ReadExReq_hits::total 179586 # number of ReadExReq hits | 484system.cpu.l2cache.ReadExReq_hits::cpu.data 179720 # number of ReadExReq hits 485system.cpu.l2cache.ReadExReq_hits::total 179720 # number of ReadExReq hits |
| 486system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits 487system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits 488system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits | 486system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits 487system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits 488system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits |
| 489system.cpu.l2cache.demand_hits::cpu.data 1455217 # number of demand (read+write) hits 490system.cpu.l2cache.demand_hits::total 2242285 # number of demand (read+write) hits | 489system.cpu.l2cache.demand_hits::cpu.data 1455212 # number of demand (read+write) hits 490system.cpu.l2cache.demand_hits::total 2242280 # number of demand (read+write) hits |
| 491system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits 492system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits 493system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits | 491system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits 492system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits 493system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits |
| 494system.cpu.l2cache.overall_hits::cpu.data 1455217 # number of overall hits 495system.cpu.l2cache.overall_hits::total 2242285 # number of overall hits | 494system.cpu.l2cache.overall_hits::cpu.data 1455212 # number of overall hits 495system.cpu.l2cache.overall_hits::total 2242280 # number of overall hits |
| 496system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 497system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 498system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses | 496system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 497system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 498system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses |
| 499system.cpu.l2cache.ReadReq_misses::cpu.data 32248 # number of ReadReq misses 500system.cpu.l2cache.ReadReq_misses::total 45580 # number of ReadReq misses | 499system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 500system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses |
| 501system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses 502system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses | 501system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses 502system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses |
| 503system.cpu.l2cache.ReadExReq_misses::cpu.data 134391 # number of ReadExReq misses 504system.cpu.l2cache.ReadExReq_misses::total 134391 # number of ReadExReq misses | 503system.cpu.l2cache.ReadExReq_misses::cpu.data 134393 # number of ReadExReq misses 504system.cpu.l2cache.ReadExReq_misses::total 134393 # number of ReadExReq misses |
| 505system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 506system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 507system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses 508system.cpu.l2cache.demand_misses::cpu.data 166639 # number of demand (read+write) misses 509system.cpu.l2cache.demand_misses::total 179971 # number of demand (read+write) misses 510system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 511system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 512system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 513system.cpu.l2cache.overall_misses::cpu.data 166639 # number of overall misses 514system.cpu.l2cache.overall_misses::total 179971 # number of overall misses 515system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses) 516system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) 517system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses) | 505system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 506system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 507system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses 508system.cpu.l2cache.demand_misses::cpu.data 166639 # number of demand (read+write) misses 509system.cpu.l2cache.demand_misses::total 179971 # number of demand (read+write) misses 510system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 511system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 512system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 513system.cpu.l2cache.overall_misses::cpu.data 166639 # number of overall misses 514system.cpu.l2cache.overall_misses::total 179971 # number of overall misses 515system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses) 516system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) 517system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses) |
| 518system.cpu.l2cache.ReadReq_accesses::cpu.data 1307879 # number of ReadReq accesses(hits+misses) 519system.cpu.l2cache.ReadReq_accesses::total 2108279 # number of ReadReq accesses(hits+misses) 520system.cpu.l2cache.Writeback_accesses::writebacks 1538634 # number of Writeback accesses(hits+misses) 521system.cpu.l2cache.Writeback_accesses::total 1538634 # number of Writeback accesses(hits+misses) | 518system.cpu.l2cache.ReadReq_accesses::cpu.data 1307738 # number of ReadReq accesses(hits+misses) 519system.cpu.l2cache.ReadReq_accesses::total 2108138 # number of ReadReq accesses(hits+misses) 520system.cpu.l2cache.Writeback_accesses::writebacks 1538639 # number of Writeback accesses(hits+misses) 521system.cpu.l2cache.Writeback_accesses::total 1538639 # number of Writeback accesses(hits+misses) |
| 522system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) 523system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) | 522system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) 523system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) |
| 524system.cpu.l2cache.ReadExReq_accesses::cpu.data 313977 # number of ReadExReq accesses(hits+misses) 525system.cpu.l2cache.ReadExReq_accesses::total 313977 # number of ReadExReq accesses(hits+misses) | 524system.cpu.l2cache.ReadExReq_accesses::cpu.data 314113 # number of ReadExReq accesses(hits+misses) 525system.cpu.l2cache.ReadExReq_accesses::total 314113 # number of ReadExReq accesses(hits+misses) |
| 526system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses 527system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses 528system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses | 526system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses 527system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses 528system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses |
| 529system.cpu.l2cache.demand_accesses::cpu.data 1621856 # number of demand (read+write) accesses 530system.cpu.l2cache.demand_accesses::total 2422256 # number of demand (read+write) accesses | 529system.cpu.l2cache.demand_accesses::cpu.data 1621851 # number of demand (read+write) accesses 530system.cpu.l2cache.demand_accesses::total 2422251 # number of demand (read+write) accesses |
| 531system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses 532system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses 533system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses | 531system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses 532system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses 533system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses |
| 534system.cpu.l2cache.overall_accesses::cpu.data 1621856 # number of overall (read+write) accesses 535system.cpu.l2cache.overall_accesses::total 2422256 # number of overall (read+write) accesses | 534system.cpu.l2cache.overall_accesses::cpu.data 1621851 # number of overall (read+write) accesses 535system.cpu.l2cache.overall_accesses::total 2422251 # number of overall (read+write) accesses |
| 536system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses 537system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses 538system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses | 536system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses 537system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses 538system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses |
| 539system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses | 539system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024658 # miss rate for ReadReq accesses |
| 540system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses 541system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses 542system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses | 540system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses 541system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses 542system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses |
| 543system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428028 # miss rate for ReadExReq accesses 544system.cpu.l2cache.ReadExReq_miss_rate::total 0.428028 # miss rate for ReadExReq accesses | 543system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427849 # miss rate for ReadExReq accesses 544system.cpu.l2cache.ReadExReq_miss_rate::total 0.427849 # miss rate for ReadExReq accesses |
| 545system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses 546system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses 547system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses 548system.cpu.l2cache.demand_miss_rate::cpu.data 0.102746 # miss rate for demand accesses 549system.cpu.l2cache.demand_miss_rate::total 0.074299 # miss rate for demand accesses 550system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses 551system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses 552system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses --- 15 unchanged lines hidden --- | 545system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses 546system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses 547system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses 548system.cpu.l2cache.demand_miss_rate::cpu.data 0.102746 # miss rate for demand accesses 549system.cpu.l2cache.demand_miss_rate::total 0.074299 # miss rate for demand accesses 550system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses 551system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses 552system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses --- 15 unchanged lines hidden --- |