| stats.txt (9568:cd1351d4d850) | stats.txt (9625:47591444a7c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.112041 # Number of seconds simulated 4sim_ticks 5112040970500 # Number of ticks simulated 5final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.112100 # Number of seconds simulated 4sim_ticks 5112099860500 # Number of ticks simulated 5final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1074050 # Simulator instruction rate (inst/s) 8host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27479001055 # Simulator tick rate (ticks/s) 10host_mem_usage 583620 # Number of bytes of host memory used 11host_seconds 186.03 # Real time elapsed on the host 12sim_insts 199810242 # Number of instructions simulated 13sim_ops 409125913 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory | 7host_inst_rate 1028107 # Simulator instruction rate (inst/s) 8host_op_rate 2105009 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26291327617 # Simulator tick rate (ticks/s) 10host_mem_usage 628192 # Number of bytes of host memory used 11host_seconds 194.44 # Real time elapsed on the host 12sim_insts 199905607 # Number of instructions simulated 13sim_ops 409299132 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9264448 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9264448 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 37827 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 25system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s) | 27system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 165706 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 216864 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 144757 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 144757 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 473568 # Total read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s) | 35system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2074526 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2714989 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1812259 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1812259 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1812259 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 473568 # Total bandwidth to/from this memory (bytes/s) |
| 44system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) | 44system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) | 46system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2074526 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4527248 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.readReqs 0 # Total number of read requests seen 50system.physmem.writeReqs 0 # Total number of write requests seen 51system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 0 # Total number of bytes read from memory 53system.physmem.bytesWritten 0 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q --- 127 unchanged lines hidden (view full) --- 184system.physmem.busUtil 0.00 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.00 # Average read queue length over time 186system.physmem.avgWrQLen 0.00 # Average write queue length over time 187system.physmem.readRowHits 0 # Number of row buffer hits during reads 188system.physmem.writeRowHits 0 # Number of row buffer hits during writes 189system.physmem.readRowHitRate nan # Row buffer hit rate for reads 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 191system.physmem.avgGap nan # Average gap between requests | 49system.physmem.readReqs 0 # Total number of read requests seen 50system.physmem.writeReqs 0 # Total number of write requests seen 51system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady 52system.physmem.bytesRead 0 # Total number of bytes read from memory 53system.physmem.bytesWritten 0 # Total number of bytes written to memory 54system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 55system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 56system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q --- 127 unchanged lines hidden (view full) --- 184system.physmem.busUtil 0.00 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.00 # Average read queue length over time 186system.physmem.avgWrQLen 0.00 # Average write queue length over time 187system.physmem.readRowHits 0 # Number of row buffer hits during reads 188system.physmem.writeRowHits 0 # Number of row buffer hits during writes 189system.physmem.readRowHitRate nan # Row buffer hit rate for reads 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 191system.physmem.avgGap nan # Average gap between requests |
| 192system.iocache.replacements 47569 # number of replacements 193system.iocache.tagsinuse 0.042402 # Cycle average of tags in use | 192system.iocache.replacements 47568 # number of replacements 193system.iocache.tagsinuse 0.042441 # Cycle average of tags in use |
| 194system.iocache.total_refs 0 # Total number of references to valid blocks. | 194system.iocache.total_refs 0 # Total number of references to valid blocks. |
| 195system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. | 195system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. |
| 196system.iocache.avg_refs 0 # Average number of references to valid blocks. | 196system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 197system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit. 198system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor 199system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy 200system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy 201system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 202system.iocache.ReadReq_misses::total 904 # number of ReadReq misses | 197system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit. 198system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor 199system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 200system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy 201system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses 202system.iocache.ReadReq_misses::total 903 # number of ReadReq misses |
| 203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses | 203system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 204system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses |
| 205system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 206system.iocache.demand_misses::total 47624 # number of demand (read+write) misses 207system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 208system.iocache.overall_misses::total 47624 # number of overall misses 209system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 210system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) | 205system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses 206system.iocache.demand_misses::total 47623 # number of demand (read+write) misses 207system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses 208system.iocache.overall_misses::total 47623 # number of overall misses 209system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) 210system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) |
| 211system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 212system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) | 211system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 212system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) |
| 213system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 214system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 215system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 216system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses | 213system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses 214system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses 215system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses 216system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses |
| 217system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 218system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 219system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 220system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 221system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 222system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 223system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 224system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses --- 15 unchanged lines hidden (view full) --- 240system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 241system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 242system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 243system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 244system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 245system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 246system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 247system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 217system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 218system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 219system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 220system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 221system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 222system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 223system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 224system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses --- 15 unchanged lines hidden (view full) --- 240system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 241system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 242system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 243system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 244system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 245system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 246system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 247system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 248system.cpu.numCycles 10224081964 # number of cpu cycles simulated | 248system.cpu.numCycles 10224199744 # number of cpu cycles simulated |
| 249system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 250system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 249system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 250system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 251system.cpu.committedInsts 199810242 # Number of instructions committed 252system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed 253system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses | 251system.cpu.committedInsts 199905607 # Number of instructions committed 252system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed 253system.cpu.num_int_alu_accesses 374462045 # Number of integer alu accesses |
| 254system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 255system.cpu.num_func_calls 0 # number of times a function call or return occured | 254system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 255system.cpu.num_func_calls 0 # number of times a function call or return occured |
| 256system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls 257system.cpu.num_int_insts 374289904 # number of integer instructions | 256system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls 257system.cpu.num_int_insts 374462045 # number of integer instructions |
| 258system.cpu.num_fp_insts 0 # number of float instructions | 258system.cpu.num_fp_insts 0 # number of float instructions |
| 259system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read 260system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written | 259system.cpu.num_int_register_reads 915890298 # number of times the integer registers were read 260system.cpu.num_int_register_writes 480542887 # number of times the integer registers were written |
| 261system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 262system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 261system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 262system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 263system.cpu.num_mem_refs 35624590 # number of memory refs 264system.cpu.num_load_insts 27216588 # Number of load instructions 265system.cpu.num_store_insts 8408002 # Number of store instructions 266system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles 267system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles 268system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles 269system.cpu.idle_fraction 0.955647 # Percentage of idle cycles | 263system.cpu.num_mem_refs 35654170 # number of memory refs 264system.cpu.num_load_insts 27234345 # Number of load instructions 265system.cpu.num_store_insts 8419825 # Number of store instructions 266system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles 267system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles 268system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles 269system.cpu.idle_fraction 0.955627 # Percentage of idle cycles |
| 270system.cpu.kern.inst.arm 0 # number of arm instructions executed 271system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 270system.cpu.kern.inst.arm 0 # number of arm instructions executed 271system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 272system.cpu.icache.replacements 790732 # number of replacements 273system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use 274system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks. 275system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks. 276system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks. 277system.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit. 278system.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor 279system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy 280system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy 281system.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits 282system.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits 283system.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits 284system.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits 285system.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits 286system.cpu.icache.overall_hits::total 243360727 # number of overall hits 287system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses 288system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses 289system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses 290system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses 291system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses 292system.cpu.icache.overall_misses::total 791251 # number of overall misses 293system.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses) 294system.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses) 295system.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses 296system.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses 297system.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses 298system.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses 299system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses 300system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses 301system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses 302system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses 303system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses 304system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses | 272system.cpu.icache.replacements 790584 # number of replacements 273system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use 274system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks. 275system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks. 276system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks. 277system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. 278system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor 279system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy 280system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy 281system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits 282system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits 283system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits 284system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits 285system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits 286system.cpu.icache.overall_hits::total 243492014 # number of overall hits 287system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses 288system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses 289system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses 290system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses 291system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses 292system.cpu.icache.overall_misses::total 791103 # number of overall misses 293system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses) 294system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses) 295system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses 296system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses 297system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses 298system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses 299system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 300system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 301system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 302system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 303system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 304system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses |
| 305system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 306system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 307system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 308system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 309system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 310system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 311system.cpu.icache.fast_writes 0 # number of fast writes performed 312system.cpu.icache.cache_copies 0 # number of cache copies performed 313system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 305system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 306system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 307system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 308system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 309system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 310system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 311system.cpu.icache.fast_writes 0 # number of fast writes performed 312system.cpu.icache.cache_copies 0 # number of cache copies performed 313system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 314system.cpu.itb_walker_cache.replacements 3335 # number of replacements 315system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use 316system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. 317system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. 318system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. 319system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit. 320system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor 321system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy 322system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy 323system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits 324system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits | 314system.cpu.itb_walker_cache.replacements 3477 # number of replacements 315system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cycle average of tags in use 316system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks. 317system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks. 318system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks. 319system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit. 320system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor 321system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy 322system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy 323system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 324system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits |
| 325system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 326system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 325system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 326system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 327system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits 328system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits 329system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits 330system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits 331system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses 332system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses 333system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses 334system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses 335system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses 336system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses 337system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) 338system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) | 327system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits 328system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits 329system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits 330system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits 331system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses 332system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses 333system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses 334system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses 335system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses 336system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses 337system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) 338system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) |
| 339system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 340system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) | 339system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 340system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
| 341system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses 342system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 343system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses 344system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 345system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses 346system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses 347system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses 348system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses 349system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses 350system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses | 341system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses 342system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses 343system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses 344system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses 345system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses 346system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses 347system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses 348system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses 349system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses 350system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses |
| 351system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 352system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 353system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 354system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 355system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 356system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 357system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 358system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 351system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 352system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 353system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 354system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 355system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 356system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 357system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 358system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 359system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks 360system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks | 359system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 360system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks |
| 361system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 361system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 362system.cpu.dtb_walker_cache.replacements 7597 # number of replacements 363system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use 364system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. 365system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. 366system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. 367system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit. 368system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor 369system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy 370system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy 371system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits 372system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits 373system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits 374system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits 375system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits 376system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits 377system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses 378system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses 379system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses 380system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses 381system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses 382system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses 383system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) 384system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 385system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses 386system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 387system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses 388system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses 389system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses 390system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses 391system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses 392system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses 393system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses 394system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses | 362system.cpu.dtb_walker_cache.replacements 7629 # number of replacements 363system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cycle average of tags in use 364system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks. 365system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks. 366system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks. 367system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit. 368system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor 369system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy 370system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy 371system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12955 # number of ReadReq hits 372system.cpu.dtb_walker_cache.ReadReq_hits::total 12955 # number of ReadReq hits 373system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12955 # number of demand (read+write) hits 374system.cpu.dtb_walker_cache.demand_hits::total 12955 # number of demand (read+write) hits 375system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12955 # number of overall hits 376system.cpu.dtb_walker_cache.overall_hits::total 12955 # number of overall hits 377system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8819 # number of ReadReq misses 378system.cpu.dtb_walker_cache.ReadReq_misses::total 8819 # number of ReadReq misses 379system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8819 # number of demand (read+write) misses 380system.cpu.dtb_walker_cache.demand_misses::total 8819 # number of demand (read+write) misses 381system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8819 # number of overall misses 382system.cpu.dtb_walker_cache.overall_misses::total 8819 # number of overall misses 383system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21774 # number of ReadReq accesses(hits+misses) 384system.cpu.dtb_walker_cache.ReadReq_accesses::total 21774 # number of ReadReq accesses(hits+misses) 385system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21774 # number of demand (read+write) accesses 386system.cpu.dtb_walker_cache.demand_accesses::total 21774 # number of demand (read+write) accesses 387system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21774 # number of overall (read+write) accesses 388system.cpu.dtb_walker_cache.overall_accesses::total 21774 # number of overall (read+write) accesses 389system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405024 # miss rate for ReadReq accesses 390system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405024 # miss rate for ReadReq accesses 391system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405024 # miss rate for demand accesses 392system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405024 # miss rate for demand accesses 393system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405024 # miss rate for overall accesses 394system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405024 # miss rate for overall accesses |
| 395system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 398system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 401system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 402system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 395system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 396system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 397system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 398system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 399system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 400system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 401system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 402system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 403system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks 404system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks | 403system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks 404system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks |
| 405system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 405system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 406system.cpu.dcache.replacements 1621135 # number of replacements 407system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use 408system.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks. 409system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks. 410system.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks. | 406system.cpu.dcache.replacements 1621965 # number of replacements 407system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use 408system.cpu.dcache.total_refs 20168700 # Total number of references to valid blocks. 409system.cpu.dcache.sampled_refs 1622477 # Sample count of references to valid blocks. 410system.cpu.dcache.avg_refs 12.430808 # Average number of references to valid blocks. |
| 411system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. | 411system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. |
| 412system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor | 412system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor |
| 413system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 414system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy | 413system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 414system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy |
| 415system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits 416system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits 417system.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits 418system.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits 419system.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits 420system.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits 421system.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits 422system.cpu.dcache.overall_hits::total 20138169 # number of overall hits 423system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses 424system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses 425system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses 427system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses 428system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses 429system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses 430system.cpu.dcache.overall_misses::total 1623919 # number of overall misses 431system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses) 432system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses) 433system.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses) 434system.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses) 435system.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses 436system.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses 437system.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses 438system.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses 439system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses 440system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses 441system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses 442system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses 443system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses 444system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses 445system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses 446system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses | 415system.cpu.dcache.ReadReq_hits::cpu.data 12073043 # number of ReadReq hits 416system.cpu.dcache.ReadReq_hits::total 12073043 # number of ReadReq hits 417system.cpu.dcache.WriteReq_hits::cpu.data 8093389 # number of WriteReq hits 418system.cpu.dcache.WriteReq_hits::total 8093389 # number of WriteReq hits 419system.cpu.dcache.demand_hits::cpu.data 20166432 # number of demand (read+write) hits 420system.cpu.dcache.demand_hits::total 20166432 # number of demand (read+write) hits 421system.cpu.dcache.overall_hits::cpu.data 20166432 # number of overall hits 422system.cpu.dcache.overall_hits::total 20166432 # number of overall hits 423system.cpu.dcache.ReadReq_misses::cpu.data 1308511 # number of ReadReq misses 424system.cpu.dcache.ReadReq_misses::total 1308511 # number of ReadReq misses 425system.cpu.dcache.WriteReq_misses::cpu.data 316250 # number of WriteReq misses 426system.cpu.dcache.WriteReq_misses::total 316250 # number of WriteReq misses 427system.cpu.dcache.demand_misses::cpu.data 1624761 # number of demand (read+write) misses 428system.cpu.dcache.demand_misses::total 1624761 # number of demand (read+write) misses 429system.cpu.dcache.overall_misses::cpu.data 1624761 # number of overall misses 430system.cpu.dcache.overall_misses::total 1624761 # number of overall misses 431system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses) 432system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses) 433system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses) 434system.cpu.dcache.WriteReq_accesses::total 8409639 # number of WriteReq accesses(hits+misses) 435system.cpu.dcache.demand_accesses::cpu.data 21791193 # number of demand (read+write) accesses 436system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses 437system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses 438system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses 439system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097785 # miss rate for ReadReq accesses 440system.cpu.dcache.ReadReq_miss_rate::total 0.097785 # miss rate for ReadReq accesses 441system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037606 # miss rate for WriteReq accesses 442system.cpu.dcache.WriteReq_miss_rate::total 0.037606 # miss rate for WriteReq accesses 443system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses 444system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses 445system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses 446system.cpu.dcache.overall_miss_rate::total 0.074560 # miss rate for overall accesses |
| 447system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 448system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 449system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 451system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 453system.cpu.dcache.fast_writes 0 # number of fast writes performed 454system.cpu.dcache.cache_copies 0 # number of cache copies performed | 447system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 448system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 449system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 451system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 453system.cpu.dcache.fast_writes 0 # number of fast writes performed 454system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 455system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks 456system.cpu.dcache.writebacks::total 1534848 # number of writebacks | 455system.cpu.dcache.writebacks::writebacks 1535695 # number of writebacks 456system.cpu.dcache.writebacks::total 1535695 # number of writebacks |
| 457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 458system.cpu.l2cache.replacements 106558 # number of replacements 459system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use 460system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. 461system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. 462system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. | 458system.cpu.l2cache.replacements 105930 # number of replacements 459system.cpu.l2cache.tagsinuse 64821.868749 # Cycle average of tags in use 460system.cpu.l2cache.total_refs 3456653 # Total number of references to valid blocks. 461system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks. 462system.cpu.l2cache.avg_refs 20.326318 # Average number of references to valid blocks. |
| 463system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 463system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 464system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor 465system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor 466system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor 467system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor 468system.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor 469system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy | 464system.cpu.l2cache.occ_blocks::writebacks 51906.789291 # Average occupied blocks per requestor 465system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor 466system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor 467system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor 468system.cpu.l2cache.occ_blocks::cpu.data 10424.349245 # Average occupied blocks per requestor 469system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy |
| 470system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 471system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy | 470system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 471system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy |
| 472system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy 473system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy 474system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy 475system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits 476system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits 477system.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits 478system.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits 479system.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits 480system.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits 481system.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits 482system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 483system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 484system.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits 485system.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits 486system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits 487system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits 488system.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits 489system.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits 490system.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits 491system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits 492system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits 493system.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits 494system.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits 495system.cpu.l2cache.overall_hits::total 2241638 # number of overall hits | 472system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 473system.cpu.l2cache.occ_percent::cpu.data 0.159063 # Average percentage of cache occupancy 474system.cpu.l2cache.occ_percent::total 0.989103 # Average percentage of cache occupancy 475system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits 476system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits 477system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits 478system.cpu.l2cache.ReadReq_hits::cpu.data 1275631 # number of ReadReq hits 479system.cpu.l2cache.ReadReq_hits::total 2062699 # number of ReadReq hits 480system.cpu.l2cache.Writeback_hits::writebacks 1538634 # number of Writeback hits 481system.cpu.l2cache.Writeback_hits::total 1538634 # number of Writeback hits 482system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 483system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 484system.cpu.l2cache.ReadExReq_hits::cpu.data 179586 # number of ReadExReq hits 485system.cpu.l2cache.ReadExReq_hits::total 179586 # number of ReadExReq hits 486system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits 487system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits 488system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits 489system.cpu.l2cache.demand_hits::cpu.data 1455217 # number of demand (read+write) hits 490system.cpu.l2cache.demand_hits::total 2242285 # number of demand (read+write) hits 491system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits 492system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits 493system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits 494system.cpu.l2cache.overall_hits::cpu.data 1455217 # number of overall hits 495system.cpu.l2cache.overall_hits::total 2242285 # number of overall hits |
| 496system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 497system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses | 496system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 497system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses |
| 498system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses 499system.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses 500system.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses 501system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses 502system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses 503system.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses 504system.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses | 498system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 499system.cpu.l2cache.ReadReq_misses::cpu.data 32248 # number of ReadReq misses 500system.cpu.l2cache.ReadReq_misses::total 45580 # number of ReadReq misses 501system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses 502system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses 503system.cpu.l2cache.ReadExReq_misses::cpu.data 134391 # number of ReadExReq misses 504system.cpu.l2cache.ReadExReq_misses::total 134391 # number of ReadExReq misses |
| 505system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 506system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses | 505system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 506system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses |
| 507system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses 508system.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses 509system.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses | 507system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses 508system.cpu.l2cache.demand_misses::cpu.data 166639 # number of demand (read+write) misses 509system.cpu.l2cache.demand_misses::total 179971 # number of demand (read+write) misses |
| 510system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 511system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses | 510system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 511system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses |
| 512system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses 513system.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses 514system.cpu.l2cache.overall_misses::total 179909 # number of overall misses 515system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) 516system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) 517system.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses) 518system.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses) 519system.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses) 520system.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses) 521system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses) 522system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) 523system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) 524system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses) 525system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses) 526system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses 527system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses 528system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses 529system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses 530system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses 531system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses 532system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses 533system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses 534system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses 535system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses 536system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses 537system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses 538system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses 539system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses 540system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 541system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses 542system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses 543system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses 544system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses 545system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses 546system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses 547system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses 548system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses 549system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses 550system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses 551system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses 552system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses 553system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses 554system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses | 512system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 513system.cpu.l2cache.overall_misses::cpu.data 166639 # number of overall misses 514system.cpu.l2cache.overall_misses::total 179971 # number of overall misses 515system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses) 516system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) 517system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses) 518system.cpu.l2cache.ReadReq_accesses::cpu.data 1307879 # number of ReadReq accesses(hits+misses) 519system.cpu.l2cache.ReadReq_accesses::total 2108279 # number of ReadReq accesses(hits+misses) 520system.cpu.l2cache.Writeback_accesses::writebacks 1538634 # number of Writeback accesses(hits+misses) 521system.cpu.l2cache.Writeback_accesses::total 1538634 # number of Writeback accesses(hits+misses) 522system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) 523system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) 524system.cpu.l2cache.ReadExReq_accesses::cpu.data 313977 # number of ReadExReq accesses(hits+misses) 525system.cpu.l2cache.ReadExReq_accesses::total 313977 # number of ReadExReq accesses(hits+misses) 526system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses 527system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses 528system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses 529system.cpu.l2cache.demand_accesses::cpu.data 1621856 # number of demand (read+write) accesses 530system.cpu.l2cache.demand_accesses::total 2422256 # number of demand (read+write) accesses 531system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses 532system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses 533system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses 534system.cpu.l2cache.overall_accesses::cpu.data 1621856 # number of overall (read+write) accesses 535system.cpu.l2cache.overall_accesses::total 2422256 # number of overall (read+write) accesses 536system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses 537system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses 538system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses 539system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses 540system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses 541system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses 542system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses 543system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428028 # miss rate for ReadExReq accesses 544system.cpu.l2cache.ReadExReq_miss_rate::total 0.428028 # miss rate for ReadExReq accesses 545system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses 546system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses 547system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses 548system.cpu.l2cache.demand_miss_rate::cpu.data 0.102746 # miss rate for demand accesses 549system.cpu.l2cache.demand_miss_rate::total 0.074299 # miss rate for demand accesses 550system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses 551system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses 552system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses 553system.cpu.l2cache.overall_miss_rate::cpu.data 0.102746 # miss rate for overall accesses 554system.cpu.l2cache.overall_miss_rate::total 0.074299 # miss rate for overall accesses |
| 555system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 556system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 559system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 560system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 561system.cpu.l2cache.fast_writes 0 # number of fast writes performed 562system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 555system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 556system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 557system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 558system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 559system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 560system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 561system.cpu.l2cache.fast_writes 0 # number of fast writes performed 562system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 563system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks 564system.cpu.l2cache.writebacks::total 98530 # number of writebacks | 563system.cpu.l2cache.writebacks::writebacks 98090 # number of writebacks 564system.cpu.l2cache.writebacks::total 98090 # number of writebacks |
| 565system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 566 567---------- End Simulation Statistics ---------- | 565system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 566 567---------- End Simulation Statistics ---------- |