| stats.txt (9283:490958b032d6) | stats.txt (9289:a31a1243a3ed) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.112041 # Number of seconds simulated 4sim_ticks 5112040968500 # Number of ticks simulated 5final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1011485 # Simulator instruction rate (inst/s) 8host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 25877843451 # Simulator tick rate (ticks/s) 10host_mem_usage 397304 # Number of bytes of host memory used 11host_seconds 197.55 # Real time elapsed on the host 12sim_insts 199813914 # Number of instructions simulated 13sim_ops 409133298 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory | 7host_inst_rate 923075 # Simulator instruction rate (inst/s) 8host_op_rate 1890063 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 23616389220 # Simulator tick rate (ticks/s) 10host_mem_usage 353316 # Number of bytes of host memory used 11host_seconds 216.46 # Real time elapsed on the host 12sim_insts 199810236 # Number of instructions simulated 13sim_ops 409125915 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory |
| 20system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory | 20system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory |
| 22system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory | 22system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory | 25system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s) | 28system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) |
| 36system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) | 38system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) |
| 40system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) | 40system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s) |
| 44system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) | 44system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) 49system.cpu.l2cache.replacements 106561 # number of replacements 50system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use 51system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks. 52system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks. 53system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks. 54system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 55system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor 56system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor 57system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor 58system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor 59system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor 60system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy 61system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 62system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 63system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy 64system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy 65system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy 66system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits 67system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits 68system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits 69system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits 70system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits 71system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits 72system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits 73system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 74system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 75system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits 76system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits 77system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits 78system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits 79system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits 80system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits 81system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits 82system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits 83system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits 84system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits 85system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits 86system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits 87system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 88system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 89system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses 90system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses 91system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses 92system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses 93system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses 94system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses 95system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses 96system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 97system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 98system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses 99system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses 100system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses 101system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 102system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 103system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses 104system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses 105system.cpu.l2cache.overall_misses::total 179910 # number of overall misses 106system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) 107system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) 108system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) 109system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) 110system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) 111system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) 112system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) 113system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) 114system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) 115system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) 116system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) 117system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses 118system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses 119system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses 120system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses 121system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses 122system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses 123system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses 124system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses 125system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses 126system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses 127system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses 128system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses 129system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses 130system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses 131system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses 132system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses 133system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses 134system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses 135system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses 136system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses 137system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses 138system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses 139system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses 140system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses 141system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses 142system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses 143system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses 144system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses 145system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses 146system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 147system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 148system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 149system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 150system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 151system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 152system.cpu.l2cache.fast_writes 0 # number of fast writes performed 153system.cpu.l2cache.cache_copies 0 # number of cache copies performed 154system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks 155system.cpu.l2cache.writebacks::total 98533 # number of writebacks 156system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 157system.iocache.replacements 47570 # number of replacements 158system.iocache.tagsinuse 0.042409 # Cycle average of tags in use | 47system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) 49system.iocache.replacements 47569 # number of replacements 50system.iocache.tagsinuse 0.042402 # Cycle average of tags in use |
| 159system.iocache.total_refs 0 # Total number of references to valid blocks. | 51system.iocache.total_refs 0 # Total number of references to valid blocks. |
| 160system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. | 52system.iocache.sampled_refs 47585 # Sample count of references to valid blocks. |
| 161system.iocache.avg_refs 0 # Average number of references to valid blocks. | 53system.iocache.avg_refs 0 # Average number of references to valid blocks. |
| 162system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. 163system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor 164system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy 165system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy 166system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses 167system.iocache.ReadReq_misses::total 905 # number of ReadReq misses | 54system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit. 55system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor 56system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy 57system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy 58system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 59system.iocache.ReadReq_misses::total 904 # number of ReadReq misses |
| 168system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 169system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses | 60system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 61system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses |
| 170system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses 171system.iocache.demand_misses::total 47625 # number of demand (read+write) misses 172system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses 173system.iocache.overall_misses::total 47625 # number of overall misses 174system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses) 175system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) | 62system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 63system.iocache.demand_misses::total 47624 # number of demand (read+write) misses 64system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 65system.iocache.overall_misses::total 47624 # number of overall misses 66system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 67system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) |
| 176system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 177system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) | 68system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 69system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) |
| 178system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses 179system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses 180system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses 181system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses | 70system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 71system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 72system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 73system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses |
| 182system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 183system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 184system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 185system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 186system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 187system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 188system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 189system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses --- 5 unchanged lines hidden (view full) --- 195system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 196system.iocache.fast_writes 0 # number of fast writes performed 197system.iocache.cache_copies 0 # number of cache copies performed 198system.iocache.writebacks::writebacks 46667 # number of writebacks 199system.iocache.writebacks::total 46667 # number of writebacks 200system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 201system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 202system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). | 74system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 75system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 76system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 77system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 78system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 79system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 80system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 81system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses --- 5 unchanged lines hidden (view full) --- 87system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 88system.iocache.fast_writes 0 # number of fast writes performed 89system.iocache.cache_copies 0 # number of cache copies performed 90system.iocache.writebacks::writebacks 46667 # number of writebacks 91system.iocache.writebacks::total 46667 # number of writebacks 92system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 93system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 94system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). |
| 203system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). | 95system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). |
| 204system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 205system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 206system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 207system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 208system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 209system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 210system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 211system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 212system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. | 96system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 97system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 98system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 99system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 100system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 101system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 102system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 103system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 104system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
| 213system.cpu.numCycles 10224086531 # number of cpu cycles simulated | 105system.cpu.numCycles 10224081960 # number of cpu cycles simulated |
| 214system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 215system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 106system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 107system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 216system.cpu.committedInsts 199813914 # Number of instructions committed 217system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed 218system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses | 108system.cpu.committedInsts 199810236 # Number of instructions committed 109system.cpu.committedOps 409125915 # Number of ops (including micro ops) committed 110system.cpu.num_int_alu_accesses 374289906 # Number of integer alu accesses |
| 219system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 220system.cpu.num_func_calls 0 # number of times a function call or return occured | 111system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 112system.cpu.num_func_calls 0 # number of times a function call or return occured |
| 221system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls 222system.cpu.num_int_insts 374297264 # number of integer instructions | 113system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls 114system.cpu.num_int_insts 374289906 # number of integer instructions |
| 223system.cpu.num_fp_insts 0 # number of float instructions | 115system.cpu.num_fp_insts 0 # number of float instructions |
| 224system.cpu.num_int_register_reads 915470380 # number of times the integer registers were read 225system.cpu.num_int_register_writes 480331069 # number of times the integer registers were written | 116system.cpu.num_int_register_reads 915450684 # number of times the integer registers were read 117system.cpu.num_int_register_writes 480322735 # number of times the integer registers were written |
| 226system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 227system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 118system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 119system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 228system.cpu.num_mem_refs 35626517 # number of memory refs 229system.cpu.num_load_insts 27217782 # Number of load instructions 230system.cpu.num_store_insts 8408735 # Number of store instructions 231system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles 232system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles 233system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles 234system.cpu.idle_fraction 0.955646 # Percentage of idle cycles | 120system.cpu.num_mem_refs 35624588 # number of memory refs 121system.cpu.num_load_insts 27216588 # Number of load instructions 122system.cpu.num_store_insts 8408000 # Number of store instructions 123system.cpu.num_idle_cycles 9770609605.299961 # Number of idle cycles 124system.cpu.num_busy_cycles 453472354.700038 # Number of busy cycles 125system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles 126system.cpu.idle_fraction 0.955647 # Percentage of idle cycles |
| 235system.cpu.kern.inst.arm 0 # number of arm instructions executed 236system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 127system.cpu.kern.inst.arm 0 # number of arm instructions executed 128system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 237system.cpu.icache.replacements 790793 # number of replacements | 129system.cpu.icache.replacements 790732 # number of replacements |
| 238system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use | 130system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use |
| 239system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks. 240system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. 241system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks. | 131system.cpu.icache.total_refs 243360722 # Total number of references to valid blocks. 132system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks. 133system.cpu.icache.avg_refs 307.567226 # Average number of references to valid blocks. |
| 242system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit. 243system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor 244system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy 245system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy | 134system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit. 135system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor 136system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy 137system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy |
| 246system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits 247system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits 248system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits 249system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits 250system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits 251system.cpu.icache.overall_hits::total 243365779 # number of overall hits 252system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses 253system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses 254system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses 255system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses 256system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses 257system.cpu.icache.overall_misses::total 791312 # number of overall misses 258system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) 259system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) 260system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses 261system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses 262system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses 263system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses | 138system.cpu.icache.ReadReq_hits::cpu.inst 243360722 # number of ReadReq hits 139system.cpu.icache.ReadReq_hits::total 243360722 # number of ReadReq hits 140system.cpu.icache.demand_hits::cpu.inst 243360722 # number of demand (read+write) hits 141system.cpu.icache.demand_hits::total 243360722 # number of demand (read+write) hits 142system.cpu.icache.overall_hits::cpu.inst 243360722 # number of overall hits 143system.cpu.icache.overall_hits::total 243360722 # number of overall hits 144system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses 145system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses 146system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses 147system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses 148system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses 149system.cpu.icache.overall_misses::total 791251 # number of overall misses 150system.cpu.icache.ReadReq_accesses::cpu.inst 244151973 # number of ReadReq accesses(hits+misses) 151system.cpu.icache.ReadReq_accesses::total 244151973 # number of ReadReq accesses(hits+misses) 152system.cpu.icache.demand_accesses::cpu.inst 244151973 # number of demand (read+write) accesses 153system.cpu.icache.demand_accesses::total 244151973 # number of demand (read+write) accesses 154system.cpu.icache.overall_accesses::cpu.inst 244151973 # number of overall (read+write) accesses 155system.cpu.icache.overall_accesses::total 244151973 # number of overall (read+write) accesses |
| 264system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses 265system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses 266system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses 267system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses 268system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses 269system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses 270system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 271system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 272system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 273system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 274system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 275system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 276system.cpu.icache.fast_writes 0 # number of fast writes performed 277system.cpu.icache.cache_copies 0 # number of cache copies performed 278system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 279system.cpu.itb_walker_cache.replacements 3335 # number of replacements | 156system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses 157system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses 158system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses 159system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses 160system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses 161system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses 162system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 163system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 164system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 165system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 166system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 167system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 168system.cpu.icache.fast_writes 0 # number of fast writes performed 169system.cpu.icache.cache_copies 0 # number of cache copies performed 170system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 171system.cpu.itb_walker_cache.replacements 3335 # number of replacements |
| 280system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use | 172system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use |
| 281system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. 282system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. 283system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. | 173system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. 174system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. 175system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. |
| 284system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit. 285system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor 286system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy 287system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy | 176system.cpu.itb_walker_cache.warmup_cycle 5102019603000 # Cycle when the warmup percentage was hit. 177system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor 178system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy 179system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy |
| 288system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits 289system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits 290system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 291system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 292system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits 293system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits 294system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits 295system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits --- 23 unchanged lines hidden (view full) --- 319system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 320system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 321system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 322system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 323system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 324system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks 325system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks 326system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 180system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits 181system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits 182system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 183system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 184system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits 185system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits 186system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits 187system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits --- 23 unchanged lines hidden (view full) --- 211system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 212system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 213system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 214system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 215system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 216system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks 217system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks 218system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 327system.cpu.dtb_walker_cache.replacements 7598 # number of replacements 328system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use 329system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks. 330system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks. 331system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks. 332system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit. 333system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor 334system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy 335system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy 336system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits 337system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits 338system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits 339system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits 340system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits 341system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits 342system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses 343system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses 344system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses 345system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses 346system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses 347system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses | 219system.cpu.dtb_walker_cache.replacements 7597 # number of replacements 220system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use 221system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. 222system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. 223system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. 224system.cpu.dtb_walker_cache.warmup_cycle 5101206381500 # Cycle when the warmup percentage was hit. 225system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor 226system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy 227system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy 228system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits 229system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits 230system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits 231system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits 232system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits 233system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits 234system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses 235system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses 236system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses 237system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses 238system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses 239system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses |
| 348system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) 349system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 350system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses 351system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 352system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses 353system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses | 240system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) 241system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 242system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses 243system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 244system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses 245system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses |
| 354system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses 355system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses 356system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses 357system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses 358system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses 359system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses | 246system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses 247system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses 248system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses 249system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses 250system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses 251system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses |
| 360system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 361system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 362system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 363system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 364system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 365system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 366system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 367system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 368system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks 369system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks 370system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 252system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 253system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 254system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 255system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 256system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 257system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 258system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 259system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 260system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks 261system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks 262system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 371system.cpu.dcache.replacements 1621273 # number of replacements | 263system.cpu.dcache.replacements 1621135 # number of replacements |
| 372system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use | 264system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use |
| 373system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks. 374system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks. 375system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks. | 265system.cpu.dcache.total_refs 20140429 # Total number of references to valid blocks. 266system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks. 267system.cpu.dcache.avg_refs 12.419737 # Average number of references to valid blocks. |
| 376system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 377system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor 378system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 379system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy | 268system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 269system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor 270system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 271system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy |
| 380system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits 381system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits 382system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits 383system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits 384system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits 385system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits 386system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits 387system.cpu.dcache.overall_hits::total 20139960 # number of overall hits 388system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses 389system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses 390system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses 391system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses 392system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses 393system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses 394system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses 395system.cpu.dcache.overall_misses::total 1624057 # number of overall misses 396system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses) 397system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses) 398system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) 399system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) 400system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses 401system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses 402system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses 403system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses | 272system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits 273system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits 274system.cpu.dcache.WriteReq_hits::cpu.data 8082226 # number of WriteReq hits 275system.cpu.dcache.WriteReq_hits::total 8082226 # number of WriteReq hits 276system.cpu.dcache.demand_hits::cpu.data 20138167 # number of demand (read+write) hits 277system.cpu.dcache.demand_hits::total 20138167 # number of demand (read+write) hits 278system.cpu.dcache.overall_hits::cpu.data 20138167 # number of overall hits 279system.cpu.dcache.overall_hits::total 20138167 # number of overall hits 280system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses 281system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses 282system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses 283system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses 284system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses 285system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses 286system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses 287system.cpu.dcache.overall_misses::total 1623919 # number of overall misses 288system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses) 289system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses) 290system.cpu.dcache.WriteReq_accesses::cpu.data 8398054 # number of WriteReq accesses(hits+misses) 291system.cpu.dcache.WriteReq_accesses::total 8398054 # number of WriteReq accesses(hits+misses) 292system.cpu.dcache.demand_accesses::cpu.data 21762086 # number of demand (read+write) accesses 293system.cpu.dcache.demand_accesses::total 21762086 # number of demand (read+write) accesses 294system.cpu.dcache.overall_accesses::cpu.data 21762086 # number of overall (read+write) accesses 295system.cpu.dcache.overall_accesses::total 21762086 # number of overall (read+write) accesses |
| 404system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses 405system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses 406system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses 407system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses 408system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses 409system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses 410system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses 411system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses 412system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 413system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 417system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 418system.cpu.dcache.fast_writes 0 # number of fast writes performed 419system.cpu.dcache.cache_copies 0 # number of cache copies performed | 296system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses 297system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses 298system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses 299system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses 300system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses 301system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses 302system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses 303system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses 304system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 305system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 306system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 307system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 308system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 309system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 310system.cpu.dcache.fast_writes 0 # number of fast writes performed 311system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 420system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks 421system.cpu.dcache.writebacks::total 1534981 # number of writebacks | 312system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks 313system.cpu.dcache.writebacks::total 1534848 # number of writebacks |
| 422system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 314system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 315system.cpu.l2cache.replacements 106558 # number of replacements 316system.cpu.l2cache.tagsinuse 64822.149249 # Cycle average of tags in use 317system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. 318system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. 319system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. 320system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 321system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor 322system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor 323system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor 324system.cpu.l2cache.occ_blocks::cpu.inst 2434.994085 # Average occupied blocks per requestor 325system.cpu.l2cache.occ_blocks::cpu.data 10405.564956 # Average occupied blocks per requestor 326system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy 327system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 328system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 329system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy 330system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy 331system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy 332system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits 333system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits 334system.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits 335system.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits 336system.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits 337system.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits 338system.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits 339system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 340system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 341system.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits 342system.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits 343system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits 344system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits 345system.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits 346system.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits 347system.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits 348system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits 349system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits 350system.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits 351system.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits 352system.cpu.l2cache.overall_hits::total 2241638 # number of overall hits 353system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 354system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 355system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses 356system.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses 357system.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses 358system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses 359system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses 360system.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses 361system.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses 362system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 363system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 364system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses 365system.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses 366system.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses 367system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 368system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 369system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses 370system.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses 371system.cpu.l2cache.overall_misses::total 179909 # number of overall misses 372system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) 373system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) 374system.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses) 375system.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses) 376system.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses) 377system.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses) 378system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses) 379system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) 380system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) 381system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses) 382system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses) 383system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses 384system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses 385system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses 386system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses 387system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses 388system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses 389system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses 390system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses 391system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses 392system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses 393system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses 394system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses 395system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses 396system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses 397system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 398system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses 399system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses 400system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses 401system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses 402system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses 403system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses 404system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses 405system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses 406system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses 407system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses 408system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses 409system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses 410system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses 411system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses 412system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 413system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 414system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 415system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 416system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 417system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 418system.cpu.l2cache.fast_writes 0 # number of fast writes performed 419system.cpu.l2cache.cache_copies 0 # number of cache copies performed 420system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks 421system.cpu.l2cache.writebacks::total 98530 # number of writebacks 422system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
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| 423 424---------- End Simulation Statistics ---------- | 423 424---------- End Simulation Statistics ---------- |