| stats.txt (9213:5cab5448909c) | stats.txt (9283:490958b032d6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1011485 # Simulator instruction rate (inst/s) 8host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s) --- 32 unchanged lines hidden (view full) --- 41system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1011485 # Simulator instruction rate (inst/s) 8host_op_rate 2071087 # Simulator op (including micro ops) rate (op/s) --- 32 unchanged lines hidden (view full) --- 41system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) |
| 49system.l2c.replacements 106561 # number of replacements 50system.l2c.tagsinuse 64822.143261 # Cycle average of tags in use 51system.l2c.total_refs 3456533 # Total number of references to valid blocks. 52system.l2c.sampled_refs 170680 # Sample count of references to valid blocks. 53system.l2c.avg_refs 20.251541 # Average number of references to valid blocks. 54system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 55system.l2c.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor 56system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor 57system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor 60system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy 61system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 62system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy 65system.l2c.occ_percent::total 0.989107 # Average percentage of cache occupancy 66system.l2c.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits 67system.l2c.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits 68system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits 70system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits 71system.l2c.Writeback_hits::writebacks 1538130 # number of Writeback hits 72system.l2c.Writeback_hits::total 1538130 # number of Writeback hits 73system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 74system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits 75system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits 76system.l2c.ReadExReq_hits::total 179208 # number of ReadExReq hits 77system.l2c.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits 78system.l2c.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits 79system.l2c.demand_hits::cpu.inst 777957 # number of demand (read+write) hits 80system.l2c.demand_hits::cpu.data 1454603 # number of demand (read+write) hits 81system.l2c.demand_hits::total 2241838 # number of demand (read+write) hits 82system.l2c.overall_hits::cpu.dtb.walker 6578 # number of overall hits 83system.l2c.overall_hits::cpu.itb.walker 2700 # number of overall hits 84system.l2c.overall_hits::cpu.inst 777957 # number of overall hits 85system.l2c.overall_hits::cpu.data 1454603 # number of overall hits 86system.l2c.overall_hits::total 2241838 # number of overall hits 87system.l2c.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 88system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 89system.l2c.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses 90system.l2c.ReadReq_misses::cpu.data 32184 # number of ReadReq misses 91system.l2c.ReadReq_misses::total 45533 # number of ReadReq misses 92system.l2c.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses 93system.l2c.UpgradeReq_misses::total 1796 # number of UpgradeReq misses 94system.l2c.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses 95system.l2c.ReadExReq_misses::total 134377 # number of ReadExReq misses 96system.l2c.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 97system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 98system.l2c.demand_misses::cpu.inst 13342 # number of demand (read+write) misses 99system.l2c.demand_misses::cpu.data 166561 # number of demand (read+write) misses 100system.l2c.demand_misses::total 179910 # number of demand (read+write) misses 101system.l2c.overall_misses::cpu.dtb.walker 2 # number of overall misses 102system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses 103system.l2c.overall_misses::cpu.inst 13342 # number of overall misses 104system.l2c.overall_misses::cpu.data 166561 # number of overall misses 105system.l2c.overall_misses::total 179910 # number of overall misses 106system.l2c.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) 107system.l2c.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) 108system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) 109system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) 110system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) 111system.l2c.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) 112system.l2c.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) 113system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) 114system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) 115system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) 116system.l2c.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) 117system.l2c.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses 118system.l2c.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses 119system.l2c.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses 120system.l2c.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses 121system.l2c.demand_accesses::total 2421748 # number of demand (read+write) accesses 122system.l2c.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses 123system.l2c.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses 124system.l2c.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses 125system.l2c.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses 126system.l2c.overall_accesses::total 2421748 # number of overall (read+write) accesses 127system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses 128system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses 129system.l2c.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses 130system.l2c.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses 131system.l2c.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses 132system.l2c.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses 133system.l2c.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses 134system.l2c.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses 135system.l2c.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses 136system.l2c.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses 137system.l2c.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses 138system.l2c.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses 139system.l2c.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses 140system.l2c.demand_miss_rate::total 0.074289 # miss rate for demand accesses 141system.l2c.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses 142system.l2c.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses 143system.l2c.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses 144system.l2c.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses 145system.l2c.overall_miss_rate::total 0.074289 # miss rate for overall accesses 146system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 147system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 148system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 149system.l2c.blocked::no_targets 0 # number of cycles access was blocked 150system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 151system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 152system.l2c.fast_writes 0 # number of fast writes performed 153system.l2c.cache_copies 0 # number of cache copies performed 154system.l2c.writebacks::writebacks 98533 # number of writebacks 155system.l2c.writebacks::total 98533 # number of writebacks 156system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate | 49system.cpu.l2cache.replacements 106561 # number of replacements 50system.cpu.l2cache.tagsinuse 64822.143261 # Cycle average of tags in use 51system.cpu.l2cache.total_refs 3456533 # Total number of references to valid blocks. 52system.cpu.l2cache.sampled_refs 170680 # Sample count of references to valid blocks. 53system.cpu.l2cache.avg_refs 20.251541 # Average number of references to valid blocks. 54system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 55system.cpu.l2cache.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor 56system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor 57system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor 58system.cpu.l2cache.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor 59system.cpu.l2cache.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor 60system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy 61system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 62system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 63system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy 64system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy 65system.cpu.l2cache.occ_percent::total 0.989107 # Average percentage of cache occupancy 66system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits 67system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits 68system.cpu.l2cache.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits 69system.cpu.l2cache.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits 70system.cpu.l2cache.ReadReq_hits::total 2062630 # number of ReadReq hits 71system.cpu.l2cache.Writeback_hits::writebacks 1538130 # number of Writeback hits 72system.cpu.l2cache.Writeback_hits::total 1538130 # number of Writeback hits 73system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 74system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 75system.cpu.l2cache.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits 76system.cpu.l2cache.ReadExReq_hits::total 179208 # number of ReadExReq hits 77system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits 78system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits 79system.cpu.l2cache.demand_hits::cpu.inst 777957 # number of demand (read+write) hits 80system.cpu.l2cache.demand_hits::cpu.data 1454603 # number of demand (read+write) hits 81system.cpu.l2cache.demand_hits::total 2241838 # number of demand (read+write) hits 82system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits 83system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits 84system.cpu.l2cache.overall_hits::cpu.inst 777957 # number of overall hits 85system.cpu.l2cache.overall_hits::cpu.data 1454603 # number of overall hits 86system.cpu.l2cache.overall_hits::total 2241838 # number of overall hits 87system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 88system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 89system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses 90system.cpu.l2cache.ReadReq_misses::cpu.data 32184 # number of ReadReq misses 91system.cpu.l2cache.ReadReq_misses::total 45533 # number of ReadReq misses 92system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses 93system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses 94system.cpu.l2cache.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses 95system.cpu.l2cache.ReadExReq_misses::total 134377 # number of ReadExReq misses 96system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 97system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 98system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses 99system.cpu.l2cache.demand_misses::cpu.data 166561 # number of demand (read+write) misses 100system.cpu.l2cache.demand_misses::total 179910 # number of demand (read+write) misses 101system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 102system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 103system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses 104system.cpu.l2cache.overall_misses::cpu.data 166561 # number of overall misses 105system.cpu.l2cache.overall_misses::total 179910 # number of overall misses 106system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) 107system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) 108system.cpu.l2cache.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) 109system.cpu.l2cache.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) 110system.cpu.l2cache.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) 111system.cpu.l2cache.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) 112system.cpu.l2cache.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) 113system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) 114system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) 115system.cpu.l2cache.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) 116system.cpu.l2cache.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) 117system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses 118system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses 119system.cpu.l2cache.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses 120system.cpu.l2cache.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses 121system.cpu.l2cache.demand_accesses::total 2421748 # number of demand (read+write) accesses 122system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses 123system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses 124system.cpu.l2cache.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses 125system.cpu.l2cache.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses 126system.cpu.l2cache.overall_accesses::total 2421748 # number of overall (read+write) accesses 127system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses 128system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses 129system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses 130system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses 131system.cpu.l2cache.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses 132system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses 133system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses 134system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses 135system.cpu.l2cache.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses 136system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses 137system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses 138system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses 139system.cpu.l2cache.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses 140system.cpu.l2cache.demand_miss_rate::total 0.074289 # miss rate for demand accesses 141system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses 142system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses 143system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses 144system.cpu.l2cache.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses 145system.cpu.l2cache.overall_miss_rate::total 0.074289 # miss rate for overall accesses 146system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 147system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 148system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 149system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 150system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 151system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 152system.cpu.l2cache.fast_writes 0 # number of fast writes performed 153system.cpu.l2cache.cache_copies 0 # number of cache copies performed 154system.cpu.l2cache.writebacks::writebacks 98533 # number of writebacks 155system.cpu.l2cache.writebacks::total 98533 # number of writebacks 156system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 157system.iocache.replacements 47570 # number of replacements 158system.iocache.tagsinuse 0.042409 # Cycle average of tags in use 159system.iocache.total_refs 0 # Total number of references to valid blocks. 160system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. 161system.iocache.avg_refs 0 # Average number of references to valid blocks. 162system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. 163system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor 164system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy --- 260 unchanged lines hidden --- | 157system.iocache.replacements 47570 # number of replacements 158system.iocache.tagsinuse 0.042409 # Cycle average of tags in use 159system.iocache.total_refs 0 # Total number of references to valid blocks. 160system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. 161system.iocache.avg_refs 0 # Average number of references to valid blocks. 162system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. 163system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor 164system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy --- 260 unchanged lines hidden --- |