| stats.txt (9055:38f1926fb599) | stats.txt (9079:9a244ebdc3c9) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1304311 # Simulator instruction rate (inst/s) 8host_op_rate 2670670 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33369516688 # Simulator tick rate (ticks/s) 10host_mem_usage 357276 # Number of bytes of host memory used 11host_seconds 153.20 # Real time elapsed on the host 12sim_insts 199813913 # Number of instructions simulated 13sim_ops 409133277 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2786624 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 704 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 972736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 11807616 # Number of bytes read from this memory 19system.physmem.bytes_read::total 15568704 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 972736 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 972736 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 12232896 # Number of bytes written to this memory 23system.physmem.bytes_written::total 12232896 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 43541 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 11 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 15199 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 184494 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 243261 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 191139 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 191139 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 545110 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 200 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 138 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 190283 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2309764 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 3045495 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 190283 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 190283 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 2392956 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 2392956 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 2392956 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 545110 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 200 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 138 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 190283 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2309764 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 5438452 # Total bandwidth to/from this memory (bytes/s) 49system.l2c.replacements 164044 # number of replacements 50system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use 51system.l2c.total_refs 3332458 # Total number of references to valid blocks. 52system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. 53system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. | 7host_inst_rate 1996585 # Simulator instruction rate (inst/s) 8host_op_rate 4088150 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 51080652430 # Simulator tick rate (ticks/s) 10host_mem_usage 357308 # Number of bytes of host memory used 11host_seconds 100.08 # Real time elapsed on the host 12sim_insts 199813912 # Number of instructions simulated 13sim_ops 409133288 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9292800 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9292800 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38512 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 165628 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 217488 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 145200 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 145200 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 482149 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2073572 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2722831 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1817825 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1817825 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) 49system.l2c.replacements 106561 # number of replacements 50system.l2c.tagsinuse 64822.143270 # Cycle average of tags in use 51system.l2c.total_refs 3457342 # Total number of references to valid blocks. 52system.l2c.sampled_refs 170680 # Sample count of references to valid blocks. 53system.l2c.avg_refs 20.256281 # Average number of references to valid blocks. |
| 54system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 54system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 55system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor 56system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor 57system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor 60system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy 61system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy 62system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy 65system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy 66system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits 67system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits 68system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits 70system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits 71system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits 72system.l2c.Writeback_hits::total 1529403 # number of Writeback hits 73system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits 74system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits 75system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits 76system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits 77system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits 78system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits 79system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits 80system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits 81system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits 82system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits 83system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits 84system.l2c.overall_hits::cpu.inst 776101 # number of overall hits 85system.l2c.overall_hits::cpu.data 1435764 # number of overall hits 86system.l2c.overall_hits::total 2221403 # number of overall hits 87system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses 88system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses 89system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses 90system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses 91system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses 92system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses 93system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses 94system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses 95system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses 96system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses 97system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses 98system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses 99system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses 100system.l2c.demand_misses::total 200638 # number of demand (read+write) misses 101system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses 102system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses 103system.l2c.overall_misses::cpu.inst 15200 # number of overall misses 104system.l2c.overall_misses::cpu.data 185411 # number of overall misses 105system.l2c.overall_misses::total 200638 # number of overall misses 106system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses) 107system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses) 108system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses) 109system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses) 110system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses) 111system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses) 112system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses) 113system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) 114system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) 115system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses) 116system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses) 117system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses 118system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses 119system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses 120system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses 121system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses 122system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses 123system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses 124system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses 125system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses 126system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses 127system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses 128system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses 129system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses 130system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses 131system.l2c.ReadReq_miss_rate::total 0.026559 # miss rate for ReadReq accesses 132system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses 133system.l2c.UpgradeReq_miss_rate::total 0.982995 # miss rate for UpgradeReq accesses 134system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses 135system.l2c.ReadExReq_miss_rate::total 0.461240 # miss rate for ReadExReq accesses 136system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses 137system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses 138system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses 139system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses 140system.l2c.demand_miss_rate::total 0.082838 # miss rate for demand accesses 141system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses 142system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses 143system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses 144system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses 145system.l2c.overall_miss_rate::total 0.082838 # miss rate for overall accesses | 55system.l2c.occ_blocks::writebacks 51981.461992 # Average occupied blocks per requestor 56system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor 57system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor 58system.l2c.occ_blocks::cpu.inst 2434.983597 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu.data 10405.560616 # Average occupied blocks per requestor 60system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy 61system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 62system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy 65system.l2c.occ_percent::total 0.989107 # Average percentage of cache occupancy 66system.l2c.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits 67system.l2c.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits 68system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits 69system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits 70system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits 71system.l2c.Writeback_hits::writebacks 1538939 # number of Writeback hits 72system.l2c.Writeback_hits::total 1538939 # number of Writeback hits 73system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 74system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits 75system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits 76system.l2c.ReadExReq_hits::total 179208 # number of ReadExReq hits 77system.l2c.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits 78system.l2c.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits 79system.l2c.demand_hits::cpu.inst 777957 # number of demand (read+write) hits 80system.l2c.demand_hits::cpu.data 1454603 # number of demand (read+write) hits 81system.l2c.demand_hits::total 2241838 # number of demand (read+write) hits 82system.l2c.overall_hits::cpu.dtb.walker 6578 # number of overall hits 83system.l2c.overall_hits::cpu.itb.walker 2700 # number of overall hits 84system.l2c.overall_hits::cpu.inst 777957 # number of overall hits 85system.l2c.overall_hits::cpu.data 1454603 # number of overall hits 86system.l2c.overall_hits::total 2241838 # number of overall hits 87system.l2c.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 88system.l2c.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 89system.l2c.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses 90system.l2c.ReadReq_misses::cpu.data 32184 # number of ReadReq misses 91system.l2c.ReadReq_misses::total 45533 # number of ReadReq misses 92system.l2c.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses 93system.l2c.UpgradeReq_misses::total 1796 # number of UpgradeReq misses 94system.l2c.ReadExReq_misses::cpu.data 134377 # number of ReadExReq misses 95system.l2c.ReadExReq_misses::total 134377 # number of ReadExReq misses 96system.l2c.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 97system.l2c.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 98system.l2c.demand_misses::cpu.inst 13342 # number of demand (read+write) misses 99system.l2c.demand_misses::cpu.data 166561 # number of demand (read+write) misses 100system.l2c.demand_misses::total 179910 # number of demand (read+write) misses 101system.l2c.overall_misses::cpu.dtb.walker 2 # number of overall misses 102system.l2c.overall_misses::cpu.itb.walker 5 # number of overall misses 103system.l2c.overall_misses::cpu.inst 13342 # number of overall misses 104system.l2c.overall_misses::cpu.data 166561 # number of overall misses 105system.l2c.overall_misses::total 179910 # number of overall misses 106system.l2c.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) 107system.l2c.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) 108system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) 109system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) 110system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) 111system.l2c.Writeback_accesses::writebacks 1538939 # number of Writeback accesses(hits+misses) 112system.l2c.Writeback_accesses::total 1538939 # number of Writeback accesses(hits+misses) 113system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) 114system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) 115system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) 116system.l2c.ReadExReq_accesses::total 313585 # number of ReadExReq accesses(hits+misses) 117system.l2c.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses 118system.l2c.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses 119system.l2c.demand_accesses::cpu.inst 791299 # number of demand (read+write) accesses 120system.l2c.demand_accesses::cpu.data 1621164 # number of demand (read+write) accesses 121system.l2c.demand_accesses::total 2421748 # number of demand (read+write) accesses 122system.l2c.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses 123system.l2c.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses 124system.l2c.overall_accesses::cpu.inst 791299 # number of overall (read+write) accesses 125system.l2c.overall_accesses::cpu.data 1621164 # number of overall (read+write) accesses 126system.l2c.overall_accesses::total 2421748 # number of overall (read+write) accesses 127system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses 128system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses 129system.l2c.ReadReq_miss_rate::cpu.inst 0.016861 # miss rate for ReadReq accesses 130system.l2c.ReadReq_miss_rate::cpu.data 0.024613 # miss rate for ReadReq accesses 131system.l2c.ReadReq_miss_rate::total 0.021598 # miss rate for ReadReq accesses 132system.l2c.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses 133system.l2c.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses 134system.l2c.ReadExReq_miss_rate::cpu.data 0.428519 # miss rate for ReadExReq accesses 135system.l2c.ReadExReq_miss_rate::total 0.428519 # miss rate for ReadExReq accesses 136system.l2c.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses 137system.l2c.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses 138system.l2c.demand_miss_rate::cpu.inst 0.016861 # miss rate for demand accesses 139system.l2c.demand_miss_rate::cpu.data 0.102742 # miss rate for demand accesses 140system.l2c.demand_miss_rate::total 0.074289 # miss rate for demand accesses 141system.l2c.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses 142system.l2c.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses 143system.l2c.overall_miss_rate::cpu.inst 0.016861 # miss rate for overall accesses 144system.l2c.overall_miss_rate::cpu.data 0.102742 # miss rate for overall accesses 145system.l2c.overall_miss_rate::total 0.074289 # miss rate for overall accesses |
| 146system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 147system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 148system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 149system.l2c.blocked::no_targets 0 # number of cycles access was blocked 150system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 151system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 152system.l2c.fast_writes 0 # number of fast writes performed 153system.l2c.cache_copies 0 # number of cache copies performed | 146system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 147system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 148system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 149system.l2c.blocked::no_targets 0 # number of cycles access was blocked 150system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 151system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 152system.l2c.fast_writes 0 # number of fast writes performed 153system.l2c.cache_copies 0 # number of cache copies performed |
| 154system.l2c.writebacks::writebacks 144472 # number of writebacks 155system.l2c.writebacks::total 144472 # number of writebacks | 154system.l2c.writebacks::writebacks 98533 # number of writebacks 155system.l2c.writebacks::total 98533 # number of writebacks |
| 156system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 157system.iocache.replacements 47570 # number of replacements 158system.iocache.tagsinuse 0.042409 # Cycle average of tags in use 159system.iocache.total_refs 0 # Total number of references to valid blocks. 160system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. 161system.iocache.avg_refs 0 # Average number of references to valid blocks. 162system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. 163system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor --- 44 unchanged lines hidden (view full) --- 208system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 209system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 210system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 211system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 212system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 213system.cpu.numCycles 10224086531 # number of cpu cycles simulated 214system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 215system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 156system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 157system.iocache.replacements 47570 # number of replacements 158system.iocache.tagsinuse 0.042409 # Cycle average of tags in use 159system.iocache.total_refs 0 # Total number of references to valid blocks. 160system.iocache.sampled_refs 47586 # Sample count of references to valid blocks. 161system.iocache.avg_refs 0 # Average number of references to valid blocks. 162system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit. 163system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor --- 44 unchanged lines hidden (view full) --- 208system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 209system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 210system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 211system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 212system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 213system.cpu.numCycles 10224086531 # number of cpu cycles simulated 214system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 215system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 216system.cpu.committedInsts 199813913 # Number of instructions committed 217system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed 218system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses | 216system.cpu.committedInsts 199813912 # Number of instructions committed 217system.cpu.committedOps 409133288 # Number of ops (including micro ops) committed 218system.cpu.num_int_alu_accesses 374297254 # Number of integer alu accesses |
| 219system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 220system.cpu.num_func_calls 0 # number of times a function call or return occured | 219system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 220system.cpu.num_func_calls 0 # number of times a function call or return occured |
| 221system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls 222system.cpu.num_int_insts 374297244 # number of integer instructions | 221system.cpu.num_conditional_control_insts 39954972 # number of instructions that are conditional controls 222system.cpu.num_int_insts 374297254 # number of integer instructions |
| 223system.cpu.num_fp_insts 0 # number of float instructions | 223system.cpu.num_fp_insts 0 # number of float instructions |
| 224system.cpu.num_int_register_reads 1159028861 # number of times the integer registers were read 225system.cpu.num_int_register_writes 636431619 # number of times the integer registers were written | 224system.cpu.num_int_register_reads 1159028950 # number of times the integer registers were read 225system.cpu.num_int_register_writes 636431660 # number of times the integer registers were written |
| 226system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 227system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 226system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 227system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 228system.cpu.num_mem_refs 35626519 # number of memory refs 229system.cpu.num_load_insts 27217784 # Number of load instructions | 228system.cpu.num_mem_refs 35626517 # number of memory refs 229system.cpu.num_load_insts 27217782 # Number of load instructions |
| 230system.cpu.num_store_insts 8408735 # Number of store instructions | 230system.cpu.num_store_insts 8408735 # Number of store instructions |
| 231system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles 232system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles | 231system.cpu.num_idle_cycles 9770605328.086651 # Number of idle cycles 232system.cpu.num_busy_cycles 453481202.913350 # Number of busy cycles |
| 233system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles 234system.cpu.idle_fraction 0.955646 # Percentage of idle cycles 235system.cpu.kern.inst.arm 0 # number of arm instructions executed 236system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 233system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles 234system.cpu.idle_fraction 0.955646 # Percentage of idle cycles 235system.cpu.kern.inst.arm 0 # number of arm instructions executed 236system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 237system.cpu.icache.replacements 790795 # number of replacements | 237system.cpu.icache.replacements 790793 # number of replacements |
| 238system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use 239system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. | 238system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use 239system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks. |
| 240system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks. 241system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks. | 240system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. 241system.cpu.icache.avg_refs 307.549904 # Average number of references to valid blocks. |
| 242system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. 243system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor 244system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy 245system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy 246system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits 247system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits 248system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits 249system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits 250system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits 251system.cpu.icache.overall_hits::total 243365777 # number of overall hits | 242system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit. 243system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor 244system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy 245system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy 246system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits 247system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits 248system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits 249system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits 250system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits 251system.cpu.icache.overall_hits::total 243365777 # number of overall hits |
| 252system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses 253system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses 254system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses 255system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses 256system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses 257system.cpu.icache.overall_misses::total 791314 # number of overall misses 258system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) 259system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) 260system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses 261system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses 262system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses 263system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses | 252system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses 253system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses 254system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses 255system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses 256system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses 257system.cpu.icache.overall_misses::total 791312 # number of overall misses 258system.cpu.icache.ReadReq_accesses::cpu.inst 244157089 # number of ReadReq accesses(hits+misses) 259system.cpu.icache.ReadReq_accesses::total 244157089 # number of ReadReq accesses(hits+misses) 260system.cpu.icache.demand_accesses::cpu.inst 244157089 # number of demand (read+write) accesses 261system.cpu.icache.demand_accesses::total 244157089 # number of demand (read+write) accesses 262system.cpu.icache.overall_accesses::cpu.inst 244157089 # number of overall (read+write) accesses 263system.cpu.icache.overall_accesses::total 244157089 # number of overall (read+write) accesses |
| 264system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses 265system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses 266system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses 267system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses 268system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses 269system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses 270system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 271system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 272system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 273system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 274system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 275system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 276system.cpu.icache.fast_writes 0 # number of fast writes performed 277system.cpu.icache.cache_copies 0 # number of cache copies performed 278system.cpu.icache.writebacks::writebacks 809 # number of writebacks 279system.cpu.icache.writebacks::total 809 # number of writebacks 280system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 264system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses 265system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses 266system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses 267system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses 268system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses 269system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses 270system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 271system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 272system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 273system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 274system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 275system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 276system.cpu.icache.fast_writes 0 # number of fast writes performed 277system.cpu.icache.cache_copies 0 # number of cache copies performed 278system.cpu.icache.writebacks::writebacks 809 # number of writebacks 279system.cpu.icache.writebacks::total 809 # number of writebacks 280system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 281system.cpu.itb_walker_cache.replacements 3435 # number of replacements 282system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use 283system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. 284system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks. 285system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks. 286system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit. 287system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor 288system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy 289system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy 290system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits 291system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits | 281system.cpu.itb_walker_cache.replacements 3335 # number of replacements 282system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use 283system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. 284system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. 285system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. 286system.cpu.itb_walker_cache.warmup_cycle 5102048603500 # Cycle when the warmup percentage was hit. 287system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026444 # Average occupied blocks per requestor 288system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy 289system.cpu.itb_walker_cache.occ_percent::total 0.189153 # Average percentage of cache occupancy 290system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits 291system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits |
| 292system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 293system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits | 292system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 293system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
| 294system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits 295system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits 296system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits 297system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits 298system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses 299system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses 300system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses 301system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses 302system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses 303system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses | 294system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits 295system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits 296system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits 297system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits 298system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses 299system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses 300system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses 301system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses 302system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses 303system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses |
| 304system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) 305system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) 306system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 307system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 308system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses 309system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 310system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses 311system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses | 304system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) 305system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) 306system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 307system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 308system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses 309system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 310system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses 311system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses |
| 312system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses 313system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349939 # miss rate for ReadReq accesses 314system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses 315system.cpu.itb_walker_cache.demand_miss_rate::total 0.349881 # miss rate for demand accesses 316system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses 317system.cpu.itb_walker_cache.overall_miss_rate::total 0.349881 # miss rate for overall accesses | 312system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses 313system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses 314system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses 315system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses 316system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses 317system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses |
| 318system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 321system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 322system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 325system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | 318system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 321system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 322system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 325system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
| 326system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks 327system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks | 326system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks 327system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks |
| 328system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 328system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 329system.cpu.dtb_walker_cache.replacements 7755 # number of replacements 330system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use 331system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. 332system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks. 333system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks. 334system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit. 335system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor 336system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy 337system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy 338system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits 339system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits 340system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits 341system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits 342system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits 343system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits 344system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses 345system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses 346system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses 347system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses 348system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses 349system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses | 329system.cpu.dtb_walker_cache.replacements 7598 # number of replacements 330system.cpu.dtb_walker_cache.tagsinuse 5.013733 # Cycle average of tags in use 331system.cpu.dtb_walker_cache.total_refs 13014 # Total number of references to valid blocks. 332system.cpu.dtb_walker_cache.sampled_refs 7612 # Sample count of references to valid blocks. 333system.cpu.dtb_walker_cache.avg_refs 1.709669 # Average number of references to valid blocks. 334system.cpu.dtb_walker_cache.warmup_cycle 5101231664000 # Cycle when the warmup percentage was hit. 335system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013733 # Average occupied blocks per requestor 336system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313358 # Average percentage of cache occupancy 337system.cpu.dtb_walker_cache.occ_percent::total 0.313358 # Average percentage of cache occupancy 338system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13016 # number of ReadReq hits 339system.cpu.dtb_walker_cache.ReadReq_hits::total 13016 # number of ReadReq hits 340system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13016 # number of demand (read+write) hits 341system.cpu.dtb_walker_cache.demand_hits::total 13016 # number of demand (read+write) hits 342system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13016 # number of overall hits 343system.cpu.dtb_walker_cache.overall_hits::total 13016 # number of overall hits 344system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8792 # number of ReadReq misses 345system.cpu.dtb_walker_cache.ReadReq_misses::total 8792 # number of ReadReq misses 346system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8792 # number of demand (read+write) misses 347system.cpu.dtb_walker_cache.demand_misses::total 8792 # number of demand (read+write) misses 348system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8792 # number of overall misses 349system.cpu.dtb_walker_cache.overall_misses::total 8792 # number of overall misses |
| 350system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) 351system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 352system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses 353system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 354system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses 355system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses | 350system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) 351system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 352system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses 353system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 354system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses 355system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses |
| 356system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses 357system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409620 # miss rate for ReadReq accesses 358system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses 359system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409620 # miss rate for demand accesses 360system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses 361system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409620 # miss rate for overall accesses | 356system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403155 # miss rate for ReadReq accesses 357system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403155 # miss rate for ReadReq accesses 358system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403155 # miss rate for demand accesses 359system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403155 # miss rate for demand accesses 360system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403155 # miss rate for overall accesses 361system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403155 # miss rate for overall accesses |
| 362system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 369system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | 362system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 369system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
| 370system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks 371system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks | 370system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks 371system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks |
| 372system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 372system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 373system.cpu.dcache.replacements 1621277 # number of replacements 374system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use 375system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. 376system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks. 377system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks. | 373system.cpu.dcache.replacements 1621273 # number of replacements 374system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use 375system.cpu.dcache.total_refs 20142222 # Total number of references to valid blocks. 376system.cpu.dcache.sampled_refs 1621785 # Sample count of references to valid blocks. 377system.cpu.dcache.avg_refs 12.419786 # Average number of references to valid blocks. |
| 378system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. | 378system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. |
| 379system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor | 379system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor |
| 380system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 381system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy 382system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits 383system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits | 380system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 381system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy 382system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits 383system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits |
| 384system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits 385system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits 386system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits 387system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits 388system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits 389system.cpu.dcache.overall_hits::total 20139962 # number of overall hits 390system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses 391system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses 392system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses 393system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses | 384system.cpu.dcache.WriteReq_hits::cpu.data 8082936 # number of WriteReq hits 385system.cpu.dcache.WriteReq_hits::total 8082936 # number of WriteReq hits 386system.cpu.dcache.demand_hits::cpu.data 20139960 # number of demand (read+write) hits 387system.cpu.dcache.demand_hits::total 20139960 # number of demand (read+write) hits 388system.cpu.dcache.overall_hits::cpu.data 20139960 # number of overall hits 389system.cpu.dcache.overall_hits::total 20139960 # number of overall hits 390system.cpu.dcache.ReadReq_misses::cpu.data 1308205 # number of ReadReq misses 391system.cpu.dcache.ReadReq_misses::total 1308205 # number of ReadReq misses 392system.cpu.dcache.WriteReq_misses::cpu.data 315852 # number of WriteReq misses 393system.cpu.dcache.WriteReq_misses::total 315852 # number of WriteReq misses |
| 394system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses 395system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses 396system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses 397system.cpu.dcache.overall_misses::total 1624057 # number of overall misses | 394system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses 395system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses 396system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses 397system.cpu.dcache.overall_misses::total 1624057 # number of overall misses |
| 398system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses) 399system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) | 398system.cpu.dcache.ReadReq_accesses::cpu.data 13365229 # number of ReadReq accesses(hits+misses) 399system.cpu.dcache.ReadReq_accesses::total 13365229 # number of ReadReq accesses(hits+misses) |
| 400system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) 401system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) | 400system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) 401system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) |
| 402system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses 403system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses 404system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses 405system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses | 402system.cpu.dcache.demand_accesses::cpu.data 21764017 # number of demand (read+write) accesses 403system.cpu.dcache.demand_accesses::total 21764017 # number of demand (read+write) accesses 404system.cpu.dcache.overall_accesses::cpu.data 21764017 # number of overall (read+write) accesses 405system.cpu.dcache.overall_accesses::total 21764017 # number of overall (read+write) accesses |
| 406system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses 407system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses 408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses 409system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses 410system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses 411system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses 412system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses 413system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 418system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 420system.cpu.dcache.fast_writes 0 # number of fast writes performed 421system.cpu.dcache.cache_copies 0 # number of cache copies performed | 406system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses 407system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses 408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses 409system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses 410system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses 411system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses 412system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses 413system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 418system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 420system.cpu.dcache.fast_writes 0 # number of fast writes performed 421system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 422system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks 423system.cpu.dcache.writebacks::total 1525559 # number of writebacks | 422system.cpu.dcache.writebacks::writebacks 1534981 # number of writebacks 423system.cpu.dcache.writebacks::total 1534981 # number of writebacks |
| 424system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 425 426---------- End Simulation Statistics ---------- | 424system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 425 426---------- End Simulation Statistics ---------- |