| stats.txt (9039:9a22621c741c) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 704165 # Simulator instruction rate (inst/s) 8host_op_rate 1441828 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18015373871 # Simulator tick rate (ticks/s) 10host_mem_usage 378116 # Number of bytes of host memory used 11host_seconds 283.76 # Real time elapsed on the host | 7host_inst_rate 1304311 # Simulator instruction rate (inst/s) 8host_op_rate 2670670 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33369516688 # Simulator tick rate (ticks/s) 10host_mem_usage 357276 # Number of bytes of host memory used 11host_seconds 153.20 # Real time elapsed on the host |
| 12sim_insts 199813913 # Number of instructions simulated 13sim_ops 409133277 # Number of ops (including micro ops) simulated | 12sim_insts 199813913 # Number of instructions simulated 13sim_ops 409133277 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 15568704 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 12232896 # Number of bytes written to this memory 17system.physmem.num_reads 243261 # Number of read requests responded to by this memory 18system.physmem.num_writes 191139 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 3045495 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 190283 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 2392956 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 5438452 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::pc.south_bridge.ide 2786624 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 1024 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 704 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 972736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 11807616 # Number of bytes read from this memory 19system.physmem.bytes_read::total 15568704 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 972736 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 972736 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 12232896 # Number of bytes written to this memory 23system.physmem.bytes_written::total 12232896 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 43541 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 16 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 11 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 15199 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 184494 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 243261 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 191139 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 191139 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 545110 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 200 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 138 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 190283 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2309764 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 3045495 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 190283 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 190283 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 2392956 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 2392956 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 2392956 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 545110 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 200 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 138 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 190283 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2309764 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 5438452 # Total bandwidth to/from this memory (bytes/s) |
| 24system.l2c.replacements 164044 # number of replacements 25system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use 26system.l2c.total_refs 3332458 # Total number of references to valid blocks. 27system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. 28system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. 29system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 30system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor 31system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor --- 66 unchanged lines hidden (view full) --- 98system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses 99system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses 100system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses 101system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses 102system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses 103system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses 104system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses 105system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses | 49system.l2c.replacements 164044 # number of replacements 50system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use 51system.l2c.total_refs 3332458 # Total number of references to valid blocks. 52system.l2c.sampled_refs 196390 # Sample count of references to valid blocks. 53system.l2c.avg_refs 16.968573 # Average number of references to valid blocks. 54system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 55system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor 56system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor --- 66 unchanged lines hidden (view full) --- 123system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses 124system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses 125system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses 126system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses 127system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses 128system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses 129system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses 130system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses |
| 131system.l2c.ReadReq_miss_rate::total 0.026559 # miss rate for ReadReq accesses |
|
| 106system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses | 132system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses |
| 133system.l2c.UpgradeReq_miss_rate::total 0.982995 # miss rate for UpgradeReq accesses |
|
| 107system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses | 134system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses |
| 135system.l2c.ReadExReq_miss_rate::total 0.461240 # miss rate for ReadExReq accesses |
|
| 108system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses 109system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses 110system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses 111system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses | 136system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses 137system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses 138system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses 139system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses |
| 140system.l2c.demand_miss_rate::total 0.082838 # miss rate for demand accesses |
|
| 112system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses 113system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses 114system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses 115system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses | 141system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses 142system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses 143system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses 144system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses |
| 145system.l2c.overall_miss_rate::total 0.082838 # miss rate for overall accesses |
|
| 116system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 119system.l2c.blocked::no_targets 0 # number of cycles access was blocked 120system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 121system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 122system.l2c.fast_writes 0 # number of fast writes performed 123system.l2c.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 145system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) 146system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 147system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 148system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses 149system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses 150system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses 151system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses 152system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses | 146system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 147system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 148system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 149system.l2c.blocked::no_targets 0 # number of cycles access was blocked 150system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 151system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 152system.l2c.fast_writes 0 # number of fast writes performed 153system.l2c.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 175system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses) 176system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 177system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 178system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses 179system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses 180system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses 181system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses 182system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses |
| 183system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
|
| 153system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses | 184system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses |
| 185system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses |
|
| 154system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses | 186system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses |
| 187system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses |
|
| 155system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses | 188system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses |
| 189system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses |
|
| 156system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 157system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 158system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 159system.iocache.blocked::no_targets 0 # number of cycles access was blocked 160system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 161system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 162system.iocache.fast_writes 0 # number of fast writes performed 163system.iocache.cache_copies 0 # number of cache copies performed --- 59 unchanged lines hidden (view full) --- 223system.cpu.icache.overall_misses::total 791314 # number of overall misses 224system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) 225system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) 226system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses 227system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses 228system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses 229system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses 230system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses | 190system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 191system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 192system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 193system.iocache.blocked::no_targets 0 # number of cycles access was blocked 194system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 195system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 196system.iocache.fast_writes 0 # number of fast writes performed 197system.iocache.cache_copies 0 # number of cache copies performed --- 59 unchanged lines hidden (view full) --- 257system.cpu.icache.overall_misses::total 791314 # number of overall misses 258system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) 259system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) 260system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses 261system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses 262system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses 263system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses 264system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses |
| 265system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses |
|
| 231system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses | 266system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses |
| 267system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses |
|
| 232system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses | 268system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses |
| 269system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses |
|
| 233system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 234system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 235system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 236system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 237system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 238system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 239system.cpu.icache.fast_writes 0 # number of fast writes performed 240system.cpu.icache.cache_copies 0 # number of cache copies performed --- 27 unchanged lines hidden (view full) --- 268system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) 269system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 270system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 271system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses 272system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 273system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses 274system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 275system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses | 270system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 271system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 272system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 273system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 274system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 275system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 276system.cpu.icache.fast_writes 0 # number of fast writes performed 277system.cpu.icache.cache_copies 0 # number of cache copies performed --- 27 unchanged lines hidden (view full) --- 305system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) 306system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 307system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 308system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses 309system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 310system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses 311system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 312system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses |
| 313system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.349939 # miss rate for ReadReq accesses |
|
| 276system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses | 314system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses |
| 315system.cpu.itb_walker_cache.demand_miss_rate::total 0.349881 # miss rate for demand accesses |
|
| 277system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses | 316system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses |
| 317system.cpu.itb_walker_cache.overall_miss_rate::total 0.349881 # miss rate for overall accesses |
|
| 278system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 279system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 280system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 281system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 282system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 283system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 284system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 285system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed --- 23 unchanged lines hidden (view full) --- 309system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses 310system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) 311system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 312system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses 313system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 314system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses 315system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses 316system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses | 318system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 319system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 320system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 321system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 322system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 323system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 324system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 325system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed --- 23 unchanged lines hidden (view full) --- 349system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses 350system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) 351system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 352system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses 353system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 354system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses 355system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses 356system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses |
| 357system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409620 # miss rate for ReadReq accesses |
|
| 317system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses | 358system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses |
| 359system.cpu.dtb_walker_cache.demand_miss_rate::total 0.409620 # miss rate for demand accesses |
|
| 318system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses | 360system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses |
| 361system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409620 # miss rate for overall accesses |
|
| 319system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 320system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 321system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 322system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 323system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 324system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 325system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 326system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed --- 29 unchanged lines hidden (view full) --- 356system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) 357system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) 358system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) 359system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses 360system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses 361system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses 362system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses 363system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses | 362system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 369system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed --- 29 unchanged lines hidden (view full) --- 399system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses) 400system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses) 401system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses) 402system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses 403system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses 404system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses 405system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses 406system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses |
| 407system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses |
|
| 364system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses | 408system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses |
| 409system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses |
|
| 365system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses | 410system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses |
| 411system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses |
|
| 366system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses | 412system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses |
| 413system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses |
|
| 367system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 368system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 369system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 370system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 371system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 372system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 373system.cpu.dcache.fast_writes 0 # number of fast writes performed 374system.cpu.dcache.cache_copies 0 # number of cache copies performed 375system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks 376system.cpu.dcache.writebacks::total 1525559 # number of writebacks 377system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 378 379---------- End Simulation Statistics ---------- | 414system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 415system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 416system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 417system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 418system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 419system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 420system.cpu.dcache.fast_writes 0 # number of fast writes performed 421system.cpu.dcache.cache_copies 0 # number of cache copies performed 422system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks 423system.cpu.dcache.writebacks::total 1525559 # number of writebacks 424system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 425 426---------- End Simulation Statistics ---------- |