| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1772716 # Simulator instruction rate (inst/s) 8host_op_rate 3629762 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45353186641 # Simulator tick rate (ticks/s) 10host_mem_usage 350348 # Number of bytes of host memory used 11host_seconds 112.72 # Real time elapsed on the host | 7host_inst_rate 720353 # Simulator instruction rate (inst/s) 8host_op_rate 1474974 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 18429520570 # Simulator tick rate (ticks/s) 10host_mem_usage 355156 # Number of bytes of host memory used 11host_seconds 277.38 # Real time elapsed on the host |
| 12sim_insts 199813913 # Number of instructions simulated 13sim_ops 409133277 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 15568704 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 12232896 # Number of bytes written to this memory 17system.physmem.num_reads 243261 # Number of read requests responded to by this memory 18system.physmem.num_writes 191139 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 92 unchanged lines hidden (view full) --- 112system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses 113system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses 114system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses 115system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses 116system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 119system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 199813913 # Number of instructions simulated 13sim_ops 409133277 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 15568704 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 12232896 # Number of bytes written to this memory 17system.physmem.num_reads 243261 # Number of read requests responded to by this memory 18system.physmem.num_writes 191139 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 92 unchanged lines hidden (view full) --- 112system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses 113system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses 114system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses 115system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses 116system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 117system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 118system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 119system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 120system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 121system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 120system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 121system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 122system.l2c.fast_writes 0 # number of fast writes performed 123system.l2c.cache_copies 0 # number of cache copies performed 124system.l2c.writebacks::writebacks 144472 # number of writebacks 125system.l2c.writebacks::total 144472 # number of writebacks 126system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 127system.iocache.replacements 47570 # number of replacements 128system.iocache.tagsinuse 0.042409 # Cycle average of tags in use 129system.iocache.total_refs 0 # Total number of references to valid blocks. --- 22 unchanged lines hidden (view full) --- 152system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 153system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 154system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 155system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 156system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 157system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 158system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 159system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 122system.l2c.fast_writes 0 # number of fast writes performed 123system.l2c.cache_copies 0 # number of cache copies performed 124system.l2c.writebacks::writebacks 144472 # number of writebacks 125system.l2c.writebacks::total 144472 # number of writebacks 126system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 127system.iocache.replacements 47570 # number of replacements 128system.iocache.tagsinuse 0.042409 # Cycle average of tags in use 129system.iocache.total_refs 0 # Total number of references to valid blocks. --- 22 unchanged lines hidden (view full) --- 152system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 153system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 154system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 155system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 156system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 157system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 158system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 159system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 160system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 161system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 160system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 161system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 162system.iocache.fast_writes 0 # number of fast writes performed 163system.iocache.cache_copies 0 # number of cache copies performed 164system.iocache.writebacks::writebacks 46667 # number of writebacks 165system.iocache.writebacks::total 46667 # number of writebacks 166system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 167system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 168system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 169system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). --- 59 unchanged lines hidden (view full) --- 229system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses 230system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses 231system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses 232system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses 233system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 234system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 235system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 236system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 162system.iocache.fast_writes 0 # number of fast writes performed 163system.iocache.cache_copies 0 # number of cache copies performed 164system.iocache.writebacks::writebacks 46667 # number of writebacks 165system.iocache.writebacks::total 46667 # number of writebacks 166system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 167system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 168system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 169system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). --- 59 unchanged lines hidden (view full) --- 229system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses 230system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses 231system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses 232system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses 233system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 234system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 235system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 236system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 237system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 238system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 237system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 238system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 239system.cpu.icache.fast_writes 0 # number of fast writes performed 240system.cpu.icache.cache_copies 0 # number of cache copies performed 241system.cpu.icache.writebacks::writebacks 809 # number of writebacks 242system.cpu.icache.writebacks::total 809 # number of writebacks 243system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 244system.cpu.itb_walker_cache.replacements 3435 # number of replacements 245system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use 246system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. --- 27 unchanged lines hidden (view full) --- 274system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 275system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses 276system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses 277system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses 278system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 279system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 280system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 281system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked | 239system.cpu.icache.fast_writes 0 # number of fast writes performed 240system.cpu.icache.cache_copies 0 # number of cache copies performed 241system.cpu.icache.writebacks::writebacks 809 # number of writebacks 242system.cpu.icache.writebacks::total 809 # number of writebacks 243system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 244system.cpu.itb_walker_cache.replacements 3435 # number of replacements 245system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use 246system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks. --- 27 unchanged lines hidden (view full) --- 274system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 275system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses 276system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses 277system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses 278system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 279system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 280system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 281system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked |
| 282system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 283system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 282system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 283system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 284system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 285system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 286system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks 287system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks 288system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 289system.cpu.dtb_walker_cache.replacements 7755 # number of replacements 290system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use 291system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. --- 23 unchanged lines hidden (view full) --- 315system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses 316system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses 317system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses 318system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses 319system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 320system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 321system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 322system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked | 284system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 285system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 286system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks 287system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks 288system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 289system.cpu.dtb_walker_cache.replacements 7755 # number of replacements 290system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use 291system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks. --- 23 unchanged lines hidden (view full) --- 315system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses 316system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses 317system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses 318system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses 319system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 320system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 321system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 322system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked |
| 323system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 324system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 323system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 324system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 325system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 326system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 327system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks 328system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks 329system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 330system.cpu.dcache.replacements 1621277 # number of replacements 331system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use 332system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. --- 30 unchanged lines hidden (view full) --- 363system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses 364system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses 365system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses 366system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses 367system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 368system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 369system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 370system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 325system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 326system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 327system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks 328system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks 329system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 330system.cpu.dcache.replacements 1621277 # number of replacements 331system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use 332system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks. --- 30 unchanged lines hidden (view full) --- 363system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses 364system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses 365system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses 366system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses 367system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 368system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 369system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 370system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 371system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 372system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 371system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 372system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 373system.cpu.dcache.fast_writes 0 # number of fast writes performed 374system.cpu.dcache.cache_copies 0 # number of cache copies performed 375system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks 376system.cpu.dcache.writebacks::total 1525559 # number of writebacks 377system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 378 379---------- End Simulation Statistics ---------- | 373system.cpu.dcache.fast_writes 0 # number of fast writes performed 374system.cpu.dcache.cache_copies 0 # number of cache copies performed 375system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks 376system.cpu.dcache.writebacks::total 1525559 # number of writebacks 377system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 378 379---------- End Simulation Statistics ---------- |