| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112152 # Number of seconds simulated 4sim_ticks 5112151729000 # Number of ticks simulated 5final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112152 # Number of seconds simulated 4sim_ticks 5112151729000 # Number of ticks simulated 5final_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1266983 # Simulator instruction rate (inst/s) 8host_op_rate 2593792 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32374197845 # Simulator tick rate (ticks/s) 10host_mem_usage 659352 # Number of bytes of host memory used 11host_seconds 157.91 # Real time elapsed on the host | 7host_inst_rate 1369712 # Simulator instruction rate (inst/s) 8host_op_rate 2804100 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34999130987 # Simulator tick rate (ticks/s) 10host_mem_usage 614748 # Number of bytes of host memory used 11host_seconds 146.07 # Real time elapsed on the host |
| 12sim_insts 200067055 # Number of instructions simulated 13sim_ops 409581065 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 846912 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10615104 # Number of bytes read from this memory --- 149 unchanged lines hidden (view full) --- 169system.cpu.dcache.overall_miss_rate::cpu.data 0.074512 # miss rate for overall accesses 170system.cpu.dcache.overall_miss_rate::total 0.074512 # miss rate for overall accesses 171system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 174system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 175system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 176system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 200067055 # Number of instructions simulated 13sim_ops 409581065 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 846912 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10615104 # Number of bytes read from this memory --- 149 unchanged lines hidden (view full) --- 169system.cpu.dcache.overall_miss_rate::cpu.data 0.074512 # miss rate for overall accesses 170system.cpu.dcache.overall_miss_rate::total 0.074512 # miss rate for overall accesses 171system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 174system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 175system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 176system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 177system.cpu.dcache.fast_writes 0 # number of fast writes performed 178system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 179system.cpu.dcache.writebacks::writebacks 1535790 # number of writebacks 180system.cpu.dcache.writebacks::total 1535790 # number of writebacks | 177system.cpu.dcache.writebacks::writebacks 1535790 # number of writebacks 178system.cpu.dcache.writebacks::total 1535790 # number of writebacks |
| 181system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 182system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements 183system.cpu.dtb_walker_cache.tags.tagsinuse 5.014001 # Cycle average of tags in use 184system.cpu.dtb_walker_cache.tags.total_refs 12936 # Total number of references to valid blocks. 185system.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks. 186system.cpu.dtb_walker_cache.tags.avg_refs 1.666366 # Average number of references to valid blocks. 187system.cpu.dtb_walker_cache.tags.warmup_cycle 5100450626500 # Cycle when the warmup percentage was hit. 188system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014001 # Average occupied blocks per requestor 189system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy --- 30 unchanged lines hidden (view full) --- 220system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409108 # miss rate for overall accesses 221system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409108 # miss rate for overall accesses 222system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 223system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 224system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 225system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 226system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 227system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 179system.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements 180system.cpu.dtb_walker_cache.tags.tagsinuse 5.014001 # Cycle average of tags in use 181system.cpu.dtb_walker_cache.tags.total_refs 12936 # Total number of references to valid blocks. 182system.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks. 183system.cpu.dtb_walker_cache.tags.avg_refs 1.666366 # Average number of references to valid blocks. 184system.cpu.dtb_walker_cache.tags.warmup_cycle 5100450626500 # Cycle when the warmup percentage was hit. 185system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014001 # Average occupied blocks per requestor 186system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy --- 30 unchanged lines hidden (view full) --- 217system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409108 # miss rate for overall accesses 218system.cpu.dtb_walker_cache.overall_miss_rate::total 0.409108 # miss rate for overall accesses 219system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 220system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 221system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 222system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 223system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 224system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 228system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 229system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed | |
| 230system.cpu.dtb_walker_cache.writebacks::writebacks 2897 # number of writebacks 231system.cpu.dtb_walker_cache.writebacks::total 2897 # number of writebacks | 225system.cpu.dtb_walker_cache.writebacks::writebacks 2897 # number of writebacks 226system.cpu.dtb_walker_cache.writebacks::total 2897 # number of writebacks |
| 232system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 233system.cpu.icache.tags.replacements 792340 # number of replacements 234system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use 235system.cpu.icache.tags.total_refs 243675443 # Total number of references to valid blocks. 236system.cpu.icache.tags.sampled_refs 792852 # Sample count of references to valid blocks. 237system.cpu.icache.tags.avg_refs 307.340390 # Average number of references to valid blocks. 238system.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit. 239system.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor 240system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy --- 31 unchanged lines hidden (view full) --- 272system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses 273system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses 274system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 275system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 276system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 277system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 278system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 279system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 227system.cpu.icache.tags.replacements 792340 # number of replacements 228system.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use 229system.cpu.icache.tags.total_refs 243675443 # Total number of references to valid blocks. 230system.cpu.icache.tags.sampled_refs 792852 # Sample count of references to valid blocks. 231system.cpu.icache.tags.avg_refs 307.340390 # Average number of references to valid blocks. 232system.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit. 233system.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor 234system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy --- 31 unchanged lines hidden (view full) --- 266system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses 267system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses 268system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 269system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 270system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 271system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 272system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 273system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 280system.cpu.icache.fast_writes 0 # number of fast writes performed 281system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 282system.cpu.icache.writebacks::writebacks 792340 # number of writebacks 283system.cpu.icache.writebacks::total 792340 # number of writebacks | 274system.cpu.icache.writebacks::writebacks 792340 # number of writebacks 275system.cpu.icache.writebacks::total 792340 # number of writebacks |
| 284system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 285system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements 286system.cpu.itb_walker_cache.tags.tagsinuse 3.026555 # Cycle average of tags in use 287system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks. 288system.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks. 289system.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks. 290system.cpu.itb_walker_cache.tags.warmup_cycle 5102137159500 # Cycle when the warmup percentage was hit. 291system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026555 # Average occupied blocks per requestor 292system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189160 # Average percentage of cache occupancy --- 34 unchanged lines hidden (view full) --- 327system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.364507 # miss rate for overall accesses 328system.cpu.itb_walker_cache.overall_miss_rate::total 0.364507 # miss rate for overall accesses 329system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 330system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 331system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 332system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 333system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 334system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 276system.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements 277system.cpu.itb_walker_cache.tags.tagsinuse 3.026555 # Cycle average of tags in use 278system.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks. 279system.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks. 280system.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks. 281system.cpu.itb_walker_cache.tags.warmup_cycle 5102137159500 # Cycle when the warmup percentage was hit. 282system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026555 # Average occupied blocks per requestor 283system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189160 # Average percentage of cache occupancy --- 34 unchanged lines hidden (view full) --- 318system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.364507 # miss rate for overall accesses 319system.cpu.itb_walker_cache.overall_miss_rate::total 0.364507 # miss rate for overall accesses 320system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 321system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 322system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 323system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 324system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 325system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 335system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 336system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed | |
| 337system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks 338system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks | 326system.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks 327system.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks |
| 339system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 340system.cpu.l2cache.tags.replacements 106202 # number of replacements 341system.cpu.l2cache.tags.tagsinuse 64823.935074 # Cycle average of tags in use 342system.cpu.l2cache.tags.total_refs 4340729 # Total number of references to valid blocks. 343system.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks. 344system.cpu.l2cache.tags.avg_refs 25.509391 # Average number of references to valid blocks. 345system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 346system.cpu.l2cache.tags.occ_blocks::writebacks 51928.967732 # Average occupied blocks per requestor 347system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor --- 104 unchanged lines hidden (view full) --- 452system.cpu.l2cache.overall_miss_rate::cpu.data 0.102865 # miss rate for overall accesses 453system.cpu.l2cache.overall_miss_rate::total 0.074281 # miss rate for overall accesses 454system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 455system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 456system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 457system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 458system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 459system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 328system.cpu.l2cache.tags.replacements 106202 # number of replacements 329system.cpu.l2cache.tags.tagsinuse 64823.935074 # Cycle average of tags in use 330system.cpu.l2cache.tags.total_refs 4340729 # Total number of references to valid blocks. 331system.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks. 332system.cpu.l2cache.tags.avg_refs 25.509391 # Average number of references to valid blocks. 333system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 334system.cpu.l2cache.tags.occ_blocks::writebacks 51928.967732 # Average occupied blocks per requestor 335system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor --- 104 unchanged lines hidden (view full) --- 440system.cpu.l2cache.overall_miss_rate::cpu.data 0.102865 # miss rate for overall accesses 441system.cpu.l2cache.overall_miss_rate::total 0.074281 # miss rate for overall accesses 442system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 443system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 444system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 445system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 446system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 447system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 460system.cpu.l2cache.fast_writes 0 # number of fast writes performed 461system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 462system.cpu.l2cache.writebacks::writebacks 98175 # number of writebacks 463system.cpu.l2cache.writebacks::total 98175 # number of writebacks | 448system.cpu.l2cache.writebacks::writebacks 98175 # number of writebacks 449system.cpu.l2cache.writebacks::total 98175 # number of writebacks |
| 464system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 465system.cpu.toL2Bus.snoop_filter.tot_requests 4856494 # Total number of requests made to the snoop filter. 466system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425336 # Number of requests hitting in the snoop filter with a single holder of the requested data. 467system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 468system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter. 469system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 470system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 471system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution 472system.cpu.toL2Bus.trans_dist::ReadResp 15971629 # Transaction distribution --- 97 unchanged lines hidden (view full) --- 570system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 571system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 572system.iocache.tags.tag_accesses 428607 # Number of tag accesses 573system.iocache.tags.data_accesses 428607 # Number of data accesses 574system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses 575system.iocache.ReadReq_misses::total 903 # number of ReadReq misses 576system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 577system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses | 450system.cpu.toL2Bus.snoop_filter.tot_requests 4856494 # Total number of requests made to the snoop filter. 451system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425336 # Number of requests hitting in the snoop filter with a single holder of the requested data. 452system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 453system.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter. 454system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 455system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 456system.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution 457system.cpu.toL2Bus.trans_dist::ReadResp 15971629 # Transaction distribution --- 97 unchanged lines hidden (view full) --- 555system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 556system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 557system.iocache.tags.tag_accesses 428607 # Number of tag accesses 558system.iocache.tags.data_accesses 428607 # Number of data accesses 559system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses 560system.iocache.ReadReq_misses::total 903 # number of ReadReq misses 561system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 562system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses |
| 578system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses 579system.iocache.demand_misses::total 903 # number of demand (read+write) misses 580system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses 581system.iocache.overall_misses::total 903 # number of overall misses | 563system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses 564system.iocache.demand_misses::total 47623 # number of demand (read+write) misses 565system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses 566system.iocache.overall_misses::total 47623 # number of overall misses |
| 582system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) 583system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) 584system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 585system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) | 567system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) 568system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) 569system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 570system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) |
| 586system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses 587system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses 588system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses 589system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses | 571system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses 572system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses 573system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses 574system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses |
| 590system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 591system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 592system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 593system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 594system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 595system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 596system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 597system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 598system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 599system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 600system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 601system.iocache.blocked::no_targets 0 # number of cycles access was blocked 602system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 603system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 575system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 576system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 577system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 578system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 579system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 580system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 581system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 582system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 583system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 584system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 585system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 586system.iocache.blocked::no_targets 0 # number of cycles access was blocked 587system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 588system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 604system.iocache.fast_writes 0 # number of fast writes performed 605system.iocache.cache_copies 0 # number of cache copies performed | |
| 606system.iocache.writebacks::writebacks 46667 # number of writebacks 607system.iocache.writebacks::total 46667 # number of writebacks | 589system.iocache.writebacks::writebacks 46667 # number of writebacks 590system.iocache.writebacks::total 46667 # number of writebacks |
| 608system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 609system.membus.trans_dist::ReadReq 13857337 # Transaction distribution 610system.membus.trans_dist::ReadResp 13903644 # Transaction distribution 611system.membus.trans_dist::WriteReq 13943 # Transaction distribution 612system.membus.trans_dist::WriteResp 13943 # Transaction distribution 613system.membus.trans_dist::WritebackDirty 144842 # Transaction distribution 614system.membus.trans_dist::CleanEvict 8802 # Transaction distribution 615system.membus.trans_dist::UpgradeReq 2189 # Transaction distribution 616system.membus.trans_dist::UpgradeResp 1650 # Transaction distribution --- 51 unchanged lines hidden --- | 591system.membus.trans_dist::ReadReq 13857337 # Transaction distribution 592system.membus.trans_dist::ReadResp 13903644 # Transaction distribution 593system.membus.trans_dist::WriteReq 13943 # Transaction distribution 594system.membus.trans_dist::WriteResp 13943 # Transaction distribution 595system.membus.trans_dist::WritebackDirty 144842 # Transaction distribution 596system.membus.trans_dist::CleanEvict 8802 # Transaction distribution 597system.membus.trans_dist::UpgradeReq 2189 # Transaction distribution 598system.membus.trans_dist::UpgradeResp 1650 # Transaction distribution --- 51 unchanged lines hidden --- |