| stats.txt (10549:6317351a288c) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 5.112155 # Number of seconds simulated 4sim_ticks 5112155173500 # Number of ticks simulated 5final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 5.112156 # Number of seconds simulated 4sim_ticks 5112155738500 # Number of ticks simulated 5final_tick 5112155738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1977176 # Simulator instruction rate (inst/s) 8host_op_rate 4047982 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 50529549296 # Simulator tick rate (ticks/s) 10host_mem_usage 594968 # Number of bytes of host memory used 11host_seconds 101.17 # Real time elapsed on the host 12sim_insts 200033988 # Number of instructions simulated 13sim_ops 409540726 # Number of ops (including micro ops) simulated | 7host_inst_rate 1511003 # Simulator instruction rate (inst/s) 8host_op_rate 3093560 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38615908446 # Simulator tick rate (ticks/s) 10host_mem_usage 595640 # Number of bytes of host memory used 11host_seconds 132.38 # Real time elapsed on the host 12sim_insts 200033669 # Number of instructions simulated 13sim_ops 409539941 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.inst 852224 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10636736 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory | 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
| 21system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory 26system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory | 21system.physmem.bytes_read::total 11517696 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 852224 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 852224 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9281152 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9281152 # Number of bytes written to this memory |
| 27system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 26system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.inst 13316 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 166199 # Number of read requests responded to by this memory |
| 31system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory | 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
| 32system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory | 31system.physmem.num_reads::total 179964 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 145018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 145018 # Number of write requests responded to by this memory |
| 36system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s) | 36system.physmem.bw_read::cpu.inst 166705 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 2080675 # Total read bandwidth from this memory (bytes/s) |
| 40system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) | 38system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) |
| 41system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1231249 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::total 2253002 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 166705 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 166705 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1815507 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1815507 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1815507 # Total bandwidth to/from this memory (bytes/s) |
| 48system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) | 45system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) |
| 50system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s) | 47system.physmem.bw_total::cpu.inst 166705 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 2080675 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4068508 # Total bandwidth to/from this memory (bytes/s) |
| 54system.cpu_clk_domain.clock 500 # Clock period in ticks 55system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 51system.cpu_clk_domain.clock 500 # Clock period in ticks 52system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 56system.cpu.numCycles 10224314318 # number of cpu cycles simulated | 53system.cpu.numCycles 10224315447 # number of cpu cycles simulated |
| 57system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 58system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 54system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 55system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 59system.cpu.committedInsts 200033988 # Number of instructions committed 60system.cpu.committedOps 409540726 # Number of ops (including micro ops) committed 61system.cpu.num_int_alu_accesses 374550150 # Number of integer alu accesses | 56system.cpu.committedInsts 200033669 # Number of instructions committed 57system.cpu.committedOps 409539941 # Number of ops (including micro ops) committed 58system.cpu.num_int_alu_accesses 374549395 # Number of integer alu accesses |
| 62system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses | 59system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses |
| 63system.cpu.num_func_calls 2308777 # number of times a function call or return occured 64system.cpu.num_conditional_control_insts 39994865 # number of instructions that are conditional controls 65system.cpu.num_int_insts 374550150 # number of integer instructions | 60system.cpu.num_func_calls 2308749 # number of times a function call or return occured 61system.cpu.num_conditional_control_insts 39994798 # number of instructions that are conditional controls 62system.cpu.num_int_insts 374549395 # number of integer instructions |
| 66system.cpu.num_fp_insts 0 # number of float instructions | 63system.cpu.num_fp_insts 0 # number of float instructions |
| 67system.cpu.num_int_register_reads 682630172 # number of times the integer registers were read 68system.cpu.num_int_register_writes 323525861 # number of times the integer registers were written | 64system.cpu.num_int_register_reads 682628451 # number of times the integer registers were read 65system.cpu.num_int_register_writes 323525110 # number of times the integer registers were written |
| 69system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 70system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 66system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 67system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 71system.cpu.num_cc_register_reads 233820803 # number of times the CC registers were read 72system.cpu.num_cc_register_writes 157313619 # number of times the CC registers were written 73system.cpu.num_mem_refs 35680563 # number of memory refs 74system.cpu.num_load_insts 27249389 # Number of load instructions 75system.cpu.num_store_insts 8431174 # Number of store instructions 76system.cpu.num_idle_cycles 9770366809.410368 # Number of idle cycles 77system.cpu.num_busy_cycles 453947508.589632 # Number of busy cycles | 68system.cpu.num_cc_register_reads 233820400 # number of times the CC registers were read 69system.cpu.num_cc_register_writes 157313425 # number of times the CC registers were written 70system.cpu.num_mem_refs 35680406 # number of memory refs 71system.cpu.num_load_insts 27249300 # Number of load instructions 72system.cpu.num_store_insts 8431106 # Number of store instructions 73system.cpu.num_idle_cycles 9770368815.449127 # Number of idle cycles 74system.cpu.num_busy_cycles 453946631.550873 # Number of busy cycles |
| 78system.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles 79system.cpu.idle_fraction 0.955601 # Percentage of idle cycles | 75system.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles 76system.cpu.idle_fraction 0.955601 # Percentage of idle cycles |
| 80system.cpu.Branches 43145769 # Number of branches fetched 81system.cpu.op_class::No_OpClass 175400 0.04% 0.04% # Class of executed instruction 82system.cpu.op_class::IntAlu 373418196 91.18% 91.22% # Class of executed instruction 83system.cpu.op_class::IntMult 144548 0.04% 91.26% # Class of executed instruction 84system.cpu.op_class::IntDiv 123054 0.03% 91.29% # Class of executed instruction | 77system.cpu.Branches 43145649 # Number of branches fetched 78system.cpu.op_class::No_OpClass 175370 0.04% 0.04% # Class of executed instruction 79system.cpu.op_class::IntAlu 373417675 91.18% 91.22% # Class of executed instruction 80system.cpu.op_class::IntMult 144551 0.04% 91.26% # Class of executed instruction 81system.cpu.op_class::IntDiv 122974 0.03% 91.29% # Class of executed instruction |
| 85system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction 86system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction 87system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction 88system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction 89system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction 90system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction 91system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction 92system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 103system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction 104system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction 105system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction 106system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction 107system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction 108system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction 109system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction 110system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction | 82system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction 83system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction 84system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction 85system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction 86system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction 87system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction 88system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction 89system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 100system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction 101system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction 102system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction 103system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction 104system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction 105system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction 106system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction 107system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction |
| 111system.cpu.op_class::MemRead 27249389 6.65% 97.94% # Class of executed instruction 112system.cpu.op_class::MemWrite 8431174 2.06% 100.00% # Class of executed instruction | 108system.cpu.op_class::MemRead 27249300 6.65% 97.94% # Class of executed instruction 109system.cpu.op_class::MemWrite 8431106 2.06% 100.00% # Class of executed instruction |
| 113system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 114system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 110system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 111system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 115system.cpu.op_class::total 409541761 # Class of executed instruction | 112system.cpu.op_class::total 409540976 # Class of executed instruction |
| 116system.cpu.kern.inst.arm 0 # number of arm instructions executed 117system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 113system.cpu.kern.inst.arm 0 # number of arm instructions executed 114system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 118system.cpu.dcache.tags.replacements 1623441 # number of replacements | 115system.cpu.dcache.tags.replacements 1623460 # number of replacements |
| 119system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use | 116system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use |
| 120system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks. 121system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks. 122system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks. | 117system.cpu.dcache.tags.total_refs 20193083 # Total number of references to valid blocks. 118system.cpu.dcache.tags.sampled_refs 1623972 # Sample count of references to valid blocks. 119system.cpu.dcache.tags.avg_refs 12.434379 # Average number of references to valid blocks. |
| 123system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 124system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor 125system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 126system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 127system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 128system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id 129system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id 130system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 131system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 120system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 121system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor 122system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 123system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 124system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 125system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id 126system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id 127system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 128system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 132system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses 133system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses 134system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits 135system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits 136system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits 137system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits 138system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits 139system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits 140system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits 141system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits 142system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits 143system.cpu.dcache.overall_hits::total 20190999 # number of overall hits 144system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses 145system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses 146system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses 147system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses 148system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses 149system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses 150system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses 151system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses 152system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses 153system.cpu.dcache.overall_misses::total 1626230 # number of overall misses 154system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses) 155system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses) 156system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses) 157system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses) | 129system.cpu.dcache.tags.tag_accesses 88892257 # Number of tag accesses 130system.cpu.dcache.tags.data_accesses 88892257 # Number of data accesses 131system.cpu.dcache.ReadReq_hits::cpu.data 12028370 # number of ReadReq hits 132system.cpu.dcache.ReadReq_hits::total 12028370 # number of ReadReq hits 133system.cpu.dcache.WriteReq_hits::cpu.data 8103548 # number of WriteReq hits 134system.cpu.dcache.WriteReq_hits::total 8103548 # number of WriteReq hits 135system.cpu.dcache.SoftPFReq_hits::cpu.data 58901 # number of SoftPFReq hits 136system.cpu.dcache.SoftPFReq_hits::total 58901 # number of SoftPFReq hits 137system.cpu.dcache.demand_hits::cpu.data 20131918 # number of demand (read+write) hits 138system.cpu.dcache.demand_hits::total 20131918 # number of demand (read+write) hits 139system.cpu.dcache.overall_hits::cpu.data 20190819 # number of overall hits 140system.cpu.dcache.overall_hits::total 20190819 # number of overall hits 141system.cpu.dcache.ReadReq_misses::cpu.data 906001 # number of ReadReq misses 142system.cpu.dcache.ReadReq_misses::total 906001 # number of ReadReq misses 143system.cpu.dcache.WriteReq_misses::cpu.data 317188 # number of WriteReq misses 144system.cpu.dcache.WriteReq_misses::total 317188 # number of WriteReq misses 145system.cpu.dcache.SoftPFReq_misses::cpu.data 403060 # number of SoftPFReq misses 146system.cpu.dcache.SoftPFReq_misses::total 403060 # number of SoftPFReq misses 147system.cpu.dcache.demand_misses::cpu.data 1223189 # number of demand (read+write) misses 148system.cpu.dcache.demand_misses::total 1223189 # number of demand (read+write) misses 149system.cpu.dcache.overall_misses::cpu.data 1626249 # number of overall misses 150system.cpu.dcache.overall_misses::total 1626249 # number of overall misses 151system.cpu.dcache.ReadReq_accesses::cpu.data 12934371 # number of ReadReq accesses(hits+misses) 152system.cpu.dcache.ReadReq_accesses::total 12934371 # number of ReadReq accesses(hits+misses) 153system.cpu.dcache.WriteReq_accesses::cpu.data 8420736 # number of WriteReq accesses(hits+misses) 154system.cpu.dcache.WriteReq_accesses::total 8420736 # number of WriteReq accesses(hits+misses) |
| 158system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses) 159system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses) | 155system.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses) 156system.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses) |
| 160system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses 161system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses 162system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses 163system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses 164system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses 165system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses 166system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses 167system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses 168system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses 169system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses 170system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses 171system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses 172system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses 173system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses | 157system.cpu.dcache.demand_accesses::cpu.data 21355107 # number of demand (read+write) accesses 158system.cpu.dcache.demand_accesses::total 21355107 # number of demand (read+write) accesses 159system.cpu.dcache.overall_accesses::cpu.data 21817068 # number of overall (read+write) accesses 160system.cpu.dcache.overall_accesses::total 21817068 # number of overall (read+write) accesses 161system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070046 # miss rate for ReadReq accesses 162system.cpu.dcache.ReadReq_miss_rate::total 0.070046 # miss rate for ReadReq accesses 163system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037667 # miss rate for WriteReq accesses 164system.cpu.dcache.WriteReq_miss_rate::total 0.037667 # miss rate for WriteReq accesses 165system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872498 # miss rate for SoftPFReq accesses 166system.cpu.dcache.SoftPFReq_miss_rate::total 0.872498 # miss rate for SoftPFReq accesses 167system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses 168system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses 169system.cpu.dcache.overall_miss_rate::cpu.data 0.074540 # miss rate for overall accesses 170system.cpu.dcache.overall_miss_rate::total 0.074540 # miss rate for overall accesses |
| 174system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 175system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 176system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 177system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 178system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 179system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 180system.cpu.dcache.fast_writes 0 # number of fast writes performed 181system.cpu.dcache.cache_copies 0 # number of cache copies performed | 171system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 172system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 173system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 174system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 175system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 176system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 177system.cpu.dcache.fast_writes 0 # number of fast writes performed 178system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 182system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks 183system.cpu.dcache.writebacks::total 1536849 # number of writebacks | 179system.cpu.dcache.writebacks::writebacks 1536867 # number of writebacks 180system.cpu.dcache.writebacks::total 1536867 # number of writebacks |
| 184system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 185system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements | 181system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 182system.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements |
| 186system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use 187system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks. | 183system.cpu.dtb_walker_cache.tags.tagsinuse 5.013943 # Cycle average of tags in use 184system.cpu.dtb_walker_cache.tags.total_refs 12520 # Total number of references to valid blocks. |
| 188system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks. | 185system.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks. |
| 189system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks. 190system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit. 191system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor 192system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy 193system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy | 186system.cpu.dtb_walker_cache.tags.avg_refs 1.529067 # Average number of references to valid blocks. 187system.cpu.dtb_walker_cache.tags.warmup_cycle 5101318572500 # Cycle when the warmup percentage was hit. 188system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013943 # Average occupied blocks per requestor 189system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313371 # Average percentage of cache occupancy 190system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313371 # Average percentage of cache occupancy |
| 194system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 195system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 196system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 197system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 198system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id | 191system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 192system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 193system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 194system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 195system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id |
| 199system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses 200system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses 201system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits 202system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits 203system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits 204system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits 205system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits 206system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits | 196system.cpu.dtb_walker_cache.tags.tag_accesses 53161 # Number of tag accesses 197system.cpu.dtb_walker_cache.tags.data_accesses 53161 # Number of data accesses 198system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12521 # number of ReadReq hits 199system.cpu.dtb_walker_cache.ReadReq_hits::total 12521 # number of ReadReq hits 200system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12521 # number of demand (read+write) hits 201system.cpu.dtb_walker_cache.demand_hits::total 12521 # number of demand (read+write) hits 202system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12521 # number of overall hits 203system.cpu.dtb_walker_cache.overall_hits::total 12521 # number of overall hits |
| 207system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses 208system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses 209system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses 210system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses 211system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses 212system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses | 204system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses 205system.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses 206system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses 207system.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses 208system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses 209system.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses |
| 213system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses) 214system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses) 215system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses 216system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses 217system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses 218system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses 219system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses 220system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses 221system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses 222system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses 223system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses 224system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses | 210system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses) 211system.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses) 212system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses 213system.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses 214system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses 215system.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses 216system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428108 # miss rate for ReadReq accesses 217system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428108 # miss rate for ReadReq accesses 218system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428108 # miss rate for demand accesses 219system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428108 # miss rate for demand accesses 220system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428108 # miss rate for overall accesses 221system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428108 # miss rate for overall accesses |
| 225system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 226system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 227system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 228system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 229system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 230system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 231system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 232system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 233system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks 234system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks 235system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 222system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 223system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 224system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 225system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 226system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 227system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 228system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 229system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 230system.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks 231system.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks 232system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 236system.cpu.icache.tags.replacements 791952 # number of replacements | 233system.cpu.icache.tags.replacements 791846 # number of replacements |
| 237system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use | 234system.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use |
| 238system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks. 239system.cpu.icache.tags.sampled_refs 792464 # Sample count of references to valid blocks. 240system.cpu.icache.tags.avg_refs 307.453687 # Average number of references to valid blocks. | 235system.cpu.icache.tags.total_refs 243645674 # Total number of references to valid blocks. 236system.cpu.icache.tags.sampled_refs 792358 # Sample count of references to valid blocks. 237system.cpu.icache.tags.avg_refs 307.494433 # Average number of references to valid blocks. |
| 241system.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit. 242system.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor 243system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy 244system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy 245system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 246system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 247system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 248system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id 249system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 250system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 238system.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit. 239system.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor 240system.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy 241system.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy 242system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 243system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 244system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 245system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id 246system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 247system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 251system.cpu.icache.tags.tag_accesses 245230921 # Number of tag accesses 252system.cpu.icache.tags.data_accesses 245230921 # Number of data accesses 253system.cpu.icache.ReadReq_hits::cpu.inst 243645979 # number of ReadReq hits 254system.cpu.icache.ReadReq_hits::total 243645979 # number of ReadReq hits 255system.cpu.icache.demand_hits::cpu.inst 243645979 # number of demand (read+write) hits 256system.cpu.icache.demand_hits::total 243645979 # number of demand (read+write) hits 257system.cpu.icache.overall_hits::cpu.inst 243645979 # number of overall hits 258system.cpu.icache.overall_hits::total 243645979 # number of overall hits 259system.cpu.icache.ReadReq_misses::cpu.inst 792471 # number of ReadReq misses 260system.cpu.icache.ReadReq_misses::total 792471 # number of ReadReq misses 261system.cpu.icache.demand_misses::cpu.inst 792471 # number of demand (read+write) misses 262system.cpu.icache.demand_misses::total 792471 # number of demand (read+write) misses 263system.cpu.icache.overall_misses::cpu.inst 792471 # number of overall misses 264system.cpu.icache.overall_misses::total 792471 # number of overall misses 265system.cpu.icache.ReadReq_accesses::cpu.inst 244438450 # number of ReadReq accesses(hits+misses) 266system.cpu.icache.ReadReq_accesses::total 244438450 # number of ReadReq accesses(hits+misses) 267system.cpu.icache.demand_accesses::cpu.inst 244438450 # number of demand (read+write) accesses 268system.cpu.icache.demand_accesses::total 244438450 # number of demand (read+write) accesses 269system.cpu.icache.overall_accesses::cpu.inst 244438450 # number of overall (read+write) accesses 270system.cpu.icache.overall_accesses::total 244438450 # number of overall (read+write) accesses | 248system.cpu.icache.tags.tag_accesses 245230404 # Number of tag accesses 249system.cpu.icache.tags.data_accesses 245230404 # Number of data accesses 250system.cpu.icache.ReadReq_hits::cpu.inst 243645674 # number of ReadReq hits 251system.cpu.icache.ReadReq_hits::total 243645674 # number of ReadReq hits 252system.cpu.icache.demand_hits::cpu.inst 243645674 # number of demand (read+write) hits 253system.cpu.icache.demand_hits::total 243645674 # number of demand (read+write) hits 254system.cpu.icache.overall_hits::cpu.inst 243645674 # number of overall hits 255system.cpu.icache.overall_hits::total 243645674 # number of overall hits 256system.cpu.icache.ReadReq_misses::cpu.inst 792365 # number of ReadReq misses 257system.cpu.icache.ReadReq_misses::total 792365 # number of ReadReq misses 258system.cpu.icache.demand_misses::cpu.inst 792365 # number of demand (read+write) misses 259system.cpu.icache.demand_misses::total 792365 # number of demand (read+write) misses 260system.cpu.icache.overall_misses::cpu.inst 792365 # number of overall misses 261system.cpu.icache.overall_misses::total 792365 # number of overall misses 262system.cpu.icache.ReadReq_accesses::cpu.inst 244438039 # number of ReadReq accesses(hits+misses) 263system.cpu.icache.ReadReq_accesses::total 244438039 # number of ReadReq accesses(hits+misses) 264system.cpu.icache.demand_accesses::cpu.inst 244438039 # number of demand (read+write) accesses 265system.cpu.icache.demand_accesses::total 244438039 # number of demand (read+write) accesses 266system.cpu.icache.overall_accesses::cpu.inst 244438039 # number of overall (read+write) accesses 267system.cpu.icache.overall_accesses::total 244438039 # number of overall (read+write) accesses |
| 271system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses 272system.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses 273system.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses 274system.cpu.icache.demand_miss_rate::total 0.003242 # miss rate for demand accesses 275system.cpu.icache.overall_miss_rate::cpu.inst 0.003242 # miss rate for overall accesses 276system.cpu.icache.overall_miss_rate::total 0.003242 # miss rate for overall accesses 277system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 278system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 279system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 280system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 281system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 282system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 283system.cpu.icache.fast_writes 0 # number of fast writes performed 284system.cpu.icache.cache_copies 0 # number of cache copies performed 285system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 286system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements | 268system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses 269system.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses 270system.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses 271system.cpu.icache.demand_miss_rate::total 0.003242 # miss rate for demand accesses 272system.cpu.icache.overall_miss_rate::cpu.inst 0.003242 # miss rate for overall accesses 273system.cpu.icache.overall_miss_rate::total 0.003242 # miss rate for overall accesses 274system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 275system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 276system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 277system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 278system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 279system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 280system.cpu.icache.fast_writes 0 # number of fast writes performed 281system.cpu.icache.cache_copies 0 # number of cache copies performed 282system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 283system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements |
| 287system.cpu.itb_walker_cache.tags.tagsinuse 3.026453 # Cycle average of tags in use | 284system.cpu.itb_walker_cache.tags.tagsinuse 3.026443 # Cycle average of tags in use |
| 288system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks. 289system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks. 290system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks. | 285system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks. 286system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks. 287system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks. |
| 291system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000 # Cycle when the warmup percentage was hit. 292system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026453 # Average occupied blocks per requestor | 288system.cpu.itb_walker_cache.tags.warmup_cycle 5102148365500 # Cycle when the warmup percentage was hit. 289system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026443 # Average occupied blocks per requestor |
| 293system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy 294system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy 295system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 296system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 297system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 298system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 299system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 300system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id --- 33 unchanged lines hidden (view full) --- 334system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 335system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 336system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 337system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 338system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 339system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks 340system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks 341system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 290system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy 291system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy 292system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 293system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 294system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 295system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 296system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 297system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id --- 33 unchanged lines hidden (view full) --- 331system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 332system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 333system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 334system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 335system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 336system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks 337system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks 338system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 342system.cpu.l2cache.tags.replacements 106197 # number of replacements 343system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use 344system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks. 345system.cpu.l2cache.tags.sampled_refs 170308 # Sample count of references to valid blocks. 346system.cpu.l2cache.tags.avg_refs 20.327125 # Average number of references to valid blocks. | 339system.cpu.l2cache.tags.replacements 106199 # number of replacements 340system.cpu.l2cache.tags.tagsinuse 64825.456332 # Cycle average of tags in use 341system.cpu.l2cache.tags.total_refs 3461789 # Total number of references to valid blocks. 342system.cpu.l2cache.tags.sampled_refs 170310 # Sample count of references to valid blocks. 343system.cpu.l2cache.tags.avg_refs 20.326399 # Average number of references to valid blocks. |
| 347system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 344system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 348system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327 # Average occupied blocks per requestor | 345system.cpu.l2cache.tags.occ_blocks::writebacks 51911.006068 # Average occupied blocks per requestor |
| 349system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor | 346system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor |
| 350system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132278 # Average occupied blocks per requestor 351system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.291417 # Average occupied blocks per requestor 352system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412 # Average occupied blocks per requestor | 347system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132276 # Average occupied blocks per requestor 348system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.288805 # Average occupied blocks per requestor 349system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.026704 # Average occupied blocks per requestor |
| 353system.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy 354system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 355system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 356system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037999 # Average percentage of cache occupancy 357system.cpu.l2cache.tags.occ_percent::cpu.data 0.159058 # Average percentage of cache occupancy 358system.cpu.l2cache.tags.occ_percent::total 0.989158 # Average percentage of cache occupancy 359system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 # Occupied blocks per task id 360system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 361system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 362system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id | 350system.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy 351system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 352system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 353system.cpu.l2cache.tags.occ_percent::cpu.inst 0.037999 # Average percentage of cache occupancy 354system.cpu.l2cache.tags.occ_percent::cpu.data 0.159058 # Average percentage of cache occupancy 355system.cpu.l2cache.tags.occ_percent::total 0.989158 # Average percentage of cache occupancy 356system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 # Occupied blocks per task id 357system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 358system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 359system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id |
| 363system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id 364system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id | 360system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20721 # Occupied blocks per task id 361system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39577 # Occupied blocks per task id |
| 365system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id | 362system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id |
| 366system.cpu.l2cache.tags.tag_accesses 32246059 # Number of tag accesses 367system.cpu.l2cache.tags.data_accesses 32246059 # Number of data accesses | 363system.cpu.l2cache.tags.tag_accesses 32245523 # Number of tag accesses 364system.cpu.l2cache.tags.data_accesses 32245523 # Number of data accesses |
| 368system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits 369system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits | 365system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits 366system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits |
| 370system.cpu.l2cache.ReadReq_hits::cpu.inst 779141 # number of ReadReq hits 371system.cpu.l2cache.ReadReq_hits::cpu.data 1276184 # number of ReadReq hits 372system.cpu.l2cache.ReadReq_hits::total 2065993 # number of ReadReq hits 373system.cpu.l2cache.Writeback_hits::writebacks 1540445 # number of Writeback hits 374system.cpu.l2cache.Writeback_hits::total 1540445 # number of Writeback hits | 367system.cpu.l2cache.ReadReq_hits::cpu.inst 779035 # number of ReadReq hits 368system.cpu.l2cache.ReadReq_hits::cpu.data 1276188 # number of ReadReq hits 369system.cpu.l2cache.ReadReq_hits::total 2065891 # number of ReadReq hits 370system.cpu.l2cache.Writeback_hits::writebacks 1540463 # number of Writeback hits 371system.cpu.l2cache.Writeback_hits::total 1540463 # number of Writeback hits |
| 375system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits 376system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits | 372system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits 373system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits |
| 377system.cpu.l2cache.ReadExReq_hits::cpu.data 180006 # number of ReadExReq hits 378system.cpu.l2cache.ReadExReq_hits::total 180006 # number of ReadExReq hits | 374system.cpu.l2cache.ReadExReq_hits::cpu.data 180020 # number of ReadExReq hits 375system.cpu.l2cache.ReadExReq_hits::total 180020 # number of ReadExReq hits |
| 379system.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits 380system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits | 376system.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits 377system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits |
| 381system.cpu.l2cache.demand_hits::cpu.inst 779141 # number of demand (read+write) hits 382system.cpu.l2cache.demand_hits::cpu.data 1456190 # number of demand (read+write) hits 383system.cpu.l2cache.demand_hits::total 2245999 # number of demand (read+write) hits | 378system.cpu.l2cache.demand_hits::cpu.inst 779035 # number of demand (read+write) hits 379system.cpu.l2cache.demand_hits::cpu.data 1456208 # number of demand (read+write) hits 380system.cpu.l2cache.demand_hits::total 2245911 # number of demand (read+write) hits |
| 384system.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits 385system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits | 381system.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits 382system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits |
| 386system.cpu.l2cache.overall_hits::cpu.inst 779141 # number of overall hits 387system.cpu.l2cache.overall_hits::cpu.data 1456190 # number of overall hits 388system.cpu.l2cache.overall_hits::total 2245999 # number of overall hits | 383system.cpu.l2cache.overall_hits::cpu.inst 779035 # number of overall hits 384system.cpu.l2cache.overall_hits::cpu.data 1456208 # number of overall hits 385system.cpu.l2cache.overall_hits::total 2245911 # number of overall hits |
| 389system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 390system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 391system.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses 392system.cpu.l2cache.ReadReq_misses::cpu.data 32232 # number of ReadReq misses 393system.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses 394system.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses 395system.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses | 386system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 387system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 388system.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses 389system.cpu.l2cache.ReadReq_misses::cpu.data 32232 # number of ReadReq misses 390system.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses 391system.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses 392system.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses |
| 396system.cpu.l2cache.ReadExReq_misses::cpu.data 134898 # number of ReadExReq misses 397system.cpu.l2cache.ReadExReq_misses::total 134898 # number of ReadExReq misses | 393system.cpu.l2cache.ReadExReq_misses::cpu.data 134899 # number of ReadExReq misses 394system.cpu.l2cache.ReadExReq_misses::total 134899 # number of ReadExReq misses |
| 398system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 399system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 400system.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses | 395system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 396system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 397system.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses |
| 401system.cpu.l2cache.demand_misses::cpu.data 167130 # number of demand (read+write) misses 402system.cpu.l2cache.demand_misses::total 180453 # number of demand (read+write) misses | 398system.cpu.l2cache.demand_misses::cpu.data 167131 # number of demand (read+write) misses 399system.cpu.l2cache.demand_misses::total 180454 # number of demand (read+write) misses |
| 403system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 404system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 405system.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses | 400system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 401system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 402system.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses |
| 406system.cpu.l2cache.overall_misses::cpu.data 167130 # number of overall misses 407system.cpu.l2cache.overall_misses::total 180453 # number of overall misses | 403system.cpu.l2cache.overall_misses::cpu.data 167131 # number of overall misses 404system.cpu.l2cache.overall_misses::total 180454 # number of overall misses |
| 408system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses) 409system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses) | 405system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses) 406system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses) |
| 410system.cpu.l2cache.ReadReq_accesses::cpu.inst 792458 # number of ReadReq accesses(hits+misses) 411system.cpu.l2cache.ReadReq_accesses::cpu.data 1308416 # number of ReadReq accesses(hits+misses) 412system.cpu.l2cache.ReadReq_accesses::total 2111548 # number of ReadReq accesses(hits+misses) 413system.cpu.l2cache.Writeback_accesses::writebacks 1540445 # number of Writeback accesses(hits+misses) 414system.cpu.l2cache.Writeback_accesses::total 1540445 # number of Writeback accesses(hits+misses) | 407system.cpu.l2cache.ReadReq_accesses::cpu.inst 792352 # number of ReadReq accesses(hits+misses) 408system.cpu.l2cache.ReadReq_accesses::cpu.data 1308420 # number of ReadReq accesses(hits+misses) 409system.cpu.l2cache.ReadReq_accesses::total 2111446 # number of ReadReq accesses(hits+misses) 410system.cpu.l2cache.Writeback_accesses::writebacks 1540463 # number of Writeback accesses(hits+misses) 411system.cpu.l2cache.Writeback_accesses::total 1540463 # number of Writeback accesses(hits+misses) |
| 415system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses) 416system.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses) | 412system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses) 413system.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses) |
| 417system.cpu.l2cache.ReadExReq_accesses::cpu.data 314904 # number of ReadExReq accesses(hits+misses) 418system.cpu.l2cache.ReadExReq_accesses::total 314904 # number of ReadExReq accesses(hits+misses) | 414system.cpu.l2cache.ReadExReq_accesses::cpu.data 314919 # number of ReadExReq accesses(hits+misses) 415system.cpu.l2cache.ReadExReq_accesses::total 314919 # number of ReadExReq accesses(hits+misses) |
| 419system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses 420system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses | 416system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses 417system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses |
| 421system.cpu.l2cache.demand_accesses::cpu.inst 792458 # number of demand (read+write) accesses 422system.cpu.l2cache.demand_accesses::cpu.data 1623320 # number of demand (read+write) accesses 423system.cpu.l2cache.demand_accesses::total 2426452 # number of demand (read+write) accesses | 418system.cpu.l2cache.demand_accesses::cpu.inst 792352 # number of demand (read+write) accesses 419system.cpu.l2cache.demand_accesses::cpu.data 1623339 # number of demand (read+write) accesses 420system.cpu.l2cache.demand_accesses::total 2426365 # number of demand (read+write) accesses |
| 424system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses 425system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses | 421system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses 422system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses |
| 426system.cpu.l2cache.overall_accesses::cpu.inst 792458 # number of overall (read+write) accesses 427system.cpu.l2cache.overall_accesses::cpu.data 1623320 # number of overall (read+write) accesses 428system.cpu.l2cache.overall_accesses::total 2426452 # number of overall (read+write) accesses | 423system.cpu.l2cache.overall_accesses::cpu.inst 792352 # number of overall (read+write) accesses 424system.cpu.l2cache.overall_accesses::cpu.data 1623339 # number of overall (read+write) accesses 425system.cpu.l2cache.overall_accesses::total 2426365 # number of overall (read+write) accesses |
| 429system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses 430system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses | 426system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses 427system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses |
| 431system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016805 # miss rate for ReadReq accesses | 428system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses |
| 432system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses | 429system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses |
| 433system.cpu.l2cache.ReadReq_miss_rate::total 0.021574 # miss rate for ReadReq accesses | 430system.cpu.l2cache.ReadReq_miss_rate::total 0.021575 # miss rate for ReadReq accesses |
| 434system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses 435system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses | 431system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses 432system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses |
| 436system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428378 # miss rate for ReadExReq accesses 437system.cpu.l2cache.ReadExReq_miss_rate::total 0.428378 # miss rate for ReadExReq accesses | 433system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428361 # miss rate for ReadExReq accesses 434system.cpu.l2cache.ReadExReq_miss_rate::total 0.428361 # miss rate for ReadExReq accesses |
| 438system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses 439system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses | 435system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses 436system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses |
| 440system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016805 # miss rate for demand accesses 441system.cpu.l2cache.demand_miss_rate::cpu.data 0.102956 # miss rate for demand accesses 442system.cpu.l2cache.demand_miss_rate::total 0.074369 # miss rate for demand accesses | 437system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses 438system.cpu.l2cache.demand_miss_rate::cpu.data 0.102955 # miss rate for demand accesses 439system.cpu.l2cache.demand_miss_rate::total 0.074372 # miss rate for demand accesses |
| 443system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses 444system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses | 440system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses 441system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses |
| 445system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016805 # miss rate for overall accesses 446system.cpu.l2cache.overall_miss_rate::cpu.data 0.102956 # miss rate for overall accesses 447system.cpu.l2cache.overall_miss_rate::total 0.074369 # miss rate for overall accesses | 442system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses 443system.cpu.l2cache.overall_miss_rate::cpu.data 0.102955 # miss rate for overall accesses 444system.cpu.l2cache.overall_miss_rate::total 0.074372 # miss rate for overall accesses |
| 448system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 449system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 451system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 453system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 454system.cpu.l2cache.fast_writes 0 # number of fast writes performed 455system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 445system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 446system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 447system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 448system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 449system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 450system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 451system.cpu.l2cache.fast_writes 0 # number of fast writes performed 452system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 456system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks 457system.cpu.l2cache.writebacks::total 98349 # number of writebacks | 453system.cpu.l2cache.writebacks::writebacks 98351 # number of writebacks 454system.cpu.l2cache.writebacks::total 98351 # number of writebacks |
| 458system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 455system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 459system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution 460system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution | 456system.cpu.toL2Bus.trans_dist::ReadReq 15972684 # Transaction distribution 457system.cpu.toL2Bus.trans_dist::ReadResp 15972684 # Transaction distribution |
| 461system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution | 458system.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution 459system.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution |
| 463system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution | 460system.cpu.toL2Bus.trans_dist::Writeback 1540463 # Transaction distribution |
| 464system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution | 461system.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution 462system.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution |
| 466system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution 468system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes) 469system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes) | 463system.cpu.toL2Bus.trans_dist::ReadExReq 314924 # Transaction distribution 464system.cpu.toL2Bus.trans_dist::ReadExResp 314924 # Transaction distribution 465system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584730 # Packet count per connected master and slave (bytes) 466system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531797 # Packet count per connected master and slave (bytes) |
| 470system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes) | 467system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) 468system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes) |
| 472system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes) 473system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes) 474system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes) | 469system.cpu.toL2Bus.pkt_count::total 34148029 # Packet count per connected master and slave (bytes) 470system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50711360 # Cumulative packet size per connected master and slave (bytes) 471system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227719225 # Cumulative packet size per connected master and slave (bytes) |
| 475system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) 476system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes) | 472system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) 473system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes) |
| 477system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes) | 474system.cpu.toL2Bus.pkt_size::total 279553721 # Cumulative packet size per connected master and slave (bytes) |
| 478system.cpu.toL2Bus.snoops 48008 # Total snoops (count) | 475system.cpu.toL2Bus.snoops 48008 # Total snoops (count) |
| 479system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram | 476system.cpu.toL2Bus.snoop_fanout::samples 4020658 # Request fanout histogram |
| 480system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram | 477system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram |
| 481system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram | 478system.cpu.toL2Bus.snoop_fanout::stdev 0.108192 # Request fanout histogram |
| 482system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 483system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 484system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 485system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 479system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 480system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 481system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 482system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 486system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram | 483system.cpu.toL2Bus.snoop_fanout::3 3973030 98.82% 98.82% # Request fanout histogram |
| 487system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram 488system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 490system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram | 484system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram 485system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 486system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 487system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram |
| 491system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram | 488system.cpu.toL2Bus.snoop_fanout::total 4020658 # Request fanout histogram |
| 492system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution 493system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution 494system.iobus.trans_dist::WriteReq 57692 # Transaction distribution 495system.iobus.trans_dist::WriteResp 10972 # Transaction distribution 496system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 497system.iobus.trans_dist::MessageReq 1696 # Transaction distribution 498system.iobus.trans_dist::MessageResp 1696 # Transaction distribution 499system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) --- 40 unchanged lines hidden (view full) --- 540system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 541system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes) 542system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) 543system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) 544system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) 545system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) 546system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes) 547system.iocache.tags.replacements 47573 # number of replacements | 489system.iobus.trans_dist::ReadReq 10012030 # Transaction distribution 490system.iobus.trans_dist::ReadResp 10012030 # Transaction distribution 491system.iobus.trans_dist::WriteReq 57692 # Transaction distribution 492system.iobus.trans_dist::WriteResp 10972 # Transaction distribution 493system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 494system.iobus.trans_dist::MessageReq 1696 # Transaction distribution 495system.iobus.trans_dist::MessageResp 1696 # Transaction distribution 496system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) --- 40 unchanged lines hidden (view full) --- 537system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 538system.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes) 539system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) 540system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) 541system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) 542system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) 543system.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes) 544system.iocache.tags.replacements 47573 # number of replacements |
| 548system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use | 545system.iocache.tags.tagsinuse 0.042450 # Cycle average of tags in use |
| 549system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 550system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. 551system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 552system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit. | 546system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 547system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. 548system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 549system.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit. |
| 553system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor | 550system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042450 # Average occupied blocks per requestor |
| 554system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 555system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 556system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 557system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 558system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 559system.iocache.tags.tag_accesses 428652 # Number of tag accesses 560system.iocache.tags.data_accesses 428652 # Number of data accesses | 551system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 552system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 553system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 554system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 555system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 556system.iocache.tags.tag_accesses 428652 # Number of tag accesses 557system.iocache.tags.data_accesses 428652 # Number of data accesses |
| 561system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 562system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits | |
| 563system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses 564system.iocache.ReadReq_misses::total 908 # number of ReadReq misses | 558system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses 559system.iocache.ReadReq_misses::total 908 # number of ReadReq misses |
| 560system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 561system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses |
|
| 565system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses 566system.iocache.demand_misses::total 908 # number of demand (read+write) misses 567system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses 568system.iocache.overall_misses::total 908 # number of overall misses 569system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) 570system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) 571system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 572system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 573system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses 574system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses 575system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses 576system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses 577system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 578system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 562system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses 563system.iocache.demand_misses::total 908 # number of demand (read+write) misses 564system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses 565system.iocache.overall_misses::total 908 # number of overall misses 566system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) 567system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) 568system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 569system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 570system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses 571system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses 572system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses 573system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses 574system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 575system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 576system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 577system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses |
|
| 579system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 580system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 581system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 582system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 583system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 584system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 585system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 586system.iocache.blocked::no_targets 0 # number of cycles access was blocked 587system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 588system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 578system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 579system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 580system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 581system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 582system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 583system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 584system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 585system.iocache.blocked::no_targets 0 # number of cycles access was blocked 586system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 587system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 589system.iocache.fast_writes 46720 # number of fast writes performed | 588system.iocache.fast_writes 0 # number of fast writes performed |
| 590system.iocache.cache_copies 0 # number of cache copies performed | 589system.iocache.cache_copies 0 # number of cache copies performed |
| 590system.iocache.writebacks::writebacks 46667 # number of writebacks 591system.iocache.writebacks::total 46667 # number of writebacks |
|
| 591system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 592system.membus.trans_dist::ReadReq 13903768 # Transaction distribution 593system.membus.trans_dist::ReadResp 13903768 # Transaction distribution 594system.membus.trans_dist::WriteReq 13911 # Transaction distribution 595system.membus.trans_dist::WriteResp 13911 # Transaction distribution | 592system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 593system.membus.trans_dist::ReadReq 13903768 # Transaction distribution 594system.membus.trans_dist::ReadResp 13903768 # Transaction distribution 595system.membus.trans_dist::WriteReq 13911 # Transaction distribution 596system.membus.trans_dist::WriteResp 13911 # Transaction distribution |
| 596system.membus.trans_dist::Writeback 98349 # Transaction distribution | 597system.membus.trans_dist::Writeback 145018 # Transaction distribution |
| 597system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 598system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 599system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution 600system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution | 598system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 599system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 600system.membus.trans_dist::UpgradeReq 2525 # Transaction distribution 601system.membus.trans_dist::UpgradeResp 2096 # Transaction distribution |
| 601system.membus.trans_dist::ReadExReq 134620 # Transaction distribution 602system.membus.trans_dist::ReadExResp 134615 # Transaction distribution | 602system.membus.trans_dist::ReadExReq 134621 # Transaction distribution 603system.membus.trans_dist::ReadExResp 134616 # Transaction distribution |
| 603system.membus.trans_dist::MessageReq 1696 # Transaction distribution 604system.membus.trans_dist::MessageResp 1696 # Transaction distribution 605system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) 606system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) 607system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes) 608system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) | 604system.membus.trans_dist::MessageReq 1696 # Transaction distribution 605system.membus.trans_dist::MessageResp 1696 # Transaction distribution 606system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) 607system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) 608system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes) 609system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) |
| 609system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes) 610system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes) 611system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes) 612system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes) 613system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes) | 610system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463319 # Packet count per connected master and slave (bytes) 611system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205751 # Packet count per connected master and slave (bytes) 612system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141923 # Packet count per connected master and slave (bytes) 613system.membus.pkt_count_system.iocache.mem_side::total 141923 # Packet count per connected master and slave (bytes) 614system.membus.pkt_count::total 28351066 # Packet count per connected master and slave (bytes) |
| 614system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) 615system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) 616system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes) 617system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) | 615system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) 616system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) 617system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes) 618system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) |
| 618system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes) 619system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes) 620system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes) 621system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes) 622system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes) | 619system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825408 # Cumulative packet size per connected master and slave (bytes) 620system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43250105 # Cumulative packet size per connected master and slave (bytes) 621system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034880 # Cumulative packet size per connected master and slave (bytes) 622system.membus.pkt_size_system.iocache.mem_side::total 6034880 # Cumulative packet size per connected master and slave (bytes) 623system.membus.pkt_size::total 49291769 # Cumulative packet size per connected master and slave (bytes) |
| 623system.membus.snoops 0 # Total snoops (count) | 624system.membus.snoops 0 # Total snoops (count) |
| 624system.membus.snoop_fanout::samples 328677 # Request fanout histogram | 625system.membus.snoop_fanout::samples 375347 # Request fanout histogram |
| 625system.membus.snoop_fanout::mean 1 # Request fanout histogram 626system.membus.snoop_fanout::stdev 0 # Request fanout histogram 627system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 628system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 626system.membus.snoop_fanout::mean 1 # Request fanout histogram 627system.membus.snoop_fanout::stdev 0 # Request fanout histogram 628system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 629system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 629system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram | 630system.membus.snoop_fanout::1 375347 100.00% 100.00% # Request fanout histogram |
| 630system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 631system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 632system.membus.snoop_fanout::min_value 1 # Request fanout histogram 633system.membus.snoop_fanout::max_value 1 # Request fanout histogram | 631system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 632system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 633system.membus.snoop_fanout::min_value 1 # Request fanout histogram 634system.membus.snoop_fanout::max_value 1 # Request fanout histogram |
| 634system.membus.snoop_fanout::total 328677 # Request fanout histogram | 635system.membus.snoop_fanout::total 375347 # Request fanout histogram |
| 635system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 636system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 637system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 638system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 639system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 640system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 641system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 642system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 643system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 644system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 645system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 646system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 647 648---------- End Simulation Statistics ---------- | 636system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 637system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 638system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 639system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 640system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 641system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 642system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 643system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 644system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 645system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 646system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 647system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 648 649---------- End Simulation Statistics ---------- |