| stats.txt (10220:9eab5efc02e8) | stats.txt (10352:5f1f92bf76ee) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112126 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112126 # Number of seconds simulated |
| 4sim_ticks 5112126264500 # Number of ticks simulated 5final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 5112125984500 # Number of ticks simulated 5final_tick 5112125984500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1285356 # Simulator instruction rate (inst/s) 8host_op_rate 2631685 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32866027497 # Simulator tick rate (ticks/s) 10host_mem_usage 626676 # Number of bytes of host memory used 11host_seconds 155.54 # Real time elapsed on the host 12sim_insts 199929810 # Number of instructions simulated 13sim_ops 409343850 # Number of ops (including micro ops) simulated | 7host_inst_rate 1274105 # Simulator instruction rate (inst/s) 8host_op_rate 2608650 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32578287771 # Simulator tick rate (ticks/s) 10host_mem_usage 593532 # Number of bytes of host memory used 11host_seconds 156.92 # Real time elapsed on the host 12sim_insts 199930130 # Number of instructions simulated 13sim_ops 409344539 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory | 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory 21system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory 26system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::cpu.inst 852800 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10650880 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11532416 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 852800 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 852800 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6281856 # Number of bytes written to this memory 25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory 26system.physmem.bytes_written::total 9271936 # Number of bytes written to this memory 27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory 34system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s) | 30system.physmem.num_reads::cpu.inst 13325 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 166420 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 180194 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 98154 # Number of write requests responded to by this memory 34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 144874 # Number of write requests responded to by this memory 36system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) | 37system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2715827 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_read::cpu.inst 166819 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 2083454 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2255894 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 166819 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 166819 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1228815 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 584900 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1813714 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1228815 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::pc.south_bridge.ide 590446 # Total bandwidth to/from this memory (bytes/s) |
| 46system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) | 49system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) |
| 48system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s) 51system.membus.throughput 9634332 # Throughput (bytes/s) 52system.membus.data_through_bus 49251923 # Total data (bytes) | 51system.physmem.bw_total::cpu.inst 166819 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 2083454 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 4069609 # Total bandwidth to/from this memory (bytes/s) 54system.membus.throughput 9050072 # Throughput (bytes/s) 55system.membus.data_through_bus 46265107 # Total data (bytes) |
| 53system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 54system.iocache.tags.replacements 47569 # number of replacements | 56system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 57system.iocache.tags.replacements 47569 # number of replacements |
| 55system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use | 58system.iocache.tags.tagsinuse 0.042447 # Cycle average of tags in use |
| 56system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 57system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 58system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 59system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. | 59system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 60system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 61system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 62system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. |
| 60system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor | 63system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042447 # Average occupied blocks per requestor |
| 61system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 62system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 63system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 64system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 65system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 66system.iocache.tags.tag_accesses 428616 # Number of tag accesses 67system.iocache.tags.data_accesses 428616 # Number of data accesses | 64system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 65system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 66system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 67system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 68system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 69system.iocache.tags.tag_accesses 428616 # Number of tag accesses 70system.iocache.tags.data_accesses 428616 # Number of data accesses |
| 71system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 72system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits |
|
| 68system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 69system.iocache.ReadReq_misses::total 904 # number of ReadReq misses | 73system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 74system.iocache.ReadReq_misses::total 904 # number of ReadReq misses |
| 70system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 71system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 72system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 73system.iocache.demand_misses::total 47624 # number of demand (read+write) misses 74system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 75system.iocache.overall_misses::total 47624 # number of overall misses | 75system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses 76system.iocache.demand_misses::total 904 # number of demand (read+write) misses 77system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses 78system.iocache.overall_misses::total 904 # number of overall misses |
| 76system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 77system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) | 79system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 80system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) |
| 78system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 79system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 80system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 81system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 82system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 83system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses | 81system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 82system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 83system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses 84system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses 85system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses 86system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses |
| 84system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 85system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses | 87system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 88system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses |
| 86system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 87system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses | |
| 88system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 89system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 90system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 91system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 92system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 93system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 94system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 95system.iocache.blocked::no_targets 0 # number of cycles access was blocked 96system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 97system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 89system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 90system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 91system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 92system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 93system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 94system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 95system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 96system.iocache.blocked::no_targets 0 # number of cycles access was blocked 97system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 98system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 98system.iocache.fast_writes 0 # number of fast writes performed | 99system.iocache.fast_writes 46720 # number of fast writes performed |
| 99system.iocache.cache_copies 0 # number of cache copies performed | 100system.iocache.cache_copies 0 # number of cache copies performed |
| 100system.iocache.writebacks::writebacks 46667 # number of writebacks 101system.iocache.writebacks::total 46667 # number of writebacks | |
| 102system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 103system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 104system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 105system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 106system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 107system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 108system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 109system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 110system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 111system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 112system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 113system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 114system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 115system.iobus.throughput 2555207 # Throughput (bytes/s) 116system.iobus.data_through_bus 13062542 # Total data (bytes) 117system.cpu_clk_domain.clock 500 # Clock period in ticks 118system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks | 101system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 102system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 103system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 104system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 105system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 106system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 107system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 108system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 109system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 110system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 111system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 112system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 113system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 114system.iobus.throughput 2555207 # Throughput (bytes/s) 115system.iobus.data_through_bus 13062542 # Total data (bytes) 116system.cpu_clk_domain.clock 500 # Clock period in ticks 117system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
| 119system.cpu.numCycles 10224253904 # number of cpu cycles simulated | 118system.cpu.numCycles 10224253344 # number of cpu cycles simulated |
| 120system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 121system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 119system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 120system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 122system.cpu.committedInsts 199929810 # Number of instructions committed 123system.cpu.committedOps 409343850 # Number of ops (including micro ops) committed 124system.cpu.num_int_alu_accesses 374364636 # Number of integer alu accesses | 121system.cpu.committedInsts 199930130 # Number of instructions committed 122system.cpu.committedOps 409344539 # Number of ops (including micro ops) committed 123system.cpu.num_int_alu_accesses 374365317 # Number of integer alu accesses |
| 125system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses | 124system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses |
| 126system.cpu.num_func_calls 2307717 # number of times a function call or return occured 127system.cpu.num_conditional_control_insts 39976328 # number of instructions that are conditional controls 128system.cpu.num_int_insts 374364636 # number of integer instructions | 125system.cpu.num_func_calls 2307745 # number of times a function call or return occured 126system.cpu.num_conditional_control_insts 39976374 # number of instructions that are conditional controls 127system.cpu.num_int_insts 374365317 # number of integer instructions |
| 129system.cpu.num_fp_insts 0 # number of float instructions | 128system.cpu.num_fp_insts 0 # number of float instructions |
| 130system.cpu.num_int_register_reads 682285475 # number of times the integer registers were read 131system.cpu.num_int_register_writes 323369236 # number of times the integer registers were written | 129system.cpu.num_int_register_reads 682286798 # number of times the integer registers were read 130system.cpu.num_int_register_writes 323369753 # number of times the integer registers were written |
| 132system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 133system.cpu.num_fp_register_writes 0 # number of times the floating registers were written | 131system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 132system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| 134system.cpu.num_cc_register_reads 233715040 # number of times the CC registers were read 135system.cpu.num_cc_register_writes 157233555 # number of times the CC registers were written 136system.cpu.num_mem_refs 35660913 # number of memory refs 137system.cpu.num_load_insts 27238816 # Number of load instructions 138system.cpu.num_store_insts 8422097 # Number of store instructions 139system.cpu.num_idle_cycles 9770518213.691833 # Number of idle cycles 140system.cpu.num_busy_cycles 453735690.308166 # Number of busy cycles | 133system.cpu.num_cc_register_reads 233715334 # number of times the CC registers were read 134system.cpu.num_cc_register_writes 157233726 # number of times the CC registers were written 135system.cpu.num_mem_refs 35661072 # number of memory refs 136system.cpu.num_load_insts 27238907 # Number of load instructions 137system.cpu.num_store_insts 8422165 # Number of store instructions 138system.cpu.num_idle_cycles 9770516870.697727 # Number of idle cycles 139system.cpu.num_busy_cycles 453736473.302274 # Number of busy cycles |
| 141system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles 142system.cpu.idle_fraction 0.955622 # Percentage of idle cycles | 140system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles 141system.cpu.idle_fraction 0.955622 # Percentage of idle cycles |
| 143system.cpu.Branches 43125514 # Number of branches fetched 144system.cpu.op_class::No_OpClass 175310 0.04% 0.04% # Class of executed instruction 145system.cpu.op_class::IntAlu 373241321 91.18% 91.22% # Class of executed instruction 146system.cpu.op_class::IntMult 144368 0.04% 91.26% # Class of executed instruction | 142system.cpu.Branches 43125613 # Number of branches fetched 143system.cpu.op_class::No_OpClass 175318 0.04% 0.04% # Class of executed instruction 144system.cpu.op_class::IntAlu 373241846 91.18% 91.22% # Class of executed instruction 145system.cpu.op_class::IntMult 144365 0.04% 91.26% # Class of executed instruction |
| 147system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction 148system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction 149system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction 150system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction 151system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction 152system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction 153system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction 154system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 166system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction 167system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction 168system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction 169system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction 170system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction 171system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction 172system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction 173system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction | 146system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction 147system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction 148system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction 149system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction 150system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction 151system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction 152system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction 153system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction --- 11 unchanged lines hidden (view full) --- 165system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction 166system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction 167system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction 168system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction 169system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction 170system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction 171system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction 172system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction |
| 174system.cpu.op_class::MemRead 27238816 6.65% 97.94% # Class of executed instruction 175system.cpu.op_class::MemWrite 8422097 2.06% 100.00% # Class of executed instruction | 173system.cpu.op_class::MemRead 27238907 6.65% 97.94% # Class of executed instruction 174system.cpu.op_class::MemWrite 8422165 2.06% 100.00% # Class of executed instruction |
| 176system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 177system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 175system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 176system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 178system.cpu.op_class::total 409344880 # Class of executed instruction | 177system.cpu.op_class::total 409345569 # Class of executed instruction |
| 179system.cpu.kern.inst.arm 0 # number of arm instructions executed 180system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed | 178system.cpu.kern.inst.arm 0 # number of arm instructions executed 179system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
| 181system.cpu.icache.tags.replacements 790558 # number of replacements | 180system.cpu.icache.tags.replacements 790679 # number of replacements |
| 182system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use | 181system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use |
| 183system.cpu.icache.tags.total_refs 243525778 # Total number of references to valid blocks. 184system.cpu.icache.tags.sampled_refs 791070 # Sample count of references to valid blocks. 185system.cpu.icache.tags.avg_refs 307.843526 # Average number of references to valid blocks. | 182system.cpu.icache.tags.total_refs 243526070 # Total number of references to valid blocks. 183system.cpu.icache.tags.sampled_refs 791191 # Sample count of references to valid blocks. 184system.cpu.icache.tags.avg_refs 307.796815 # Average number of references to valid blocks. |
| 186system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. 187system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor 188system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy 189system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy 190system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 191system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 192system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 193system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id 194system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 185system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. 186system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor 187system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy 188system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy 189system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 190system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 191system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 192system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id 193system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 195system.cpu.icache.tags.tag_accesses 245107932 # Number of tag accesses 196system.cpu.icache.tags.data_accesses 245107932 # Number of data accesses 197system.cpu.icache.ReadReq_hits::cpu.inst 243525778 # number of ReadReq hits 198system.cpu.icache.ReadReq_hits::total 243525778 # number of ReadReq hits 199system.cpu.icache.demand_hits::cpu.inst 243525778 # number of demand (read+write) hits 200system.cpu.icache.demand_hits::total 243525778 # number of demand (read+write) hits 201system.cpu.icache.overall_hits::cpu.inst 243525778 # number of overall hits 202system.cpu.icache.overall_hits::total 243525778 # number of overall hits 203system.cpu.icache.ReadReq_misses::cpu.inst 791077 # number of ReadReq misses 204system.cpu.icache.ReadReq_misses::total 791077 # number of ReadReq misses 205system.cpu.icache.demand_misses::cpu.inst 791077 # number of demand (read+write) misses 206system.cpu.icache.demand_misses::total 791077 # number of demand (read+write) misses 207system.cpu.icache.overall_misses::cpu.inst 791077 # number of overall misses 208system.cpu.icache.overall_misses::total 791077 # number of overall misses 209system.cpu.icache.ReadReq_accesses::cpu.inst 244316855 # number of ReadReq accesses(hits+misses) 210system.cpu.icache.ReadReq_accesses::total 244316855 # number of ReadReq accesses(hits+misses) 211system.cpu.icache.demand_accesses::cpu.inst 244316855 # number of demand (read+write) accesses 212system.cpu.icache.demand_accesses::total 244316855 # number of demand (read+write) accesses 213system.cpu.icache.overall_accesses::cpu.inst 244316855 # number of overall (read+write) accesses 214system.cpu.icache.overall_accesses::total 244316855 # number of overall (read+write) accesses | 194system.cpu.icache.tags.tag_accesses 245108466 # Number of tag accesses 195system.cpu.icache.tags.data_accesses 245108466 # Number of data accesses 196system.cpu.icache.ReadReq_hits::cpu.inst 243526070 # number of ReadReq hits 197system.cpu.icache.ReadReq_hits::total 243526070 # number of ReadReq hits 198system.cpu.icache.demand_hits::cpu.inst 243526070 # number of demand (read+write) hits 199system.cpu.icache.demand_hits::total 243526070 # number of demand (read+write) hits 200system.cpu.icache.overall_hits::cpu.inst 243526070 # number of overall hits 201system.cpu.icache.overall_hits::total 243526070 # number of overall hits 202system.cpu.icache.ReadReq_misses::cpu.inst 791198 # number of ReadReq misses 203system.cpu.icache.ReadReq_misses::total 791198 # number of ReadReq misses 204system.cpu.icache.demand_misses::cpu.inst 791198 # number of demand (read+write) misses 205system.cpu.icache.demand_misses::total 791198 # number of demand (read+write) misses 206system.cpu.icache.overall_misses::cpu.inst 791198 # number of overall misses 207system.cpu.icache.overall_misses::total 791198 # number of overall misses 208system.cpu.icache.ReadReq_accesses::cpu.inst 244317268 # number of ReadReq accesses(hits+misses) 209system.cpu.icache.ReadReq_accesses::total 244317268 # number of ReadReq accesses(hits+misses) 210system.cpu.icache.demand_accesses::cpu.inst 244317268 # number of demand (read+write) accesses 211system.cpu.icache.demand_accesses::total 244317268 # number of demand (read+write) accesses 212system.cpu.icache.overall_accesses::cpu.inst 244317268 # number of overall (read+write) accesses 213system.cpu.icache.overall_accesses::total 244317268 # number of overall (read+write) accesses |
| 215system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 216system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 217system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 218system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 219system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 220system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 221system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 222system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 223system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 224system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 225system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 226system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 227system.cpu.icache.fast_writes 0 # number of fast writes performed 228system.cpu.icache.cache_copies 0 # number of cache copies performed 229system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 230system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements | 214system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 215system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 216system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 217system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 218system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 219system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 220system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 221system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 222system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 223system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 224system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 225system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 226system.cpu.icache.fast_writes 0 # number of fast writes performed 227system.cpu.icache.cache_copies 0 # number of cache copies performed 228system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 229system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements |
| 231system.cpu.itb_walker_cache.tags.tagsinuse 3.026303 # Cycle average of tags in use | 230system.cpu.itb_walker_cache.tags.tagsinuse 3.026310 # Cycle average of tags in use |
| 232system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 233system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 234system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. | 231system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 232system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 233system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. |
| 235system.cpu.itb_walker_cache.tags.warmup_cycle 5102116468000 # Cycle when the warmup percentage was hit. 236system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026303 # Average occupied blocks per requestor | 234system.cpu.itb_walker_cache.tags.warmup_cycle 5102111082500 # Cycle when the warmup percentage was hit. 235system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026310 # Average occupied blocks per requestor |
| 237system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy 238system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy 239system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 240system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 241system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 242system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 243system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id 244system.cpu.itb_walker_cache.tags.tag_accesses 28774 # Number of tag accesses --- 33 unchanged lines hidden (view full) --- 278system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 279system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 280system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 281system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 282system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 283system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 284system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 285system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements | 236system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy 237system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy 238system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 239system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 240system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 241system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 242system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id 243system.cpu.itb_walker_cache.tags.tag_accesses 28774 # Number of tag accesses --- 33 unchanged lines hidden (view full) --- 277system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 278system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 279system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 280system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 281system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 282system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 283system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 284system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements |
| 286system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use 287system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks. | 285system.cpu.dtb_walker_cache.tags.tagsinuse 5.014183 # Cycle average of tags in use 286system.cpu.dtb_walker_cache.tags.total_refs 12951 # Total number of references to valid blocks. |
| 288system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. | 287system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. |
| 289system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks. 290system.cpu.dtb_walker_cache.tags.warmup_cycle 5100462243000 # Cycle when the warmup percentage was hit. 291system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor | 288system.cpu.dtb_walker_cache.tags.avg_refs 1.694270 # Average number of references to valid blocks. 289system.cpu.dtb_walker_cache.tags.warmup_cycle 5100459675500 # Cycle when the warmup percentage was hit. 290system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014183 # Average occupied blocks per requestor |
| 292system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 293system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 294system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 295system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 296system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 297system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 298system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id | 291system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 292system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 293system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id 294system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 295system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 296system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 297system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id |
| 299system.cpu.dtb_walker_cache.tags.tag_accesses 52398 # Number of tag accesses 300system.cpu.dtb_walker_cache.tags.data_accesses 52398 # Number of data accesses 301system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits 302system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits 303system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits 304system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits 305system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits 306system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits | 298system.cpu.dtb_walker_cache.tags.tag_accesses 52390 # Number of tag accesses 299system.cpu.dtb_walker_cache.tags.data_accesses 52390 # Number of data accesses 300system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12959 # number of ReadReq hits 301system.cpu.dtb_walker_cache.ReadReq_hits::total 12959 # number of ReadReq hits 302system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12959 # number of demand (read+write) hits 303system.cpu.dtb_walker_cache.demand_hits::total 12959 # number of demand (read+write) hits 304system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12959 # number of overall hits 305system.cpu.dtb_walker_cache.overall_hits::total 12959 # number of overall hits |
| 307system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses 308system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses 309system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses 310system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses 311system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses 312system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses | 306system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses 307system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses 308system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses 309system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses 310system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses 311system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses |
| 313system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses) 314system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses) 315system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses 316system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses 317system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses 318system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses 319system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses 320system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses 321system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses 322system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses 323system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses 324system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses | 312system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21783 # number of ReadReq accesses(hits+misses) 313system.cpu.dtb_walker_cache.ReadReq_accesses::total 21783 # number of ReadReq accesses(hits+misses) 314system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21783 # number of demand (read+write) accesses 315system.cpu.dtb_walker_cache.demand_accesses::total 21783 # number of demand (read+write) accesses 316system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21783 # number of overall (read+write) accesses 317system.cpu.dtb_walker_cache.overall_accesses::total 21783 # number of overall (read+write) accesses 318system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405087 # miss rate for ReadReq accesses 319system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405087 # miss rate for ReadReq accesses 320system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405087 # miss rate for demand accesses 321system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405087 # miss rate for demand accesses 322system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405087 # miss rate for overall accesses 323system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405087 # miss rate for overall accesses |
| 325system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 326system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 327system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 328system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 329system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 330system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 331system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 332system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 333system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks 334system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks 335system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate | 324system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 325system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 326system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 327system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 328system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 329system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 330system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 331system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 332system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks 333system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks 334system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 336system.cpu.dcache.tags.replacements 1622097 # number of replacements | 335system.cpu.dcache.tags.replacements 1622084 # number of replacements |
| 337system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use | 336system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use |
| 338system.cpu.dcache.tags.total_refs 20175179 # Total number of references to valid blocks. 339system.cpu.dcache.tags.sampled_refs 1622609 # Sample count of references to valid blocks. 340system.cpu.dcache.tags.avg_refs 12.433790 # Average number of references to valid blocks. | 337system.cpu.dcache.tags.total_refs 20175355 # Total number of references to valid blocks. 338system.cpu.dcache.tags.sampled_refs 1622596 # Sample count of references to valid blocks. 339system.cpu.dcache.tags.avg_refs 12.433998 # Average number of references to valid blocks. |
| 341system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 342system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 343system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 344system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 345system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 346system.cpu.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id 347system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id 348system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id 349system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 340system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 341system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 342system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 343system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 344system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 345system.cpu.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id 346system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id 347system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id 348system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 350system.cpu.dcache.tags.tag_accesses 88813841 # Number of tag accesses 351system.cpu.dcache.tags.data_accesses 88813841 # Number of data accesses 352system.cpu.dcache.ReadReq_hits::cpu.data 12077531 # number of ReadReq hits 353system.cpu.dcache.ReadReq_hits::total 12077531 # number of ReadReq hits 354system.cpu.dcache.WriteReq_hits::cpu.data 8095378 # number of WriteReq hits 355system.cpu.dcache.WriteReq_hits::total 8095378 # number of WriteReq hits 356system.cpu.dcache.demand_hits::cpu.data 20172909 # number of demand (read+write) hits 357system.cpu.dcache.demand_hits::total 20172909 # number of demand (read+write) hits 358system.cpu.dcache.overall_hits::cpu.data 20172909 # number of overall hits 359system.cpu.dcache.overall_hits::total 20172909 # number of overall hits 360system.cpu.dcache.ReadReq_misses::cpu.data 1308430 # number of ReadReq misses 361system.cpu.dcache.ReadReq_misses::total 1308430 # number of ReadReq misses 362system.cpu.dcache.WriteReq_misses::cpu.data 316465 # number of WriteReq misses 363system.cpu.dcache.WriteReq_misses::total 316465 # number of WriteReq misses 364system.cpu.dcache.demand_misses::cpu.data 1624895 # number of demand (read+write) misses 365system.cpu.dcache.demand_misses::total 1624895 # number of demand (read+write) misses 366system.cpu.dcache.overall_misses::cpu.data 1624895 # number of overall misses 367system.cpu.dcache.overall_misses::total 1624895 # number of overall misses 368system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses) 369system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses) 370system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses) 371system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses) 372system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses 373system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses 374system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses 375system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses 376system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses 377system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses | 349system.cpu.dcache.tags.tag_accesses 88814480 # Number of tag accesses 350system.cpu.dcache.tags.data_accesses 88814480 # Number of data accesses 351system.cpu.dcache.ReadReq_hits::cpu.data 12018728 # number of ReadReq hits 352system.cpu.dcache.ReadReq_hits::total 12018728 # number of ReadReq hits 353system.cpu.dcache.WriteReq_hits::cpu.data 8095451 # number of WriteReq hits 354system.cpu.dcache.WriteReq_hits::total 8095451 # number of WriteReq hits 355system.cpu.dcache.SoftPFReq_hits::cpu.data 58906 # number of SoftPFReq hits 356system.cpu.dcache.SoftPFReq_hits::total 58906 # number of SoftPFReq hits 357system.cpu.dcache.demand_hits::cpu.data 20114179 # number of demand (read+write) hits 358system.cpu.dcache.demand_hits::total 20114179 # number of demand (read+write) hits 359system.cpu.dcache.overall_hits::cpu.data 20173085 # number of overall hits 360system.cpu.dcache.overall_hits::total 20173085 # number of overall hits 361system.cpu.dcache.ReadReq_misses::cpu.data 905666 # number of ReadReq misses 362system.cpu.dcache.ReadReq_misses::total 905666 # number of ReadReq misses 363system.cpu.dcache.WriteReq_misses::cpu.data 316462 # number of WriteReq misses 364system.cpu.dcache.WriteReq_misses::total 316462 # number of WriteReq misses 365system.cpu.dcache.SoftPFReq_misses::cpu.data 402754 # number of SoftPFReq misses 366system.cpu.dcache.SoftPFReq_misses::total 402754 # number of SoftPFReq misses 367system.cpu.dcache.demand_misses::cpu.data 1222128 # number of demand (read+write) misses 368system.cpu.dcache.demand_misses::total 1222128 # number of demand (read+write) misses 369system.cpu.dcache.overall_misses::cpu.data 1624882 # number of overall misses 370system.cpu.dcache.overall_misses::total 1624882 # number of overall misses 371system.cpu.dcache.ReadReq_accesses::cpu.data 12924394 # number of ReadReq accesses(hits+misses) 372system.cpu.dcache.ReadReq_accesses::total 12924394 # number of ReadReq accesses(hits+misses) 373system.cpu.dcache.WriteReq_accesses::cpu.data 8411913 # number of WriteReq accesses(hits+misses) 374system.cpu.dcache.WriteReq_accesses::total 8411913 # number of WriteReq accesses(hits+misses) 375system.cpu.dcache.SoftPFReq_accesses::cpu.data 461660 # number of SoftPFReq accesses(hits+misses) 376system.cpu.dcache.SoftPFReq_accesses::total 461660 # number of SoftPFReq accesses(hits+misses) 377system.cpu.dcache.demand_accesses::cpu.data 21336307 # number of demand (read+write) accesses 378system.cpu.dcache.demand_accesses::total 21336307 # number of demand (read+write) accesses 379system.cpu.dcache.overall_accesses::cpu.data 21797967 # number of overall (read+write) accesses 380system.cpu.dcache.overall_accesses::total 21797967 # number of overall (read+write) accesses 381system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070074 # miss rate for ReadReq accesses 382system.cpu.dcache.ReadReq_miss_rate::total 0.070074 # miss rate for ReadReq accesses |
| 378system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses 379system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses | 383system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses 384system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses |
| 380system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses 381system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses 382system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses 383system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses | 385system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872404 # miss rate for SoftPFReq accesses 386system.cpu.dcache.SoftPFReq_miss_rate::total 0.872404 # miss rate for SoftPFReq accesses 387system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses 388system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses 389system.cpu.dcache.overall_miss_rate::cpu.data 0.074543 # miss rate for overall accesses 390system.cpu.dcache.overall_miss_rate::total 0.074543 # miss rate for overall accesses |
| 384system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 385system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 386system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 387system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 388system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 389system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 390system.cpu.dcache.fast_writes 0 # number of fast writes performed 391system.cpu.dcache.cache_copies 0 # number of cache copies performed | 391system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 392system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 393system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 394system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 395system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 396system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 397system.cpu.dcache.fast_writes 0 # number of fast writes performed 398system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 392system.cpu.dcache.writebacks::writebacks 1535825 # number of writebacks 393system.cpu.dcache.writebacks::total 1535825 # number of writebacks | 399system.cpu.dcache.writebacks::writebacks 1535815 # number of writebacks 400system.cpu.dcache.writebacks::total 1535815 # number of writebacks |
| 394system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 401system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 395system.cpu.toL2Bus.throughput 54625221 # Throughput (bytes/s) 396system.cpu.toL2Bus.data_through_bus 279225555 # Total data (bytes) 397system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) 398system.cpu.l2cache.tags.replacements 105999 # number of replacements 399system.cpu.l2cache.tags.tagsinuse 64822.034013 # Cycle average of tags in use 400system.cpu.l2cache.tags.total_refs 3456623 # Total number of references to valid blocks. 401system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks. 402system.cpu.l2cache.tags.avg_refs 20.317898 # Average number of references to valid blocks. | 402system.cpu.toL2Bus.throughput 55211163 # Throughput (bytes/s) 403system.cpu.toL2Bus.data_through_bus 279231827 # Total data (bytes) 404system.cpu.toL2Bus.snoop_data_through_bus 3014592 # Total snoop data (bytes) 405system.cpu.l2cache.tags.replacements 105997 # number of replacements 406system.cpu.l2cache.tags.tagsinuse 64822.035422 # Cycle average of tags in use 407system.cpu.l2cache.tags.total_refs 3456726 # Total number of references to valid blocks. 408system.cpu.l2cache.tags.sampled_refs 170125 # Sample count of references to valid blocks. 409system.cpu.l2cache.tags.avg_refs 20.318742 # Average number of references to valid blocks. |
| 403system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 410system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 404system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839094 # Average occupied blocks per requestor | 411system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839631 # Average occupied blocks per requestor |
| 405system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor | 412system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor |
| 406system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor 407system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.539598 # Average occupied blocks per requestor 408system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.520587 # Average occupied blocks per requestor | 413system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132256 # Average occupied blocks per requestor 414system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.541573 # Average occupied blocks per requestor 415system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.519483 # Average occupied blocks per requestor |
| 409system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy 410system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 411system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 412system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 413system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy 414system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy 415system.cpu.l2cache.tags.occ_task_id_blocks::1024 64128 # Occupied blocks per task id 416system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 417system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id 418system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id | 416system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy 417system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 418system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 419system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 420system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy 421system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy 422system.cpu.l2cache.tags.occ_task_id_blocks::1024 64128 # Occupied blocks per task id 423system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 424system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id 425system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id |
| 419system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20892 # Occupied blocks per task id 420system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39453 # Occupied blocks per task id | 426system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20884 # Occupied blocks per task id 427system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39461 # Occupied blocks per task id |
| 421system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id | 428system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id |
| 422system.cpu.l2cache.tags.tag_accesses 32198887 # Number of tag accesses 423system.cpu.l2cache.tags.data_accesses 32198887 # Number of data accesses | 429system.cpu.l2cache.tags.tag_accesses 32199668 # Number of tag accesses 430system.cpu.l2cache.tags.data_accesses 32199668 # Number of data accesses |
| 424system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits 425system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits | 431system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits 432system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits |
| 426system.cpu.l2cache.ReadReq_hits::cpu.inst 777739 # number of ReadReq hits 427system.cpu.l2cache.ReadReq_hits::cpu.data 1275554 # number of ReadReq hits 428system.cpu.l2cache.ReadReq_hits::total 2062599 # number of ReadReq hits 429system.cpu.l2cache.Writeback_hits::writebacks 1538784 # number of Writeback hits 430system.cpu.l2cache.Writeback_hits::total 1538784 # number of Writeback hits | 433system.cpu.l2cache.ReadReq_hits::cpu.inst 777860 # number of ReadReq hits 434system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits 435system.cpu.l2cache.ReadReq_hits::total 2062710 # number of ReadReq hits 436system.cpu.l2cache.Writeback_hits::writebacks 1538774 # number of Writeback hits 437system.cpu.l2cache.Writeback_hits::total 1538774 # number of Writeback hits |
| 431system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 432system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits | 438system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 439system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits |
| 433system.cpu.l2cache.ReadExReq_hits::cpu.data 179732 # number of ReadExReq hits 434system.cpu.l2cache.ReadExReq_hits::total 179732 # number of ReadExReq hits | 440system.cpu.l2cache.ReadExReq_hits::cpu.data 179729 # number of ReadExReq hits 441system.cpu.l2cache.ReadExReq_hits::total 179729 # number of ReadExReq hits |
| 435system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits 436system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits | 442system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits 443system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits |
| 437system.cpu.l2cache.demand_hits::cpu.inst 777739 # number of demand (read+write) hits 438system.cpu.l2cache.demand_hits::cpu.data 1455286 # number of demand (read+write) hits 439system.cpu.l2cache.demand_hits::total 2242331 # number of demand (read+write) hits | 444system.cpu.l2cache.demand_hits::cpu.inst 777860 # number of demand (read+write) hits 445system.cpu.l2cache.demand_hits::cpu.data 1455273 # number of demand (read+write) hits 446system.cpu.l2cache.demand_hits::total 2242439 # number of demand (read+write) hits |
| 440system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits 441system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits | 447system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits 448system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits |
| 442system.cpu.l2cache.overall_hits::cpu.inst 777739 # number of overall hits 443system.cpu.l2cache.overall_hits::cpu.data 1455286 # number of overall hits 444system.cpu.l2cache.overall_hits::total 2242331 # number of overall hits | 449system.cpu.l2cache.overall_hits::cpu.inst 777860 # number of overall hits 450system.cpu.l2cache.overall_hits::cpu.data 1455273 # number of overall hits 451system.cpu.l2cache.overall_hits::total 2242439 # number of overall hits |
| 445system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 446system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 447system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 448system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 449system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses 450system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses 451system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses 452system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses --- 5 unchanged lines hidden (view full) --- 458system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses 459system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 460system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 461system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 462system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses 463system.cpu.l2cache.overall_misses::total 180035 # number of overall misses 464system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses) 465system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) | 452system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 453system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 454system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 455system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 456system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses 457system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses 458system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses 459system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses --- 5 unchanged lines hidden (view full) --- 465system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses 466system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 467system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 468system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 469system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses 470system.cpu.l2cache.overall_misses::total 180035 # number of overall misses 471system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses) 472system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) |
| 466system.cpu.l2cache.ReadReq_accesses::cpu.inst 791064 # number of ReadReq accesses(hits+misses) 467system.cpu.l2cache.ReadReq_accesses::cpu.data 1307800 # number of ReadReq accesses(hits+misses) 468system.cpu.l2cache.ReadReq_accesses::total 2108176 # number of ReadReq accesses(hits+misses) 469system.cpu.l2cache.Writeback_accesses::writebacks 1538784 # number of Writeback accesses(hits+misses) 470system.cpu.l2cache.Writeback_accesses::total 1538784 # number of Writeback accesses(hits+misses) | 473system.cpu.l2cache.ReadReq_accesses::cpu.inst 791185 # number of ReadReq accesses(hits+misses) 474system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses) 475system.cpu.l2cache.ReadReq_accesses::total 2108287 # number of ReadReq accesses(hits+misses) 476system.cpu.l2cache.Writeback_accesses::writebacks 1538774 # number of Writeback accesses(hits+misses) 477system.cpu.l2cache.Writeback_accesses::total 1538774 # number of Writeback accesses(hits+misses) |
| 471system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) 472system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) | 478system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) 479system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) |
| 473system.cpu.l2cache.ReadExReq_accesses::cpu.data 314190 # number of ReadExReq accesses(hits+misses) 474system.cpu.l2cache.ReadExReq_accesses::total 314190 # number of ReadExReq accesses(hits+misses) | 480system.cpu.l2cache.ReadExReq_accesses::cpu.data 314187 # number of ReadExReq accesses(hits+misses) 481system.cpu.l2cache.ReadExReq_accesses::total 314187 # number of ReadExReq accesses(hits+misses) |
| 475system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses 476system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses | 482system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses 483system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses |
| 477system.cpu.l2cache.demand_accesses::cpu.inst 791064 # number of demand (read+write) accesses 478system.cpu.l2cache.demand_accesses::cpu.data 1621990 # number of demand (read+write) accesses 479system.cpu.l2cache.demand_accesses::total 2422366 # number of demand (read+write) accesses | 484system.cpu.l2cache.demand_accesses::cpu.inst 791185 # number of demand (read+write) accesses 485system.cpu.l2cache.demand_accesses::cpu.data 1621977 # number of demand (read+write) accesses 486system.cpu.l2cache.demand_accesses::total 2422474 # number of demand (read+write) accesses |
| 480system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses 481system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses | 487system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses 488system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses |
| 482system.cpu.l2cache.overall_accesses::cpu.inst 791064 # number of overall (read+write) accesses 483system.cpu.l2cache.overall_accesses::cpu.data 1621990 # number of overall (read+write) accesses 484system.cpu.l2cache.overall_accesses::total 2422366 # number of overall (read+write) accesses | 489system.cpu.l2cache.overall_accesses::cpu.inst 791185 # number of overall (read+write) accesses 490system.cpu.l2cache.overall_accesses::cpu.data 1621977 # number of overall (read+write) accesses 491system.cpu.l2cache.overall_accesses::total 2422474 # number of overall (read+write) accesses |
| 485system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses 486system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses | 492system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses 493system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses |
| 487system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses | 494system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016842 # miss rate for ReadReq accesses |
| 488system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses | 495system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses |
| 489system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses | 496system.cpu.l2cache.ReadReq_miss_rate::total 0.021618 # miss rate for ReadReq accesses |
| 490system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses 491system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses | 497system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses 498system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses |
| 492system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427951 # miss rate for ReadExReq accesses 493system.cpu.l2cache.ReadExReq_miss_rate::total 0.427951 # miss rate for ReadExReq accesses | 499system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427955 # miss rate for ReadExReq accesses 500system.cpu.l2cache.ReadExReq_miss_rate::total 0.427955 # miss rate for ReadExReq accesses |
| 494system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses 495system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses | 501system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses 502system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses |
| 496system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses 497system.cpu.l2cache.demand_miss_rate::cpu.data 0.102777 # miss rate for demand accesses 498system.cpu.l2cache.demand_miss_rate::total 0.074322 # miss rate for demand accesses | 503system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016842 # miss rate for demand accesses 504system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses 505system.cpu.l2cache.demand_miss_rate::total 0.074319 # miss rate for demand accesses |
| 499system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses 500system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses | 506system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses 507system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses |
| 501system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses 502system.cpu.l2cache.overall_miss_rate::cpu.data 0.102777 # miss rate for overall accesses 503system.cpu.l2cache.overall_miss_rate::total 0.074322 # miss rate for overall accesses | 508system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016842 # miss rate for overall accesses 509system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses 510system.cpu.l2cache.overall_miss_rate::total 0.074319 # miss rate for overall accesses |
| 504system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 505system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 506system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 507system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 508system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 509system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 510system.cpu.l2cache.fast_writes 0 # number of fast writes performed 511system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 511system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 512system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 513system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 514system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 515system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 516system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 517system.cpu.l2cache.fast_writes 0 # number of fast writes performed 518system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 512system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks 513system.cpu.l2cache.writebacks::total 98156 # number of writebacks | 519system.cpu.l2cache.writebacks::writebacks 98154 # number of writebacks 520system.cpu.l2cache.writebacks::total 98154 # number of writebacks |
| 514system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 515 516---------- End Simulation Statistics ---------- | 521system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 522 523---------- End Simulation Statistics ---------- |