1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112043 # Number of seconds simulated 4sim_ticks 5112043255000 # Number of ticks simulated 5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 1067695 # Simulator instruction rate (inst/s) 8host_op_rate 2186181 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27315912254 # Simulator tick rate (ticks/s) 10host_mem_usage 409548 # Number of bytes of host memory used 11host_seconds 187.15 # Real time elapsed on the host 12sim_insts 199813914 # Number of instructions simulated 13sim_ops 409133298 # Number of ops (including micro ops) simulated |
14system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10600192 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13919232 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory --- 20 unchanged lines hidden (view full) --- 42system.physmem.bw_total::writebacks 1817825 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 482149 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2073572 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) 49system.l2c.replacements 106561 # number of replacements |
50system.l2c.tagsinuse 64822.143261 # Cycle average of tags in use |
51system.l2c.total_refs 3457342 # Total number of references to valid blocks. 52system.l2c.sampled_refs 170680 # Sample count of references to valid blocks. 53system.l2c.avg_refs 20.256281 # Average number of references to valid blocks. 54system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
55system.l2c.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor |
56system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor 57system.l2c.occ_blocks::cpu.itb.walker 0.132110 # Average occupied blocks per requestor |
58system.l2c.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor 59system.l2c.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor |
60system.l2c.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy 61system.l2c.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 62system.l2c.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 63system.l2c.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy 64system.l2c.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy 65system.l2c.occ_percent::total 0.989107 # Average percentage of cache occupancy 66system.l2c.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits 67system.l2c.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits --- 140 unchanged lines hidden (view full) --- 208system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 209system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 210system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 211system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 212system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 213system.cpu.numCycles 10224086531 # number of cpu cycles simulated 214system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 215system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
216system.cpu.committedInsts 199813914 # Number of instructions committed 217system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed 218system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses |
219system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 220system.cpu.num_func_calls 0 # number of times a function call or return occured |
221system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls 222system.cpu.num_int_insts 374297264 # number of integer instructions |
223system.cpu.num_fp_insts 0 # number of float instructions |
224system.cpu.num_int_register_reads 1159028989 # number of times the integer registers were read 225system.cpu.num_int_register_writes 636431681 # number of times the integer registers were written |
226system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 227system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 228system.cpu.num_mem_refs 35626517 # number of memory refs 229system.cpu.num_load_insts 27217782 # Number of load instructions 230system.cpu.num_store_insts 8408735 # Number of store instructions |
231system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles 232system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles |
233system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles 234system.cpu.idle_fraction 0.955646 # Percentage of idle cycles 235system.cpu.kern.inst.arm 0 # number of arm instructions executed 236system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 237system.cpu.icache.replacements 790793 # number of replacements 238system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use |
239system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks. |
240system.cpu.icache.sampled_refs 791305 # Sample count of references to valid blocks. |
241system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks. 242system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit. |
243system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor 244system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy 245system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy |
246system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits 247system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits 248system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits 249system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits 250system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits 251system.cpu.icache.overall_hits::total 243365779 # number of overall hits |
252system.cpu.icache.ReadReq_misses::cpu.inst 791312 # number of ReadReq misses 253system.cpu.icache.ReadReq_misses::total 791312 # number of ReadReq misses 254system.cpu.icache.demand_misses::cpu.inst 791312 # number of demand (read+write) misses 255system.cpu.icache.demand_misses::total 791312 # number of demand (read+write) misses 256system.cpu.icache.overall_misses::cpu.inst 791312 # number of overall misses 257system.cpu.icache.overall_misses::total 791312 # number of overall misses |
258system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses) 259system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses) 260system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses 261system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses 262system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses 263system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses |
264system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses 265system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses 266system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses 267system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses 268system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses 269system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses 270system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 271system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked --- 155 unchanged lines hidden --- |