1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 5.112127 # Number of seconds simulated 4sim_ticks 5112126720000 # Number of ticks simulated 5final_tick 5112126720000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 1627732 # Simulator instruction rate (inst/s) 8host_op_rate 3332615 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 41616843658 # Simulator tick rate (ticks/s) 10host_mem_usage 647148 # Number of bytes of host memory used 11host_seconds 122.84 # Real time elapsed on the host 12sim_insts 199947158 # Number of instructions simulated 13sim_ops 409371517 # Number of ops (including micro ops) simulated |
14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory |
19system.physmem.bytes_read::cpu.inst 852352 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10669504 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11550592 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 852352 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 852352 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6285632 # Number of bytes written to this memory |
25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory |
26system.physmem.bytes_written::total 9275712 # Number of bytes written to this memory |
27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory |
30system.physmem.num_reads::cpu.inst 13318 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 166711 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 180478 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 98213 # Number of write requests responded to by this memory |
34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory |
35system.physmem.num_writes::total 144933 # Number of write requests responded to by this memory |
36system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) |
39system.physmem.bw_read::cpu.inst 166731 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 2087097 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2259449 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 166731 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 166731 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1229553 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::pc.south_bridge.ide 584899 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1814453 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1229553 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::pc.south_bridge.ide 590445 # Total bandwidth to/from this memory (bytes/s) |
49system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) |
51system.physmem.bw_total::cpu.inst 166731 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 2087097 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 4073902 # Total bandwidth to/from this memory (bytes/s) 54system.membus.trans_dist::ReadReq 13903648 # Transaction distribution 55system.membus.trans_dist::ReadResp 13903648 # Transaction distribution 56system.membus.trans_dist::WriteReq 13796 # Transaction distribution 57system.membus.trans_dist::WriteResp 13796 # Transaction distribution 58system.membus.trans_dist::Writeback 98213 # Transaction distribution 59system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 60system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 61system.membus.trans_dist::UpgradeReq 2521 # Transaction distribution 62system.membus.trans_dist::UpgradeResp 2092 # Transaction distribution 63system.membus.trans_dist::ReadExReq 134490 # Transaction distribution 64system.membus.trans_dist::ReadExResp 134485 # Transaction distribution 65system.membus.trans_dist::MessageReq 1696 # Transaction distribution 66system.membus.trans_dist::MessageResp 1696 # Transaction distribution 67system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) 68system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) 69system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20043728 # Packet count per connected master and slave (bytes) 70system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) 71system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462901 # Packet count per connected master and slave (bytes) 72system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28204873 # Packet count per connected master and slave (bytes) 73system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes) 74system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes) 75system.membus.pkt_count::total 28303521 # Packet count per connected master and slave (bytes) 76system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) 77system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) 78system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10027982 # Cumulative packet size per connected master and slave (bytes) 79system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) 80system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17807872 # Cumulative packet size per connected master and slave (bytes) 81system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43232339 # Cumulative packet size per connected master and slave (bytes) 82system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes) 83system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes) 84system.membus.pkt_size::total 46287315 # Cumulative packet size per connected master and slave (bytes) 85system.membus.snoops 0 # Total snoops (count) 86system.membus.snoop_fanout::samples 328402 # Request fanout histogram 87system.membus.snoop_fanout::mean 1 # Request fanout histogram 88system.membus.snoop_fanout::stdev 0 # Request fanout histogram 89system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 90system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 91system.membus.snoop_fanout::1 328402 100.00% 100.00% # Request fanout histogram 92system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 93system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 94system.membus.snoop_fanout::min_value 1 # Request fanout histogram 95system.membus.snoop_fanout::max_value 1 # Request fanout histogram 96system.membus.snoop_fanout::total 328402 # Request fanout histogram 97system.iocache.tags.replacements 47573 # number of replacements 98system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use |
99system.iocache.tags.total_refs 0 # Total number of references to valid blocks. |
100system.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. |
101system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. |
102system.iocache.tags.warmup_cycle 4994846765009 # Cycle when the warmup percentage was hit. 103system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor |
104system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 105system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 106system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 107system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 108system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id |
109system.iocache.tags.tag_accesses 428652 # Number of tag accesses 110system.iocache.tags.data_accesses 428652 # Number of data accesses |
111system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits 112system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits |
113system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses 114system.iocache.ReadReq_misses::total 908 # number of ReadReq misses 115system.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses 116system.iocache.demand_misses::total 908 # number of demand (read+write) misses 117system.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses 118system.iocache.overall_misses::total 908 # number of overall misses 119system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) 120system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) |
121system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 122system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) |
123system.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses 124system.iocache.demand_accesses::total 908 # number of demand (read+write) accesses 125system.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses 126system.iocache.overall_accesses::total 908 # number of overall (read+write) accesses |
127system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 128system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 129system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 130system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 131system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 132system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 133system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 134system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked --- 11 unchanged lines hidden (view full) --- 146system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 147system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 148system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 149system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 150system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 151system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 152system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 153system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. |
154system.iobus.trans_dist::ReadReq 10011915 # Transaction distribution 155system.iobus.trans_dist::ReadResp 10011915 # Transaction distribution 156system.iobus.trans_dist::WriteReq 57577 # Transaction distribution 157system.iobus.trans_dist::WriteResp 10857 # Transaction distribution 158system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 159system.iobus.trans_dist::MessageReq 1696 # Transaction distribution 160system.iobus.trans_dist::MessageResp 1696 # Transaction distribution 161system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 162system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 163system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 164system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 165system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 166system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 167system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 168system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 169system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes) 170system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) 171system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) 172system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 173system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27352 # Packet count per connected master and slave (bytes) 174system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 175system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 176system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 177system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 178system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 179system.iobus.pkt_count_system.bridge.master::total 20043728 # Packet count per connected master and slave (bytes) 180system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) 181system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) 182system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) 183system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) 184system.iobus.pkt_count::total 20142376 # Packet count per connected master and slave (bytes) 185system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 186system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 187system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 188system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 189system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 190system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 191system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 192system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 193system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes) 194system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) 195system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) 196system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 197system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13676 # Cumulative packet size per connected master and slave (bytes) 198system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 199system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 200system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 201system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 202system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 203system.iobus.pkt_size_system.bridge.master::total 10027982 # Cumulative packet size per connected master and slave (bytes) 204system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) 205system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) 206system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) 207system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) 208system.iobus.pkt_size::total 13062574 # Cumulative packet size per connected master and slave (bytes) |
209system.cpu_clk_domain.clock 500 # Clock period in ticks 210system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks |
211system.cpu.numCycles 10224257410 # number of cpu cycles simulated |
212system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 213system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
214system.cpu.committedInsts 199947158 # Number of instructions committed 215system.cpu.committedOps 409371517 # Number of ops (including micro ops) committed 216system.cpu.num_int_alu_accesses 374392167 # Number of integer alu accesses |
217system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses |
218system.cpu.num_func_calls 2307997 # number of times a function call or return occured 219system.cpu.num_conditional_control_insts 39978602 # number of instructions that are conditional controls 220system.cpu.num_int_insts 374392167 # number of integer instructions |
221system.cpu.num_fp_insts 0 # number of float instructions |
222system.cpu.num_int_register_reads 682348609 # number of times the integer registers were read 223system.cpu.num_int_register_writes 323388730 # number of times the integer registers were written |
224system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 225system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
226system.cpu.num_cc_register_reads 233729759 # number of times the CC registers were read 227system.cpu.num_cc_register_writes 157242019 # number of times the CC registers were written 228system.cpu.num_mem_refs 35671209 # number of memory refs 229system.cpu.num_load_insts 27243676 # Number of load instructions 230system.cpu.num_store_insts 8427533 # Number of store instructions 231system.cpu.num_idle_cycles 9770491320.524229 # Number of idle cycles 232system.cpu.num_busy_cycles 453766089.475771 # Number of busy cycles 233system.cpu.not_idle_fraction 0.044381 # Percentage of non-idle cycles 234system.cpu.idle_fraction 0.955619 # Percentage of idle cycles 235system.cpu.Branches 43128209 # Number of branches fetched 236system.cpu.op_class::No_OpClass 175380 0.04% 0.04% # Class of executed instruction 237system.cpu.op_class::IntAlu 373258577 91.18% 91.22% # Class of executed instruction 238system.cpu.op_class::IntMult 144442 0.04% 91.26% # Class of executed instruction 239system.cpu.op_class::IntDiv 122944 0.03% 91.29% # Class of executed instruction |
240system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction 241system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction 242system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction 243system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction 244system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction 245system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction 246system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction 247system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction --- 10 unchanged lines hidden (view full) --- 258system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction 259system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction 260system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction 261system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction 262system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction 263system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction 264system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction 265system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction |
266system.cpu.op_class::MemRead 27243676 6.65% 97.94% # Class of executed instruction 267system.cpu.op_class::MemWrite 8427533 2.06% 100.00% # Class of executed instruction |
268system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 269system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
270system.cpu.op_class::total 409372552 # Class of executed instruction |
271system.cpu.kern.inst.arm 0 # number of arm instructions executed 272system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |
273system.cpu.icache.tags.replacements 791918 # number of replacements |
274system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use |
275system.cpu.icache.tags.total_refs 243546972 # Total number of references to valid blocks. 276system.cpu.icache.tags.sampled_refs 792430 # Sample count of references to valid blocks. 277system.cpu.icache.tags.avg_refs 307.341938 # Average number of references to valid blocks. |
278system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. 279system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor 280system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy 281system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy 282system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 283system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 284system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id |
285system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id 286system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id |
287system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
288system.cpu.icache.tags.tag_accesses 245131846 # Number of tag accesses 289system.cpu.icache.tags.data_accesses 245131846 # Number of data accesses 290system.cpu.icache.ReadReq_hits::cpu.inst 243546972 # number of ReadReq hits 291system.cpu.icache.ReadReq_hits::total 243546972 # number of ReadReq hits 292system.cpu.icache.demand_hits::cpu.inst 243546972 # number of demand (read+write) hits 293system.cpu.icache.demand_hits::total 243546972 # number of demand (read+write) hits 294system.cpu.icache.overall_hits::cpu.inst 243546972 # number of overall hits 295system.cpu.icache.overall_hits::total 243546972 # number of overall hits 296system.cpu.icache.ReadReq_misses::cpu.inst 792437 # number of ReadReq misses 297system.cpu.icache.ReadReq_misses::total 792437 # number of ReadReq misses 298system.cpu.icache.demand_misses::cpu.inst 792437 # number of demand (read+write) misses 299system.cpu.icache.demand_misses::total 792437 # number of demand (read+write) misses 300system.cpu.icache.overall_misses::cpu.inst 792437 # number of overall misses 301system.cpu.icache.overall_misses::total 792437 # number of overall misses 302system.cpu.icache.ReadReq_accesses::cpu.inst 244339409 # number of ReadReq accesses(hits+misses) 303system.cpu.icache.ReadReq_accesses::total 244339409 # number of ReadReq accesses(hits+misses) 304system.cpu.icache.demand_accesses::cpu.inst 244339409 # number of demand (read+write) accesses 305system.cpu.icache.demand_accesses::total 244339409 # number of demand (read+write) accesses 306system.cpu.icache.overall_accesses::cpu.inst 244339409 # number of overall (read+write) accesses 307system.cpu.icache.overall_accesses::total 244339409 # number of overall (read+write) accesses 308system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses 309system.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses 310system.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses 311system.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses 312system.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses 313system.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses |
314system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 315system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 316system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 317system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 318system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 319system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 320system.cpu.icache.fast_writes 0 # number of fast writes performed 321system.cpu.icache.cache_copies 0 # number of cache copies performed 322system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
323system.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements 324system.cpu.itb_walker_cache.tags.tagsinuse 3.026447 # Cycle average of tags in use 325system.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks. 326system.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks. 327system.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks. 328system.cpu.itb_walker_cache.tags.warmup_cycle 5102112149000 # Cycle when the warmup percentage was hit. 329system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026447 # Average occupied blocks per requestor 330system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy 331system.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy 332system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id |
333system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id |
334system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 335system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 336system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 337system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 338system.cpu.itb_walker_cache.tags.tag_accesses 29024 # Number of tag accesses 339system.cpu.itb_walker_cache.tags.data_accesses 29024 # Number of data accesses 340system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7640 # number of ReadReq hits 341system.cpu.itb_walker_cache.ReadReq_hits::total 7640 # number of ReadReq hits |
342system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 343system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits |
344system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits 345system.cpu.itb_walker_cache.demand_hits::total 7642 # number of demand (read+write) hits 346system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7642 # number of overall hits 347system.cpu.itb_walker_cache.overall_hits::total 7642 # number of overall hits 348system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4580 # number of ReadReq misses 349system.cpu.itb_walker_cache.ReadReq_misses::total 4580 # number of ReadReq misses 350system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4580 # number of demand (read+write) misses 351system.cpu.itb_walker_cache.demand_misses::total 4580 # number of demand (read+write) misses 352system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4580 # number of overall misses 353system.cpu.itb_walker_cache.overall_misses::total 4580 # number of overall misses 354system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) 355system.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) |
356system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 357system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) |
358system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses 359system.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses 360system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses 361system.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses 362system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374795 # miss rate for ReadReq accesses 363system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374795 # miss rate for ReadReq accesses 364system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374734 # miss rate for demand accesses 365system.cpu.itb_walker_cache.demand_miss_rate::total 0.374734 # miss rate for demand accesses 366system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374734 # miss rate for overall accesses 367system.cpu.itb_walker_cache.overall_miss_rate::total 0.374734 # miss rate for overall accesses |
368system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 369system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 370system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 371system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 372system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 373system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 374system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 375system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed |
376system.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks 377system.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks |
378system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
379system.cpu.dtb_walker_cache.tags.replacements 8177 # number of replacements 380system.cpu.dtb_walker_cache.tags.tagsinuse 5.013955 # Cycle average of tags in use 381system.cpu.dtb_walker_cache.tags.total_refs 12514 # Total number of references to valid blocks. 382system.cpu.dtb_walker_cache.tags.sampled_refs 8191 # Sample count of references to valid blocks. 383system.cpu.dtb_walker_cache.tags.avg_refs 1.527774 # Average number of references to valid blocks. 384system.cpu.dtb_walker_cache.tags.warmup_cycle 5101283486500 # Cycle when the warmup percentage was hit. 385system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013955 # Average occupied blocks per requestor 386system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy 387system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy 388system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 389system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 390system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 391system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 392system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id 393system.cpu.dtb_walker_cache.tags.tag_accesses 53146 # Number of tag accesses 394system.cpu.dtb_walker_cache.tags.data_accesses 53146 # Number of data accesses 395system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12515 # number of ReadReq hits 396system.cpu.dtb_walker_cache.ReadReq_hits::total 12515 # number of ReadReq hits 397system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12515 # number of demand (read+write) hits 398system.cpu.dtb_walker_cache.demand_hits::total 12515 # number of demand (read+write) hits 399system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12515 # number of overall hits 400system.cpu.dtb_walker_cache.overall_hits::total 12515 # number of overall hits 401system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9372 # number of ReadReq misses 402system.cpu.dtb_walker_cache.ReadReq_misses::total 9372 # number of ReadReq misses 403system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9372 # number of demand (read+write) misses 404system.cpu.dtb_walker_cache.demand_misses::total 9372 # number of demand (read+write) misses 405system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9372 # number of overall misses 406system.cpu.dtb_walker_cache.overall_misses::total 9372 # number of overall misses 407system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21887 # number of ReadReq accesses(hits+misses) 408system.cpu.dtb_walker_cache.ReadReq_accesses::total 21887 # number of ReadReq accesses(hits+misses) 409system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21887 # number of demand (read+write) accesses 410system.cpu.dtb_walker_cache.demand_accesses::total 21887 # number of demand (read+write) accesses 411system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21887 # number of overall (read+write) accesses 412system.cpu.dtb_walker_cache.overall_accesses::total 21887 # number of overall (read+write) accesses 413system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428199 # miss rate for ReadReq accesses 414system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428199 # miss rate for ReadReq accesses 415system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428199 # miss rate for demand accesses 416system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428199 # miss rate for demand accesses 417system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428199 # miss rate for overall accesses 418system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428199 # miss rate for overall accesses |
419system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 420system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 421system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 422system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 423system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 424system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 425system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 426system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed |
427system.cpu.dtb_walker_cache.writebacks::writebacks 2797 # number of writebacks 428system.cpu.dtb_walker_cache.writebacks::total 2797 # number of writebacks |
429system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate |
430system.cpu.dcache.tags.replacements 1623316 # number of replacements 431system.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use 432system.cpu.dcache.tags.total_refs 20184260 # Total number of references to valid blocks. 433system.cpu.dcache.tags.sampled_refs 1623828 # Sample count of references to valid blocks. 434system.cpu.dcache.tags.avg_refs 12.430048 # Average number of references to valid blocks. |
435system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. |
436system.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor |
437system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 438system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 439system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
440system.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id 441system.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id 442system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id |
443system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
444system.cpu.dcache.tags.tag_accesses 88856245 # Number of tag accesses 445system.cpu.dcache.tags.data_accesses 88856245 # Number of data accesses 446system.cpu.dcache.ReadReq_hits::cpu.data 12022868 # number of ReadReq hits 447system.cpu.dcache.ReadReq_hits::total 12022868 # number of ReadReq hits 448system.cpu.dcache.WriteReq_hits::cpu.data 8100233 # number of WriteReq hits 449system.cpu.dcache.WriteReq_hits::total 8100233 # number of WriteReq hits 450system.cpu.dcache.SoftPFReq_hits::cpu.data 58899 # number of SoftPFReq hits 451system.cpu.dcache.SoftPFReq_hits::total 58899 # number of SoftPFReq hits 452system.cpu.dcache.demand_hits::cpu.data 20123101 # number of demand (read+write) hits 453system.cpu.dcache.demand_hits::total 20123101 # number of demand (read+write) hits 454system.cpu.dcache.overall_hits::cpu.data 20182000 # number of overall hits 455system.cpu.dcache.overall_hits::total 20182000 # number of overall hits 456system.cpu.dcache.ReadReq_misses::cpu.data 905995 # number of ReadReq misses 457system.cpu.dcache.ReadReq_misses::total 905995 # number of ReadReq misses 458system.cpu.dcache.WriteReq_misses::cpu.data 317045 # number of WriteReq misses 459system.cpu.dcache.WriteReq_misses::total 317045 # number of WriteReq misses 460system.cpu.dcache.SoftPFReq_misses::cpu.data 403061 # number of SoftPFReq misses 461system.cpu.dcache.SoftPFReq_misses::total 403061 # number of SoftPFReq misses 462system.cpu.dcache.demand_misses::cpu.data 1223040 # number of demand (read+write) misses 463system.cpu.dcache.demand_misses::total 1223040 # number of demand (read+write) misses 464system.cpu.dcache.overall_misses::cpu.data 1626101 # number of overall misses 465system.cpu.dcache.overall_misses::total 1626101 # number of overall misses 466system.cpu.dcache.ReadReq_accesses::cpu.data 12928863 # number of ReadReq accesses(hits+misses) 467system.cpu.dcache.ReadReq_accesses::total 12928863 # number of ReadReq accesses(hits+misses) 468system.cpu.dcache.WriteReq_accesses::cpu.data 8417278 # number of WriteReq accesses(hits+misses) 469system.cpu.dcache.WriteReq_accesses::total 8417278 # number of WriteReq accesses(hits+misses) 470system.cpu.dcache.SoftPFReq_accesses::cpu.data 461960 # number of SoftPFReq accesses(hits+misses) 471system.cpu.dcache.SoftPFReq_accesses::total 461960 # number of SoftPFReq accesses(hits+misses) 472system.cpu.dcache.demand_accesses::cpu.data 21346141 # number of demand (read+write) accesses 473system.cpu.dcache.demand_accesses::total 21346141 # number of demand (read+write) accesses 474system.cpu.dcache.overall_accesses::cpu.data 21808101 # number of overall (read+write) accesses 475system.cpu.dcache.overall_accesses::total 21808101 # number of overall (read+write) accesses 476system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070075 # miss rate for ReadReq accesses 477system.cpu.dcache.ReadReq_miss_rate::total 0.070075 # miss rate for ReadReq accesses 478system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037666 # miss rate for WriteReq accesses 479system.cpu.dcache.WriteReq_miss_rate::total 0.037666 # miss rate for WriteReq accesses 480system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872502 # miss rate for SoftPFReq accesses 481system.cpu.dcache.SoftPFReq_miss_rate::total 0.872502 # miss rate for SoftPFReq accesses 482system.cpu.dcache.demand_miss_rate::cpu.data 0.057296 # miss rate for demand accesses 483system.cpu.dcache.demand_miss_rate::total 0.057296 # miss rate for demand accesses 484system.cpu.dcache.overall_miss_rate::cpu.data 0.074564 # miss rate for overall accesses 485system.cpu.dcache.overall_miss_rate::total 0.074564 # miss rate for overall accesses |
486system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 487system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 488system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 489system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 490system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 491system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 492system.cpu.dcache.fast_writes 0 # number of fast writes performed 493system.cpu.dcache.cache_copies 0 # number of cache copies performed |
494system.cpu.dcache.writebacks::writebacks 1536734 # number of writebacks 495system.cpu.dcache.writebacks::total 1536734 # number of writebacks |
496system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
497system.cpu.toL2Bus.trans_dist::ReadReq 15972635 # Transaction distribution 498system.cpu.toL2Bus.trans_dist::ReadResp 15972635 # Transaction distribution 499system.cpu.toL2Bus.trans_dist::WriteReq 13796 # Transaction distribution 500system.cpu.toL2Bus.trans_dist::WriteResp 13796 # Transaction distribution 501system.cpu.toL2Bus.trans_dist::Writeback 1540333 # Transaction distribution 502system.cpu.toL2Bus.trans_dist::UpgradeReq 2260 # Transaction distribution 503system.cpu.toL2Bus.trans_dist::UpgradeResp 2260 # Transaction distribution 504system.cpu.toL2Bus.trans_dist::ReadExReq 314785 # Transaction distribution 505system.cpu.toL2Bus.trans_dist::ReadExResp 314785 # Transaction distribution 506system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584874 # Packet count per connected master and slave (bytes) 507system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32530908 # Packet count per connected master and slave (bytes) 508system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) 509system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21541 # Packet count per connected master and slave (bytes) 510system.cpu.toL2Bus.pkt_count::total 34147285 # Packet count per connected master and slave (bytes) 511system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50715968 # Cumulative packet size per connected master and slave (bytes) 512system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227701267 # Cumulative packet size per connected master and slave (bytes) 513system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) 514system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778816 # Cumulative packet size per connected master and slave (bytes) 515system.cpu.toL2Bus.pkt_size::total 279540499 # Cumulative packet size per connected master and slave (bytes) 516system.cpu.toL2Bus.snoops 48008 # Total snoops (count) 517system.cpu.toL2Bus.snoop_fanout::samples 4020451 # Request fanout histogram 518system.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram 519system.cpu.toL2Bus.snoop_fanout::stdev 0.108195 # Request fanout histogram 520system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 521system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 522system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 523system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 524system.cpu.toL2Bus.snoop_fanout::3 3972823 98.82% 98.82% # Request fanout histogram 525system.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram 526system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 527system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 528system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 529system.cpu.toL2Bus.snoop_fanout::total 4020451 # Request fanout histogram 530system.cpu.l2cache.tags.replacements 106060 # number of replacements 531system.cpu.l2cache.tags.tagsinuse 64822.097552 # Cycle average of tags in use 532system.cpu.l2cache.tags.total_refs 3461863 # Total number of references to valid blocks. 533system.cpu.l2cache.tags.sampled_refs 170171 # Sample count of references to valid blocks. 534system.cpu.l2cache.tags.avg_refs 20.343437 # Average number of references to valid blocks. |
535system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
536system.cpu.l2cache.tags.occ_blocks::writebacks 51909.062113 # Average occupied blocks per requestor |
537system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor 538system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132256 # Average occupied blocks per requestor |
539system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.551712 # Average occupied blocks per requestor 540system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.348992 # Average occupied blocks per requestor 541system.cpu.l2cache.tags.occ_percent::writebacks 0.792069 # Average percentage of cache occupancy |
542system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 543system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 544system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy |
545system.cpu.l2cache.tags.occ_percent::cpu.data 0.159032 # Average percentage of cache occupancy 546system.cpu.l2cache.tags.occ_percent::total 0.989107 # Average percentage of cache occupancy 547system.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 # Occupied blocks per task id 548system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 549system.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 550system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id 551system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id 552system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id 553system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id 554system.cpu.l2cache.tags.tag_accesses 32243624 # Number of tag accesses 555system.cpu.l2cache.tags.data_accesses 32243624 # Number of data accesses 556system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7334 # number of ReadReq hits 557system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits 558system.cpu.l2cache.ReadReq_hits::cpu.inst 779106 # number of ReadReq hits 559system.cpu.l2cache.ReadReq_hits::cpu.data 1276189 # number of ReadReq hits 560system.cpu.l2cache.ReadReq_hits::total 2065966 # number of ReadReq hits 561system.cpu.l2cache.Writeback_hits::writebacks 1540333 # number of Writeback hits 562system.cpu.l2cache.Writeback_hits::total 1540333 # number of Writeback hits 563system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits 564system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits 565system.cpu.l2cache.ReadExReq_hits::cpu.data 180012 # number of ReadExReq hits 566system.cpu.l2cache.ReadExReq_hits::total 180012 # number of ReadExReq hits 567system.cpu.l2cache.demand_hits::cpu.dtb.walker 7334 # number of demand (read+write) hits 568system.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits 569system.cpu.l2cache.demand_hits::cpu.inst 779106 # number of demand (read+write) hits 570system.cpu.l2cache.demand_hits::cpu.data 1456201 # number of demand (read+write) hits 571system.cpu.l2cache.demand_hits::total 2245978 # number of demand (read+write) hits 572system.cpu.l2cache.overall_hits::cpu.dtb.walker 7334 # number of overall hits 573system.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits 574system.cpu.l2cache.overall_hits::cpu.inst 779106 # number of overall hits 575system.cpu.l2cache.overall_hits::cpu.data 1456201 # number of overall hits 576system.cpu.l2cache.overall_hits::total 2245978 # number of overall hits |
577system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 578system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses |
579system.cpu.l2cache.ReadReq_misses::cpu.inst 13318 # number of ReadReq misses 580system.cpu.l2cache.ReadReq_misses::cpu.data 32226 # number of ReadReq misses 581system.cpu.l2cache.ReadReq_misses::total 45550 # number of ReadReq misses 582system.cpu.l2cache.UpgradeReq_misses::cpu.data 1809 # number of UpgradeReq misses 583system.cpu.l2cache.UpgradeReq_misses::total 1809 # number of UpgradeReq misses 584system.cpu.l2cache.ReadExReq_misses::cpu.data 134768 # number of ReadExReq misses 585system.cpu.l2cache.ReadExReq_misses::total 134768 # number of ReadExReq misses |
586system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 587system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses |
588system.cpu.l2cache.demand_misses::cpu.inst 13318 # number of demand (read+write) misses 589system.cpu.l2cache.demand_misses::cpu.data 166994 # number of demand (read+write) misses 590system.cpu.l2cache.demand_misses::total 180318 # number of demand (read+write) misses |
591system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 592system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses |
593system.cpu.l2cache.overall_misses::cpu.inst 13318 # number of overall misses 594system.cpu.l2cache.overall_misses::cpu.data 166994 # number of overall misses 595system.cpu.l2cache.overall_misses::total 180318 # number of overall misses 596system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7335 # number of ReadReq accesses(hits+misses) 597system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses) 598system.cpu.l2cache.ReadReq_accesses::cpu.inst 792424 # number of ReadReq accesses(hits+misses) 599system.cpu.l2cache.ReadReq_accesses::cpu.data 1308415 # number of ReadReq accesses(hits+misses) 600system.cpu.l2cache.ReadReq_accesses::total 2111516 # number of ReadReq accesses(hits+misses) 601system.cpu.l2cache.Writeback_accesses::writebacks 1540333 # number of Writeback accesses(hits+misses) 602system.cpu.l2cache.Writeback_accesses::total 1540333 # number of Writeback accesses(hits+misses) 603system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1831 # number of UpgradeReq accesses(hits+misses) 604system.cpu.l2cache.UpgradeReq_accesses::total 1831 # number of UpgradeReq accesses(hits+misses) 605system.cpu.l2cache.ReadExReq_accesses::cpu.data 314780 # number of ReadExReq accesses(hits+misses) 606system.cpu.l2cache.ReadExReq_accesses::total 314780 # number of ReadExReq accesses(hits+misses) 607system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7335 # number of demand (read+write) accesses 608system.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses 609system.cpu.l2cache.demand_accesses::cpu.inst 792424 # number of demand (read+write) accesses 610system.cpu.l2cache.demand_accesses::cpu.data 1623195 # number of demand (read+write) accesses 611system.cpu.l2cache.demand_accesses::total 2426296 # number of demand (read+write) accesses 612system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7335 # number of overall (read+write) accesses 613system.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses 614system.cpu.l2cache.overall_accesses::cpu.inst 792424 # number of overall (read+write) accesses 615system.cpu.l2cache.overall_accesses::cpu.data 1623195 # number of overall (read+write) accesses 616system.cpu.l2cache.overall_accesses::total 2426296 # number of overall (read+write) accesses 617system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses 618system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses 619system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses 620system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024630 # miss rate for ReadReq accesses 621system.cpu.l2cache.ReadReq_miss_rate::total 0.021572 # miss rate for ReadReq accesses 622system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987985 # miss rate for UpgradeReq accesses 623system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987985 # miss rate for UpgradeReq accesses 624system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428134 # miss rate for ReadExReq accesses 625system.cpu.l2cache.ReadExReq_miss_rate::total 0.428134 # miss rate for ReadExReq accesses 626system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses 627system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses 628system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses 629system.cpu.l2cache.demand_miss_rate::cpu.data 0.102880 # miss rate for demand accesses 630system.cpu.l2cache.demand_miss_rate::total 0.074318 # miss rate for demand accesses 631system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses 632system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses 633system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses 634system.cpu.l2cache.overall_miss_rate::cpu.data 0.102880 # miss rate for overall accesses 635system.cpu.l2cache.overall_miss_rate::total 0.074318 # miss rate for overall accesses |
636system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 637system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 639system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 641system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.l2cache.fast_writes 0 # number of fast writes performed 643system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
644system.cpu.l2cache.writebacks::writebacks 98213 # number of writebacks 645system.cpu.l2cache.writebacks::total 98213 # number of writebacks |
646system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 647 648---------- End Simulation Statistics ---------- |