3,5c3,5
< sim_seconds 5.112102 # Number of seconds simulated
< sim_ticks 5112102211000 # Number of ticks simulated
< final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.112126 # Number of seconds simulated
> sim_ticks 5112126311000 # Number of ticks simulated
> final_tick 5112126311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,15c7,15
< host_inst_rate 856407 # Simulator instruction rate (inst/s)
< host_op_rate 1753461 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 21900233108 # Simulator tick rate (ticks/s)
< host_mem_usage 584104 # Number of bytes of host memory used
< host_seconds 233.43 # Real time elapsed on the host
< sim_insts 199908396 # Number of instructions simulated
< sim_ops 409304707 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
---
> host_inst_rate 1020096 # Simulator instruction rate (inst/s)
> host_op_rate 2088583 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 26083435490 # Simulator tick rate (ticks/s)
> host_mem_usage 587152 # Number of bytes of host memory used
> host_seconds 195.99 # Real time elapsed on the host
> sim_insts 199929810 # Number of instructions simulated
> sim_ops 409343980 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
18,19c18,19
< system.physmem.bytes_read::cpu.data 10605120 # Number of bytes read from this memory
< system.physmem.bytes_read::total 13879360 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory
> system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory
22,25c22,25
< system.physmem.bytes_written::writebacks 9264512 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9264512 # Number of bytes written to this memory
< system.physmem.num_reads::pc.south_bridge.ide 37829 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory
> system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
28,33c28,33
< system.physmem.num_reads::cpu.data 165705 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 216865 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 144758 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 144758 # Number of write requests responded to by this memory
< system.physmem.bw_read::pc.south_bridge.ide 473593 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory
> system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
36,37c36,37
< system.physmem.bw_read::cpu.data 2074513 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2715000 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2715826 # Total read bandwidth from this memory (bytes/s)
40,44c40,44
< system.physmem.bw_write::writebacks 1812270 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1812270 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1812270 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 473593 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
47,48c47,48
< system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s)
196,197c196,197
< system.membus.throughput 9632725 # Throughput (bytes/s)
< system.membus.data_through_bus 49243475 # Total data (bytes)
---
> system.membus.throughput 9634332 # Throughput (bytes/s)
> system.membus.data_through_bus 49251923 # Total data (bytes)
200c200
< system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
204,205c204,205
< system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
255,257c255,257
< system.iobus.throughput 2555194 # Throughput (bytes/s)
< system.iobus.data_through_bus 13062414 # Total data (bytes)
< system.cpu.numCycles 10224204444 # number of cpu cycles simulated
---
> system.iobus.throughput 2555207 # Throughput (bytes/s)
> system.iobus.data_through_bus 13062542 # Total data (bytes)
> system.cpu.numCycles 10224252644 # number of cpu cycles simulated
260,262c260,262
< system.cpu.committedInsts 199908396 # Number of instructions committed
< system.cpu.committedOps 409304707 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 374467605 # Number of integer alu accesses
---
> system.cpu.committedInsts 199929810 # Number of instructions committed
> system.cpu.committedOps 409343980 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 374506599 # Number of integer alu accesses
264,266c264,266
< system.cpu.num_func_calls 2307395 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 39972475 # number of instructions that are conditional controls
< system.cpu.num_int_insts 374467605 # number of integer instructions
---
> system.cpu.num_func_calls 2307717 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 39976354 # number of instructions that are conditional controls
> system.cpu.num_int_insts 374506599 # number of integer instructions
268,269c268,269
< system.cpu.num_int_register_reads 915905592 # number of times the integer registers were read
< system.cpu.num_int_register_writes 480549431 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 916001165 # number of times the integer registers were read
> system.cpu.num_int_register_writes 480603129 # number of times the integer registers were written
272,278c272,278
< system.cpu.num_mem_refs 35655576 # number of memory refs
< system.cpu.num_load_insts 27235236 # Number of load instructions
< system.cpu.num_store_insts 8420340 # Number of store instructions
< system.cpu.num_idle_cycles 9770516372.735863 # Number of idle cycles
< system.cpu.num_busy_cycles 453688071.264138 # Number of busy cycles
< system.cpu.not_idle_fraction 0.044374 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.955626 # Percentage of idle cycles
---
> system.cpu.num_mem_refs 35660913 # number of memory refs
> system.cpu.num_load_insts 27238816 # Number of load instructions
> system.cpu.num_store_insts 8422097 # Number of store instructions
> system.cpu.num_idle_cycles 9770516880.735765 # Number of idle cycles
> system.cpu.num_busy_cycles 453735763.264236 # Number of busy cycles
> system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
281,307c281,307
< system.cpu.icache.tags.replacements 790522 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 243495984 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 243495984 # number of overall hits
< system.cpu.icache.overall_hits::total 243495984 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 791041 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 791041 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 791041 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 791041 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 791041 # number of overall misses
< system.cpu.icache.overall_misses::total 791041 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 244287025 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 244287025 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 244287025 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 244287025 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 244287025 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 244287025 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.replacements 790541 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 243525798 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 791053 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 307.850167 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 243525798 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 243525798 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 243525798 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 243525798 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 243525798 # number of overall hits
> system.cpu.icache.overall_hits::total 243525798 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 791060 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 791060 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 791060 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 791060 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 791060 # number of overall misses
> system.cpu.icache.overall_misses::total 791060 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 244316858 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 244316858 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 244316858 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 244316858 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 244316858 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 244316858 # number of overall (read+write) accesses
324c324
< system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use
---
> system.cpu.itb_walker_cache.tags.tagsinuse 3.026300 # Cycle average of tags in use
328,331c328,331
< system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_percent::total 0.189143 # Average percentage of cache occupancy
---
> system.cpu.itb_walker_cache.tags.warmup_cycle 5102118322000 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026300 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy
372,373c372,373
< system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks.
---
> system.cpu.dtb_walker_cache.tags.tagsinuse 5.014180 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks.
375,377c375,377
< system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor
---
> system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 5100463009500 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014180 # Average occupied blocks per requestor
380,403c380,403
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12956 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 12956 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12956 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 12956 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12956 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 12956 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8822 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 8822 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8822 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 8822 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8822 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 8822 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21778 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 21778 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21778 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 21778 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21778 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 21778 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405088 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405088 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405088 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405088 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405088 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405088 # miss rate for overall accesses
---
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses
412,413c412,413
< system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks
415c415
< system.cpu.dcache.tags.replacements 1622027 # number of replacements
---
> system.cpu.dcache.tags.replacements 1622093 # number of replacements
417,419c417,419
< system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 20175183 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1622605 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 12.433823 # Average number of references to valid blocks.
424,449c424,449
< system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8093747 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20167772 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20167772 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20167772 # number of overall hits
< system.cpu.dcache.overall_hits::total 20167772 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1308420 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1308420 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 316403 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 316403 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 1624823 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1624823 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1624823 # number of overall misses
< system.cpu.dcache.overall_misses::total 1624823 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 13382445 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13382445 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8410150 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8410150 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21792595 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21792595 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21792595 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21792595 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097771 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.097771 # miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_hits::cpu.data 12077542 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 12077542 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8095371 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8095371 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20172913 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20172913 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20172913 # number of overall hits
> system.cpu.dcache.overall_hits::total 20172913 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1308419 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1308419 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 316472 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 316472 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 1624891 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1624891 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1624891 # number of overall misses
> system.cpu.dcache.overall_misses::total 1624891 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses
452,455c452,455
< system.cpu.dcache.demand_miss_rate::cpu.data 0.074558 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.074558 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.074558 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.074558 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses
464,465c464,465
< system.cpu.dcache.writebacks::writebacks 1535756 # number of writebacks
< system.cpu.dcache.writebacks::total 1535756 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 1535822 # number of writebacks
> system.cpu.dcache.writebacks::total 1535822 # number of writebacks
467,468c467,468
< system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s)
< system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes)
---
> system.cpu.toL2Bus.throughput 54624920 # Throughput (bytes/s)
> system.cpu.toL2Bus.data_through_bus 279224019 # Total data (bytes)
470,474c470,474
< system.cpu.l2cache.tags.replacements 105931 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 105999 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64822.033663 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3456588 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 20.317692 # Average number of references to valid blocks.
476,481c476,481
< system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 51908.841728 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.538603 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.518599 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy
485,487c485,487
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits
489,493c489,493
< system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2062551 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1538695 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1538695 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 777722 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1275543 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2062571 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits
496,498c496,498
< system.cpu.l2cache.ReadExReq_hits::cpu.data 179738 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 179738 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 6502 # number of demand (read+write) hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 179739 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 179739 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits
500c500
< system.cpu.l2cache.demand_hits::cpu.inst 777703 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 777722 # number of demand (read+write) hits
502,503c502,503
< system.cpu.l2cache.demand_hits::total 2242289 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 6502 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 2242310 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits
505c505
< system.cpu.l2cache.overall_hits::cpu.inst 777703 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 777722 # number of overall hits
507,508c507,508
< system.cpu.l2cache.overall_hits::total 2242289 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
---
> system.cpu.l2cache.overall_hits::total 2242310 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
512,517c512,517
< system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 134392 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 134392 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
520,522c520,522
< system.cpu.l2cache.demand_misses::cpu.data 166638 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 179970 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
---
> system.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
525,527c525,527
< system.cpu.l2cache.overall_misses::cpu.data 166638 # number of overall misses
< system.cpu.l2cache.overall_misses::total 179970 # number of overall misses
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6504 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses
> system.cpu.l2cache.overall_misses::total 180035 # number of overall misses
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses)
529,538c529,538
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 791028 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2108129 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1538695 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1538695 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 314130 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 314130 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6504 # number of demand (read+write) accesses
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 791047 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1307789 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2108148 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 314197 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 314197 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses
540,543c540,543
< system.cpu.l2cache.demand_accesses::cpu.inst 791028 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1621920 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2422259 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6504 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 791047 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1621986 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2422345 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses
545,548c545,548
< system.cpu.l2cache.overall_accesses::cpu.inst 791028 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1621920 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2422259 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 791047 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1621986 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2422345 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses
552,557c552,557
< system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427823 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.427823 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427942 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.427942 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses
560,562c560,562
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102741 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.074298 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.074323 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses
565,566c565,566
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102741 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.074298 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.074323 # miss rate for overall accesses
575,576c575,576
< system.cpu.l2cache.writebacks::writebacks 98091 # number of writebacks
< system.cpu.l2cache.writebacks::total 98091 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks
> system.cpu.l2cache.writebacks::total 98156 # number of writebacks
< sim_seconds 5.112102 # Number of seconds simulated
< sim_ticks 5112102211000 # Number of ticks simulated
< final_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.112126 # Number of seconds simulated
> sim_ticks 5112126311000 # Number of ticks simulated
> final_tick 5112126311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,15c7,15
< host_inst_rate 856407 # Simulator instruction rate (inst/s)
< host_op_rate 1753461 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 21900233108 # Simulator tick rate (ticks/s)
< host_mem_usage 584104 # Number of bytes of host memory used
< host_seconds 233.43 # Real time elapsed on the host
< sim_insts 199908396 # Number of instructions simulated
< sim_ops 409304707 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
---
> host_inst_rate 1020096 # Simulator instruction rate (inst/s)
> host_op_rate 2088583 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 26083435490 # Simulator tick rate (ticks/s)
> host_mem_usage 587152 # Number of bytes of host memory used
> host_seconds 195.99 # Real time elapsed on the host
> sim_insts 199929810 # Number of instructions simulated
> sim_ops 409343980 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
18,19c18,19
< system.physmem.bytes_read::cpu.data 10605120 # Number of bytes read from this memory
< system.physmem.bytes_read::total 13879360 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory
> system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory
22,25c22,25
< system.physmem.bytes_written::writebacks 9264512 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9264512 # Number of bytes written to this memory
< system.physmem.num_reads::pc.south_bridge.ide 37829 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
---
> system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory
> system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
28,33c28,33
< system.physmem.num_reads::cpu.data 165705 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 216865 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 144758 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 144758 # Number of write requests responded to by this memory
< system.physmem.bw_read::pc.south_bridge.ide 473593 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory
> system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
36,37c36,37
< system.physmem.bw_read::cpu.data 2074513 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2715000 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2715826 # Total read bandwidth from this memory (bytes/s)
40,44c40,44
< system.physmem.bw_write::writebacks 1812270 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1812270 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1812270 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 473593 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
47,48c47,48
< system.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s)
196,197c196,197
< system.membus.throughput 9632725 # Throughput (bytes/s)
< system.membus.data_through_bus 49243475 # Total data (bytes)
---
> system.membus.throughput 9634332 # Throughput (bytes/s)
> system.membus.data_through_bus 49251923 # Total data (bytes)
200c200
< system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
204,205c204,205
< system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit.
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor
---
> system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit.
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
255,257c255,257
< system.iobus.throughput 2555194 # Throughput (bytes/s)
< system.iobus.data_through_bus 13062414 # Total data (bytes)
< system.cpu.numCycles 10224204444 # number of cpu cycles simulated
---
> system.iobus.throughput 2555207 # Throughput (bytes/s)
> system.iobus.data_through_bus 13062542 # Total data (bytes)
> system.cpu.numCycles 10224252644 # number of cpu cycles simulated
260,262c260,262
< system.cpu.committedInsts 199908396 # Number of instructions committed
< system.cpu.committedOps 409304707 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 374467605 # Number of integer alu accesses
---
> system.cpu.committedInsts 199929810 # Number of instructions committed
> system.cpu.committedOps 409343980 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 374506599 # Number of integer alu accesses
264,266c264,266
< system.cpu.num_func_calls 2307395 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 39972475 # number of instructions that are conditional controls
< system.cpu.num_int_insts 374467605 # number of integer instructions
---
> system.cpu.num_func_calls 2307717 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 39976354 # number of instructions that are conditional controls
> system.cpu.num_int_insts 374506599 # number of integer instructions
268,269c268,269
< system.cpu.num_int_register_reads 915905592 # number of times the integer registers were read
< system.cpu.num_int_register_writes 480549431 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 916001165 # number of times the integer registers were read
> system.cpu.num_int_register_writes 480603129 # number of times the integer registers were written
272,278c272,278
< system.cpu.num_mem_refs 35655576 # number of memory refs
< system.cpu.num_load_insts 27235236 # Number of load instructions
< system.cpu.num_store_insts 8420340 # Number of store instructions
< system.cpu.num_idle_cycles 9770516372.735863 # Number of idle cycles
< system.cpu.num_busy_cycles 453688071.264138 # Number of busy cycles
< system.cpu.not_idle_fraction 0.044374 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.955626 # Percentage of idle cycles
---
> system.cpu.num_mem_refs 35660913 # number of memory refs
> system.cpu.num_load_insts 27238816 # Number of load instructions
> system.cpu.num_store_insts 8422097 # Number of store instructions
> system.cpu.num_idle_cycles 9770516880.735765 # Number of idle cycles
> system.cpu.num_busy_cycles 453735763.264236 # Number of busy cycles
> system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
281,307c281,307
< system.cpu.icache.tags.replacements 790522 # number of replacements
< system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks.
< system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 243495984 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 243495984 # number of overall hits
< system.cpu.icache.overall_hits::total 243495984 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 791041 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 791041 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 791041 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 791041 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 791041 # number of overall misses
< system.cpu.icache.overall_misses::total 791041 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 244287025 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 244287025 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 244287025 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 244287025 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 244287025 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 244287025 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.replacements 790541 # number of replacements
> system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 243525798 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 791053 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 307.850167 # Average number of references to valid blocks.
> system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 243525798 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 243525798 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 243525798 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 243525798 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 243525798 # number of overall hits
> system.cpu.icache.overall_hits::total 243525798 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 791060 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 791060 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 791060 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 791060 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 791060 # number of overall misses
> system.cpu.icache.overall_misses::total 791060 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 244316858 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 244316858 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 244316858 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 244316858 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 244316858 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 244316858 # number of overall (read+write) accesses
324c324
< system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use
---
> system.cpu.itb_walker_cache.tags.tagsinuse 3.026300 # Cycle average of tags in use
328,331c328,331
< system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.tags.occ_percent::total 0.189143 # Average percentage of cache occupancy
---
> system.cpu.itb_walker_cache.tags.warmup_cycle 5102118322000 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026300 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy
372,373c372,373
< system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks.
---
> system.cpu.dtb_walker_cache.tags.tagsinuse 5.014180 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks.
375,377c375,377
< system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor
---
> system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 5100463009500 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014180 # Average occupied blocks per requestor
380,403c380,403
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12956 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 12956 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12956 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 12956 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12956 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 12956 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8822 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 8822 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8822 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 8822 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8822 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 8822 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21778 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 21778 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21778 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 21778 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21778 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 21778 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405088 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405088 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405088 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405088 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405088 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405088 # miss rate for overall accesses
---
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses
412,413c412,413
< system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks
415c415
< system.cpu.dcache.tags.replacements 1622027 # number of replacements
---
> system.cpu.dcache.tags.replacements 1622093 # number of replacements
417,419c417,419
< system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 20175183 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1622605 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 12.433823 # Average number of references to valid blocks.
424,449c424,449
< system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8093747 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20167772 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20167772 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20167772 # number of overall hits
< system.cpu.dcache.overall_hits::total 20167772 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1308420 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1308420 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 316403 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 316403 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 1624823 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1624823 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1624823 # number of overall misses
< system.cpu.dcache.overall_misses::total 1624823 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 13382445 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13382445 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8410150 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8410150 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21792595 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21792595 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21792595 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21792595 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097771 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.097771 # miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_hits::cpu.data 12077542 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 12077542 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8095371 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8095371 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20172913 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20172913 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20172913 # number of overall hits
> system.cpu.dcache.overall_hits::total 20172913 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1308419 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1308419 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 316472 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 316472 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 1624891 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1624891 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1624891 # number of overall misses
> system.cpu.dcache.overall_misses::total 1624891 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses
452,455c452,455
< system.cpu.dcache.demand_miss_rate::cpu.data 0.074558 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.074558 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.074558 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.074558 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses
464,465c464,465
< system.cpu.dcache.writebacks::writebacks 1535756 # number of writebacks
< system.cpu.dcache.writebacks::total 1535756 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 1535822 # number of writebacks
> system.cpu.dcache.writebacks::total 1535822 # number of writebacks
467,468c467,468
< system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s)
< system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes)
---
> system.cpu.toL2Bus.throughput 54624920 # Throughput (bytes/s)
> system.cpu.toL2Bus.data_through_bus 279224019 # Total data (bytes)
470,474c470,474
< system.cpu.l2cache.tags.replacements 105931 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 105999 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64822.033663 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3456588 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 20.317692 # Average number of references to valid blocks.
476,481c476,481
< system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 51908.841728 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.538603 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.518599 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy
485,487c485,487
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits
489,493c489,493
< system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2062551 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1538695 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1538695 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 777722 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1275543 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2062571 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits
496,498c496,498
< system.cpu.l2cache.ReadExReq_hits::cpu.data 179738 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 179738 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 6502 # number of demand (read+write) hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 179739 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 179739 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits
500c500
< system.cpu.l2cache.demand_hits::cpu.inst 777703 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 777722 # number of demand (read+write) hits
502,503c502,503
< system.cpu.l2cache.demand_hits::total 2242289 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 6502 # number of overall hits
---
> system.cpu.l2cache.demand_hits::total 2242310 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits
505c505
< system.cpu.l2cache.overall_hits::cpu.inst 777703 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 777722 # number of overall hits
507,508c507,508
< system.cpu.l2cache.overall_hits::total 2242289 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses
---
> system.cpu.l2cache.overall_hits::total 2242310 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
512,517c512,517
< system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 134392 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 134392 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
520,522c520,522
< system.cpu.l2cache.demand_misses::cpu.data 166638 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 179970 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses
---
> system.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
525,527c525,527
< system.cpu.l2cache.overall_misses::cpu.data 166638 # number of overall misses
< system.cpu.l2cache.overall_misses::total 179970 # number of overall misses
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6504 # number of ReadReq accesses(hits+misses)
---
> system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses
> system.cpu.l2cache.overall_misses::total 180035 # number of overall misses
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses)
529,538c529,538
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 791028 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2108129 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1538695 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1538695 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 314130 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 314130 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6504 # number of demand (read+write) accesses
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 791047 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1307789 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2108148 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 314197 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 314197 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses
540,543c540,543
< system.cpu.l2cache.demand_accesses::cpu.inst 791028 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1621920 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2422259 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6504 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 791047 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1621986 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2422345 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses
545,548c545,548
< system.cpu.l2cache.overall_accesses::cpu.inst 791028 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1621920 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2422259 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 791047 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1621986 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2422345 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses
552,557c552,557
< system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427823 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.427823 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427942 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.427942 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses
560,562c560,562
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102741 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.074298 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.074323 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses
565,566c565,566
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102741 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.074298 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.074323 # miss rate for overall accesses
575,576c575,576
< system.cpu.l2cache.writebacks::writebacks 98091 # number of writebacks
< system.cpu.l2cache.writebacks::total 98091 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks
> system.cpu.l2cache.writebacks::total 98156 # number of writebacks