3,5c3,5
< sim_seconds 5.112041 # Number of seconds simulated
< sim_ticks 5112040970500 # Number of ticks simulated
< final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.112100 # Number of seconds simulated
> sim_ticks 5112099860500 # Number of ticks simulated
> final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,14c7,14
< host_inst_rate 1074050 # Simulator instruction rate (inst/s)
< host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 27479001055 # Simulator tick rate (ticks/s)
< host_mem_usage 583620 # Number of bytes of host memory used
< host_seconds 186.03 # Real time elapsed on the host
< sim_insts 199810242 # Number of instructions simulated
< sim_ops 409125913 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
---
> host_inst_rate 1028107 # Simulator instruction rate (inst/s)
> host_op_rate 2105009 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 26291327617 # Simulator tick rate (ticks/s)
> host_mem_usage 628192 # Number of bytes of host memory used
> host_seconds 194.44 # Real time elapsed on the host
> sim_insts 199905607 # Number of instructions simulated
> sim_ops 409299132 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory
17,24c17,24
< system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory
< system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory
< system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory
> system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 9264448 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9264448 # Number of bytes written to this memory
> system.physmem.num_reads::pc.south_bridge.ide 37827 # Number of read requests responded to by this memory
27,32c27,32
< system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory
< system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 165706 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 216864 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 144757 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 144757 # Number of write requests responded to by this memory
> system.physmem.bw_read::pc.south_bridge.ide 473568 # Total read bandwidth from this memory (bytes/s)
35,43c35,43
< system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2074526 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2714989 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1812259 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1812259 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1812259 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 473568 # Total bandwidth to/from this memory (bytes/s)
46,48c46,48
< system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2074526 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4527248 # Total bandwidth to/from this memory (bytes/s)
192,193c192,193
< system.iocache.replacements 47569 # number of replacements
< system.iocache.tagsinuse 0.042402 # Cycle average of tags in use
---
> system.iocache.replacements 47568 # number of replacements
> system.iocache.tagsinuse 0.042441 # Cycle average of tags in use
195c195
< system.iocache.sampled_refs 47585 # Sample count of references to valid blocks.
---
> system.iocache.sampled_refs 47584 # Sample count of references to valid blocks.
197,202c197,202
< system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit.
< system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor
< system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy
< system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy
< system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
---
> system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit.
> system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor
> system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
> system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy
> system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
205,210c205,210
< system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
< system.iocache.demand_misses::total 47624 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses
< system.iocache.overall_misses::total 47624 # number of overall misses
< system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses
> system.iocache.demand_misses::total 47623 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses
> system.iocache.overall_misses::total 47623 # number of overall misses
> system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
213,216c213,216
< system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses
248c248
< system.cpu.numCycles 10224081964 # number of cpu cycles simulated
---
> system.cpu.numCycles 10224199744 # number of cpu cycles simulated
251,253c251,253
< system.cpu.committedInsts 199810242 # Number of instructions committed
< system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses
---
> system.cpu.committedInsts 199905607 # Number of instructions committed
> system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 374462045 # Number of integer alu accesses
256,257c256,257
< system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls
< system.cpu.num_int_insts 374289904 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls
> system.cpu.num_int_insts 374462045 # number of integer instructions
259,260c259,260
< system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read
< system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 915890298 # number of times the integer registers were read
> system.cpu.num_int_register_writes 480542887 # number of times the integer registers were written
263,269c263,269
< system.cpu.num_mem_refs 35624590 # number of memory refs
< system.cpu.num_load_insts 27216588 # Number of load instructions
< system.cpu.num_store_insts 8408002 # Number of store instructions
< system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles
< system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles
< system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
---
> system.cpu.num_mem_refs 35654170 # number of memory refs
> system.cpu.num_load_insts 27234345 # Number of load instructions
> system.cpu.num_store_insts 8419825 # Number of store instructions
> system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles
> system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles
> system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.955627 # Percentage of idle cycles
272,304c272,304
< system.cpu.icache.replacements 790732 # number of replacements
< system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use
< system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits
< system.cpu.icache.overall_hits::total 243360727 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses
< system.cpu.icache.overall_misses::total 791251 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses
---
> system.cpu.icache.replacements 790584 # number of replacements
> system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use
> system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits
> system.cpu.icache.overall_hits::total 243492014 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses
> system.cpu.icache.overall_misses::total 791103 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses
314,324c314,324
< system.cpu.itb_walker_cache.replacements 3335 # number of replacements
< system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use
< system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.replacements 3477 # number of replacements
> system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cycle average of tags in use
> system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits
327,338c327,338
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses)
341,350c341,350
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses
359,360c359,360
< system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks
---
> system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
362,394c362,394
< system.cpu.dtb_walker_cache.replacements 7597 # number of replacements
< system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses
---
> system.cpu.dtb_walker_cache.replacements 7629 # number of replacements
> system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12955 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 12955 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12955 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 12955 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12955 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 12955 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8819 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 8819 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8819 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 8819 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8819 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 8819 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21774 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 21774 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21774 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 21774 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21774 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 21774 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405024 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405024 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405024 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405024 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405024 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405024 # miss rate for overall accesses
403,404c403,404
< system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks
406,410c406,410
< system.cpu.dcache.replacements 1621135 # number of replacements
< system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use
< system.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks.
---
> system.cpu.dcache.replacements 1621965 # number of replacements
> system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use
> system.cpu.dcache.total_refs 20168700 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1622477 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 12.430808 # Average number of references to valid blocks.
412c412
< system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor
---
> system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor
415,446c415,446
< system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits
< system.cpu.dcache.overall_hits::total 20138169 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses
< system.cpu.dcache.overall_misses::total 1623919 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses
---
> system.cpu.dcache.ReadReq_hits::cpu.data 12073043 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 12073043 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8093389 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8093389 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20166432 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20166432 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20166432 # number of overall hits
> system.cpu.dcache.overall_hits::total 20166432 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1308511 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1308511 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 316250 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 316250 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 1624761 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1624761 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1624761 # number of overall misses
> system.cpu.dcache.overall_misses::total 1624761 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8409639 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21791193 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097785 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.097785 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037606 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.037606 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.074560 # miss rate for overall accesses
455,456c455,456
< system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks
< system.cpu.dcache.writebacks::total 1534848 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 1535695 # number of writebacks
> system.cpu.dcache.writebacks::total 1535695 # number of writebacks
458,462c458,462
< system.cpu.l2cache.replacements 106558 # number of replacements
< system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks.
---
> system.cpu.l2cache.replacements 105930 # number of replacements
> system.cpu.l2cache.tagsinuse 64821.868749 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 3456653 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 20.326318 # Average number of references to valid blocks.
464,469c464,469
< system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::writebacks 51906.789291 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 10424.349245 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy
472,495c472,495
< system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2241638 # number of overall hits
---
> system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.159063 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.989103 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1275631 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2062699 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1538634 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1538634 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 179586 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 179586 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1455217 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2242285 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1455217 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2242285 # number of overall hits
498,504c498,504
< system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 32248 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 45580 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 134391 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 134391 # number of ReadExReq misses
507,509c507,509
< system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 166639 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 179971 # number of demand (read+write) misses
512,554c512,554
< system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses
< system.cpu.l2cache.overall_misses::total 179909 # number of overall misses
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 166639 # number of overall misses
> system.cpu.l2cache.overall_misses::total 179971 # number of overall misses
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1307879 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2108279 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1538634 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1538634 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 313977 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 313977 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1621856 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2422256 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1621856 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2422256 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428028 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.428028 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.102746 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.074299 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.102746 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.074299 # miss rate for overall accesses
563,564c563,564
< system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks
< system.cpu.l2cache.writebacks::total 98530 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 98090 # number of writebacks
> system.cpu.l2cache.writebacks::total 98090 # number of writebacks
< sim_seconds 5.112041 # Number of seconds simulated
< sim_ticks 5112040970500 # Number of ticks simulated
< final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.112100 # Number of seconds simulated
> sim_ticks 5112099860500 # Number of ticks simulated
> final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,14c7,14
< host_inst_rate 1074050 # Simulator instruction rate (inst/s)
< host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 27479001055 # Simulator tick rate (ticks/s)
< host_mem_usage 583620 # Number of bytes of host memory used
< host_seconds 186.03 # Real time elapsed on the host
< sim_insts 199810242 # Number of instructions simulated
< sim_ops 409125913 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
---
> host_inst_rate 1028107 # Simulator instruction rate (inst/s)
> host_op_rate 2105009 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 26291327617 # Simulator tick rate (ticks/s)
> host_mem_usage 628192 # Number of bytes of host memory used
> host_seconds 194.44 # Real time elapsed on the host
> sim_insts 199905607 # Number of instructions simulated
> sim_ops 409299132 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory
17,24c17,24
< system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory
< system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory
< system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory
> system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 9264448 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9264448 # Number of bytes written to this memory
> system.physmem.num_reads::pc.south_bridge.ide 37827 # Number of read requests responded to by this memory
27,32c27,32
< system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory
< system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 165706 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 216864 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 144757 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 144757 # Number of write requests responded to by this memory
> system.physmem.bw_read::pc.south_bridge.ide 473568 # Total read bandwidth from this memory (bytes/s)
35,43c35,43
< system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2074526 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2714989 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1812259 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1812259 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1812259 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 473568 # Total bandwidth to/from this memory (bytes/s)
46,48c46,48
< system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2074526 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4527248 # Total bandwidth to/from this memory (bytes/s)
192,193c192,193
< system.iocache.replacements 47569 # number of replacements
< system.iocache.tagsinuse 0.042402 # Cycle average of tags in use
---
> system.iocache.replacements 47568 # number of replacements
> system.iocache.tagsinuse 0.042441 # Cycle average of tags in use
195c195
< system.iocache.sampled_refs 47585 # Sample count of references to valid blocks.
---
> system.iocache.sampled_refs 47584 # Sample count of references to valid blocks.
197,202c197,202
< system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit.
< system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor
< system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy
< system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy
< system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
< system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
---
> system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit.
> system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor
> system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
> system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy
> system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
> system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
205,210c205,210
< system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
< system.iocache.demand_misses::total 47624 # number of demand (read+write) misses
< system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses
< system.iocache.overall_misses::total 47624 # number of overall misses
< system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
< system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
---
> system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses
> system.iocache.demand_misses::total 47623 # number of demand (read+write) misses
> system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses
> system.iocache.overall_misses::total 47623 # number of overall misses
> system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
> system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
213,216c213,216
< system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses
< system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses
< system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses
< system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses
---
> system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses
> system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses
> system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses
> system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses
248c248
< system.cpu.numCycles 10224081964 # number of cpu cycles simulated
---
> system.cpu.numCycles 10224199744 # number of cpu cycles simulated
251,253c251,253
< system.cpu.committedInsts 199810242 # Number of instructions committed
< system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses
---
> system.cpu.committedInsts 199905607 # Number of instructions committed
> system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 374462045 # Number of integer alu accesses
256,257c256,257
< system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls
< system.cpu.num_int_insts 374289904 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls
> system.cpu.num_int_insts 374462045 # number of integer instructions
259,260c259,260
< system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read
< system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 915890298 # number of times the integer registers were read
> system.cpu.num_int_register_writes 480542887 # number of times the integer registers were written
263,269c263,269
< system.cpu.num_mem_refs 35624590 # number of memory refs
< system.cpu.num_load_insts 27216588 # Number of load instructions
< system.cpu.num_store_insts 8408002 # Number of store instructions
< system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles
< system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles
< system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
< system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
---
> system.cpu.num_mem_refs 35654170 # number of memory refs
> system.cpu.num_load_insts 27234345 # Number of load instructions
> system.cpu.num_store_insts 8419825 # Number of store instructions
> system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles
> system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles
> system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles
> system.cpu.idle_fraction 0.955627 # Percentage of idle cycles
272,304c272,304
< system.cpu.icache.replacements 790732 # number of replacements
< system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use
< system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits
< system.cpu.icache.overall_hits::total 243360727 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses
< system.cpu.icache.overall_misses::total 791251 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses
---
> system.cpu.icache.replacements 790584 # number of replacements
> system.cpu.icache.tagsinuse 510.666660 # Cycle average of tags in use
> system.cpu.icache.total_refs 243492014 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 791096 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 307.790728 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.997396 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 243492014 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 243492014 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 243492014 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 243492014 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 243492014 # number of overall hits
> system.cpu.icache.overall_hits::total 243492014 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 791103 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 791103 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 791103 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 791103 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 791103 # number of overall misses
> system.cpu.icache.overall_misses::total 791103 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 244283117 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 244283117 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 244283117 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 244283117 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 244283117 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 244283117 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses
314,324c314,324
< system.cpu.itb_walker_cache.replacements 3335 # number of replacements
< system.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use
< system.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks.
< system.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks.
< system.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks.
< system.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor
< system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy
< system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits
< system.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits
---
> system.cpu.itb_walker_cache.replacements 3477 # number of replacements
> system.cpu.itb_walker_cache.tagsinuse 3.026333 # Cycle average of tags in use
> system.cpu.itb_walker_cache.total_refs 7886 # Total number of references to valid blocks.
> system.cpu.itb_walker_cache.sampled_refs 3489 # Sample count of references to valid blocks.
> system.cpu.itb_walker_cache.avg_refs 2.260246 # Average number of references to valid blocks.
> system.cpu.itb_walker_cache.warmup_cycle 5102064745500 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026333 # Average occupied blocks per requestor
> system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189146 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.occ_percent::total 0.189146 # Average percentage of cache occupancy
> system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits
> system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits
327,338c327,338
< system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits
< system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits
< system.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits
< system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses
< system.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses
< system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses
< system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses
< system.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses
< system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
< system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
---
> system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits
> system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits
> system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits
> system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses
> system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses
> system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses
> system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses
> system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses
> system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses)
> system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses)
341,350c341,350
< system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses
< system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses
< system.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses
< system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses
< system.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses
---
> system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses
> system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses
> system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses
> system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses
> system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses
359,360c359,360
< system.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks
< system.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks
---
> system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks
> system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
362,394c362,394
< system.cpu.dtb_walker_cache.replacements 7597 # number of replacements
< system.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks.
< system.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks.
< system.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits
< system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses
< system.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses
< system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses
< system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses
< system.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses
---
> system.cpu.dtb_walker_cache.replacements 7629 # number of replacements
> system.cpu.dtb_walker_cache.tagsinuse 5.014191 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.total_refs 12947 # Total number of references to valid blocks.
> system.cpu.dtb_walker_cache.sampled_refs 7641 # Sample count of references to valid blocks.
> system.cpu.dtb_walker_cache.avg_refs 1.694412 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.warmup_cycle 5100425401500 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.014191 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313387 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.occ_percent::total 0.313387 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12955 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 12955 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12955 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 12955 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12955 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 12955 # number of overall hits
> system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8819 # number of ReadReq misses
> system.cpu.dtb_walker_cache.ReadReq_misses::total 8819 # number of ReadReq misses
> system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8819 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.demand_misses::total 8819 # number of demand (read+write) misses
> system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8819 # number of overall misses
> system.cpu.dtb_walker_cache.overall_misses::total 8819 # number of overall misses
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21774 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 21774 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21774 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 21774 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21774 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 21774 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405024 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405024 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405024 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405024 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405024 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405024 # miss rate for overall accesses
403,404c403,404
< system.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks
< system.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks
---
> system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks
> system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks
406,410c406,410
< system.cpu.dcache.replacements 1621135 # number of replacements
< system.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use
< system.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks.
---
> system.cpu.dcache.replacements 1621965 # number of replacements
> system.cpu.dcache.tagsinuse 511.999425 # Cycle average of tags in use
> system.cpu.dcache.total_refs 20168700 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 1622477 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 12.430808 # Average number of references to valid blocks.
412c412
< system.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor
---
> system.cpu.dcache.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor
415,446c415,446
< system.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits
< system.cpu.dcache.overall_hits::total 20138169 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses
< system.cpu.dcache.overall_misses::total 1623919 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses
---
> system.cpu.dcache.ReadReq_hits::cpu.data 12073043 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 12073043 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8093389 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8093389 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20166432 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20166432 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20166432 # number of overall hits
> system.cpu.dcache.overall_hits::total 20166432 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 1308511 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 1308511 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 316250 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 316250 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 1624761 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1624761 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1624761 # number of overall misses
> system.cpu.dcache.overall_misses::total 1624761 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 13381554 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 13381554 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8409639 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8409639 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21791193 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21791193 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21791193 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21791193 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097785 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.097785 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037606 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.037606 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.074560 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.074560 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.074560 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.074560 # miss rate for overall accesses
455,456c455,456
< system.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks
< system.cpu.dcache.writebacks::total 1534848 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 1535695 # number of writebacks
> system.cpu.dcache.writebacks::total 1535695 # number of writebacks
458,462c458,462
< system.cpu.l2cache.replacements 106558 # number of replacements
< system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks.
---
> system.cpu.l2cache.replacements 105930 # number of replacements
> system.cpu.l2cache.tagsinuse 64821.868749 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 3456653 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 170058 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 20.326318 # Average number of references to valid blocks.
464,469c464,469
< system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::writebacks 51906.789291 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132241 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 2490.593013 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 10424.349245 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy
472,495c472,495
< system.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits
< system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits
< system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2241638 # number of overall hits
---
> system.cpu.l2cache.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.159063 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.989103 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6501 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.inst 777765 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1275631 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2062699 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1538634 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1538634 # number of Writeback hits
> system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
> system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 179586 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 179586 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.dtb.walker 6501 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.inst 777765 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1455217 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2242285 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.dtb.walker 6501 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.inst 777765 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1455217 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2242285 # number of overall hits
498,504c498,504
< system.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 32248 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 45580 # number of ReadReq misses
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 134391 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 134391 # number of ReadExReq misses
507,509c507,509
< system.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 166639 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 179971 # number of demand (read+write) misses
512,554c512,554
< system.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses
< system.cpu.l2cache.overall_misses::total 179909 # number of overall misses
< system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 166639 # number of overall misses
> system.cpu.l2cache.overall_misses::total 179971 # number of overall misses
> system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6503 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 791090 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1307879 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2108279 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1538634 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1538634 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 313977 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 313977 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6503 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.inst 791090 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1621856 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2422256 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6503 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 791090 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1621856 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2422256 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428028 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.428028 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.102746 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.074299 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.102746 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.074299 # miss rate for overall accesses
563,564c563,564
< system.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks
< system.cpu.l2cache.writebacks::total 98530 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 98090 # number of writebacks
> system.cpu.l2cache.writebacks::total 98090 # number of writebacks