4,5c4,5
< sim_ticks 5112040968500 # Number of ticks simulated
< final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 5112040970500 # Number of ticks simulated
> final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 468346 # Simulator instruction rate (inst/s)
< host_op_rate 958973 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 11982395829 # Simulator tick rate (ticks/s)
< host_mem_usage 354180 # Number of bytes of host memory used
< host_seconds 426.63 # Real time elapsed on the host
< sim_insts 199810236 # Number of instructions simulated
< sim_ops 409125920 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1661898 # Simulator instruction rate (inst/s)
> host_op_rate 3402855 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 42518772648 # Simulator tick rate (ticks/s)
> host_mem_usage 621064 # Number of bytes of host memory used
> host_seconds 120.23 # Real time elapsed on the host
> sim_insts 199810242 # Number of instructions simulated
> sim_ops 409125923 # Number of ops (including micro ops) simulated
212c212
< system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit.
---
> system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit.
263c263
< system.cpu.numCycles 10224081960 # number of cpu cycles simulated
---
> system.cpu.numCycles 10224081964 # number of cpu cycles simulated
266,268c266,268
< system.cpu.committedInsts 199810236 # Number of instructions committed
< system.cpu.committedOps 409125920 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 374289911 # Number of integer alu accesses
---
> system.cpu.committedInsts 199810242 # Number of instructions committed
> system.cpu.committedOps 409125923 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 374289914 # Number of integer alu accesses
271,272c271,272
< system.cpu.num_conditional_control_insts 39954536 # number of instructions that are conditional controls
< system.cpu.num_int_insts 374289911 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls
> system.cpu.num_int_insts 374289914 # number of integer instructions
274,275c274,275
< system.cpu.num_int_register_reads 915450709 # number of times the integer registers were read
< system.cpu.num_int_register_writes 480322748 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 915450706 # number of times the integer registers were read
> system.cpu.num_int_register_writes 480322745 # number of times the integer registers were written
278c278
< system.cpu.num_mem_refs 35624588 # number of memory refs
---
> system.cpu.num_mem_refs 35624590 # number of memory refs
280,282c280,282
< system.cpu.num_store_insts 8408000 # Number of store instructions
< system.cpu.num_idle_cycles 9770609595.971962 # Number of idle cycles
< system.cpu.num_busy_cycles 453472364.028039 # Number of busy cycles
---
> system.cpu.num_store_insts 8408002 # Number of store instructions
> system.cpu.num_idle_cycles 9770609597.971960 # Number of idle cycles
> system.cpu.num_busy_cycles 453472366.028039 # Number of busy cycles
288,289c288,289
< system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
< system.cpu.icache.total_refs 243360722 # Total number of references to valid blocks.
---
> system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use
> system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks.
291,293c291,293
< system.cpu.icache.avg_refs 307.567226 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
---
> system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor
296,301c296,301
< system.cpu.icache.ReadReq_hits::cpu.inst 243360722 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 243360722 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 243360722 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 243360722 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 243360722 # number of overall hits
< system.cpu.icache.overall_hits::total 243360722 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits
> system.cpu.icache.overall_hits::total 243360727 # number of overall hits
308,313c308,313
< system.cpu.icache.ReadReq_accesses::cpu.inst 244151973 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 244151973 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 244151973 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 244151973 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 244151973 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 244151973 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses
334c334
< system.cpu.itb_walker_cache.warmup_cycle 5102019608500 # Cycle when the warmup percentage was hit.
---
> system.cpu.itb_walker_cache.warmup_cycle 5102019610500 # Cycle when the warmup percentage was hit.
382c382
< system.cpu.dtb_walker_cache.warmup_cycle 5101206384000 # Cycle when the warmup percentage was hit.
---
> system.cpu.dtb_walker_cache.warmup_cycle 5101206386000 # Cycle when the warmup percentage was hit.
423c423
< system.cpu.dcache.total_refs 20140429 # Total number of references to valid blocks.
---
> system.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks.
425c425
< system.cpu.dcache.avg_refs 12.419737 # Average number of references to valid blocks.
---
> system.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks.
432,437c432,437
< system.cpu.dcache.WriteReq_hits::cpu.data 8082226 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8082226 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20138167 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20138167 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20138167 # number of overall hits
< system.cpu.dcache.overall_hits::total 20138167 # number of overall hits
---
> system.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits
> system.cpu.dcache.overall_hits::total 20138169 # number of overall hits
448,453c448,453
< system.cpu.dcache.WriteReq_accesses::cpu.data 8398054 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8398054 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21762086 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21762086 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21762086 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21762086 # number of overall (read+write) accesses
---
> system.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses
474c474
< system.cpu.l2cache.tagsinuse 64822.149247 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 64822.149219 # Cycle average of tags in use
479c479
< system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor
482,483c482,483
< system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 10405.564957 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 2434.994082 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 10405.564951 # Average occupied blocks per requestor
< sim_ticks 5112040968500 # Number of ticks simulated
< final_tick 5112040968500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 5112040970500 # Number of ticks simulated
> final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 468346 # Simulator instruction rate (inst/s)
< host_op_rate 958973 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 11982395829 # Simulator tick rate (ticks/s)
< host_mem_usage 354180 # Number of bytes of host memory used
< host_seconds 426.63 # Real time elapsed on the host
< sim_insts 199810236 # Number of instructions simulated
< sim_ops 409125920 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1661898 # Simulator instruction rate (inst/s)
> host_op_rate 3402855 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 42518772648 # Simulator tick rate (ticks/s)
> host_mem_usage 621064 # Number of bytes of host memory used
> host_seconds 120.23 # Real time elapsed on the host
> sim_insts 199810242 # Number of instructions simulated
> sim_ops 409125923 # Number of ops (including micro ops) simulated
212c212
< system.iocache.warmup_cycle 4994776680059 # Cycle when the warmup percentage was hit.
---
> system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit.
263c263
< system.cpu.numCycles 10224081960 # number of cpu cycles simulated
---
> system.cpu.numCycles 10224081964 # number of cpu cycles simulated
266,268c266,268
< system.cpu.committedInsts 199810236 # Number of instructions committed
< system.cpu.committedOps 409125920 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 374289911 # Number of integer alu accesses
---
> system.cpu.committedInsts 199810242 # Number of instructions committed
> system.cpu.committedOps 409125923 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 374289914 # Number of integer alu accesses
271,272c271,272
< system.cpu.num_conditional_control_insts 39954536 # number of instructions that are conditional controls
< system.cpu.num_int_insts 374289911 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 39954535 # number of instructions that are conditional controls
> system.cpu.num_int_insts 374289914 # number of integer instructions
274,275c274,275
< system.cpu.num_int_register_reads 915450709 # number of times the integer registers were read
< system.cpu.num_int_register_writes 480322748 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 915450706 # number of times the integer registers were read
> system.cpu.num_int_register_writes 480322745 # number of times the integer registers were written
278c278
< system.cpu.num_mem_refs 35624588 # number of memory refs
---
> system.cpu.num_mem_refs 35624590 # number of memory refs
280,282c280,282
< system.cpu.num_store_insts 8408000 # Number of store instructions
< system.cpu.num_idle_cycles 9770609595.971962 # Number of idle cycles
< system.cpu.num_busy_cycles 453472364.028039 # Number of busy cycles
---
> system.cpu.num_store_insts 8408002 # Number of store instructions
> system.cpu.num_idle_cycles 9770609597.971960 # Number of idle cycles
> system.cpu.num_busy_cycles 453472366.028039 # Number of busy cycles
288,289c288,289
< system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
< system.cpu.icache.total_refs 243360722 # Total number of references to valid blocks.
---
> system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use
> system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks.
291,293c291,293
< system.cpu.icache.avg_refs 307.567226 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit.
< system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
---
> system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit.
> system.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor
296,301c296,301
< system.cpu.icache.ReadReq_hits::cpu.inst 243360722 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 243360722 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 243360722 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 243360722 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 243360722 # number of overall hits
< system.cpu.icache.overall_hits::total 243360722 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits
> system.cpu.icache.overall_hits::total 243360727 # number of overall hits
308,313c308,313
< system.cpu.icache.ReadReq_accesses::cpu.inst 244151973 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 244151973 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 244151973 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 244151973 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 244151973 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 244151973 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses
334c334
< system.cpu.itb_walker_cache.warmup_cycle 5102019608500 # Cycle when the warmup percentage was hit.
---
> system.cpu.itb_walker_cache.warmup_cycle 5102019610500 # Cycle when the warmup percentage was hit.
382c382
< system.cpu.dtb_walker_cache.warmup_cycle 5101206384000 # Cycle when the warmup percentage was hit.
---
> system.cpu.dtb_walker_cache.warmup_cycle 5101206386000 # Cycle when the warmup percentage was hit.
423c423
< system.cpu.dcache.total_refs 20140429 # Total number of references to valid blocks.
---
> system.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks.
425c425
< system.cpu.dcache.avg_refs 12.419737 # Average number of references to valid blocks.
---
> system.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks.
432,437c432,437
< system.cpu.dcache.WriteReq_hits::cpu.data 8082226 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8082226 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 20138167 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20138167 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20138167 # number of overall hits
< system.cpu.dcache.overall_hits::total 20138167 # number of overall hits
---
> system.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits
> system.cpu.dcache.overall_hits::total 20138169 # number of overall hits
448,453c448,453
< system.cpu.dcache.WriteReq_accesses::cpu.data 8398054 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8398054 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 21762086 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21762086 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21762086 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21762086 # number of overall (read+write) accesses
---
> system.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses
474c474
< system.cpu.l2cache.tagsinuse 64822.149247 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 64822.149219 # Cycle average of tags in use
479c479
< system.cpu.l2cache.occ_blocks::writebacks 51981.453140 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor
482,483c482,483
< system.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 10405.564957 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 2434.994082 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 10405.564951 # Average occupied blocks per requestor