7,13c7,13
< host_inst_rate 1996585 # Simulator instruction rate (inst/s)
< host_op_rate 4088150 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 51080652430 # Simulator tick rate (ticks/s)
< host_mem_usage 357308 # Number of bytes of host memory used
< host_seconds 100.08 # Real time elapsed on the host
< sim_insts 199813912 # Number of instructions simulated
< sim_ops 409133288 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1067695 # Simulator instruction rate (inst/s)
> host_op_rate 2186181 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 27315912254 # Simulator tick rate (ticks/s)
> host_mem_usage 409548 # Number of bytes of host memory used
> host_seconds 187.15 # Real time elapsed on the host
> sim_insts 199813914 # Number of instructions simulated
> sim_ops 409133298 # Number of ops (including micro ops) simulated
50c50
< system.l2c.tagsinuse 64822.143270 # Cycle average of tags in use
---
> system.l2c.tagsinuse 64822.143261 # Cycle average of tags in use
55c55
< system.l2c.occ_blocks::writebacks 51981.461992 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor
58,59c58,59
< system.l2c.occ_blocks::cpu.inst 2434.983597 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 10405.560616 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor
216,218c216,218
< system.cpu.committedInsts 199813912 # Number of instructions committed
< system.cpu.committedOps 409133288 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 374297254 # Number of integer alu accesses
---
> system.cpu.committedInsts 199813914 # Number of instructions committed
> system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses
221,222c221,222
< system.cpu.num_conditional_control_insts 39954972 # number of instructions that are conditional controls
< system.cpu.num_int_insts 374297254 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls
> system.cpu.num_int_insts 374297264 # number of integer instructions
224,225c224,225
< system.cpu.num_int_register_reads 1159028950 # number of times the integer registers were read
< system.cpu.num_int_register_writes 636431660 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 1159028989 # number of times the integer registers were read
> system.cpu.num_int_register_writes 636431681 # number of times the integer registers were written
231,232c231,232
< system.cpu.num_idle_cycles 9770605328.086651 # Number of idle cycles
< system.cpu.num_busy_cycles 453481202.913350 # Number of busy cycles
---
> system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles
> system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles
239c239
< system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
---
> system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks.
241,242c241,242
< system.cpu.icache.avg_refs 307.549904 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
---
> system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit.
246,251c246,251
< system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits
< system.cpu.icache.overall_hits::total 243365777 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits
> system.cpu.icache.overall_hits::total 243365779 # number of overall hits
258,263c258,263
< system.cpu.icache.ReadReq_accesses::cpu.inst 244157089 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 244157089 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 244157089 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 244157089 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 244157089 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 244157089 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
< host_inst_rate 1996585 # Simulator instruction rate (inst/s)
< host_op_rate 4088150 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 51080652430 # Simulator tick rate (ticks/s)
< host_mem_usage 357308 # Number of bytes of host memory used
< host_seconds 100.08 # Real time elapsed on the host
< sim_insts 199813912 # Number of instructions simulated
< sim_ops 409133288 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1067695 # Simulator instruction rate (inst/s)
> host_op_rate 2186181 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 27315912254 # Simulator tick rate (ticks/s)
> host_mem_usage 409548 # Number of bytes of host memory used
> host_seconds 187.15 # Real time elapsed on the host
> sim_insts 199813914 # Number of instructions simulated
> sim_ops 409133298 # Number of ops (including micro ops) simulated
50c50
< system.l2c.tagsinuse 64822.143270 # Cycle average of tags in use
---
> system.l2c.tagsinuse 64822.143261 # Cycle average of tags in use
55c55
< system.l2c.occ_blocks::writebacks 51981.461992 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor
58,59c58,59
< system.l2c.occ_blocks::cpu.inst 2434.983597 # Average occupied blocks per requestor
< system.l2c.occ_blocks::cpu.data 10405.560616 # Average occupied blocks per requestor
---
> system.l2c.occ_blocks::cpu.inst 2434.983596 # Average occupied blocks per requestor
> system.l2c.occ_blocks::cpu.data 10405.560614 # Average occupied blocks per requestor
216,218c216,218
< system.cpu.committedInsts 199813912 # Number of instructions committed
< system.cpu.committedOps 409133288 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 374297254 # Number of integer alu accesses
---
> system.cpu.committedInsts 199813914 # Number of instructions committed
> system.cpu.committedOps 409133298 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 374297264 # Number of integer alu accesses
221,222c221,222
< system.cpu.num_conditional_control_insts 39954972 # number of instructions that are conditional controls
< system.cpu.num_int_insts 374297254 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 39954974 # number of instructions that are conditional controls
> system.cpu.num_int_insts 374297264 # number of integer instructions
224,225c224,225
< system.cpu.num_int_register_reads 1159028950 # number of times the integer registers were read
< system.cpu.num_int_register_writes 636431660 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 1159028989 # number of times the integer registers were read
> system.cpu.num_int_register_writes 636431681 # number of times the integer registers were written
231,232c231,232
< system.cpu.num_idle_cycles 9770605328.086651 # Number of idle cycles
< system.cpu.num_busy_cycles 453481202.913350 # Number of busy cycles
---
> system.cpu.num_idle_cycles 9770605318.086651 # Number of idle cycles
> system.cpu.num_busy_cycles 453481212.913350 # Number of busy cycles
239c239
< system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
---
> system.cpu.icache.total_refs 243365779 # Total number of references to valid blocks.
241,242c241,242
< system.cpu.icache.avg_refs 307.549904 # Average number of references to valid blocks.
< system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
---
> system.cpu.icache.avg_refs 307.549907 # Average number of references to valid blocks.
> system.cpu.icache.warmup_cycle 148763110500 # Cycle when the warmup percentage was hit.
246,251c246,251
< system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits
< system.cpu.icache.overall_hits::total 243365777 # number of overall hits
---
> system.cpu.icache.ReadReq_hits::cpu.inst 243365779 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 243365779 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 243365779 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 243365779 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 243365779 # number of overall hits
> system.cpu.icache.overall_hits::total 243365779 # number of overall hits
258,263c258,263
< system.cpu.icache.ReadReq_accesses::cpu.inst 244157089 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 244157089 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 244157089 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 244157089 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 244157089 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 244157089 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses