3,5c3,5
< sim_seconds 5.112155 # Number of seconds simulated
< sim_ticks 5112155173500 # Number of ticks simulated
< final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.112156 # Number of seconds simulated
> sim_ticks 5112155738500 # Number of ticks simulated
> final_tick 5112155738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1977176 # Simulator instruction rate (inst/s)
< host_op_rate 4047982 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 50529549296 # Simulator tick rate (ticks/s)
< host_mem_usage 594968 # Number of bytes of host memory used
< host_seconds 101.17 # Real time elapsed on the host
< sim_insts 200033988 # Number of instructions simulated
< sim_ops 409540726 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1511003 # Simulator instruction rate (inst/s)
> host_op_rate 3093560 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 38615908446 # Simulator tick rate (ticks/s)
> host_mem_usage 595640 # Number of bytes of host memory used
> host_seconds 132.38 # Real time elapsed on the host
> sim_insts 200033669 # Number of instructions simulated
> sim_ops 409539941 # Number of ops (including micro ops) simulated
18,19c18,19
< system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 852224 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10636736 # Number of bytes read from this memory
21,26c21,25
< system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory
< system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 11517696 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 852224 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 852224 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 9281152 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9281152 # Number of bytes written to this memory
29,30c28,29
< system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 13316 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 166199 # Number of read requests responded to by this memory
32,35c31,33
< system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory
< system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 179964 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 145018 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 145018 # Number of write requests responded to by this memory
38,39c36,37
< system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 166705 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2080675 # Total read bandwidth from this memory (bytes/s)
41,47c39,44
< system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1231249 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 2253002 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 166705 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 166705 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1815507 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1815507 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1815507 # Total bandwidth to/from this memory (bytes/s)
50,53c47,50
< system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 166705 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2080675 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4068508 # Total bandwidth to/from this memory (bytes/s)
56c53
< system.cpu.numCycles 10224314318 # number of cpu cycles simulated
---
> system.cpu.numCycles 10224315447 # number of cpu cycles simulated
59,61c56,58
< system.cpu.committedInsts 200033988 # Number of instructions committed
< system.cpu.committedOps 409540726 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 374550150 # Number of integer alu accesses
---
> system.cpu.committedInsts 200033669 # Number of instructions committed
> system.cpu.committedOps 409539941 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 374549395 # Number of integer alu accesses
63,65c60,62
< system.cpu.num_func_calls 2308777 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 39994865 # number of instructions that are conditional controls
< system.cpu.num_int_insts 374550150 # number of integer instructions
---
> system.cpu.num_func_calls 2308749 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 39994798 # number of instructions that are conditional controls
> system.cpu.num_int_insts 374549395 # number of integer instructions
67,68c64,65
< system.cpu.num_int_register_reads 682630172 # number of times the integer registers were read
< system.cpu.num_int_register_writes 323525861 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 682628451 # number of times the integer registers were read
> system.cpu.num_int_register_writes 323525110 # number of times the integer registers were written
71,77c68,74
< system.cpu.num_cc_register_reads 233820803 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 157313619 # number of times the CC registers were written
< system.cpu.num_mem_refs 35680563 # number of memory refs
< system.cpu.num_load_insts 27249389 # Number of load instructions
< system.cpu.num_store_insts 8431174 # Number of store instructions
< system.cpu.num_idle_cycles 9770366809.410368 # Number of idle cycles
< system.cpu.num_busy_cycles 453947508.589632 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 233820400 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 157313425 # number of times the CC registers were written
> system.cpu.num_mem_refs 35680406 # number of memory refs
> system.cpu.num_load_insts 27249300 # Number of load instructions
> system.cpu.num_store_insts 8431106 # Number of store instructions
> system.cpu.num_idle_cycles 9770368815.449127 # Number of idle cycles
> system.cpu.num_busy_cycles 453946631.550873 # Number of busy cycles
80,84c77,81
< system.cpu.Branches 43145769 # Number of branches fetched
< system.cpu.op_class::No_OpClass 175400 0.04% 0.04% # Class of executed instruction
< system.cpu.op_class::IntAlu 373418196 91.18% 91.22% # Class of executed instruction
< system.cpu.op_class::IntMult 144548 0.04% 91.26% # Class of executed instruction
< system.cpu.op_class::IntDiv 123054 0.03% 91.29% # Class of executed instruction
---
> system.cpu.Branches 43145649 # Number of branches fetched
> system.cpu.op_class::No_OpClass 175370 0.04% 0.04% # Class of executed instruction
> system.cpu.op_class::IntAlu 373417675 91.18% 91.22% # Class of executed instruction
> system.cpu.op_class::IntMult 144551 0.04% 91.26% # Class of executed instruction
> system.cpu.op_class::IntDiv 122974 0.03% 91.29% # Class of executed instruction
111,112c108,109
< system.cpu.op_class::MemRead 27249389 6.65% 97.94% # Class of executed instruction
< system.cpu.op_class::MemWrite 8431174 2.06% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 27249300 6.65% 97.94% # Class of executed instruction
> system.cpu.op_class::MemWrite 8431106 2.06% 100.00% # Class of executed instruction
115c112
< system.cpu.op_class::total 409541761 # Class of executed instruction
---
> system.cpu.op_class::total 409540976 # Class of executed instruction
118c115
< system.cpu.dcache.tags.replacements 1623441 # number of replacements
---
> system.cpu.dcache.tags.replacements 1623460 # number of replacements
120,122c117,119
< system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 20193083 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1623972 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 12.434379 # Average number of references to valid blocks.
132,157c129,154
< system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits
< system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits
< system.cpu.dcache.overall_hits::total 20190999 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses
< system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses
< system.cpu.dcache.overall_misses::total 1626230 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.tags.tag_accesses 88892257 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 88892257 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 12028370 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 12028370 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8103548 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8103548 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 58901 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 58901 # number of SoftPFReq hits
> system.cpu.dcache.demand_hits::cpu.data 20131918 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20131918 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20190819 # number of overall hits
> system.cpu.dcache.overall_hits::total 20190819 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 906001 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 906001 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 317188 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 317188 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 403060 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 403060 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 1223189 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1223189 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1626249 # number of overall misses
> system.cpu.dcache.overall_misses::total 1626249 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 12934371 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 12934371 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8420736 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8420736 # number of WriteReq accesses(hits+misses)
160,173c157,170
< system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 21355107 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21355107 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21817068 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21817068 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070046 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.070046 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037667 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.037667 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872498 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.872498 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.074540 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.074540 # miss rate for overall accesses
182,183c179,180
< system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks
< system.cpu.dcache.writebacks::total 1536849 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 1536867 # number of writebacks
> system.cpu.dcache.writebacks::total 1536867 # number of writebacks
186,187c183,184
< system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks.
---
> system.cpu.dtb_walker_cache.tags.tagsinuse 5.013943 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 12520 # Total number of references to valid blocks.
189,193c186,190
< system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy
---
> system.cpu.dtb_walker_cache.tags.avg_refs 1.529067 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 5101318572500 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013943 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313371 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313371 # Average percentage of cache occupancy
199,206c196,203
< system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses
< system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits
---
> system.cpu.dtb_walker_cache.tags.tag_accesses 53161 # Number of tag accesses
> system.cpu.dtb_walker_cache.tags.data_accesses 53161 # Number of data accesses
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12521 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 12521 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12521 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 12521 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12521 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 12521 # number of overall hits
213,224c210,221
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses
---
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428108 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428108 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428108 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428108 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428108 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428108 # miss rate for overall accesses
236c233
< system.cpu.icache.tags.replacements 791952 # number of replacements
---
> system.cpu.icache.tags.replacements 791846 # number of replacements
238,240c235,237
< system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 792464 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 307.453687 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 243645674 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 792358 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 307.494433 # Average number of references to valid blocks.
251,270c248,267
< system.cpu.icache.tags.tag_accesses 245230921 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 245230921 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 243645979 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 243645979 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 243645979 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 243645979 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 243645979 # number of overall hits
< system.cpu.icache.overall_hits::total 243645979 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 792471 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 792471 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 792471 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 792471 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 792471 # number of overall misses
< system.cpu.icache.overall_misses::total 792471 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 244438450 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 244438450 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 244438450 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 244438450 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 244438450 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 244438450 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 245230404 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 245230404 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 243645674 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 243645674 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 243645674 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 243645674 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 243645674 # number of overall hits
> system.cpu.icache.overall_hits::total 243645674 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 792365 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 792365 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 792365 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 792365 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 792365 # number of overall misses
> system.cpu.icache.overall_misses::total 792365 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 244438039 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 244438039 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 244438039 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 244438039 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 244438039 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 244438039 # number of overall (read+write) accesses
287c284
< system.cpu.itb_walker_cache.tags.tagsinuse 3.026453 # Cycle average of tags in use
---
> system.cpu.itb_walker_cache.tags.tagsinuse 3.026443 # Cycle average of tags in use
291,292c288,289
< system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026453 # Average occupied blocks per requestor
---
> system.cpu.itb_walker_cache.tags.warmup_cycle 5102148365500 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026443 # Average occupied blocks per requestor
342,346c339,343
< system.cpu.l2cache.tags.replacements 106197 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 170308 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 20.327125 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 106199 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64825.456332 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3461789 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 170310 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 20.326399 # Average number of references to valid blocks.
348c345
< system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 51911.006068 # Average occupied blocks per requestor
350,352c347,349
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132278 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.291417 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132276 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.288805 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.026704 # Average occupied blocks per requestor
363,364c360,361
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20721 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39577 # Occupied blocks per task id
366,367c363,364
< system.cpu.l2cache.tags.tag_accesses 32246059 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 32246059 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 32245523 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 32245523 # Number of data accesses
370,374c367,371
< system.cpu.l2cache.ReadReq_hits::cpu.inst 779141 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1276184 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2065993 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1540445 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1540445 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 779035 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1276188 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2065891 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1540463 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1540463 # number of Writeback hits
377,378c374,375
< system.cpu.l2cache.ReadExReq_hits::cpu.data 180006 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 180006 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 180020 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 180020 # number of ReadExReq hits
381,383c378,380
< system.cpu.l2cache.demand_hits::cpu.inst 779141 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1456190 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2245999 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 779035 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1456208 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2245911 # number of demand (read+write) hits
386,388c383,385
< system.cpu.l2cache.overall_hits::cpu.inst 779141 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1456190 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2245999 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 779035 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1456208 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2245911 # number of overall hits
396,397c393,394
< system.cpu.l2cache.ReadExReq_misses::cpu.data 134898 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 134898 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 134899 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 134899 # number of ReadExReq misses
401,402c398,399
< system.cpu.l2cache.demand_misses::cpu.data 167130 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 180453 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 167131 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 180454 # number of demand (read+write) misses
406,407c403,404
< system.cpu.l2cache.overall_misses::cpu.data 167130 # number of overall misses
< system.cpu.l2cache.overall_misses::total 180453 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.data 167131 # number of overall misses
> system.cpu.l2cache.overall_misses::total 180454 # number of overall misses
410,414c407,411
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 792458 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1308416 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2111548 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1540445 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1540445 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 792352 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1308420 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2111446 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1540463 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1540463 # number of Writeback accesses(hits+misses)
417,418c414,415
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 314904 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 314904 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 314919 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 314919 # number of ReadExReq accesses(hits+misses)
421,423c418,420
< system.cpu.l2cache.demand_accesses::cpu.inst 792458 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1623320 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2426452 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 792352 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1623339 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2426365 # number of demand (read+write) accesses
426,428c423,425
< system.cpu.l2cache.overall_accesses::cpu.inst 792458 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1623320 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2426452 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 792352 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1623339 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2426365 # number of overall (read+write) accesses
431c428
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016805 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses
433c430
< system.cpu.l2cache.ReadReq_miss_rate::total 0.021574 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.021575 # miss rate for ReadReq accesses
436,437c433,434
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428378 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.428378 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428361 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.428361 # miss rate for ReadExReq accesses
440,442c437,439
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016805 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102956 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.074369 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.102955 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.074372 # miss rate for demand accesses
445,447c442,444
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016805 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102956 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.074369 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.102955 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.074372 # miss rate for overall accesses
456,457c453,454
< system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks
< system.cpu.l2cache.writebacks::total 98349 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 98351 # number of writebacks
> system.cpu.l2cache.writebacks::total 98351 # number of writebacks
459,460c456,457
< system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 15972684 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 15972684 # Transaction distribution
463c460
< system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 1540463 # Transaction distribution
466,469c463,466
< system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 314924 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 314924 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584730 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531797 # Packet count per connected master and slave (bytes)
472,474c469,471
< system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 34148029 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50711360 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227719225 # Cumulative packet size per connected master and slave (bytes)
477c474
< system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 279553721 # Cumulative packet size per connected master and slave (bytes)
479c476
< system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 4020658 # Request fanout histogram
481c478
< system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::stdev 0.108192 # Request fanout histogram
486c483
< system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 3973030 98.82% 98.82% # Request fanout histogram
491c488
< system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 4020658 # Request fanout histogram
548c545
< system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.042450 # Cycle average of tags in use
553c550
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
---
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042450 # Average occupied blocks per requestor
561,562d557
< system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
< system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
564a560,561
> system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
578a576,577
> system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
589c588
< system.iocache.fast_writes 46720 # number of fast writes performed
---
> system.iocache.fast_writes 0 # number of fast writes performed
590a590,591
> system.iocache.writebacks::writebacks 46667 # number of writebacks
> system.iocache.writebacks::total 46667 # number of writebacks
596c597
< system.membus.trans_dist::Writeback 98349 # Transaction distribution
---
> system.membus.trans_dist::Writeback 145018 # Transaction distribution
601,602c602,603
< system.membus.trans_dist::ReadExReq 134620 # Transaction distribution
< system.membus.trans_dist::ReadExResp 134615 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 134621 # Transaction distribution
> system.membus.trans_dist::ReadExResp 134616 # Transaction distribution
609,613c610,614
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463319 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205751 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141923 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 141923 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 28351066 # Packet count per connected master and slave (bytes)
618,622c619,623
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825408 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43250105 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 6034880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 49291769 # Cumulative packet size per connected master and slave (bytes)
624c625
< system.membus.snoop_fanout::samples 328677 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 375347 # Request fanout histogram
629c630
< system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 375347 100.00% 100.00% # Request fanout histogram
634c635
< system.membus.snoop_fanout::total 328677 # Request fanout histogram
---
> system.membus.snoop_fanout::total 375347 # Request fanout histogram
< sim_seconds 5.112155 # Number of seconds simulated
< sim_ticks 5112155173500 # Number of ticks simulated
< final_tick 5112155173500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 5.112156 # Number of seconds simulated
> sim_ticks 5112155738500 # Number of ticks simulated
> final_tick 5112155738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,13c7,13
< host_inst_rate 1977176 # Simulator instruction rate (inst/s)
< host_op_rate 4047982 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 50529549296 # Simulator tick rate (ticks/s)
< host_mem_usage 594968 # Number of bytes of host memory used
< host_seconds 101.17 # Real time elapsed on the host
< sim_insts 200033988 # Number of instructions simulated
< sim_ops 409540726 # Number of ops (including micro ops) simulated
---
> host_inst_rate 1511003 # Simulator instruction rate (inst/s)
> host_op_rate 3093560 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 38615908446 # Simulator tick rate (ticks/s)
> host_mem_usage 595640 # Number of bytes of host memory used
> host_seconds 132.38 # Real time elapsed on the host
> sim_insts 200033669 # Number of instructions simulated
> sim_ops 409539941 # Number of ops (including micro ops) simulated
18,19c18,19
< system.physmem.bytes_read::cpu.inst 852288 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 10678208 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 852224 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 10636736 # Number of bytes read from this memory
21,26c21,25
< system.physmem.bytes_read::total 11559232 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 852288 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 852288 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 6294336 # Number of bytes written to this memory
< system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
< system.physmem.bytes_written::total 9284416 # Number of bytes written to this memory
---
> system.physmem.bytes_read::total 11517696 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 852224 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 852224 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 9281152 # Number of bytes written to this memory
> system.physmem.bytes_written::total 9281152 # Number of bytes written to this memory
29,30c28,29
< system.physmem.num_reads::cpu.inst 13317 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 166847 # Number of read requests responded to by this memory
---
> system.physmem.num_reads::cpu.inst 13316 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 166199 # Number of read requests responded to by this memory
32,35c31,33
< system.physmem.num_reads::total 180613 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 98349 # Number of write requests responded to by this memory
< system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 145069 # Number of write requests responded to by this memory
---
> system.physmem.num_reads::total 179964 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 145018 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 145018 # Number of write requests responded to by this memory
38,39c36,37
< system.physmem.bw_read::cpu.inst 166718 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 2088788 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 166705 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 2080675 # Total read bandwidth from this memory (bytes/s)
41,47c39,44
< system.physmem.bw_read::total 2261127 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 166718 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 166718 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 1231249 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::pc.south_bridge.ide 584896 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 1816145 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 1231249 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 2253002 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 166705 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 166705 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 1815507 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 1815507 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 1815507 # Total bandwidth to/from this memory (bytes/s)
50,53c47,50
< system.physmem.bw_total::cpu.inst 166718 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 2088788 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::pc.south_bridge.ide 590442 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 4077272 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.inst 166705 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 2080675 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 4068508 # Total bandwidth to/from this memory (bytes/s)
56c53
< system.cpu.numCycles 10224314318 # number of cpu cycles simulated
---
> system.cpu.numCycles 10224315447 # number of cpu cycles simulated
59,61c56,58
< system.cpu.committedInsts 200033988 # Number of instructions committed
< system.cpu.committedOps 409540726 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 374550150 # Number of integer alu accesses
---
> system.cpu.committedInsts 200033669 # Number of instructions committed
> system.cpu.committedOps 409539941 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 374549395 # Number of integer alu accesses
63,65c60,62
< system.cpu.num_func_calls 2308777 # number of times a function call or return occured
< system.cpu.num_conditional_control_insts 39994865 # number of instructions that are conditional controls
< system.cpu.num_int_insts 374550150 # number of integer instructions
---
> system.cpu.num_func_calls 2308749 # number of times a function call or return occured
> system.cpu.num_conditional_control_insts 39994798 # number of instructions that are conditional controls
> system.cpu.num_int_insts 374549395 # number of integer instructions
67,68c64,65
< system.cpu.num_int_register_reads 682630172 # number of times the integer registers were read
< system.cpu.num_int_register_writes 323525861 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 682628451 # number of times the integer registers were read
> system.cpu.num_int_register_writes 323525110 # number of times the integer registers were written
71,77c68,74
< system.cpu.num_cc_register_reads 233820803 # number of times the CC registers were read
< system.cpu.num_cc_register_writes 157313619 # number of times the CC registers were written
< system.cpu.num_mem_refs 35680563 # number of memory refs
< system.cpu.num_load_insts 27249389 # Number of load instructions
< system.cpu.num_store_insts 8431174 # Number of store instructions
< system.cpu.num_idle_cycles 9770366809.410368 # Number of idle cycles
< system.cpu.num_busy_cycles 453947508.589632 # Number of busy cycles
---
> system.cpu.num_cc_register_reads 233820400 # number of times the CC registers were read
> system.cpu.num_cc_register_writes 157313425 # number of times the CC registers were written
> system.cpu.num_mem_refs 35680406 # number of memory refs
> system.cpu.num_load_insts 27249300 # Number of load instructions
> system.cpu.num_store_insts 8431106 # Number of store instructions
> system.cpu.num_idle_cycles 9770368815.449127 # Number of idle cycles
> system.cpu.num_busy_cycles 453946631.550873 # Number of busy cycles
80,84c77,81
< system.cpu.Branches 43145769 # Number of branches fetched
< system.cpu.op_class::No_OpClass 175400 0.04% 0.04% # Class of executed instruction
< system.cpu.op_class::IntAlu 373418196 91.18% 91.22% # Class of executed instruction
< system.cpu.op_class::IntMult 144548 0.04% 91.26% # Class of executed instruction
< system.cpu.op_class::IntDiv 123054 0.03% 91.29% # Class of executed instruction
---
> system.cpu.Branches 43145649 # Number of branches fetched
> system.cpu.op_class::No_OpClass 175370 0.04% 0.04% # Class of executed instruction
> system.cpu.op_class::IntAlu 373417675 91.18% 91.22% # Class of executed instruction
> system.cpu.op_class::IntMult 144551 0.04% 91.26% # Class of executed instruction
> system.cpu.op_class::IntDiv 122974 0.03% 91.29% # Class of executed instruction
111,112c108,109
< system.cpu.op_class::MemRead 27249389 6.65% 97.94% # Class of executed instruction
< system.cpu.op_class::MemWrite 8431174 2.06% 100.00% # Class of executed instruction
---
> system.cpu.op_class::MemRead 27249300 6.65% 97.94% # Class of executed instruction
> system.cpu.op_class::MemWrite 8431106 2.06% 100.00% # Class of executed instruction
115c112
< system.cpu.op_class::total 409541761 # Class of executed instruction
---
> system.cpu.op_class::total 409540976 # Class of executed instruction
118c115
< system.cpu.dcache.tags.replacements 1623441 # number of replacements
---
> system.cpu.dcache.tags.replacements 1623460 # number of replacements
120,122c117,119
< system.cpu.dcache.tags.total_refs 20193263 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 1623953 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 12.434635 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.total_refs 20193083 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 1623972 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 12.434379 # Average number of references to valid blocks.
132,157c129,154
< system.cpu.dcache.tags.tag_accesses 88892882 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 88892882 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 12028464 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 12028464 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 8103633 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 8103633 # number of WriteReq hits
< system.cpu.dcache.SoftPFReq_hits::cpu.data 58902 # number of SoftPFReq hits
< system.cpu.dcache.SoftPFReq_hits::total 58902 # number of SoftPFReq hits
< system.cpu.dcache.demand_hits::cpu.data 20132097 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 20132097 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 20190999 # number of overall hits
< system.cpu.dcache.overall_hits::total 20190999 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 905998 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 905998 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 317173 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 317173 # number of WriteReq misses
< system.cpu.dcache.SoftPFReq_misses::cpu.data 403059 # number of SoftPFReq misses
< system.cpu.dcache.SoftPFReq_misses::total 403059 # number of SoftPFReq misses
< system.cpu.dcache.demand_misses::cpu.data 1223171 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1223171 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1626230 # number of overall misses
< system.cpu.dcache.overall_misses::total 1626230 # number of overall misses
< system.cpu.dcache.ReadReq_accesses::cpu.data 12934462 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 12934462 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 8420806 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 8420806 # number of WriteReq accesses(hits+misses)
---
> system.cpu.dcache.tags.tag_accesses 88892257 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 88892257 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 12028370 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 12028370 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 8103548 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 8103548 # number of WriteReq hits
> system.cpu.dcache.SoftPFReq_hits::cpu.data 58901 # number of SoftPFReq hits
> system.cpu.dcache.SoftPFReq_hits::total 58901 # number of SoftPFReq hits
> system.cpu.dcache.demand_hits::cpu.data 20131918 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 20131918 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 20190819 # number of overall hits
> system.cpu.dcache.overall_hits::total 20190819 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 906001 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 906001 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 317188 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 317188 # number of WriteReq misses
> system.cpu.dcache.SoftPFReq_misses::cpu.data 403060 # number of SoftPFReq misses
> system.cpu.dcache.SoftPFReq_misses::total 403060 # number of SoftPFReq misses
> system.cpu.dcache.demand_misses::cpu.data 1223189 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1223189 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1626249 # number of overall misses
> system.cpu.dcache.overall_misses::total 1626249 # number of overall misses
> system.cpu.dcache.ReadReq_accesses::cpu.data 12934371 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 12934371 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 8420736 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 8420736 # number of WriteReq accesses(hits+misses)
160,173c157,170
< system.cpu.dcache.demand_accesses::cpu.data 21355268 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 21355268 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 21817229 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 21817229 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070045 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.070045 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037665 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.037665 # miss rate for WriteReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872496 # miss rate for SoftPFReq accesses
< system.cpu.dcache.SoftPFReq_miss_rate::total 0.872496 # miss rate for SoftPFReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.057277 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.057277 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.074539 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.074539 # miss rate for overall accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 21355107 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 21355107 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 21817068 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 21817068 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070046 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.070046 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037667 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.037667 # miss rate for WriteReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872498 # miss rate for SoftPFReq accesses
> system.cpu.dcache.SoftPFReq_miss_rate::total 0.872498 # miss rate for SoftPFReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.074540 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.074540 # miss rate for overall accesses
182,183c179,180
< system.cpu.dcache.writebacks::writebacks 1536849 # number of writebacks
< system.cpu.dcache.writebacks::total 1536849 # number of writebacks
---
> system.cpu.dcache.writebacks::writebacks 1536867 # number of writebacks
> system.cpu.dcache.writebacks::total 1536867 # number of writebacks
186,187c183,184
< system.cpu.dtb_walker_cache.tags.tagsinuse 5.013947 # Cycle average of tags in use
< system.cpu.dtb_walker_cache.tags.total_refs 12516 # Total number of references to valid blocks.
---
> system.cpu.dtb_walker_cache.tags.tagsinuse 5.013943 # Cycle average of tags in use
> system.cpu.dtb_walker_cache.tags.total_refs 12520 # Total number of references to valid blocks.
189,193c186,190
< system.cpu.dtb_walker_cache.tags.avg_refs 1.528578 # Average number of references to valid blocks.
< system.cpu.dtb_walker_cache.tags.warmup_cycle 5101311942500 # Cycle when the warmup percentage was hit.
< system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013947 # Average occupied blocks per requestor
< system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313372 # Average percentage of cache occupancy
< system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313372 # Average percentage of cache occupancy
---
> system.cpu.dtb_walker_cache.tags.avg_refs 1.529067 # Average number of references to valid blocks.
> system.cpu.dtb_walker_cache.tags.warmup_cycle 5101318572500 # Cycle when the warmup percentage was hit.
> system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013943 # Average occupied blocks per requestor
> system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313371 # Average percentage of cache occupancy
> system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313371 # Average percentage of cache occupancy
199,206c196,203
< system.cpu.dtb_walker_cache.tags.tag_accesses 53153 # Number of tag accesses
< system.cpu.dtb_walker_cache.tags.data_accesses 53153 # Number of data accesses
< system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12517 # number of ReadReq hits
< system.cpu.dtb_walker_cache.ReadReq_hits::total 12517 # number of ReadReq hits
< system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12517 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.demand_hits::total 12517 # number of demand (read+write) hits
< system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12517 # number of overall hits
< system.cpu.dtb_walker_cache.overall_hits::total 12517 # number of overall hits
---
> system.cpu.dtb_walker_cache.tags.tag_accesses 53161 # Number of tag accesses
> system.cpu.dtb_walker_cache.tags.data_accesses 53161 # Number of data accesses
> system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12521 # number of ReadReq hits
> system.cpu.dtb_walker_cache.ReadReq_hits::total 12521 # number of ReadReq hits
> system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12521 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.demand_hits::total 12521 # number of demand (read+write) hits
> system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12521 # number of overall hits
> system.cpu.dtb_walker_cache.overall_hits::total 12521 # number of overall hits
213,224c210,221
< system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21890 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.ReadReq_accesses::total 21890 # number of ReadReq accesses(hits+misses)
< system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21890 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.demand_accesses::total 21890 # number of demand (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21890 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.overall_accesses::total 21890 # number of overall (read+write) accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428186 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428186 # miss rate for ReadReq accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428186 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428186 # miss rate for demand accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428186 # miss rate for overall accesses
< system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428186 # miss rate for overall accesses
---
> system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses)
> system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428108 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428108 # miss rate for ReadReq accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428108 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.demand_miss_rate::total 0.428108 # miss rate for demand accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428108 # miss rate for overall accesses
> system.cpu.dtb_walker_cache.overall_miss_rate::total 0.428108 # miss rate for overall accesses
236c233
< system.cpu.icache.tags.replacements 791952 # number of replacements
---
> system.cpu.icache.tags.replacements 791846 # number of replacements
238,240c235,237
< system.cpu.icache.tags.total_refs 243645979 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 792464 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 307.453687 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.total_refs 243645674 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 792358 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 307.494433 # Average number of references to valid blocks.
251,270c248,267
< system.cpu.icache.tags.tag_accesses 245230921 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 245230921 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 243645979 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 243645979 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 243645979 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 243645979 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 243645979 # number of overall hits
< system.cpu.icache.overall_hits::total 243645979 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 792471 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 792471 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 792471 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 792471 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 792471 # number of overall misses
< system.cpu.icache.overall_misses::total 792471 # number of overall misses
< system.cpu.icache.ReadReq_accesses::cpu.inst 244438450 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 244438450 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 244438450 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 244438450 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 244438450 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 244438450 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 245230404 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 245230404 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 243645674 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 243645674 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 243645674 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 243645674 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 243645674 # number of overall hits
> system.cpu.icache.overall_hits::total 243645674 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 792365 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 792365 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 792365 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 792365 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 792365 # number of overall misses
> system.cpu.icache.overall_misses::total 792365 # number of overall misses
> system.cpu.icache.ReadReq_accesses::cpu.inst 244438039 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 244438039 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 244438039 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 244438039 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 244438039 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 244438039 # number of overall (read+write) accesses
287c284
< system.cpu.itb_walker_cache.tags.tagsinuse 3.026453 # Cycle average of tags in use
---
> system.cpu.itb_walker_cache.tags.tagsinuse 3.026443 # Cycle average of tags in use
291,292c288,289
< system.cpu.itb_walker_cache.tags.warmup_cycle 5102140605000 # Cycle when the warmup percentage was hit.
< system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026453 # Average occupied blocks per requestor
---
> system.cpu.itb_walker_cache.tags.warmup_cycle 5102148365500 # Cycle when the warmup percentage was hit.
> system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026443 # Average occupied blocks per requestor
342,346c339,343
< system.cpu.l2cache.tags.replacements 106197 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 64825.457913 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 3461872 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 170308 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 20.327125 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 106199 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 64825.456332 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 3461789 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 170310 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 20.326399 # Average number of references to valid blocks.
348c345
< system.cpu.l2cache.tags.occ_blocks::writebacks 51911.004327 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 51911.006068 # Average occupied blocks per requestor
350,352c347,349
< system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132278 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.291417 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.027412 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132276 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.288805 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 10424.026704 # Average occupied blocks per requestor
363,364c360,361
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20716 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39582 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20721 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39577 # Occupied blocks per task id
366,367c363,364
< system.cpu.l2cache.tags.tag_accesses 32246059 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 32246059 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 32245523 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 32245523 # Number of data accesses
370,374c367,371
< system.cpu.l2cache.ReadReq_hits::cpu.inst 779141 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 1276184 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 2065993 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 1540445 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 1540445 # number of Writeback hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.inst 779035 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 1276188 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 2065891 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 1540463 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 1540463 # number of Writeback hits
377,378c374,375
< system.cpu.l2cache.ReadExReq_hits::cpu.data 180006 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 180006 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 180020 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 180020 # number of ReadExReq hits
381,383c378,380
< system.cpu.l2cache.demand_hits::cpu.inst 779141 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 1456190 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 2245999 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.inst 779035 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 1456208 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 2245911 # number of demand (read+write) hits
386,388c383,385
< system.cpu.l2cache.overall_hits::cpu.inst 779141 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 1456190 # number of overall hits
< system.cpu.l2cache.overall_hits::total 2245999 # number of overall hits
---
> system.cpu.l2cache.overall_hits::cpu.inst 779035 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 1456208 # number of overall hits
> system.cpu.l2cache.overall_hits::total 2245911 # number of overall hits
396,397c393,394
< system.cpu.l2cache.ReadExReq_misses::cpu.data 134898 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 134898 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 134899 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 134899 # number of ReadExReq misses
401,402c398,399
< system.cpu.l2cache.demand_misses::cpu.data 167130 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 180453 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 167131 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 180454 # number of demand (read+write) misses
406,407c403,404
< system.cpu.l2cache.overall_misses::cpu.data 167130 # number of overall misses
< system.cpu.l2cache.overall_misses::total 180453 # number of overall misses
---
> system.cpu.l2cache.overall_misses::cpu.data 167131 # number of overall misses
> system.cpu.l2cache.overall_misses::total 180454 # number of overall misses
410,414c407,411
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 792458 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 1308416 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 2111548 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 1540445 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 1540445 # number of Writeback accesses(hits+misses)
---
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 792352 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 1308420 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 2111446 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 1540463 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 1540463 # number of Writeback accesses(hits+misses)
417,418c414,415
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 314904 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 314904 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 314919 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 314919 # number of ReadExReq accesses(hits+misses)
421,423c418,420
< system.cpu.l2cache.demand_accesses::cpu.inst 792458 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 1623320 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 2426452 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.inst 792352 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 1623339 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 2426365 # number of demand (read+write) accesses
426,428c423,425
< system.cpu.l2cache.overall_accesses::cpu.inst 792458 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 1623320 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 2426452 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.inst 792352 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 1623339 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 2426365 # number of overall (read+write) accesses
431c428
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016805 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses
433c430
< system.cpu.l2cache.ReadReq_miss_rate::total 0.021574 # miss rate for ReadReq accesses
---
> system.cpu.l2cache.ReadReq_miss_rate::total 0.021575 # miss rate for ReadReq accesses
436,437c433,434
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428378 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.428378 # miss rate for ReadExReq accesses
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428361 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.428361 # miss rate for ReadExReq accesses
440,442c437,439
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016805 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.102956 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.074369 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.102955 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.074372 # miss rate for demand accesses
445,447c442,444
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016805 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.102956 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.074369 # miss rate for overall accesses
---
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.102955 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.074372 # miss rate for overall accesses
456,457c453,454
< system.cpu.l2cache.writebacks::writebacks 98349 # number of writebacks
< system.cpu.l2cache.writebacks::total 98349 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 98351 # number of writebacks
> system.cpu.l2cache.writebacks::total 98351 # number of writebacks
459,460c456,457
< system.cpu.toL2Bus.trans_dist::ReadReq 15972786 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 15972786 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 15972684 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 15972684 # Transaction distribution
463c460
< system.cpu.toL2Bus.trans_dist::Writeback 1540445 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 1540463 # Transaction distribution
466,469c463,466
< system.cpu.toL2Bus.trans_dist::ReadExReq 314909 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 314909 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584942 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531741 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 314924 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 314924 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584730 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531797 # Packet count per connected master and slave (bytes)
472,474c469,471
< system.cpu.toL2Bus.pkt_count::total 34148185 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50718144 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227716857 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 34148029 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50711360 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227719225 # Cumulative packet size per connected master and slave (bytes)
477c474
< system.cpu.toL2Bus.pkt_size::total 279558137 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 279553721 # Cumulative packet size per connected master and slave (bytes)
479c476
< system.cpu.toL2Bus.snoop_fanout::samples 4020727 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 4020658 # Request fanout histogram
481c478
< system.cpu.toL2Bus.snoop_fanout::stdev 0.108191 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::stdev 0.108192 # Request fanout histogram
486c483
< system.cpu.toL2Bus.snoop_fanout::3 3973099 98.82% 98.82% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 3973030 98.82% 98.82% # Request fanout histogram
491c488
< system.cpu.toL2Bus.snoop_fanout::total 4020727 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 4020658 # Request fanout histogram
548c545
< system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use
---
> system.iocache.tags.tagsinuse 0.042450 # Cycle average of tags in use
553c550
< system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor
---
> system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042450 # Average occupied blocks per requestor
561,562d557
< system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
< system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
564a560,561
> system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses
> system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses
578a576,577
> system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses
> system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses
589c588
< system.iocache.fast_writes 46720 # number of fast writes performed
---
> system.iocache.fast_writes 0 # number of fast writes performed
590a590,591
> system.iocache.writebacks::writebacks 46667 # number of writebacks
> system.iocache.writebacks::total 46667 # number of writebacks
596c597
< system.membus.trans_dist::Writeback 98349 # Transaction distribution
---
> system.membus.trans_dist::Writeback 145018 # Transaction distribution
601,602c602,603
< system.membus.trans_dist::ReadExReq 134620 # Transaction distribution
< system.membus.trans_dist::ReadExResp 134615 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 134621 # Transaction distribution
> system.membus.trans_dist::ReadExResp 134616 # Transaction distribution
609,613c610,614
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463315 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205747 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 95256 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count_system.iocache.mem_side::total 95256 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 28304395 # Packet count per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463319 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205751 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141923 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count_system.iocache.mem_side::total 141923 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 28351066 # Packet count per connected master and slave (bytes)
618,622c619,623
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825216 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43249913 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3048192 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size_system.iocache.mem_side::total 3048192 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 46304889 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825408 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43250105 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size_system.iocache.mem_side::total 6034880 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 49291769 # Cumulative packet size per connected master and slave (bytes)
624c625
< system.membus.snoop_fanout::samples 328677 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 375347 # Request fanout histogram
629c630
< system.membus.snoop_fanout::1 328677 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::1 375347 100.00% 100.00% # Request fanout histogram
634c635
< system.membus.snoop_fanout::total 328677 # Request fanout histogram
---
> system.membus.snoop_fanout::total 375347 # Request fanout histogram