1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.112043 # Number of seconds simulated
4sim_ticks 5112043255000 # Number of ticks simulated
5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.112043 # Number of seconds simulated
4sim_ticks 5112043255000 # Number of ticks simulated
5final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1772716 # Simulator instruction rate (inst/s)
8host_op_rate 3629762 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 45353186641 # Simulator tick rate (ticks/s)
10host_mem_usage 350348 # Number of bytes of host memory used
11host_seconds 112.72 # Real time elapsed on the host
| 7host_inst_rate 720353 # Simulator instruction rate (inst/s)
8host_op_rate 1474974 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 18429520570 # Simulator tick rate (ticks/s)
10host_mem_usage 355156 # Number of bytes of host memory used
11host_seconds 277.38 # Real time elapsed on the host
|
12sim_insts 199813913 # Number of instructions simulated
13sim_ops 409133277 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 15568704 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 12232896 # Number of bytes written to this memory
17system.physmem.num_reads 243261 # Number of read requests responded to by this memory
18system.physmem.num_writes 191139 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 3045495 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 190283 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 2392956 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 5438452 # Total bandwidth to/from this memory (bytes/s)
24system.l2c.replacements 164044 # number of replacements
25system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use
26system.l2c.total_refs 3332458 # Total number of references to valid blocks.
27system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
28system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
29system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
30system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor
31system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor
32system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor
33system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor
34system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor
35system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy
36system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy
37system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
38system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy
39system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy
40system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy
41system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits
42system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits
43system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits
44system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits
45system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits
46system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits
47system.l2c.Writeback_hits::total 1529403 # number of Writeback hits
48system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits
49system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
50system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits
51system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits
52system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits
53system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits
54system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits
55system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits
56system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits
57system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits
58system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits
59system.l2c.overall_hits::cpu.inst 776101 # number of overall hits
60system.l2c.overall_hits::cpu.data 1435764 # number of overall hits
61system.l2c.overall_hits::total 2221403 # number of overall hits
62system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses
63system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses
64system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses
65system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses
66system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses
67system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses
68system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses
69system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses
70system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses
71system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses
72system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses
73system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses
74system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses
75system.l2c.demand_misses::total 200638 # number of demand (read+write) misses
76system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses
77system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses
78system.l2c.overall_misses::cpu.inst 15200 # number of overall misses
79system.l2c.overall_misses::cpu.data 185411 # number of overall misses
80system.l2c.overall_misses::total 200638 # number of overall misses
81system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses)
82system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses)
83system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses)
84system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses)
85system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses)
86system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses)
87system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses)
88system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
89system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
90system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses)
91system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses)
92system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses
93system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses
94system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses
95system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses
96system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses
97system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses
98system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses
99system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses
100system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses
101system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses
102system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses
103system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses
104system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses
105system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses
106system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses
107system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses
108system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses
109system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses
110system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses
111system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses
112system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses
113system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses
114system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses
115system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses
116system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
117system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
118system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
119system.l2c.blocked::no_targets 0 # number of cycles access was blocked
| 12sim_insts 199813913 # Number of instructions simulated
13sim_ops 409133277 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 15568704 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 12232896 # Number of bytes written to this memory
17system.physmem.num_reads 243261 # Number of read requests responded to by this memory
18system.physmem.num_writes 191139 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 3045495 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 190283 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 2392956 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 5438452 # Total bandwidth to/from this memory (bytes/s)
24system.l2c.replacements 164044 # number of replacements
25system.l2c.tagsinuse 36842.944085 # Cycle average of tags in use
26system.l2c.total_refs 3332458 # Total number of references to valid blocks.
27system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
28system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
29system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
30system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor
31system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor
32system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor
33system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor
34system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor
35system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy
36system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy
37system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
38system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy
39system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy
40system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy
41system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits
42system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits
43system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits
44system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits
45system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits
46system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits
47system.l2c.Writeback_hits::total 1529403 # number of Writeback hits
48system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits
49system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
50system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits
51system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits
52system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits
53system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits
54system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits
55system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits
56system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits
57system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits
58system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits
59system.l2c.overall_hits::cpu.inst 776101 # number of overall hits
60system.l2c.overall_hits::cpu.data 1435764 # number of overall hits
61system.l2c.overall_hits::total 2221403 # number of overall hits
62system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses
63system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses
64system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses
65system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses
66system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses
67system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses
68system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses
69system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses
70system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses
71system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses
72system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses
73system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses
74system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses
75system.l2c.demand_misses::total 200638 # number of demand (read+write) misses
76system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses
77system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses
78system.l2c.overall_misses::cpu.inst 15200 # number of overall misses
79system.l2c.overall_misses::cpu.data 185411 # number of overall misses
80system.l2c.overall_misses::total 200638 # number of overall misses
81system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses)
82system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses)
83system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses)
84system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses)
85system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses)
86system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses)
87system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses)
88system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
89system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
90system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses)
91system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses)
92system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses
93system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses
94system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses
95system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses
96system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses
97system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses
98system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses
99system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses
100system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses
101system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses
102system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses
103system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses
104system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses
105system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses
106system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses
107system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses
108system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses
109system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses
110system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses
111system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses
112system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses
113system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses
114system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses
115system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses
116system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
117system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
118system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
119system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
120system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
121system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 120system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
121system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
122system.l2c.fast_writes 0 # number of fast writes performed
123system.l2c.cache_copies 0 # number of cache copies performed
124system.l2c.writebacks::writebacks 144472 # number of writebacks
125system.l2c.writebacks::total 144472 # number of writebacks
126system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
127system.iocache.replacements 47570 # number of replacements
128system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
129system.iocache.total_refs 0 # Total number of references to valid blocks.
130system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
131system.iocache.avg_refs 0 # Average number of references to valid blocks.
132system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
133system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
134system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy
135system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy
136system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
137system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
138system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
139system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
140system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
141system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
142system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
143system.iocache.overall_misses::total 47625 # number of overall misses
144system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
145system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
146system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
147system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
148system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
149system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
150system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
151system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
152system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
153system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
154system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
155system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
156system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
157system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
158system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
159system.iocache.blocked::no_targets 0 # number of cycles access was blocked
| 122system.l2c.fast_writes 0 # number of fast writes performed
123system.l2c.cache_copies 0 # number of cache copies performed
124system.l2c.writebacks::writebacks 144472 # number of writebacks
125system.l2c.writebacks::total 144472 # number of writebacks
126system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
127system.iocache.replacements 47570 # number of replacements
128system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
129system.iocache.total_refs 0 # Total number of references to valid blocks.
130system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
131system.iocache.avg_refs 0 # Average number of references to valid blocks.
132system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
133system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
134system.iocache.occ_percent::pc.south_bridge.ide 0.002651 # Average percentage of cache occupancy
135system.iocache.occ_percent::total 0.002651 # Average percentage of cache occupancy
136system.iocache.ReadReq_misses::pc.south_bridge.ide 905 # number of ReadReq misses
137system.iocache.ReadReq_misses::total 905 # number of ReadReq misses
138system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
139system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
140system.iocache.demand_misses::pc.south_bridge.ide 47625 # number of demand (read+write) misses
141system.iocache.demand_misses::total 47625 # number of demand (read+write) misses
142system.iocache.overall_misses::pc.south_bridge.ide 47625 # number of overall misses
143system.iocache.overall_misses::total 47625 # number of overall misses
144system.iocache.ReadReq_accesses::pc.south_bridge.ide 905 # number of ReadReq accesses(hits+misses)
145system.iocache.ReadReq_accesses::total 905 # number of ReadReq accesses(hits+misses)
146system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
147system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
148system.iocache.demand_accesses::pc.south_bridge.ide 47625 # number of demand (read+write) accesses
149system.iocache.demand_accesses::total 47625 # number of demand (read+write) accesses
150system.iocache.overall_accesses::pc.south_bridge.ide 47625 # number of overall (read+write) accesses
151system.iocache.overall_accesses::total 47625 # number of overall (read+write) accesses
152system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
153system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
154system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
155system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
156system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
157system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
158system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
159system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
160system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
161system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 160system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
161system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
162system.iocache.fast_writes 0 # number of fast writes performed
163system.iocache.cache_copies 0 # number of cache copies performed
164system.iocache.writebacks::writebacks 46667 # number of writebacks
165system.iocache.writebacks::total 46667 # number of writebacks
166system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
167system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
168system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
169system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
170system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
171system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
172system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
173system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
174system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
175system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
176system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
177system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
178system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
179system.cpu.numCycles 10224086531 # number of cpu cycles simulated
180system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
181system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
182system.cpu.committedInsts 199813913 # Number of instructions committed
183system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed
184system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses
185system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
186system.cpu.num_func_calls 0 # number of times a function call or return occured
187system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls
188system.cpu.num_int_insts 374297244 # number of integer instructions
189system.cpu.num_fp_insts 0 # number of float instructions
190system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read
191system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written
192system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
193system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
194system.cpu.num_mem_refs 35626519 # number of memory refs
195system.cpu.num_load_insts 27217784 # Number of load instructions
196system.cpu.num_store_insts 8408735 # Number of store instructions
197system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles
198system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles
199system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
200system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
201system.cpu.kern.inst.arm 0 # number of arm instructions executed
202system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
203system.cpu.icache.replacements 790795 # number of replacements
204system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
205system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
206system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks.
207system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks.
208system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
209system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
210system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
211system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
212system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits
213system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
214system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits
215system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
216system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits
217system.cpu.icache.overall_hits::total 243365777 # number of overall hits
218system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses
219system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses
220system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses
221system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses
222system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses
223system.cpu.icache.overall_misses::total 791314 # number of overall misses
224system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses)
225system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
226system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses
227system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
228system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses
229system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
230system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
231system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
232system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
233system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
234system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
235system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
236system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
| 162system.iocache.fast_writes 0 # number of fast writes performed
163system.iocache.cache_copies 0 # number of cache copies performed
164system.iocache.writebacks::writebacks 46667 # number of writebacks
165system.iocache.writebacks::total 46667 # number of writebacks
166system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
167system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
168system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
169system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
170system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
171system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
172system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
173system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
174system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
175system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
176system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
177system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
178system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
179system.cpu.numCycles 10224086531 # number of cpu cycles simulated
180system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
181system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
182system.cpu.committedInsts 199813913 # Number of instructions committed
183system.cpu.committedOps 409133277 # Number of ops (including micro ops) committed
184system.cpu.num_int_alu_accesses 374297244 # Number of integer alu accesses
185system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
186system.cpu.num_func_calls 0 # number of times a function call or return occured
187system.cpu.num_conditional_control_insts 39954968 # number of instructions that are conditional controls
188system.cpu.num_int_insts 374297244 # number of integer instructions
189system.cpu.num_fp_insts 0 # number of float instructions
190system.cpu.num_int_register_reads 801267455 # number of times the integer registers were read
191system.cpu.num_int_register_writes 401624559 # number of times the integer registers were written
192system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
193system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
194system.cpu.num_mem_refs 35626519 # number of memory refs
195system.cpu.num_load_insts 27217784 # Number of load instructions
196system.cpu.num_store_insts 8408735 # Number of store instructions
197system.cpu.num_idle_cycles 9770605338.086651 # Number of idle cycles
198system.cpu.num_busy_cycles 453481192.913350 # Number of busy cycles
199system.cpu.not_idle_fraction 0.044354 # Percentage of non-idle cycles
200system.cpu.idle_fraction 0.955646 # Percentage of idle cycles
201system.cpu.kern.inst.arm 0 # number of arm instructions executed
202system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
203system.cpu.icache.replacements 790795 # number of replacements
204system.cpu.icache.tagsinuse 510.627676 # Cycle average of tags in use
205system.cpu.icache.total_refs 243365777 # Total number of references to valid blocks.
206system.cpu.icache.sampled_refs 791307 # Sample count of references to valid blocks.
207system.cpu.icache.avg_refs 307.549127 # Average number of references to valid blocks.
208system.cpu.icache.warmup_cycle 148763105500 # Cycle when the warmup percentage was hit.
209system.cpu.icache.occ_blocks::cpu.inst 510.627676 # Average occupied blocks per requestor
210system.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy
211system.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy
212system.cpu.icache.ReadReq_hits::cpu.inst 243365777 # number of ReadReq hits
213system.cpu.icache.ReadReq_hits::total 243365777 # number of ReadReq hits
214system.cpu.icache.demand_hits::cpu.inst 243365777 # number of demand (read+write) hits
215system.cpu.icache.demand_hits::total 243365777 # number of demand (read+write) hits
216system.cpu.icache.overall_hits::cpu.inst 243365777 # number of overall hits
217system.cpu.icache.overall_hits::total 243365777 # number of overall hits
218system.cpu.icache.ReadReq_misses::cpu.inst 791314 # number of ReadReq misses
219system.cpu.icache.ReadReq_misses::total 791314 # number of ReadReq misses
220system.cpu.icache.demand_misses::cpu.inst 791314 # number of demand (read+write) misses
221system.cpu.icache.demand_misses::total 791314 # number of demand (read+write) misses
222system.cpu.icache.overall_misses::cpu.inst 791314 # number of overall misses
223system.cpu.icache.overall_misses::total 791314 # number of overall misses
224system.cpu.icache.ReadReq_accesses::cpu.inst 244157091 # number of ReadReq accesses(hits+misses)
225system.cpu.icache.ReadReq_accesses::total 244157091 # number of ReadReq accesses(hits+misses)
226system.cpu.icache.demand_accesses::cpu.inst 244157091 # number of demand (read+write) accesses
227system.cpu.icache.demand_accesses::total 244157091 # number of demand (read+write) accesses
228system.cpu.icache.overall_accesses::cpu.inst 244157091 # number of overall (read+write) accesses
229system.cpu.icache.overall_accesses::total 244157091 # number of overall (read+write) accesses
230system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses
231system.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses
232system.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses
233system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
234system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
235system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
236system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
237system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
238system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 237system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
238system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
239system.cpu.icache.fast_writes 0 # number of fast writes performed
240system.cpu.icache.cache_copies 0 # number of cache copies performed
241system.cpu.icache.writebacks::writebacks 809 # number of writebacks
242system.cpu.icache.writebacks::total 809 # number of writebacks
243system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
244system.cpu.itb_walker_cache.replacements 3435 # number of replacements
245system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use
246system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks.
247system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks.
248system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks.
249system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit.
250system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor
251system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy
252system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy
253system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits
254system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits
255system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
256system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
257system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits
258system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits
259system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits
260system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits
261system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses
262system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses
263system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses
264system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses
265system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses
266system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses
267system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
268system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
269system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
270system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
271system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
272system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
273system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
274system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
275system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses
276system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses
277system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses
278system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
279system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
280system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
281system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
| 239system.cpu.icache.fast_writes 0 # number of fast writes performed
240system.cpu.icache.cache_copies 0 # number of cache copies performed
241system.cpu.icache.writebacks::writebacks 809 # number of writebacks
242system.cpu.icache.writebacks::total 809 # number of writebacks
243system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
244system.cpu.itb_walker_cache.replacements 3435 # number of replacements
245system.cpu.itb_walker_cache.tagsinuse 3.021701 # Cycle average of tags in use
246system.cpu.itb_walker_cache.total_refs 7940 # Total number of references to valid blocks.
247system.cpu.itb_walker_cache.sampled_refs 3444 # Sample count of references to valid blocks.
248system.cpu.itb_walker_cache.avg_refs 2.305459 # Average number of references to valid blocks.
249system.cpu.itb_walker_cache.warmup_cycle 5105275407500 # Cycle when the warmup percentage was hit.
250system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.021701 # Average occupied blocks per requestor
251system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.188856 # Average percentage of cache occupancy
252system.cpu.itb_walker_cache.occ_percent::total 0.188856 # Average percentage of cache occupancy
253system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7947 # number of ReadReq hits
254system.cpu.itb_walker_cache.ReadReq_hits::total 7947 # number of ReadReq hits
255system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
256system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
257system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7949 # number of demand (read+write) hits
258system.cpu.itb_walker_cache.demand_hits::total 7949 # number of demand (read+write) hits
259system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7949 # number of overall hits
260system.cpu.itb_walker_cache.overall_hits::total 7949 # number of overall hits
261system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4278 # number of ReadReq misses
262system.cpu.itb_walker_cache.ReadReq_misses::total 4278 # number of ReadReq misses
263system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4278 # number of demand (read+write) misses
264system.cpu.itb_walker_cache.demand_misses::total 4278 # number of demand (read+write) misses
265system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4278 # number of overall misses
266system.cpu.itb_walker_cache.overall_misses::total 4278 # number of overall misses
267system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses)
268system.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses)
269system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
270system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
271system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses
272system.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses
273system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses
274system.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses
275system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.349939 # miss rate for ReadReq accesses
276system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.349881 # miss rate for demand accesses
277system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.349881 # miss rate for overall accesses
278system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
279system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
280system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
281system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
282system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
283system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 282system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
283system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
284system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
285system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
286system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks
287system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks
288system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
289system.cpu.dtb_walker_cache.replacements 7755 # number of replacements
290system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use
291system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks.
292system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks.
293system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks.
294system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit.
295system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor
296system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy
297system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy
298system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits
299system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits
300system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits
301system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits
302system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits
303system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits
304system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses
305system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses
306system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses
307system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses
308system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses
309system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses
310system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
311system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
312system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
313system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
314system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
315system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
316system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses
317system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses
318system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses
319system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
320system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
321system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
322system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
| 284system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
285system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
286system.cpu.itb_walker_cache.writebacks::writebacks 518 # number of writebacks
287system.cpu.itb_walker_cache.writebacks::total 518 # number of writebacks
288system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
289system.cpu.dtb_walker_cache.replacements 7755 # number of replacements
290system.cpu.dtb_walker_cache.tagsinuse 5.010998 # Cycle average of tags in use
291system.cpu.dtb_walker_cache.total_refs 12854 # Total number of references to valid blocks.
292system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks.
293system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks.
294system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit.
295system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor
296system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy
297system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy
298system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits
299system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits
300system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits
301system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits
302system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits
303system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits
304system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses
305system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses
306system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses
307system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses
308system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses
309system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses
310system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
311system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
312system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
313system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
314system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
315system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
316system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses
317system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses
318system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses
319system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
320system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
321system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
322system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
323system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
324system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 323system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
324system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
325system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
326system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
327system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks
328system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks
329system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
330system.cpu.dcache.replacements 1621277 # number of replacements
331system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use
332system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks.
333system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks.
334system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks.
335system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
336system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor
337system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
338system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
339system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits
340system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
341system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits
342system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits
343system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits
344system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits
345system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits
346system.cpu.dcache.overall_hits::total 20139962 # number of overall hits
347system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses
348system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses
349system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses
350system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses
351system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses
352system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
353system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses
354system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
355system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses)
356system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses)
357system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses)
358system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
359system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses
360system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses
361system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses
362system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses
363system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
364system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
365system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
366system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
367system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
368system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
369system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
370system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
| 325system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
326system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
327system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks
328system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks
329system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
330system.cpu.dcache.replacements 1621277 # number of replacements
331system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use
332system.cpu.dcache.total_refs 20142220 # Total number of references to valid blocks.
333system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks.
334system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks.
335system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
336system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor
337system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
338system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
339system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits
340system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
341system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits
342system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits
343system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits
344system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits
345system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits
346system.cpu.dcache.overall_hits::total 20139962 # number of overall hits
347system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses
348system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses
349system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses
350system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses
351system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses
352system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
353system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses
354system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
355system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses)
356system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses)
357system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses)
358system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
359system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses
360system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses
361system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses
362system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses
363system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
364system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
365system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
366system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
367system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
368system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
369system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
370system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
371system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
372system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
| 371system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
372system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
373system.cpu.dcache.fast_writes 0 # number of fast writes performed
374system.cpu.dcache.cache_copies 0 # number of cache copies performed
375system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks
376system.cpu.dcache.writebacks::total 1525559 # number of writebacks
377system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
378
379---------- End Simulation Statistics ----------
| 373system.cpu.dcache.fast_writes 0 # number of fast writes performed
374system.cpu.dcache.cache_copies 0 # number of cache copies performed
375system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks
376system.cpu.dcache.writebacks::total 1525559 # number of writebacks
377system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
378
379---------- End Simulation Statistics ----------
|