1
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.112126 # Number of seconds simulated
4sim_ticks 5112125984500 # Number of ticks simulated
5final_tick 5112125984500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1274105 # Simulator instruction rate (inst/s)
8host_op_rate 2608650 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 32578287771 # Simulator tick rate (ticks/s)
10host_mem_usage 593532 # Number of bytes of host memory used
11host_seconds 156.92 # Real time elapsed on the host
12sim_insts 199930130 # Number of instructions simulated
13sim_ops 409344539 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 852800 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 10650880 # Number of bytes read from this memory
21system.physmem.bytes_read::total 11532416 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 852800 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 852800 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 6281856 # Number of bytes written to this memory
25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
26system.physmem.bytes_written::total 9271936 # Number of bytes written to this memory
27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 13325 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu.data 166420 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 180194 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 98154 # Number of write requests responded to by this memory
34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 144874 # Number of write requests responded to by this memory
36system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 166819 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu.data 2083454 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 2255894 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 166819 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 166819 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 1228815 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::pc.south_bridge.ide 584900 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 1813714 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 1228815 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::pc.south_bridge.ide 590446 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 166819 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu.data 2083454 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 4069609 # Total bandwidth to/from this memory (bytes/s)
54system.membus.throughput 9050072 # Throughput (bytes/s)
55system.membus.data_through_bus 46265107 # Total data (bytes)
56system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
57system.iocache.tags.replacements 47569 # number of replacements
58system.iocache.tags.tagsinuse 0.042447 # Cycle average of tags in use
59system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
60system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
61system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
62system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit.
63system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042447 # Average occupied blocks per requestor
64system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
65system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
66system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
67system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
68system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
69system.iocache.tags.tag_accesses 428616 # Number of tag accesses
70system.iocache.tags.data_accesses 428616 # Number of data accesses
71system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
72system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
73system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
74system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
75system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses
76system.iocache.demand_misses::total 904 # number of demand (read+write) misses
77system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses
78system.iocache.overall_misses::total 904 # number of overall misses
79system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
80system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
81system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
82system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
83system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses
84system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses
85system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses
86system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses
87system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
88system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
89system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
90system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
91system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
92system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
93system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
94system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
--- 11 unchanged lines hidden (view full) ---
106system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
107system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
108system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
109system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
110system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
111system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
112system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
113system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
114system.iobus.throughput 2555207 # Throughput (bytes/s)
115system.iobus.data_through_bus 13062542 # Total data (bytes)
116system.cpu_clk_domain.clock 500 # Clock period in ticks
117system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
118system.cpu.numCycles 10224253344 # number of cpu cycles simulated
119system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
120system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
121system.cpu.committedInsts 199930130 # Number of instructions committed
122system.cpu.committedOps 409344539 # Number of ops (including micro ops) committed
123system.cpu.num_int_alu_accesses 374365317 # Number of integer alu accesses
124system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
125system.cpu.num_func_calls 2307745 # number of times a function call or return occured
126system.cpu.num_conditional_control_insts 39976374 # number of instructions that are conditional controls
127system.cpu.num_int_insts 374365317 # number of integer instructions
128system.cpu.num_fp_insts 0 # number of float instructions
129system.cpu.num_int_register_reads 682286798 # number of times the integer registers were read
130system.cpu.num_int_register_writes 323369753 # number of times the integer registers were written
131system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
132system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
133system.cpu.num_cc_register_reads 233715334 # number of times the CC registers were read
134system.cpu.num_cc_register_writes 157233726 # number of times the CC registers were written
135system.cpu.num_mem_refs 35661072 # number of memory refs
136system.cpu.num_load_insts 27238907 # Number of load instructions
137system.cpu.num_store_insts 8422165 # Number of store instructions
138system.cpu.num_idle_cycles 9770516870.697727 # Number of idle cycles
139system.cpu.num_busy_cycles 453736473.302274 # Number of busy cycles
140system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
141system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
142system.cpu.Branches 43125613 # Number of branches fetched
143system.cpu.op_class::No_OpClass 175318 0.04% 0.04% # Class of executed instruction
144system.cpu.op_class::IntAlu 373241846 91.18% 91.22% # Class of executed instruction
145system.cpu.op_class::IntMult 144365 0.04% 91.26% # Class of executed instruction
146system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction
147system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
148system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
149system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
150system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction
151system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction
152system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction
153system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction
154system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction
--- 10 unchanged lines hidden (view full) ---
165system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction
166system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction
167system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction
168system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction
169system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction
170system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
171system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
172system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
173system.cpu.op_class::MemRead 27238907 6.65% 97.94% # Class of executed instruction
174system.cpu.op_class::MemWrite 8422165 2.06% 100.00% # Class of executed instruction
175system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
176system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
177system.cpu.op_class::total 409345569 # Class of executed instruction
178system.cpu.kern.inst.arm 0 # number of arm instructions executed
179system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
180system.cpu.icache.tags.replacements 790679 # number of replacements
181system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
182system.cpu.icache.tags.total_refs 243526070 # Total number of references to valid blocks.
183system.cpu.icache.tags.sampled_refs 791191 # Sample count of references to valid blocks.
184system.cpu.icache.tags.avg_refs 307.796815 # Average number of references to valid blocks.
185system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
186system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
187system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
188system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy
189system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
190system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
191system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
192system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id
193system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
194system.cpu.icache.tags.tag_accesses 245108466 # Number of tag accesses
195system.cpu.icache.tags.data_accesses 245108466 # Number of data accesses
196system.cpu.icache.ReadReq_hits::cpu.inst 243526070 # number of ReadReq hits
197system.cpu.icache.ReadReq_hits::total 243526070 # number of ReadReq hits
198system.cpu.icache.demand_hits::cpu.inst 243526070 # number of demand (read+write) hits
199system.cpu.icache.demand_hits::total 243526070 # number of demand (read+write) hits
200system.cpu.icache.overall_hits::cpu.inst 243526070 # number of overall hits
201system.cpu.icache.overall_hits::total 243526070 # number of overall hits
202system.cpu.icache.ReadReq_misses::cpu.inst 791198 # number of ReadReq misses
203system.cpu.icache.ReadReq_misses::total 791198 # number of ReadReq misses
204system.cpu.icache.demand_misses::cpu.inst 791198 # number of demand (read+write) misses
205system.cpu.icache.demand_misses::total 791198 # number of demand (read+write) misses
206system.cpu.icache.overall_misses::cpu.inst 791198 # number of overall misses
207system.cpu.icache.overall_misses::total 791198 # number of overall misses
208system.cpu.icache.ReadReq_accesses::cpu.inst 244317268 # number of ReadReq accesses(hits+misses)
209system.cpu.icache.ReadReq_accesses::total 244317268 # number of ReadReq accesses(hits+misses)
210system.cpu.icache.demand_accesses::cpu.inst 244317268 # number of demand (read+write) accesses
211system.cpu.icache.demand_accesses::total 244317268 # number of demand (read+write) accesses
212system.cpu.icache.overall_accesses::cpu.inst 244317268 # number of overall (read+write) accesses
213system.cpu.icache.overall_accesses::total 244317268 # number of overall (read+write) accesses
214system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
215system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
216system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
217system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses
218system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses
219system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses
220system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
221system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
222system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
223system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
224system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
225system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
226system.cpu.icache.fast_writes 0 # number of fast writes performed
227system.cpu.icache.cache_copies 0 # number of cache copies performed
228system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
229system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements
230system.cpu.itb_walker_cache.tags.tagsinuse 3.026310 # Cycle average of tags in use
231system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks.
232system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks.
233system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks.
234system.cpu.itb_walker_cache.tags.warmup_cycle 5102111082500 # Cycle when the warmup percentage was hit.
235system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026310 # Average occupied blocks per requestor
236system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy
237system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy
238system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
239system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
240system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
241system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
242system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
243system.cpu.itb_walker_cache.tags.tag_accesses 28774 # Number of tag accesses
244system.cpu.itb_walker_cache.tags.data_accesses 28774 # Number of data accesses
245system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits
246system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits
247system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
248system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
249system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits
250system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits
251system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits
252system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits
253system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses
254system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses
255system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses
256system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses
257system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses
258system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses
259system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses)
260system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses)
261system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
262system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
263system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses
264system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses
265system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses
266system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses
267system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses
268system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses
269system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses
270system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses
271system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses
272system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses
273system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
274system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
275system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
276system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
277system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
278system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
279system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
280system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
281system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks
282system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
283system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
284system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements
285system.cpu.dtb_walker_cache.tags.tagsinuse 5.014183 # Cycle average of tags in use
286system.cpu.dtb_walker_cache.tags.total_refs 12951 # Total number of references to valid blocks.
287system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks.
288system.cpu.dtb_walker_cache.tags.avg_refs 1.694270 # Average number of references to valid blocks.
289system.cpu.dtb_walker_cache.tags.warmup_cycle 5100459675500 # Cycle when the warmup percentage was hit.
290system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014183 # Average occupied blocks per requestor
291system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy
292system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy
293system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
294system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
295system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
296system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
297system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
298system.cpu.dtb_walker_cache.tags.tag_accesses 52390 # Number of tag accesses
299system.cpu.dtb_walker_cache.tags.data_accesses 52390 # Number of data accesses
300system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12959 # number of ReadReq hits
301system.cpu.dtb_walker_cache.ReadReq_hits::total 12959 # number of ReadReq hits
302system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12959 # number of demand (read+write) hits
303system.cpu.dtb_walker_cache.demand_hits::total 12959 # number of demand (read+write) hits
304system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12959 # number of overall hits
305system.cpu.dtb_walker_cache.overall_hits::total 12959 # number of overall hits
306system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses
307system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses
308system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses
309system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses
310system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses
311system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses
312system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21783 # number of ReadReq accesses(hits+misses)
313system.cpu.dtb_walker_cache.ReadReq_accesses::total 21783 # number of ReadReq accesses(hits+misses)
314system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21783 # number of demand (read+write) accesses
315system.cpu.dtb_walker_cache.demand_accesses::total 21783 # number of demand (read+write) accesses
316system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21783 # number of overall (read+write) accesses
317system.cpu.dtb_walker_cache.overall_accesses::total 21783 # number of overall (read+write) accesses
318system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405087 # miss rate for ReadReq accesses
319system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405087 # miss rate for ReadReq accesses
320system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405087 # miss rate for demand accesses
321system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405087 # miss rate for demand accesses
322system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405087 # miss rate for overall accesses
323system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405087 # miss rate for overall accesses
324system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
325system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
326system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
327system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
328system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
329system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
330system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
331system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
332system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks
333system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks
334system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
335system.cpu.dcache.tags.replacements 1622084 # number of replacements
336system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use
337system.cpu.dcache.tags.total_refs 20175355 # Total number of references to valid blocks.
338system.cpu.dcache.tags.sampled_refs 1622596 # Sample count of references to valid blocks.
339system.cpu.dcache.tags.avg_refs 12.433998 # Average number of references to valid blocks.
340system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
341system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor
342system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
343system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
344system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
345system.cpu.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id
346system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
347system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
348system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
349system.cpu.dcache.tags.tag_accesses 88814480 # Number of tag accesses
350system.cpu.dcache.tags.data_accesses 88814480 # Number of data accesses
351system.cpu.dcache.ReadReq_hits::cpu.data 12018728 # number of ReadReq hits
352system.cpu.dcache.ReadReq_hits::total 12018728 # number of ReadReq hits
353system.cpu.dcache.WriteReq_hits::cpu.data 8095451 # number of WriteReq hits
354system.cpu.dcache.WriteReq_hits::total 8095451 # number of WriteReq hits
355system.cpu.dcache.SoftPFReq_hits::cpu.data 58906 # number of SoftPFReq hits
356system.cpu.dcache.SoftPFReq_hits::total 58906 # number of SoftPFReq hits
357system.cpu.dcache.demand_hits::cpu.data 20114179 # number of demand (read+write) hits
358system.cpu.dcache.demand_hits::total 20114179 # number of demand (read+write) hits
359system.cpu.dcache.overall_hits::cpu.data 20173085 # number of overall hits
360system.cpu.dcache.overall_hits::total 20173085 # number of overall hits
361system.cpu.dcache.ReadReq_misses::cpu.data 905666 # number of ReadReq misses
362system.cpu.dcache.ReadReq_misses::total 905666 # number of ReadReq misses
363system.cpu.dcache.WriteReq_misses::cpu.data 316462 # number of WriteReq misses
364system.cpu.dcache.WriteReq_misses::total 316462 # number of WriteReq misses
365system.cpu.dcache.SoftPFReq_misses::cpu.data 402754 # number of SoftPFReq misses
366system.cpu.dcache.SoftPFReq_misses::total 402754 # number of SoftPFReq misses
367system.cpu.dcache.demand_misses::cpu.data 1222128 # number of demand (read+write) misses
368system.cpu.dcache.demand_misses::total 1222128 # number of demand (read+write) misses
369system.cpu.dcache.overall_misses::cpu.data 1624882 # number of overall misses
370system.cpu.dcache.overall_misses::total 1624882 # number of overall misses
371system.cpu.dcache.ReadReq_accesses::cpu.data 12924394 # number of ReadReq accesses(hits+misses)
372system.cpu.dcache.ReadReq_accesses::total 12924394 # number of ReadReq accesses(hits+misses)
373system.cpu.dcache.WriteReq_accesses::cpu.data 8411913 # number of WriteReq accesses(hits+misses)
374system.cpu.dcache.WriteReq_accesses::total 8411913 # number of WriteReq accesses(hits+misses)
375system.cpu.dcache.SoftPFReq_accesses::cpu.data 461660 # number of SoftPFReq accesses(hits+misses)
376system.cpu.dcache.SoftPFReq_accesses::total 461660 # number of SoftPFReq accesses(hits+misses)
377system.cpu.dcache.demand_accesses::cpu.data 21336307 # number of demand (read+write) accesses
378system.cpu.dcache.demand_accesses::total 21336307 # number of demand (read+write) accesses
379system.cpu.dcache.overall_accesses::cpu.data 21797967 # number of overall (read+write) accesses
380system.cpu.dcache.overall_accesses::total 21797967 # number of overall (read+write) accesses
381system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070074 # miss rate for ReadReq accesses
382system.cpu.dcache.ReadReq_miss_rate::total 0.070074 # miss rate for ReadReq accesses
383system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses
384system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses
385system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872404 # miss rate for SoftPFReq accesses
386system.cpu.dcache.SoftPFReq_miss_rate::total 0.872404 # miss rate for SoftPFReq accesses
387system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses
388system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses
389system.cpu.dcache.overall_miss_rate::cpu.data 0.074543 # miss rate for overall accesses
390system.cpu.dcache.overall_miss_rate::total 0.074543 # miss rate for overall accesses
391system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
392system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
393system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
394system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
395system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
396system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
397system.cpu.dcache.fast_writes 0 # number of fast writes performed
398system.cpu.dcache.cache_copies 0 # number of cache copies performed
399system.cpu.dcache.writebacks::writebacks 1535815 # number of writebacks
400system.cpu.dcache.writebacks::total 1535815 # number of writebacks
401system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
402system.cpu.toL2Bus.throughput 55211163 # Throughput (bytes/s)
403system.cpu.toL2Bus.data_through_bus 279231827 # Total data (bytes)
404system.cpu.toL2Bus.snoop_data_through_bus 3014592 # Total snoop data (bytes)
405system.cpu.l2cache.tags.replacements 105997 # number of replacements
406system.cpu.l2cache.tags.tagsinuse 64822.035422 # Cycle average of tags in use
407system.cpu.l2cache.tags.total_refs 3456726 # Total number of references to valid blocks.
408system.cpu.l2cache.tags.sampled_refs 170125 # Sample count of references to valid blocks.
409system.cpu.l2cache.tags.avg_refs 20.318742 # Average number of references to valid blocks.
410system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
411system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839631 # Average occupied blocks per requestor
412system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
413system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132256 # Average occupied blocks per requestor
414system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.541573 # Average occupied blocks per requestor
415system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.519483 # Average occupied blocks per requestor
416system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy
417system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
418system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
419system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
420system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy
421system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy
422system.cpu.l2cache.tags.occ_task_id_blocks::1024 64128 # Occupied blocks per task id
423system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
424system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id
425system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id
426system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20884 # Occupied blocks per task id
427system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39461 # Occupied blocks per task id
428system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id
429system.cpu.l2cache.tags.tag_accesses 32199668 # Number of tag accesses
430system.cpu.l2cache.tags.data_accesses 32199668 # Number of data accesses
431system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits
432system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
433system.cpu.l2cache.ReadReq_hits::cpu.inst 777860 # number of ReadReq hits
434system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits
435system.cpu.l2cache.ReadReq_hits::total 2062710 # number of ReadReq hits
436system.cpu.l2cache.Writeback_hits::writebacks 1538774 # number of Writeback hits
437system.cpu.l2cache.Writeback_hits::total 1538774 # number of Writeback hits
438system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
439system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
440system.cpu.l2cache.ReadExReq_hits::cpu.data 179729 # number of ReadExReq hits
441system.cpu.l2cache.ReadExReq_hits::total 179729 # number of ReadExReq hits
442system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits
443system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits
444system.cpu.l2cache.demand_hits::cpu.inst 777860 # number of demand (read+write) hits
445system.cpu.l2cache.demand_hits::cpu.data 1455273 # number of demand (read+write) hits
446system.cpu.l2cache.demand_hits::total 2242439 # number of demand (read+write) hits
447system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits
448system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits
449system.cpu.l2cache.overall_hits::cpu.inst 777860 # number of overall hits
450system.cpu.l2cache.overall_hits::cpu.data 1455273 # number of overall hits
451system.cpu.l2cache.overall_hits::total 2242439 # number of overall hits
452system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
453system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
454system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses
455system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses
456system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses
457system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses
458system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses
459system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses
460system.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses
461system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
462system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
463system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses
464system.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses
465system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses
466system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
467system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
468system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses
469system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses
470system.cpu.l2cache.overall_misses::total 180035 # number of overall misses
471system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses)
472system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)
473system.cpu.l2cache.ReadReq_accesses::cpu.inst 791185 # number of ReadReq accesses(hits+misses)
474system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses)
475system.cpu.l2cache.ReadReq_accesses::total 2108287 # number of ReadReq accesses(hits+misses)
476system.cpu.l2cache.Writeback_accesses::writebacks 1538774 # number of Writeback accesses(hits+misses)
477system.cpu.l2cache.Writeback_accesses::total 1538774 # number of Writeback accesses(hits+misses)
478system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses)
479system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
480system.cpu.l2cache.ReadExReq_accesses::cpu.data 314187 # number of ReadExReq accesses(hits+misses)
481system.cpu.l2cache.ReadExReq_accesses::total 314187 # number of ReadExReq accesses(hits+misses)
482system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses
483system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses
484system.cpu.l2cache.demand_accesses::cpu.inst 791185 # number of demand (read+write) accesses
485system.cpu.l2cache.demand_accesses::cpu.data 1621977 # number of demand (read+write) accesses
486system.cpu.l2cache.demand_accesses::total 2422474 # number of demand (read+write) accesses
487system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses
488system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses
489system.cpu.l2cache.overall_accesses::cpu.inst 791185 # number of overall (read+write) accesses
490system.cpu.l2cache.overall_accesses::cpu.data 1621977 # number of overall (read+write) accesses
491system.cpu.l2cache.overall_accesses::total 2422474 # number of overall (read+write) accesses
492system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses
493system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
494system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016842 # miss rate for ReadReq accesses
495system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses
496system.cpu.l2cache.ReadReq_miss_rate::total 0.021618 # miss rate for ReadReq accesses
497system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses
498system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses
499system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427955 # miss rate for ReadExReq accesses
500system.cpu.l2cache.ReadExReq_miss_rate::total 0.427955 # miss rate for ReadExReq accesses
501system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses
502system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
503system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016842 # miss rate for demand accesses
504system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses
505system.cpu.l2cache.demand_miss_rate::total 0.074319 # miss rate for demand accesses
506system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses
507system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
508system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016842 # miss rate for overall accesses
509system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses
510system.cpu.l2cache.overall_miss_rate::total 0.074319 # miss rate for overall accesses
511system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
512system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
513system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
514system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
515system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
516system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
517system.cpu.l2cache.fast_writes 0 # number of fast writes performed
518system.cpu.l2cache.cache_copies 0 # number of cache copies performed
519system.cpu.l2cache.writebacks::writebacks 98154 # number of writebacks
520system.cpu.l2cache.writebacks::total 98154 # number of writebacks
521system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
522
523---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 5.112126 # Number of seconds simulated
4sim_ticks 5112125984500 # Number of ticks simulated
5final_tick 5112125984500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1274105 # Simulator instruction rate (inst/s)
8host_op_rate 2608650 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 32578287771 # Simulator tick rate (ticks/s)
10host_mem_usage 593532 # Number of bytes of host memory used
11host_seconds 156.92 # Real time elapsed on the host
12sim_insts 199930130 # Number of instructions simulated
13sim_ops 409344539 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
19system.physmem.bytes_read::cpu.inst 852800 # Number of bytes read from this memory
20system.physmem.bytes_read::cpu.data 10650880 # Number of bytes read from this memory
21system.physmem.bytes_read::total 11532416 # Number of bytes read from this memory
22system.physmem.bytes_inst_read::cpu.inst 852800 # Number of instructions bytes read from this memory
23system.physmem.bytes_inst_read::total 852800 # Number of instructions bytes read from this memory
24system.physmem.bytes_written::writebacks 6281856 # Number of bytes written to this memory
25system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
26system.physmem.bytes_written::total 9271936 # Number of bytes written to this memory
27system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
28system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
29system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
30system.physmem.num_reads::cpu.inst 13325 # Number of read requests responded to by this memory
31system.physmem.num_reads::cpu.data 166420 # Number of read requests responded to by this memory
32system.physmem.num_reads::total 180194 # Number of read requests responded to by this memory
33system.physmem.num_writes::writebacks 98154 # Number of write requests responded to by this memory
34system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
35system.physmem.num_writes::total 144874 # Number of write requests responded to by this memory
36system.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s)
37system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s)
38system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
39system.physmem.bw_read::cpu.inst 166819 # Total read bandwidth from this memory (bytes/s)
40system.physmem.bw_read::cpu.data 2083454 # Total read bandwidth from this memory (bytes/s)
41system.physmem.bw_read::total 2255894 # Total read bandwidth from this memory (bytes/s)
42system.physmem.bw_inst_read::cpu.inst 166819 # Instruction read bandwidth from this memory (bytes/s)
43system.physmem.bw_inst_read::total 166819 # Instruction read bandwidth from this memory (bytes/s)
44system.physmem.bw_write::writebacks 1228815 # Write bandwidth from this memory (bytes/s)
45system.physmem.bw_write::pc.south_bridge.ide 584900 # Write bandwidth from this memory (bytes/s)
46system.physmem.bw_write::total 1813714 # Write bandwidth from this memory (bytes/s)
47system.physmem.bw_total::writebacks 1228815 # Total bandwidth to/from this memory (bytes/s)
48system.physmem.bw_total::pc.south_bridge.ide 590446 # Total bandwidth to/from this memory (bytes/s)
49system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s)
50system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
51system.physmem.bw_total::cpu.inst 166819 # Total bandwidth to/from this memory (bytes/s)
52system.physmem.bw_total::cpu.data 2083454 # Total bandwidth to/from this memory (bytes/s)
53system.physmem.bw_total::total 4069609 # Total bandwidth to/from this memory (bytes/s)
54system.membus.throughput 9050072 # Throughput (bytes/s)
55system.membus.data_through_bus 46265107 # Total data (bytes)
56system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
57system.iocache.tags.replacements 47569 # number of replacements
58system.iocache.tags.tagsinuse 0.042447 # Cycle average of tags in use
59system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
60system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks.
61system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
62system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit.
63system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042447 # Average occupied blocks per requestor
64system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
65system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy
66system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
67system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
68system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
69system.iocache.tags.tag_accesses 428616 # Number of tag accesses
70system.iocache.tags.data_accesses 428616 # Number of data accesses
71system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
72system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
73system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
74system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
75system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses
76system.iocache.demand_misses::total 904 # number of demand (read+write) misses
77system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses
78system.iocache.overall_misses::total 904 # number of overall misses
79system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
80system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
81system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
82system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
83system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses
84system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses
85system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses
86system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses
87system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
88system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
89system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
90system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
91system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
92system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
93system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
94system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
--- 11 unchanged lines hidden (view full) ---
106system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
107system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
108system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
109system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
110system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
111system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
112system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
113system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
114system.iobus.throughput 2555207 # Throughput (bytes/s)
115system.iobus.data_through_bus 13062542 # Total data (bytes)
116system.cpu_clk_domain.clock 500 # Clock period in ticks
117system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
118system.cpu.numCycles 10224253344 # number of cpu cycles simulated
119system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
120system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
121system.cpu.committedInsts 199930130 # Number of instructions committed
122system.cpu.committedOps 409344539 # Number of ops (including micro ops) committed
123system.cpu.num_int_alu_accesses 374365317 # Number of integer alu accesses
124system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
125system.cpu.num_func_calls 2307745 # number of times a function call or return occured
126system.cpu.num_conditional_control_insts 39976374 # number of instructions that are conditional controls
127system.cpu.num_int_insts 374365317 # number of integer instructions
128system.cpu.num_fp_insts 0 # number of float instructions
129system.cpu.num_int_register_reads 682286798 # number of times the integer registers were read
130system.cpu.num_int_register_writes 323369753 # number of times the integer registers were written
131system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
132system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
133system.cpu.num_cc_register_reads 233715334 # number of times the CC registers were read
134system.cpu.num_cc_register_writes 157233726 # number of times the CC registers were written
135system.cpu.num_mem_refs 35661072 # number of memory refs
136system.cpu.num_load_insts 27238907 # Number of load instructions
137system.cpu.num_store_insts 8422165 # Number of store instructions
138system.cpu.num_idle_cycles 9770516870.697727 # Number of idle cycles
139system.cpu.num_busy_cycles 453736473.302274 # Number of busy cycles
140system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles
141system.cpu.idle_fraction 0.955622 # Percentage of idle cycles
142system.cpu.Branches 43125613 # Number of branches fetched
143system.cpu.op_class::No_OpClass 175318 0.04% 0.04% # Class of executed instruction
144system.cpu.op_class::IntAlu 373241846 91.18% 91.22% # Class of executed instruction
145system.cpu.op_class::IntMult 144365 0.04% 91.26% # Class of executed instruction
146system.cpu.op_class::IntDiv 122968 0.03% 91.29% # Class of executed instruction
147system.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction
148system.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction
149system.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction
150system.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction
151system.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction
152system.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction
153system.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction
154system.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction
--- 10 unchanged lines hidden (view full) ---
165system.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction
166system.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction
167system.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction
168system.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction
169system.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction
170system.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction
171system.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction
172system.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction
173system.cpu.op_class::MemRead 27238907 6.65% 97.94% # Class of executed instruction
174system.cpu.op_class::MemWrite 8422165 2.06% 100.00% # Class of executed instruction
175system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
176system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
177system.cpu.op_class::total 409345569 # Class of executed instruction
178system.cpu.kern.inst.arm 0 # number of arm instructions executed
179system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
180system.cpu.icache.tags.replacements 790679 # number of replacements
181system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use
182system.cpu.icache.tags.total_refs 243526070 # Total number of references to valid blocks.
183system.cpu.icache.tags.sampled_refs 791191 # Sample count of references to valid blocks.
184system.cpu.icache.tags.avg_refs 307.796815 # Average number of references to valid blocks.
185system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit.
186system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor
187system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy
188system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy
189system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
190system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id
191system.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
192system.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id
193system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
194system.cpu.icache.tags.tag_accesses 245108466 # Number of tag accesses
195system.cpu.icache.tags.data_accesses 245108466 # Number of data accesses
196system.cpu.icache.ReadReq_hits::cpu.inst 243526070 # number of ReadReq hits
197system.cpu.icache.ReadReq_hits::total 243526070 # number of ReadReq hits
198system.cpu.icache.demand_hits::cpu.inst 243526070 # number of demand (read+write) hits
199system.cpu.icache.demand_hits::total 243526070 # number of demand (read+write) hits
200system.cpu.icache.overall_hits::cpu.inst 243526070 # number of overall hits
201system.cpu.icache.overall_hits::total 243526070 # number of overall hits
202system.cpu.icache.ReadReq_misses::cpu.inst 791198 # number of ReadReq misses
203system.cpu.icache.ReadReq_misses::total 791198 # number of ReadReq misses
204system.cpu.icache.demand_misses::cpu.inst 791198 # number of demand (read+write) misses
205system.cpu.icache.demand_misses::total 791198 # number of demand (read+write) misses
206system.cpu.icache.overall_misses::cpu.inst 791198 # number of overall misses
207system.cpu.icache.overall_misses::total 791198 # number of overall misses
208system.cpu.icache.ReadReq_accesses::cpu.inst 244317268 # number of ReadReq accesses(hits+misses)
209system.cpu.icache.ReadReq_accesses::total 244317268 # number of ReadReq accesses(hits+misses)
210system.cpu.icache.demand_accesses::cpu.inst 244317268 # number of demand (read+write) accesses
211system.cpu.icache.demand_accesses::total 244317268 # number of demand (read+write) accesses
212system.cpu.icache.overall_accesses::cpu.inst 244317268 # number of overall (read+write) accesses
213system.cpu.icache.overall_accesses::total 244317268 # number of overall (read+write) accesses
214system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses
215system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses
216system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses
217system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses
218system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses
219system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses
220system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
221system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
222system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
223system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
224system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
225system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
226system.cpu.icache.fast_writes 0 # number of fast writes performed
227system.cpu.icache.cache_copies 0 # number of cache copies performed
228system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
229system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements
230system.cpu.itb_walker_cache.tags.tagsinuse 3.026310 # Cycle average of tags in use
231system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks.
232system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks.
233system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks.
234system.cpu.itb_walker_cache.tags.warmup_cycle 5102111082500 # Cycle when the warmup percentage was hit.
235system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026310 # Average occupied blocks per requestor
236system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy
237system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy
238system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
239system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
240system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
241system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
242system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
243system.cpu.itb_walker_cache.tags.tag_accesses 28774 # Number of tag accesses
244system.cpu.itb_walker_cache.tags.data_accesses 28774 # Number of data accesses
245system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits
246system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits
247system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
248system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
249system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits
250system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits
251system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits
252system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits
253system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses
254system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses
255system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses
256system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses
257system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses
258system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses
259system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses)
260system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses)
261system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
262system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
263system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses
264system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses
265system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses
266system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses
267system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses
268system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses
269system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses
270system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses
271system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses
272system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses
273system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
274system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
275system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
276system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
277system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
278system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
279system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
280system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
281system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks
282system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks
283system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
284system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements
285system.cpu.dtb_walker_cache.tags.tagsinuse 5.014183 # Cycle average of tags in use
286system.cpu.dtb_walker_cache.tags.total_refs 12951 # Total number of references to valid blocks.
287system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks.
288system.cpu.dtb_walker_cache.tags.avg_refs 1.694270 # Average number of references to valid blocks.
289system.cpu.dtb_walker_cache.tags.warmup_cycle 5100459675500 # Cycle when the warmup percentage was hit.
290system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014183 # Average occupied blocks per requestor
291system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy
292system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy
293system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 12 # Occupied blocks per task id
294system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id
295system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
296system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
297system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
298system.cpu.dtb_walker_cache.tags.tag_accesses 52390 # Number of tag accesses
299system.cpu.dtb_walker_cache.tags.data_accesses 52390 # Number of data accesses
300system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12959 # number of ReadReq hits
301system.cpu.dtb_walker_cache.ReadReq_hits::total 12959 # number of ReadReq hits
302system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12959 # number of demand (read+write) hits
303system.cpu.dtb_walker_cache.demand_hits::total 12959 # number of demand (read+write) hits
304system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12959 # number of overall hits
305system.cpu.dtb_walker_cache.overall_hits::total 12959 # number of overall hits
306system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses
307system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses
308system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses
309system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses
310system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses
311system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses
312system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21783 # number of ReadReq accesses(hits+misses)
313system.cpu.dtb_walker_cache.ReadReq_accesses::total 21783 # number of ReadReq accesses(hits+misses)
314system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21783 # number of demand (read+write) accesses
315system.cpu.dtb_walker_cache.demand_accesses::total 21783 # number of demand (read+write) accesses
316system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21783 # number of overall (read+write) accesses
317system.cpu.dtb_walker_cache.overall_accesses::total 21783 # number of overall (read+write) accesses
318system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405087 # miss rate for ReadReq accesses
319system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405087 # miss rate for ReadReq accesses
320system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405087 # miss rate for demand accesses
321system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405087 # miss rate for demand accesses
322system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405087 # miss rate for overall accesses
323system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405087 # miss rate for overall accesses
324system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
325system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
326system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
327system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
328system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
329system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
330system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
331system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
332system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks
333system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks
334system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
335system.cpu.dcache.tags.replacements 1622084 # number of replacements
336system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use
337system.cpu.dcache.tags.total_refs 20175355 # Total number of references to valid blocks.
338system.cpu.dcache.tags.sampled_refs 1622596 # Sample count of references to valid blocks.
339system.cpu.dcache.tags.avg_refs 12.433998 # Average number of references to valid blocks.
340system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
341system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor
342system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
343system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
344system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
345system.cpu.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id
346system.cpu.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id
347system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id
348system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
349system.cpu.dcache.tags.tag_accesses 88814480 # Number of tag accesses
350system.cpu.dcache.tags.data_accesses 88814480 # Number of data accesses
351system.cpu.dcache.ReadReq_hits::cpu.data 12018728 # number of ReadReq hits
352system.cpu.dcache.ReadReq_hits::total 12018728 # number of ReadReq hits
353system.cpu.dcache.WriteReq_hits::cpu.data 8095451 # number of WriteReq hits
354system.cpu.dcache.WriteReq_hits::total 8095451 # number of WriteReq hits
355system.cpu.dcache.SoftPFReq_hits::cpu.data 58906 # number of SoftPFReq hits
356system.cpu.dcache.SoftPFReq_hits::total 58906 # number of SoftPFReq hits
357system.cpu.dcache.demand_hits::cpu.data 20114179 # number of demand (read+write) hits
358system.cpu.dcache.demand_hits::total 20114179 # number of demand (read+write) hits
359system.cpu.dcache.overall_hits::cpu.data 20173085 # number of overall hits
360system.cpu.dcache.overall_hits::total 20173085 # number of overall hits
361system.cpu.dcache.ReadReq_misses::cpu.data 905666 # number of ReadReq misses
362system.cpu.dcache.ReadReq_misses::total 905666 # number of ReadReq misses
363system.cpu.dcache.WriteReq_misses::cpu.data 316462 # number of WriteReq misses
364system.cpu.dcache.WriteReq_misses::total 316462 # number of WriteReq misses
365system.cpu.dcache.SoftPFReq_misses::cpu.data 402754 # number of SoftPFReq misses
366system.cpu.dcache.SoftPFReq_misses::total 402754 # number of SoftPFReq misses
367system.cpu.dcache.demand_misses::cpu.data 1222128 # number of demand (read+write) misses
368system.cpu.dcache.demand_misses::total 1222128 # number of demand (read+write) misses
369system.cpu.dcache.overall_misses::cpu.data 1624882 # number of overall misses
370system.cpu.dcache.overall_misses::total 1624882 # number of overall misses
371system.cpu.dcache.ReadReq_accesses::cpu.data 12924394 # number of ReadReq accesses(hits+misses)
372system.cpu.dcache.ReadReq_accesses::total 12924394 # number of ReadReq accesses(hits+misses)
373system.cpu.dcache.WriteReq_accesses::cpu.data 8411913 # number of WriteReq accesses(hits+misses)
374system.cpu.dcache.WriteReq_accesses::total 8411913 # number of WriteReq accesses(hits+misses)
375system.cpu.dcache.SoftPFReq_accesses::cpu.data 461660 # number of SoftPFReq accesses(hits+misses)
376system.cpu.dcache.SoftPFReq_accesses::total 461660 # number of SoftPFReq accesses(hits+misses)
377system.cpu.dcache.demand_accesses::cpu.data 21336307 # number of demand (read+write) accesses
378system.cpu.dcache.demand_accesses::total 21336307 # number of demand (read+write) accesses
379system.cpu.dcache.overall_accesses::cpu.data 21797967 # number of overall (read+write) accesses
380system.cpu.dcache.overall_accesses::total 21797967 # number of overall (read+write) accesses
381system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070074 # miss rate for ReadReq accesses
382system.cpu.dcache.ReadReq_miss_rate::total 0.070074 # miss rate for ReadReq accesses
383system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses
384system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses
385system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872404 # miss rate for SoftPFReq accesses
386system.cpu.dcache.SoftPFReq_miss_rate::total 0.872404 # miss rate for SoftPFReq accesses
387system.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses
388system.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses
389system.cpu.dcache.overall_miss_rate::cpu.data 0.074543 # miss rate for overall accesses
390system.cpu.dcache.overall_miss_rate::total 0.074543 # miss rate for overall accesses
391system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
392system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
393system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
394system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
395system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
396system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
397system.cpu.dcache.fast_writes 0 # number of fast writes performed
398system.cpu.dcache.cache_copies 0 # number of cache copies performed
399system.cpu.dcache.writebacks::writebacks 1535815 # number of writebacks
400system.cpu.dcache.writebacks::total 1535815 # number of writebacks
401system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
402system.cpu.toL2Bus.throughput 55211163 # Throughput (bytes/s)
403system.cpu.toL2Bus.data_through_bus 279231827 # Total data (bytes)
404system.cpu.toL2Bus.snoop_data_through_bus 3014592 # Total snoop data (bytes)
405system.cpu.l2cache.tags.replacements 105997 # number of replacements
406system.cpu.l2cache.tags.tagsinuse 64822.035422 # Cycle average of tags in use
407system.cpu.l2cache.tags.total_refs 3456726 # Total number of references to valid blocks.
408system.cpu.l2cache.tags.sampled_refs 170125 # Sample count of references to valid blocks.
409system.cpu.l2cache.tags.avg_refs 20.318742 # Average number of references to valid blocks.
410system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
411system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839631 # Average occupied blocks per requestor
412system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor
413system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132256 # Average occupied blocks per requestor
414system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.541573 # Average occupied blocks per requestor
415system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.519483 # Average occupied blocks per requestor
416system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy
417system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
418system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
419system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy
420system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy
421system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy
422system.cpu.l2cache.tags.occ_task_id_blocks::1024 64128 # Occupied blocks per task id
423system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
424system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id
425system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3455 # Occupied blocks per task id
426system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20884 # Occupied blocks per task id
427system.cpu.l2cache.tags.age_task_id_blocks_1024::4 39461 # Occupied blocks per task id
428system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978516 # Percentage of cache occupancy per task id
429system.cpu.l2cache.tags.tag_accesses 32199668 # Number of tag accesses
430system.cpu.l2cache.tags.data_accesses 32199668 # Number of data accesses
431system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits
432system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits
433system.cpu.l2cache.ReadReq_hits::cpu.inst 777860 # number of ReadReq hits
434system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits
435system.cpu.l2cache.ReadReq_hits::total 2062710 # number of ReadReq hits
436system.cpu.l2cache.Writeback_hits::writebacks 1538774 # number of Writeback hits
437system.cpu.l2cache.Writeback_hits::total 1538774 # number of Writeback hits
438system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits
439system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits
440system.cpu.l2cache.ReadExReq_hits::cpu.data 179729 # number of ReadExReq hits
441system.cpu.l2cache.ReadExReq_hits::total 179729 # number of ReadExReq hits
442system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits
443system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits
444system.cpu.l2cache.demand_hits::cpu.inst 777860 # number of demand (read+write) hits
445system.cpu.l2cache.demand_hits::cpu.data 1455273 # number of demand (read+write) hits
446system.cpu.l2cache.demand_hits::total 2242439 # number of demand (read+write) hits
447system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits
448system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits
449system.cpu.l2cache.overall_hits::cpu.inst 777860 # number of overall hits
450system.cpu.l2cache.overall_hits::cpu.data 1455273 # number of overall hits
451system.cpu.l2cache.overall_hits::total 2242439 # number of overall hits
452system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
453system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
454system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses
455system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses
456system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses
457system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses
458system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses
459system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses
460system.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses
461system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
462system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
463system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses
464system.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses
465system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses
466system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
467system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
468system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses
469system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses
470system.cpu.l2cache.overall_misses::total 180035 # number of overall misses
471system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses)
472system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses)
473system.cpu.l2cache.ReadReq_accesses::cpu.inst 791185 # number of ReadReq accesses(hits+misses)
474system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses)
475system.cpu.l2cache.ReadReq_accesses::total 2108287 # number of ReadReq accesses(hits+misses)
476system.cpu.l2cache.Writeback_accesses::writebacks 1538774 # number of Writeback accesses(hits+misses)
477system.cpu.l2cache.Writeback_accesses::total 1538774 # number of Writeback accesses(hits+misses)
478system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses)
479system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses)
480system.cpu.l2cache.ReadExReq_accesses::cpu.data 314187 # number of ReadExReq accesses(hits+misses)
481system.cpu.l2cache.ReadExReq_accesses::total 314187 # number of ReadExReq accesses(hits+misses)
482system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses
483system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses
484system.cpu.l2cache.demand_accesses::cpu.inst 791185 # number of demand (read+write) accesses
485system.cpu.l2cache.demand_accesses::cpu.data 1621977 # number of demand (read+write) accesses
486system.cpu.l2cache.demand_accesses::total 2422474 # number of demand (read+write) accesses
487system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses
488system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses
489system.cpu.l2cache.overall_accesses::cpu.inst 791185 # number of overall (read+write) accesses
490system.cpu.l2cache.overall_accesses::cpu.data 1621977 # number of overall (read+write) accesses
491system.cpu.l2cache.overall_accesses::total 2422474 # number of overall (read+write) accesses
492system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses
493system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses
494system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016842 # miss rate for ReadReq accesses
495system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses
496system.cpu.l2cache.ReadReq_miss_rate::total 0.021618 # miss rate for ReadReq accesses
497system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses
498system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses
499system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427955 # miss rate for ReadExReq accesses
500system.cpu.l2cache.ReadExReq_miss_rate::total 0.427955 # miss rate for ReadExReq accesses
501system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses
502system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses
503system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016842 # miss rate for demand accesses
504system.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses
505system.cpu.l2cache.demand_miss_rate::total 0.074319 # miss rate for demand accesses
506system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses
507system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses
508system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016842 # miss rate for overall accesses
509system.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses
510system.cpu.l2cache.overall_miss_rate::total 0.074319 # miss rate for overall accesses
511system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
512system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
513system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
514system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
515system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
516system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
517system.cpu.l2cache.fast_writes 0 # number of fast writes performed
518system.cpu.l2cache.cache_copies 0 # number of cache copies performed
519system.cpu.l2cache.writebacks::writebacks 98154 # number of writebacks
520system.cpu.l2cache.writebacks::total 98154 # number of writebacks
521system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
522
523---------- End Simulation Statistics ----------