11c11
< children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
---
> children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table
14c14
< clock=1
---
> clock=1000
55c55
< clock=1
---
> clock=1000
65c65
< clock=1
---
> clock=1000
75c75
< children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache tracer
---
> children=dcache dtb dtb_walker_cache icache interrupts itb itb_walker_cache l2cache toL2Bus tracer
110c110
< clock=1
---
> clock=500
112a113
> hit_latency=2
114d114
< latency=1000
120a121
> response_latency=2
124c125
< tgts_per_mshr=8
---
> tgts_per_mshr=20
129c130
< mem_side=system.toL2Bus.slave[1]
---
> mem_side=system.cpu.toL2Bus.slave[1]
139c140
< clock=1
---
> clock=500
148c149
< clock=1
---
> clock=500
150a152
> hit_latency=2
152d153
< latency=1000
158a160
> response_latency=2
167c169
< mem_side=system.toL2Bus.slave[3]
---
> mem_side=system.cpu.toL2Bus.slave[3]
174c176
< clock=1
---
> clock=500
176a179
> hit_latency=2
178d180
< latency=1000
184a187
> response_latency=2
188c191
< tgts_per_mshr=8
---
> tgts_per_mshr=20
193c196
< mem_side=system.toL2Bus.slave[0]
---
> mem_side=system.cpu.toL2Bus.slave[0]
197c200
< clock=1
---
> clock=500
214c217
< clock=1
---
> clock=500
223c226
< clock=1
---
> clock=500
225a229
> hit_latency=2
227d230
< latency=1000
233a237
> response_latency=2
242c246
< mem_side=system.toL2Bus.slave[2]
---
> mem_side=system.cpu.toL2Bus.slave[2]
243a248,284
> [system.cpu.l2cache]
> type=BaseCache
> addr_ranges=0:18446744073709551615
> assoc=8
> block_size=64
> clock=500
> forward_snoops=true
> hash_delay=1
> hit_latency=20
> is_top_level=false
> max_miss_count=0
> mshrs=20
> prefetch_on_access=false
> prefetcher=Null
> prioritizeRequests=false
> repl=Null
> response_latency=20
> size=4194304
> subblock_size=0
> system=system
> tgts_per_mshr=12
> trace_addr=0
> two_queue=false
> write_buffers=8
> cpu_side=system.cpu.toL2Bus.master[0]
> mem_side=system.membus.slave[3]
>
> [system.cpu.toL2Bus]
> type=CoherentBus
> block_size=64
> clock=500
> header_cycles=1
> use_default_range=false
> width=32
> master=system.cpu.l2cache.cpu_side
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
>
626c667
< clock=1
---
> clock=1000
628a670
> hit_latency=50
630d671
< latency=50000
636a678
> response_latency=50
647,672d688
< [system.l2c]
< type=BaseCache
< addr_ranges=0:18446744073709551615
< assoc=8
< block_size=64
< clock=1
< forward_snoops=true
< hash_delay=1
< is_top_level=false
< latency=10000
< max_miss_count=0
< mshrs=92
< prefetch_on_access=false
< prefetcher=Null
< prioritizeRequests=false
< repl=Null
< size=4194304
< subblock_size=0
< system=system
< tgts_per_mshr=16
< trace_addr=0
< two_queue=false
< write_buffers=8
< cpu_side=system.toL2Bus.master[0]
< mem_side=system.membus.slave[3]
<
683c699
< slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master
---
> slave=system.apicbridge.master system.system_port system.iocache.mem_side system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
687c703
< clock=1
---
> clock=1000
710c726
< clock=1
---
> clock=1000
728c744
< clock=1
---
> clock=1000
752c768
< clock=1
---
> clock=1000
769c785
< clock=1
---
> clock=1000
786c802
< clock=1
---
> clock=1000
803c819
< clock=1
---
> clock=1000
820c836
< clock=1
---
> clock=1000
838c854
< clock=1
---
> clock=1000
861c877
< clock=1
---
> clock=1000
874c890
< clock=1
---
> clock=1000
921c937
< clock=1
---
> clock=1000
1056c1072
< clock=1
---
> clock=1000
1068c1084
< clock=1
---
> clock=1000
1087c1103
< clock=1
---
> clock=1000
1102c1118
< clock=1
---
> clock=1000
1117c1133
< clock=1
---
> clock=1000
1129c1145
< clock=1
---
> clock=1000
1137,1138c1153,1156
< type=SimpleMemory
< clock=1
---
> type=SimpleDRAM
> addr_mapping=openmap
> banks_per_rank=8
> clock=1000
1140d1157
< file=
1142,1143c1159,1160
< latency=30000
< latency_var=0
---
> lines_per_rowbuffer=64
> mem_sched_policy=fcfs
1144a1162
> page_policy=open
1145a1164,1174
> ranks_per_channel=2
> read_buffer_size=32
> tBURST=4000
> tCL=14000
> tRCD=14000
> tREFI=7800000
> tRFC=300000
> tRP=14000
> tWTR=1000
> write_buffer_size=32
> write_thresh_perc=70
1170,1179d1198
< [system.toL2Bus]
< type=CoherentBus
< block_size=64
< clock=1000
< header_cycles=1
< use_default_range=false
< width=8
< master=system.l2c.cpu_side
< slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
<