23d22
< physmem=system.physmem
34c33
< system_port=system.membus.port[3]
---
> system_port=system.membus.slave[1]
61,62c60,61
< master=system.membus.port[2]
< slave=system.iobus.port[1]
---
> master=system.membus.slave[0]
> slave=system.iobus.master[0]
72,73c71,72
< master=system.iobus.port[0]
< slave=system.membus.port[1]
---
> master=system.iobus.slave[0]
> slave=system.membus.master[1]
85a85
> fastmem=false
109c109
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
130c130
< mem_side=system.toL2Bus.port[2]
---
> mem_side=system.toL2Bus.slave[1]
145c145
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
166c166
< mem_side=system.toL2Bus.port[4]
---
> mem_side=system.toL2Bus.slave[3]
170c170
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
191c191
< mem_side=system.toL2Bus.port[1]
---
> mem_side=system.toL2Bus.slave[0]
199,200c199,201
< int_port=system.membus.port[7]
< pio=system.membus.port[6]
---
> int_master=system.membus.slave[4]
> int_slave=system.membus.master[3]
> pio=system.membus.master[2]
215c216
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
236c237
< mem_side=system.toL2Bus.port[3]
---
> mem_side=system.toL2Bus.slave[2]
613c614,615
< port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
---
> master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
> slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
617c619
< addr_range=0:134217727
---
> addr_ranges=0:134217727
637,638c639,640
< cpu_side=system.iobus.port[21]
< mem_side=system.membus.port[4]
---
> cpu_side=system.iobus.master[18]
> mem_side=system.membus.slave[2]
642c644
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
662,663c664,665
< cpu_side=system.toL2Bus.port[0]
< mem_side=system.membus.port[5]
---
> cpu_side=system.toL2Bus.master[0]
> mem_side=system.membus.slave[3]
675c677,678
< port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
---
> master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
> slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master
713c716
< pio=system.iobus.port[15]
---
> pio=system.iobus.master[12]
723c726
< pio=system.iobus.port[16]
---
> pio=system.iobus.master[13]
753c756
< pio=system.iobus.port[17]
---
> pio=system.iobus.master[14]
769c772
< pio=system.iobus.port[18]
---
> pio=system.iobus.master[15]
785c788
< pio=system.iobus.port[19]
---
> pio=system.iobus.master[16]
801c804
< pio=system.iobus.port[20]
---
> pio=system.iobus.master[17]
817c820
< pio=system.iobus.port[14]
---
> pio=system.iobus.master[11]
850c853
< pio=system.iobus.port[2]
---
> pio=system.iobus.master[1]
860c863
< pio=system.iobus.port[3]
---
> pio=system.iobus.master[2]
915,917c918,920
< config=system.iobus.port[5]
< dma=system.iobus.port[6]
< pio=system.iobus.port[4]
---
> config=system.iobus.master[4]
> dma=system.iobus.slave[1]
> pio=system.iobus.master[3]
1044,1045c1047,1048
< int_port=system.iobus.port[13]
< pio=system.iobus.port[12]
---
> int_master=system.iobus.slave[2]
> pio=system.iobus.master[10]
1057c1060
< pio=system.iobus.port[7]
---
> pio=system.iobus.master[5]
1074c1077
< pio=system.iobus.port[8]
---
> pio=system.iobus.master[6]
1088c1091
< pio=system.iobus.port[9]
---
> pio=system.iobus.master[7]
1100c1103
< pio=system.iobus.port[10]
---
> pio=system.iobus.master[8]
1111c1114
< pio=system.iobus.port[11]
---
> pio=system.iobus.master[9]
1114c1117,1118
< type=PhysicalMemory
---
> type=SimpleMemory
> conf_table_reported=false
1115a1120
> in_addr_map=true
1121c1126
< port=system.membus.port[0]
---
> port=system.membus.master[0]
1152c1157,1158
< port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
---
> master=system.l2c.cpu_side
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
< physmem=system.physmem
34c33
< system_port=system.membus.port[3]
---
> system_port=system.membus.slave[1]
61,62c60,61
< master=system.membus.port[2]
< slave=system.iobus.port[1]
---
> master=system.membus.slave[0]
> slave=system.iobus.master[0]
72,73c71,72
< master=system.iobus.port[0]
< slave=system.membus.port[1]
---
> master=system.iobus.slave[0]
> slave=system.membus.master[1]
85a85
> fastmem=false
109c109
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
130c130
< mem_side=system.toL2Bus.port[2]
---
> mem_side=system.toL2Bus.slave[1]
145c145
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
166c166
< mem_side=system.toL2Bus.port[4]
---
> mem_side=system.toL2Bus.slave[3]
170c170
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
191c191
< mem_side=system.toL2Bus.port[1]
---
> mem_side=system.toL2Bus.slave[0]
199,200c199,201
< int_port=system.membus.port[7]
< pio=system.membus.port[6]
---
> int_master=system.membus.slave[4]
> int_slave=system.membus.master[3]
> pio=system.membus.master[2]
215c216
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
236c237
< mem_side=system.toL2Bus.port[3]
---
> mem_side=system.toL2Bus.slave[2]
613c614,615
< port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
---
> master=system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
> slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master
617c619
< addr_range=0:134217727
---
> addr_ranges=0:134217727
637,638c639,640
< cpu_side=system.iobus.port[21]
< mem_side=system.membus.port[4]
---
> cpu_side=system.iobus.master[18]
> mem_side=system.membus.slave[2]
642c644
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
662,663c664,665
< cpu_side=system.toL2Bus.port[0]
< mem_side=system.membus.port[5]
---
> cpu_side=system.toL2Bus.master[0]
> mem_side=system.membus.slave[3]
675c677,678
< port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
---
> master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
> slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master
713c716
< pio=system.iobus.port[15]
---
> pio=system.iobus.master[12]
723c726
< pio=system.iobus.port[16]
---
> pio=system.iobus.master[13]
753c756
< pio=system.iobus.port[17]
---
> pio=system.iobus.master[14]
769c772
< pio=system.iobus.port[18]
---
> pio=system.iobus.master[15]
785c788
< pio=system.iobus.port[19]
---
> pio=system.iobus.master[16]
801c804
< pio=system.iobus.port[20]
---
> pio=system.iobus.master[17]
817c820
< pio=system.iobus.port[14]
---
> pio=system.iobus.master[11]
850c853
< pio=system.iobus.port[2]
---
> pio=system.iobus.master[1]
860c863
< pio=system.iobus.port[3]
---
> pio=system.iobus.master[2]
915,917c918,920
< config=system.iobus.port[5]
< dma=system.iobus.port[6]
< pio=system.iobus.port[4]
---
> config=system.iobus.master[4]
> dma=system.iobus.slave[1]
> pio=system.iobus.master[3]
1044,1045c1047,1048
< int_port=system.iobus.port[13]
< pio=system.iobus.port[12]
---
> int_master=system.iobus.slave[2]
> pio=system.iobus.master[10]
1057c1060
< pio=system.iobus.port[7]
---
> pio=system.iobus.master[5]
1074c1077
< pio=system.iobus.port[8]
---
> pio=system.iobus.master[6]
1088c1091
< pio=system.iobus.port[9]
---
> pio=system.iobus.master[7]
1100c1103
< pio=system.iobus.port[10]
---
> pio=system.iobus.master[8]
1111c1114
< pio=system.iobus.port[11]
---
> pio=system.iobus.master[9]
1114c1117,1118
< type=PhysicalMemory
---
> type=SimpleMemory
> conf_table_reported=false
1115a1120
> in_addr_map=true
1121c1126
< port=system.membus.port[0]
---
> port=system.membus.master[0]
1152c1157,1158
< port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side
---
> master=system.l2c.cpu_side
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walker_cache.mem_side system.cpu.dtb_walker_cache.mem_side