| stats.txt (9797:9cd5f91e7a79) | stats.txt (9838:43d22d746e7a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.615733 # Number of seconds simulated 4sim_ticks 2615733285000 # Number of ticks simulated 5final_tick 2615733285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.615716 # Number of seconds simulated 4sim_ticks 2615716222000 # Number of ticks simulated 5final_tick 2615716222000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 250012 # Simulator instruction rate (inst/s) 8host_op_rate 318151 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10863402189 # Simulator tick rate (ticks/s) 10host_mem_usage 396412 # Number of bytes of host memory used 11host_seconds 240.78 # Real time elapsed on the host 12sim_insts 60198861 # Number of instructions simulated 13sim_ops 76605713 # Number of ops (including micro ops) simulated | 7host_inst_rate 250038 # Simulator instruction rate (inst/s) 8host_op_rate 318184 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10864403710 # Simulator tick rate (ticks/s) 10host_mem_usage 394540 # Number of bytes of host memory used 11host_seconds 240.76 # Real time elapsed on the host 12sim_insts 60199078 # Number of instructions simulated 13sim_ops 76605946 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 704864 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.inst 704928 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.data 9093712 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 132482416 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 704864 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 704864 # Number of instructions bytes read from this memory | 19system.physmem.bytes_read::total 132482480 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 704928 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 704928 # Number of instructions bytes read from this memory |
| 22system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory | 22system.physmem.bytes_written::writebacks 3710144 # Number of bytes written to this memory 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory 24system.physmem.bytes_written::total 6726216 # Number of bytes written to this memory 25system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.inst 17216 # Number of read requests responded to by this memory | 28system.physmem.num_reads::cpu.inst 17217 # Number of read requests responded to by this memory |
| 29system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory | 29system.physmem.num_reads::cpu.data 142123 # Number of read requests responded to by this memory |
| 30system.physmem.num_reads::total 15494770 # Number of read requests responded to by this memory | 30system.physmem.num_reads::total 15494771 # Number of read requests responded to by this memory |
| 31system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory | 31system.physmem.num_writes::writebacks 57971 # Number of write requests responded to by this memory 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 811989 # Number of write requests responded to by this memory |
| 34system.physmem.bw_read::realview.clcd 46902103 # Total read bandwidth from this memory (bytes/s) | 34system.physmem.bw_read::realview.clcd 46902409 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.inst 269471 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3476544 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 50648289 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 269471 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 269471 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1418395 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1153050 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2571446 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1418395 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 46902103 # Total bandwidth to/from this memory (bytes/s) | 37system.physmem.bw_read::cpu.inst 269497 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3476567 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 50648644 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 269497 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 269497 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1418405 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1153058 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2571462 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1418405 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 46902409 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) | 47system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.bw_total::cpu.inst 269471 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4629594 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53219735 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15494770 # Total number of read requests seen 53system.physmem.writeReqs 811989 # Total number of write requests seen 54system.physmem.cpureqs 215180 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 991665280 # Total number of bytes read from memory | 49system.physmem.bw_total::cpu.inst 269497 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4629625 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53220107 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15494771 # Total number of read requests accepted by DRAM controller 53system.physmem.writeReqs 811989 # Total number of write requests accepted by DRAM controller 54system.physmem.readBursts 15494771 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 55system.physmem.writeBursts 811989 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 56system.physmem.bytesRead 991665344 # Total number of bytes read from memory |
| 56system.physmem.bytesWritten 51967296 # Total number of bytes written to memory | 57system.physmem.bytesWritten 51967296 # Total number of bytes written to memory |
| 57system.physmem.bytesConsumedRd 132482416 # bytesRead derated as per pkt->getSize() | 58system.physmem.bytesConsumedRd 132482480 # bytesRead derated as per pkt->getSize() |
| 58system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize() | 59system.physmem.bytesConsumedWr 6726216 # bytesWritten derated as per pkt->getSize() |
| 59system.physmem.servicedByWrQ 299 # Number of read reqs serviced by write Q | 60system.physmem.servicedByWrQ 1656 # Number of DRAM read bursts serviced by write Q |
| 60system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed | 61system.physmem.neitherReadNorWrite 4515 # Reqs where no action is needed |
| 61system.physmem.perBankRdReqs::0 968107 # Track reads on a per bank basis | 62system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis |
| 62system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis | 63system.physmem.perBankRdReqs::1 967905 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::2 967771 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::3 967944 # Track reads on a per bank basis |
| 65system.physmem.perBankRdReqs::4 974725 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 968490 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 967840 # Track reads on a per bank basis | 66system.physmem.perBankRdReqs::4 974355 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::5 968114 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::6 967591 # Track reads on a per bank basis 69system.physmem.perBankRdReqs::7 967671 # Track reads on a per bank basis |
| 69system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis 70system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis | 70system.physmem.perBankRdReqs::8 968519 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::9 968300 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::10 967957 # Track reads on a per bank basis |
| 72system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis | 73system.physmem.perBankRdReqs::11 967810 # Track reads on a per bank basis |
| 73system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis | 74system.physmem.perBankRdReqs::12 967935 # Track reads on a per bank basis 75system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis |
| 75system.physmem.perBankRdReqs::14 967887 # Track reads on a per bank basis 76system.physmem.perBankRdReqs::15 967682 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 49150 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 49013 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 50857 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 50909 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 51128 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 51425 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 51159 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 51254 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::8 51364 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::9 51157 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 50876 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 50874 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::14 50827 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::15 50677 # Track writes on a per bank basis | 76system.physmem.perBankRdReqs::14 967816 # Track reads on a per bank basis 77system.physmem.perBankRdReqs::15 967690 # Track reads on a per bank basis 78system.physmem.perBankWrReqs::0 6734 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::1 6600 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::2 6526 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::3 6493 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::4 6702 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::5 6993 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::6 6729 # Track writes on a per bank basis 85system.physmem.perBankWrReqs::7 6823 # Track writes on a per bank basis 86system.physmem.perBankWrReqs::8 7180 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::9 6976 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::10 6694 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::11 6614 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::12 6691 # Track writes on a per bank basis 91system.physmem.perBankWrReqs::13 6338 # Track writes on a per bank basis 92system.physmem.perBankWrReqs::14 6636 # Track writes on a per bank basis 93system.physmem.perBankWrReqs::15 6497 # Track writes on a per bank basis |
| 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 94system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 95system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 95system.physmem.totGap 2615728912000 # Total gap between requests | 96system.physmem.totGap 2615711849000 # Total gap between requests |
| 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 6652 # Categorize read packet sizes 99system.physmem.readPktSize::3 15335424 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes | 97system.physmem.readPktSize::0 0 # Categorize read packet sizes 98system.physmem.readPktSize::1 0 # Categorize read packet sizes 99system.physmem.readPktSize::2 6652 # Categorize read packet sizes 100system.physmem.readPktSize::3 15335424 # Categorize read packet sizes 101system.physmem.readPktSize::4 0 # Categorize read packet sizes 102system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 102system.physmem.readPktSize::6 152694 # Categorize read packet sizes | 103system.physmem.readPktSize::6 152695 # Categorize read packet sizes |
| 103system.physmem.writePktSize::0 0 # Categorize write packet sizes 104system.physmem.writePktSize::1 0 # Categorize write packet sizes 105system.physmem.writePktSize::2 754018 # Categorize write packet sizes 106system.physmem.writePktSize::3 0 # Categorize write packet sizes 107system.physmem.writePktSize::4 0 # Categorize write packet sizes 108system.physmem.writePktSize::5 0 # Categorize write packet sizes 109system.physmem.writePktSize::6 57971 # Categorize write packet sizes | 104system.physmem.writePktSize::0 0 # Categorize write packet sizes 105system.physmem.writePktSize::1 0 # Categorize write packet sizes 106system.physmem.writePktSize::2 754018 # Categorize write packet sizes 107system.physmem.writePktSize::3 0 # Categorize write packet sizes 108system.physmem.writePktSize::4 0 # Categorize write packet sizes 109system.physmem.writePktSize::5 0 # Categorize write packet sizes 110system.physmem.writePktSize::6 57971 # Categorize write packet sizes |
| 110system.physmem.rdQLenPdf::0 1128832 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 975833 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 1007328 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 3775576 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2827750 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2822812 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 2787859 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 21456 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 18919 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 32464 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 45819 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 32079 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 4562 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 4458 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 4371 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 4308 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 45 # What read queue length does an incoming req see | 111system.physmem.rdQLenPdf::0 1137574 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::1 984079 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::2 1018155 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::3 3783404 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::4 2827794 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::5 2821787 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::6 2781992 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::7 18262 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::8 15752 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::9 29208 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::10 42299 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::11 28515 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::12 1143 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::13 1054 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::14 1034 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::15 1015 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::16 48 # What read queue length does an incoming req see |
| 127system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 128system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 142system.physmem.wrQLenPdf::0 35288 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 35301 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 35304 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 35304 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 35304 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::8 35304 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 35304 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 35304 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::16 35304 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 35304 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::18 35304 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 35304 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::0 4662 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::1 4662 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::2 4662 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::3 4662 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::4 4662 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::5 4662 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::6 4662 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::7 4662 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::8 4662 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::9 4662 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::10 4662 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::11 4662 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::12 4662 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::13 4662 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::14 4662 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::15 4662 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::16 4662 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::17 4662 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::18 4662 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::19 4662 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::20 4662 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::21 4662 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::22 4662 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see |
| 168system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 174system.physmem.bytesPerActivate::samples 38488 # Bytes accessed per row activation 175system.physmem.bytesPerActivate::mean 27115.229266 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::gmean 2500.122459 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::stdev 33119.773163 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::64-127 5498 14.28% 14.28% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::128-191 3288 8.54% 22.83% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::192-255 2221 5.77% 28.60% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::256-319 1687 4.38% 32.98% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::320-383 1187 3.08% 36.07% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::384-447 1056 2.74% 38.81% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::448-511 814 2.11% 40.92% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::512-575 739 1.92% 42.84% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::576-639 550 1.43% 44.27% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::640-703 512 1.33% 45.60% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::704-767 421 1.09% 46.70% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::768-831 397 1.03% 47.73% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::832-895 314 0.82% 48.55% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::896-959 250 0.65% 49.19% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::960-1023 198 0.51% 49.71% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1024-1087 236 0.61% 50.32% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1088-1151 133 0.35% 50.67% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1152-1215 138 0.36% 51.03% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1216-1279 98 0.25% 51.28% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1280-1343 109 0.28% 51.56% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1344-1407 78 0.20% 51.77% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1408-1471 154 0.40% 52.17% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1472-1535 969 2.52% 54.68% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1536-1599 195 0.51% 55.19% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1600-1663 143 0.37% 55.56% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1664-1727 120 0.31% 55.87% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1728-1791 89 0.23% 56.11% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1792-1855 73 0.19% 56.30% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1856-1919 63 0.16% 56.46% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1920-1983 55 0.14% 56.60% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.73% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2048-2111 51 0.13% 56.87% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.95% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2176-2239 29 0.08% 57.02% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2240-2303 27 0.07% 57.09% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2304-2367 16 0.04% 57.13% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.18% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2432-2495 16 0.04% 57.22% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2496-2559 22 0.06% 57.28% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.31% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2624-2687 16 0.04% 57.35% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2688-2751 9 0.02% 57.37% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2752-2815 14 0.04% 57.41% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2816-2879 16 0.04% 57.45% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2880-2943 11 0.03% 57.48% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.52% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3008-3071 8 0.02% 57.54% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3072-3135 19 0.05% 57.59% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3136-3199 9 0.02% 57.61% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3200-3263 4 0.01% 57.62% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3264-3327 13 0.03% 57.65% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3328-3391 10 0.03% 57.68% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.70% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3456-3519 7 0.02% 57.71% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.72% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.74% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3648-3711 13 0.03% 57.77% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3712-3775 10 0.03% 57.80% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3776-3839 5 0.01% 57.81% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3840-3903 10 0.03% 57.84% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3904-3967 3 0.01% 57.84% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3968-4031 7 0.02% 57.86% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::4032-4095 8 0.02% 57.88% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4096-4159 40 0.10% 57.99% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4160-4223 2 0.01% 57.99% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.00% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.01% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4352-4415 6 0.02% 58.03% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4416-4479 4 0.01% 58.04% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4480-4543 3 0.01% 58.04% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.06% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4608-4671 6 0.02% 58.07% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.08% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.08% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.09% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4864-4927 9 0.02% 58.11% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4928-4991 2 0.01% 58.11% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.12% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.13% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5120-5183 9 0.02% 58.15% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5184-5247 2 0.01% 58.16% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.17% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5312-5375 4 0.01% 58.18% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5376-5439 3 0.01% 58.19% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5440-5503 5 0.01% 58.20% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5504-5567 4 0.01% 58.21% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5568-5631 4 0.01% 58.22% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5632-5695 6 0.02% 58.24% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.24% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5888-5951 4 0.01% 58.25% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5952-6015 1 0.00% 58.25% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.26% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6080-6143 1 0.00% 58.26% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6144-6207 184 0.48% 58.74% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6208-6271 2 0.01% 58.75% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.75% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6400-6463 2 0.01% 58.75% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6464-6527 3 0.01% 58.76% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6528-6591 4 0.01% 58.77% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.77% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.78% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.78% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.82% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.83% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.83% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.84% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7040-7103 3 0.01% 58.84% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.85% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7232-7295 4 0.01% 58.87% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7296-7359 1 0.00% 58.87% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.87% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.88% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7552-7615 5 0.01% 58.89% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.90% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7680-7743 6 0.02% 58.92% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7744-7807 4 0.01% 58.93% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::7808-7871 4 0.01% 58.94% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::7872-7935 4 0.01% 58.95% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::7936-7999 1 0.00% 58.95% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::8000-8063 1 0.00% 58.95% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::8064-8127 6 0.02% 58.97% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::8128-8191 3 0.01% 58.98% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.83% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.83% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::8576-8639 1 0.00% 59.83% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8704-8767 1 0.00% 59.83% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.84% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::9216-9279 5 0.01% 59.85% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.85% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::9856-9919 1 0.00% 59.86% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::9984-10047 1 0.00% 59.86% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::10112-10175 2 0.01% 59.86% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::10240-10303 20 0.05% 59.91% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::10624-10687 1 0.00% 59.92% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::11008-11071 1 0.00% 59.92% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::12032-12095 1 0.00% 59.92% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::12288-12351 2 0.01% 59.93% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::12544-12607 1 0.00% 59.93% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::12672-12735 1 0.00% 59.93% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::12800-12863 1 0.00% 59.94% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::13056-13119 1 0.00% 59.94% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::13696-13759 1 0.00% 59.94% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::13824-13887 1 0.00% 59.94% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::14080-14143 2 0.01% 59.95% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::14336-14399 3 0.01% 59.96% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::15360-15423 4 0.01% 59.97% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::15616-15679 1 0.00% 59.97% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::15680-15743 1 0.00% 59.97% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::16128-16191 1 0.00% 59.97% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::16384-16447 1 0.00% 59.98% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::17024-17087 1 0.00% 59.98% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::17152-17215 3 0.01% 59.99% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::17920-17983 1 0.00% 59.99% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::18048-18111 1 0.00% 59.99% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.00% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::18304-18367 1 0.00% 60.00% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::18432-18495 3 0.01% 60.01% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::18688-18751 1 0.00% 60.01% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.01% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::19456-19519 1 0.00% 60.01% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::19712-19775 2 0.01% 60.02% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.02% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::20096-20159 1 0.00% 60.02% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::20288-20351 1 0.00% 60.03% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.03% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.03% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.03% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.04% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.04% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::22016-22079 1 0.00% 60.04% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::22272-22335 2 0.01% 60.05% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::22400-22463 1 0.00% 60.05% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::22528-22591 3 0.01% 60.06% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::23040-23103 2 0.01% 60.06% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.07% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::23424-23487 1 0.00% 60.07% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::23552-23615 2 0.01% 60.07% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.08% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.08% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::24576-24639 2 0.01% 60.08% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::24832-24895 2 0.01% 60.09% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::25088-25151 2 0.01% 60.09% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::25216-25279 1 0.00% 60.10% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::25344-25407 2 0.01% 60.10% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.10% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::25664-25727 1 0.00% 60.11% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::25792-25855 1 0.00% 60.11% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::26112-26175 1 0.00% 60.11% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::26240-26303 1 0.00% 60.11% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::26368-26431 2 0.01% 60.12% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.12% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.13% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::27392-27455 1 0.00% 60.13% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::27648-27711 3 0.01% 60.14% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.14% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::28928-28991 2 0.01% 60.15% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::29184-29247 1 0.00% 60.15% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::29312-29375 1 0.00% 60.15% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.16% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::29632-29695 1 0.00% 60.16% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::29696-29759 2 0.01% 60.16% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::30272-30335 1 0.00% 60.17% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::30464-30527 1 0.00% 60.17% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::30720-30783 4 0.01% 60.18% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::30848-30911 1 0.00% 60.18% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::31424-31487 1 0.00% 60.18% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::31488-31551 1 0.00% 60.19% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::31744-31807 3 0.01% 60.20% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.20% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::32512-32575 1 0.00% 60.20% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.21% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.25% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::33088-33151 1 0.00% 60.25% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::33152-33215 24 0.06% 60.31% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::33280-33343 16 0.04% 60.35% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::33792-33855 1 0.00% 60.36% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.36% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::35072-35135 1 0.00% 60.36% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.36% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.37% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::39168-39231 1 0.00% 60.37% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::39424-39487 1 0.00% 60.37% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::40704-40767 1 0.00% 60.37% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::40960-41023 1 0.00% 60.38% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::41984-42047 2 0.01% 60.38% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::42496-42559 1 0.00% 60.39% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::42752-42815 1 0.00% 60.39% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.39% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.39% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::44032-44095 1 0.00% 60.40% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::44992-45055 1 0.00% 60.40% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::47104-47167 2 0.01% 60.40% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::47616-47679 1 0.00% 60.41% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.41% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::49152-49215 1 0.00% 60.41% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::49920-49983 1 0.00% 60.41% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.42% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::50432-50495 1 0.00% 60.42% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.42% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::51456-51519 1 0.00% 60.43% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::52736-52799 1 0.00% 60.43% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::54272-54335 1 0.00% 60.43% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::55296-55359 1 0.00% 60.43% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::56320-56383 2 0.01% 60.44% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.44% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::62464-62527 1 0.00% 60.44% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::64000-64063 1 0.00% 60.45% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::64768-64831 1 0.00% 60.45% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.50% # Bytes accessed per row activation 427system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.51% # Bytes accessed per row activation 428system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.52% # Bytes accessed per row activation 429system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.54% # Bytes accessed per row activation 430system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.55% # Bytes accessed per row activation 431system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.59% # Bytes accessed per row activation 432system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.60% # Bytes accessed per row activation 433system.physmem.bytesPerActivate::65536-65599 14794 38.44% 99.04% # Bytes accessed per row activation 434system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.04% # Bytes accessed per row activation 435system.physmem.bytesPerActivate::76928-76991 1 0.00% 99.05% # Bytes accessed per row activation 436system.physmem.bytesPerActivate::81536-81599 1 0.00% 99.05% # Bytes accessed per row activation 437system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation 438system.physmem.bytesPerActivate::95680-95743 1 0.00% 99.05% # Bytes accessed per row activation 439system.physmem.bytesPerActivate::96064-96127 1 0.00% 99.06% # Bytes accessed per row activation 440system.physmem.bytesPerActivate::98880-98943 1 0.00% 99.06% # Bytes accessed per row activation 441system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation 442system.physmem.bytesPerActivate::103488-103551 1 0.00% 99.06% # Bytes accessed per row activation 443system.physmem.bytesPerActivate::106240-106303 1 0.00% 99.07% # Bytes accessed per row activation 444system.physmem.bytesPerActivate::106624-106687 1 0.00% 99.07% # Bytes accessed per row activation 445system.physmem.bytesPerActivate::109440-109503 1 0.00% 99.07% # Bytes accessed per row activation 446system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation 447system.physmem.bytesPerActivate::111232-111295 1 0.00% 99.08% # Bytes accessed per row activation 448system.physmem.bytesPerActivate::114048-114111 1 0.00% 99.08% # Bytes accessed per row activation 449system.physmem.bytesPerActivate::117184-117247 1 0.00% 99.08% # Bytes accessed per row activation 450system.physmem.bytesPerActivate::118272-118335 1 0.00% 99.09% # Bytes accessed per row activation 451system.physmem.bytesPerActivate::120000-120063 1 0.00% 99.09% # Bytes accessed per row activation 452system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation 453system.physmem.bytesPerActivate::121792-121855 1 0.00% 99.09% # Bytes accessed per row activation 454system.physmem.bytesPerActivate::124608-124671 1 0.00% 99.10% # Bytes accessed per row activation 455system.physmem.bytesPerActivate::125696-125759 1 0.00% 99.10% # Bytes accessed per row activation 456system.physmem.bytesPerActivate::128832-128895 1 0.00% 99.10% # Bytes accessed per row activation 457system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.10% # Bytes accessed per row activation 458system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation 459system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation 460system.physmem.bytesPerActivate::130560-130623 1 0.00% 99.11% # Bytes accessed per row activation 461system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.11% # Bytes accessed per row activation 462system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation 463system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation 464system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation 465system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation 466system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation 467system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation 468system.physmem.bytesPerActivate::156992-157055 1 0.00% 99.99% # Bytes accessed per row activation 469system.physmem.bytesPerActivate::193280-193343 1 0.00% 99.99% # Bytes accessed per row activation 470system.physmem.bytesPerActivate::196096-196159 1 0.00% 99.99% # Bytes accessed per row activation 471system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation | 175system.physmem.bytesPerActivate::samples 38068 # Bytes accessed per row activation 176system.physmem.bytesPerActivate::mean 26227.310287 # Bytes accessed per row activation 177system.physmem.bytesPerActivate::gmean 2428.378300 # Bytes accessed per row activation 178system.physmem.bytesPerActivate::stdev 31656.989485 # Bytes accessed per row activation 179system.physmem.bytesPerActivate::64-127 5540 14.55% 14.55% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::128-191 3323 8.73% 23.28% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::192-255 2175 5.71% 29.00% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::256-319 1668 4.38% 33.38% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::320-383 1160 3.05% 36.42% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::384-447 1060 2.78% 39.21% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::448-511 828 2.18% 41.38% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::512-575 781 2.05% 43.44% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::576-639 514 1.35% 44.79% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::640-703 493 1.30% 46.08% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::704-767 417 1.10% 47.18% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::768-831 450 1.18% 48.36% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::832-895 283 0.74% 49.10% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::896-959 279 0.73% 49.83% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::960-1023 185 0.49% 50.32% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1024-1087 195 0.51% 50.83% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1088-1151 134 0.35% 51.18% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1152-1215 139 0.37% 51.55% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1216-1279 114 0.30% 51.85% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1280-1343 94 0.25% 52.10% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::1344-1407 76 0.20% 52.30% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1408-1471 150 0.39% 52.69% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1472-1535 792 2.08% 54.77% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.30% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::1600-1663 136 0.36% 55.66% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1664-1727 113 0.30% 55.96% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.20% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1792-1855 85 0.22% 56.42% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::1856-1919 60 0.16% 56.58% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1920-1983 34 0.09% 56.67% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1984-2047 44 0.12% 56.78% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2048-2111 48 0.13% 56.91% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2112-2175 31 0.08% 56.99% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2176-2239 35 0.09% 57.08% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::2240-2303 24 0.06% 57.15% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::2304-2367 25 0.07% 57.21% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::2368-2431 18 0.05% 57.26% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::2432-2495 18 0.05% 57.31% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::2496-2559 21 0.06% 57.36% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::2560-2623 13 0.03% 57.39% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::2624-2687 5 0.01% 57.41% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::2688-2751 11 0.03% 57.44% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::2752-2815 8 0.02% 57.46% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::2816-2879 15 0.04% 57.50% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::2880-2943 17 0.04% 57.54% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::2944-3007 7 0.02% 57.56% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.58% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3072-3135 18 0.05% 57.63% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3136-3199 8 0.02% 57.65% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.67% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::3264-3327 10 0.03% 57.69% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::3328-3391 16 0.04% 57.74% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::3392-3455 6 0.02% 57.75% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::3456-3519 11 0.03% 57.78% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::3520-3583 6 0.02% 57.80% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::3584-3647 5 0.01% 57.81% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::3648-3711 5 0.01% 57.82% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::3712-3775 7 0.02% 57.84% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::3776-3839 6 0.02% 57.86% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::3840-3903 6 0.02% 57.87% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::3904-3967 6 0.02% 57.89% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::3968-4031 9 0.02% 57.91% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.94% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4096-4159 42 0.11% 58.05% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4160-4223 2 0.01% 58.05% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::4224-4287 4 0.01% 58.06% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::4288-4351 4 0.01% 58.07% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::4352-4415 8 0.02% 58.09% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.11% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::4480-4543 4 0.01% 58.12% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.13% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::4608-4671 5 0.01% 58.15% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::4672-4735 6 0.02% 58.16% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::4736-4799 2 0.01% 58.17% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::4800-4863 1 0.00% 58.17% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::4864-4927 6 0.02% 58.19% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::4928-4991 1 0.00% 58.19% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::4992-5055 3 0.01% 58.20% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5056-5119 2 0.01% 58.20% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::5120-5183 10 0.03% 58.23% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::5248-5311 2 0.01% 58.24% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::5312-5375 5 0.01% 58.25% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::5440-5503 2 0.01% 58.27% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::5504-5567 3 0.01% 58.27% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::5568-5631 3 0.01% 58.28% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::5696-5759 2 0.01% 58.29% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::5760-5823 3 0.01% 58.30% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::5888-5951 1 0.00% 58.30% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::5952-6015 2 0.01% 58.30% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.31% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6144-6207 2 0.01% 58.31% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6272-6335 2 0.01% 58.32% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::6336-6399 1 0.00% 58.32% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::6464-6527 4 0.01% 58.33% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::6528-6591 1 0.00% 58.34% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.34% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::6656-6719 1 0.00% 58.34% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::6720-6783 6 0.02% 58.36% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::6784-6847 16 0.04% 58.40% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::6848-6911 4 0.01% 58.41% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::6976-7039 4 0.01% 58.42% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7040-7103 4 0.01% 58.43% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7104-7167 1 0.00% 58.43% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.44% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7232-7295 2 0.01% 58.45% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::7360-7423 2 0.01% 58.45% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::7424-7487 3 0.01% 58.46% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::7488-7551 2 0.01% 58.47% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.47% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::7616-7679 4 0.01% 58.48% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::7680-7743 5 0.01% 58.50% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::7744-7807 2 0.01% 58.50% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::7808-7871 1 0.00% 58.51% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::7872-7935 6 0.02% 58.52% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::7936-7999 7 0.02% 58.54% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::8000-8063 6 0.02% 58.56% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::8064-8127 8 0.02% 58.58% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::8128-8191 8 0.02% 58.60% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::8192-8255 328 0.86% 59.46% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::8256-8319 1 0.00% 59.46% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::8448-8511 24 0.06% 59.53% # Bytes accessed per row activation 302system.physmem.bytesPerActivate::8512-8575 141 0.37% 59.90% # Bytes accessed per row activation 303system.physmem.bytesPerActivate::8576-8639 169 0.44% 60.34% # Bytes accessed per row activation 304system.physmem.bytesPerActivate::8704-8767 1 0.00% 60.34% # Bytes accessed per row activation 305system.physmem.bytesPerActivate::8768-8831 1 0.00% 60.34% # Bytes accessed per row activation 306system.physmem.bytesPerActivate::8832-8895 2 0.01% 60.35% # Bytes accessed per row activation 307system.physmem.bytesPerActivate::8960-9023 3 0.01% 60.36% # Bytes accessed per row activation 308system.physmem.bytesPerActivate::9216-9279 3 0.01% 60.37% # Bytes accessed per row activation 309system.physmem.bytesPerActivate::9472-9535 1 0.00% 60.37% # Bytes accessed per row activation 310system.physmem.bytesPerActivate::10240-10303 4 0.01% 60.38% # Bytes accessed per row activation 311system.physmem.bytesPerActivate::11520-11583 1 0.00% 60.38% # Bytes accessed per row activation 312system.physmem.bytesPerActivate::11904-11967 1 0.00% 60.38% # Bytes accessed per row activation 313system.physmem.bytesPerActivate::12032-12095 2 0.01% 60.39% # Bytes accessed per row activation 314system.physmem.bytesPerActivate::12928-12991 1 0.00% 60.39% # Bytes accessed per row activation 315system.physmem.bytesPerActivate::13056-13119 4 0.01% 60.40% # Bytes accessed per row activation 316system.physmem.bytesPerActivate::13184-13247 1 0.00% 60.41% # Bytes accessed per row activation 317system.physmem.bytesPerActivate::13312-13375 1 0.00% 60.41% # Bytes accessed per row activation 318system.physmem.bytesPerActivate::13824-13887 1 0.00% 60.41% # Bytes accessed per row activation 319system.physmem.bytesPerActivate::13952-14015 1 0.00% 60.41% # Bytes accessed per row activation 320system.physmem.bytesPerActivate::14336-14399 4 0.01% 60.42% # Bytes accessed per row activation 321system.physmem.bytesPerActivate::14592-14655 1 0.00% 60.43% # Bytes accessed per row activation 322system.physmem.bytesPerActivate::14976-15039 1 0.00% 60.43% # Bytes accessed per row activation 323system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.43% # Bytes accessed per row activation 324system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.44% # Bytes accessed per row activation 325system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.44% # Bytes accessed per row activation 326system.physmem.bytesPerActivate::16640-16703 1 0.00% 60.44% # Bytes accessed per row activation 327system.physmem.bytesPerActivate::17152-17215 1 0.00% 60.44% # Bytes accessed per row activation 328system.physmem.bytesPerActivate::17408-17471 3 0.01% 60.45% # Bytes accessed per row activation 329system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.45% # Bytes accessed per row activation 330system.physmem.bytesPerActivate::18176-18239 2 0.01% 60.46% # Bytes accessed per row activation 331system.physmem.bytesPerActivate::18432-18495 5 0.01% 60.47% # Bytes accessed per row activation 332system.physmem.bytesPerActivate::18624-18687 1 0.00% 60.48% # Bytes accessed per row activation 333system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.48% # Bytes accessed per row activation 334system.physmem.bytesPerActivate::19328-19391 1 0.00% 60.48% # Bytes accessed per row activation 335system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.49% # Bytes accessed per row activation 336system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.49% # Bytes accessed per row activation 337system.physmem.bytesPerActivate::20352-20415 1 0.00% 60.49% # Bytes accessed per row activation 338system.physmem.bytesPerActivate::20480-20543 1 0.00% 60.50% # Bytes accessed per row activation 339system.physmem.bytesPerActivate::21760-21823 1 0.00% 60.50% # Bytes accessed per row activation 340system.physmem.bytesPerActivate::22016-22079 2 0.01% 60.50% # Bytes accessed per row activation 341system.physmem.bytesPerActivate::22144-22207 1 0.00% 60.51% # Bytes accessed per row activation 342system.physmem.bytesPerActivate::22272-22335 1 0.00% 60.51% # Bytes accessed per row activation 343system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.51% # Bytes accessed per row activation 344system.physmem.bytesPerActivate::23040-23103 1 0.00% 60.52% # Bytes accessed per row activation 345system.physmem.bytesPerActivate::23168-23231 1 0.00% 60.52% # Bytes accessed per row activation 346system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.52% # Bytes accessed per row activation 347system.physmem.bytesPerActivate::23552-23615 4 0.01% 60.53% # Bytes accessed per row activation 348system.physmem.bytesPerActivate::24064-24127 1 0.00% 60.53% # Bytes accessed per row activation 349system.physmem.bytesPerActivate::24192-24255 1 0.00% 60.54% # Bytes accessed per row activation 350system.physmem.bytesPerActivate::24320-24383 3 0.01% 60.54% # Bytes accessed per row activation 351system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.55% # Bytes accessed per row activation 352system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.55% # Bytes accessed per row activation 353system.physmem.bytesPerActivate::25088-25151 1 0.00% 60.55% # Bytes accessed per row activation 354system.physmem.bytesPerActivate::25344-25407 1 0.00% 60.55% # Bytes accessed per row activation 355system.physmem.bytesPerActivate::25600-25663 1 0.00% 60.56% # Bytes accessed per row activation 356system.physmem.bytesPerActivate::25728-25791 1 0.00% 60.56% # Bytes accessed per row activation 357system.physmem.bytesPerActivate::26624-26687 1 0.00% 60.56% # Bytes accessed per row activation 358system.physmem.bytesPerActivate::26880-26943 2 0.01% 60.57% # Bytes accessed per row activation 359system.physmem.bytesPerActivate::27392-27455 2 0.01% 60.57% # Bytes accessed per row activation 360system.physmem.bytesPerActivate::27648-27711 4 0.01% 60.58% # Bytes accessed per row activation 361system.physmem.bytesPerActivate::28160-28223 2 0.01% 60.59% # Bytes accessed per row activation 362system.physmem.bytesPerActivate::28416-28479 1 0.00% 60.59% # Bytes accessed per row activation 363system.physmem.bytesPerActivate::28672-28735 2 0.01% 60.60% # Bytes accessed per row activation 364system.physmem.bytesPerActivate::28800-28863 1 0.00% 60.60% # Bytes accessed per row activation 365system.physmem.bytesPerActivate::29184-29247 3 0.01% 60.61% # Bytes accessed per row activation 366system.physmem.bytesPerActivate::29440-29503 1 0.00% 60.61% # Bytes accessed per row activation 367system.physmem.bytesPerActivate::29696-29759 3 0.01% 60.62% # Bytes accessed per row activation 368system.physmem.bytesPerActivate::29952-30015 1 0.00% 60.62% # Bytes accessed per row activation 369system.physmem.bytesPerActivate::30208-30271 1 0.00% 60.62% # Bytes accessed per row activation 370system.physmem.bytesPerActivate::30336-30399 1 0.00% 60.63% # Bytes accessed per row activation 371system.physmem.bytesPerActivate::30720-30783 1 0.00% 60.63% # Bytes accessed per row activation 372system.physmem.bytesPerActivate::30976-31039 1 0.00% 60.63% # Bytes accessed per row activation 373system.physmem.bytesPerActivate::31104-31167 1 0.00% 60.63% # Bytes accessed per row activation 374system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.64% # Bytes accessed per row activation 375system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.64% # Bytes accessed per row activation 376system.physmem.bytesPerActivate::31360-31423 1 0.00% 60.64% # Bytes accessed per row activation 377system.physmem.bytesPerActivate::31488-31551 2 0.01% 60.65% # Bytes accessed per row activation 378system.physmem.bytesPerActivate::31680-31743 1 0.00% 60.65% # Bytes accessed per row activation 379system.physmem.bytesPerActivate::31744-31807 6 0.02% 60.67% # Bytes accessed per row activation 380system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.67% # Bytes accessed per row activation 381system.physmem.bytesPerActivate::32256-32319 1 0.00% 60.67% # Bytes accessed per row activation 382system.physmem.bytesPerActivate::33024-33087 16 0.04% 60.72% # Bytes accessed per row activation 383system.physmem.bytesPerActivate::33152-33215 19 0.05% 60.76% # Bytes accessed per row activation 384system.physmem.bytesPerActivate::33280-33343 23 0.06% 60.83% # Bytes accessed per row activation 385system.physmem.bytesPerActivate::33536-33599 1 0.00% 60.83% # Bytes accessed per row activation 386system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.83% # Bytes accessed per row activation 387system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.83% # Bytes accessed per row activation 388system.physmem.bytesPerActivate::36352-36415 2 0.01% 60.84% # Bytes accessed per row activation 389system.physmem.bytesPerActivate::36864-36927 1 0.00% 60.84% # Bytes accessed per row activation 390system.physmem.bytesPerActivate::37888-37951 1 0.00% 60.84% # Bytes accessed per row activation 391system.physmem.bytesPerActivate::40192-40255 1 0.00% 60.85% # Bytes accessed per row activation 392system.physmem.bytesPerActivate::41216-41279 2 0.01% 60.85% # Bytes accessed per row activation 393system.physmem.bytesPerActivate::41728-41791 1 0.00% 60.85% # Bytes accessed per row activation 394system.physmem.bytesPerActivate::41984-42047 1 0.00% 60.86% # Bytes accessed per row activation 395system.physmem.bytesPerActivate::43264-43327 1 0.00% 60.86% # Bytes accessed per row activation 396system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.86% # Bytes accessed per row activation 397system.physmem.bytesPerActivate::46336-46399 1 0.00% 60.86% # Bytes accessed per row activation 398system.physmem.bytesPerActivate::46528-46591 1 0.00% 60.87% # Bytes accessed per row activation 399system.physmem.bytesPerActivate::47104-47167 3 0.01% 60.88% # Bytes accessed per row activation 400system.physmem.bytesPerActivate::47872-47935 1 0.00% 60.88% # Bytes accessed per row activation 401system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.88% # Bytes accessed per row activation 402system.physmem.bytesPerActivate::48384-48447 1 0.00% 60.88% # Bytes accessed per row activation 403system.physmem.bytesPerActivate::48896-48959 1 0.00% 60.89% # Bytes accessed per row activation 404system.physmem.bytesPerActivate::49664-49727 1 0.00% 60.89% # Bytes accessed per row activation 405system.physmem.bytesPerActivate::51200-51263 2 0.01% 60.89% # Bytes accessed per row activation 406system.physmem.bytesPerActivate::52224-52287 2 0.01% 60.90% # Bytes accessed per row activation 407system.physmem.bytesPerActivate::56320-56383 1 0.00% 60.90% # Bytes accessed per row activation 408system.physmem.bytesPerActivate::56576-56639 1 0.00% 60.90% # Bytes accessed per row activation 409system.physmem.bytesPerActivate::57344-57407 1 0.00% 60.91% # Bytes accessed per row activation 410system.physmem.bytesPerActivate::57600-57663 1 0.00% 60.91% # Bytes accessed per row activation 411system.physmem.bytesPerActivate::58368-58431 2 0.01% 60.91% # Bytes accessed per row activation 412system.physmem.bytesPerActivate::60416-60479 1 0.00% 60.92% # Bytes accessed per row activation 413system.physmem.bytesPerActivate::60672-60735 1 0.00% 60.92% # Bytes accessed per row activation 414system.physmem.bytesPerActivate::61184-61247 1 0.00% 60.92% # Bytes accessed per row activation 415system.physmem.bytesPerActivate::61696-61759 1 0.00% 60.93% # Bytes accessed per row activation 416system.physmem.bytesPerActivate::63488-63551 1 0.00% 60.93% # Bytes accessed per row activation 417system.physmem.bytesPerActivate::65024-65087 190 0.50% 61.43% # Bytes accessed per row activation 418system.physmem.bytesPerActivate::65088-65151 6 0.02% 61.44% # Bytes accessed per row activation 419system.physmem.bytesPerActivate::65216-65279 6 0.02% 61.46% # Bytes accessed per row activation 420system.physmem.bytesPerActivate::65280-65343 1 0.00% 61.46% # Bytes accessed per row activation 421system.physmem.bytesPerActivate::65472-65535 1 0.00% 61.46% # Bytes accessed per row activation 422system.physmem.bytesPerActivate::65536-65599 14664 38.52% 99.98% # Bytes accessed per row activation 423system.physmem.bytesPerActivate::67392-67455 1 0.00% 99.99% # Bytes accessed per row activation 424system.physmem.bytesPerActivate::69760-69823 1 0.00% 99.99% # Bytes accessed per row activation 425system.physmem.bytesPerActivate::71744-71807 2 0.01% 99.99% # Bytes accessed per row activation 426system.physmem.bytesPerActivate::73984-74047 1 0.00% 100.00% # Bytes accessed per row activation |
| 472system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation | 427system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation |
| 473system.physmem.bytesPerActivate::total 38488 # Bytes accessed per row activation 474system.physmem.totQLat 303199099750 # Total cycles spent in queuing delays 475system.physmem.totMemAccLat 396944112250 # Sum of mem lat for all requests 476system.physmem.totBusLat 77472355000 # Total cycles spent in databus access 477system.physmem.totBankLat 16272657500 # Total cycles spent in bank access 478system.physmem.avgQLat 19568.21 # Average queueing delay per request 479system.physmem.avgBankLat 1050.22 # Average bank access latency per request | 428system.physmem.bytesPerActivate::total 38068 # Bytes accessed per row activation 429system.physmem.totQLat 296768605750 # Total cycles spent in queuing delays 430system.physmem.totMemAccLat 390592239500 # Sum of mem lat for all requests 431system.physmem.totBusLat 77465575000 # Total cycles spent in databus access 432system.physmem.totBankLat 16358058750 # Total cycles spent in bank access 433system.physmem.avgQLat 19154.87 # Average queueing delay per request 434system.physmem.avgBankLat 1055.83 # Average bank access latency per request |
| 480system.physmem.avgBusLat 5000.00 # Average bus latency per request | 435system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 481system.physmem.avgMemAccLat 25618.44 # Average memory access latency | 436system.physmem.avgMemAccLat 25210.70 # Average memory access latency |
| 482system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s 483system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s 484system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s 485system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s 486system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 487system.physmem.busUtil 3.12 # Data bus utilization in percentage 488system.physmem.avgRdQLen 0.15 # Average read queue length over time | 437system.physmem.avgRdBW 379.12 # Average achieved read bandwidth in MB/s 438system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s 439system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s 440system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s 441system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 442system.physmem.busUtil 3.12 # Data bus utilization in percentage 443system.physmem.avgRdQLen 0.15 # Average read queue length over time |
| 489system.physmem.avgWrQLen 10.84 # Average write queue length over time 490system.physmem.readRowHits 15469547 # Number of row buffer hits during reads 491system.physmem.writeRowHits 798405 # Number of row buffer hits during writes | 444system.physmem.avgWrQLen 13.76 # Average write queue length over time 445system.physmem.readRowHits 15468398 # Number of row buffer hits during reads 446system.physmem.writeRowHits 93875 # Number of row buffer hits during writes |
| 492system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads | 447system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads |
| 493system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes 494system.physmem.avgGap 160407.65 # Average gap between requests | 448system.physmem.writeRowHitRate 11.56 # Row buffer hit rate for writes 449system.physmem.avgGap 160406.60 # Average gap between requests |
| 495system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 496system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 497system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 498system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 499system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 500system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 501system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 502system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 503system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 504system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 505system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 506system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) | 450system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 451system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 452system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 453system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 454system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 455system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 456system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 457system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 458system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) 459system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) 460system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) 461system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) |
| 507system.membus.throughput 54136540 # Throughput (bytes/s) 508system.membus.trans_dist::ReadReq 16546595 # Transaction distribution 509system.membus.trans_dist::ReadResp 16546595 # Transaction distribution | 462system.membus.throughput 54136917 # Throughput (bytes/s) 463system.membus.trans_dist::ReadReq 16546596 # Transaction distribution 464system.membus.trans_dist::ReadResp 16546596 # Transaction distribution |
| 510system.membus.trans_dist::WriteReq 763368 # Transaction distribution 511system.membus.trans_dist::WriteResp 763368 # Transaction distribution 512system.membus.trans_dist::Writeback 57971 # Transaction distribution 513system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution 514system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution 515system.membus.trans_dist::ReadExReq 132250 # Transaction distribution 516system.membus.trans_dist::ReadExResp 132250 # Transaction distribution 517system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) 518system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) | 465system.membus.trans_dist::WriteReq 763368 # Transaction distribution 466system.membus.trans_dist::WriteResp 763368 # Transaction distribution 467system.membus.trans_dist::Writeback 57971 # Transaction distribution 468system.membus.trans_dist::UpgradeReq 4515 # Transaction distribution 469system.membus.trans_dist::UpgradeResp 4515 # Transaction distribution 470system.membus.trans_dist::ReadExReq 132250 # Transaction distribution 471system.membus.trans_dist::ReadExResp 132250 # Transaction distribution 472system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) 473system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) |
| 519system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893729 # Packet count per connected master and slave (bytes) | |
| 520system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) 521system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) | 474system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) 475system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) |
| 522system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280579 # Packet count per connected master and slave (bytes) | 476system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893731 # Packet count per connected master and slave (bytes) 477system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280581 # Packet count per connected master and slave (bytes) |
| 523system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 524system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) | 478system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) 479system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) |
| 525system.membus.pkt_count::system.bridge.slave 2382988 # Packet count per connected master and slave (bytes) 526system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 527system.membus.pkt_count::system.physmem.port 32564577 # Packet count per connected master and slave (bytes) 528system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes) 529system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) 530system.membus.pkt_count::total 34951427 # Packet count per connected master and slave (bytes) | 480system.membus.pkt_count::total 34951429 # Packet count per connected master and slave (bytes) |
| 531system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) 532system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) | 481system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) 482system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) |
| 533system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525240 # Cumulative packet size per connected master and slave (bytes) | |
| 534system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) 535system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) | 483system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) 484system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) |
| 536system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923357 # Cumulative packet size per connected master and slave (bytes) | 485system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16525304 # Cumulative packet size per connected master and slave (bytes) 486system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18923421 # Cumulative packet size per connected master and slave (bytes) |
| 537system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 538system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) | 487system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) 488system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) |
| 539system.membus.tot_pkt_size::system.bridge.slave 2390393 # Cumulative packet size per connected master and slave (bytes) 540system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 541system.membus.tot_pkt_size::system.physmem.port 139208632 # Cumulative packet size per connected master and slave (bytes) 542system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes) 543system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) 544system.membus.tot_pkt_size::total 141606749 # Cumulative packet size per connected master and slave (bytes) 545system.membus.data_through_bus 141606749 # Total data (bytes) | 489system.membus.tot_pkt_size::total 141606813 # Cumulative packet size per connected master and slave (bytes) 490system.membus.data_through_bus 141606813 # Total data (bytes) |
| 546system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 491system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 547system.membus.reqLayer0.occupancy 1206151500 # Layer occupancy (ticks) | 492system.membus.reqLayer0.occupancy 1206151000 # Layer occupancy (ticks) |
| 548system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 549system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 550system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) | 493system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 494system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 495system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) |
| 551system.membus.reqLayer2.occupancy 17903854000 # Layer occupancy (ticks) 552system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) 553system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks) 554system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 555system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks) 556system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 557system.membus.respLayer1.occupancy 4944443675 # Layer occupancy (ticks) | 496system.membus.reqLayer2.occupancy 3613000 # Layer occupancy (ticks) 497system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 498system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) 499system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 500system.membus.reqLayer6.occupancy 17904160000 # Layer occupancy (ticks) 501system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) 502system.membus.respLayer1.occupancy 4944878700 # Layer occupancy (ticks) |
| 558system.membus.respLayer1.utilization 0.2 # Layer utilization (%) | 503system.membus.respLayer1.utilization 0.2 # Layer utilization (%) |
| 559system.membus.respLayer2.occupancy 34633310000 # Layer occupancy (ticks) | 504system.membus.respLayer2.occupancy 34615555500 # Layer occupancy (ticks) |
| 560system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 561system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 562system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 563system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 564system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 565system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 566system.cf0.dma_write_txs 0 # Number of DMA write transactions. | 505system.membus.respLayer2.utilization 1.3 # Layer utilization (%) 506system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 507system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 508system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 509system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 510system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 511system.cf0.dma_write_txs 0 # Number of DMA write transactions. |
| 567system.iobus.throughput 47815955 # Throughput (bytes/s) | 512system.iobus.throughput 47816267 # Throughput (bytes/s) |
| 568system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution 569system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution 570system.iobus.trans_dist::WriteReq 8166 # Transaction distribution 571system.iobus.trans_dist::WriteResp 8166 # Transaction distribution 572system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 573system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) 574system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) 575system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 590system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 591system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 592system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 593system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 594system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 595system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) 596system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 597system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) | 513system.iobus.trans_dist::ReadReq 16518752 # Transaction distribution 514system.iobus.trans_dist::ReadResp 16518752 # Transaction distribution 515system.iobus.trans_dist::WriteReq 8166 # Transaction distribution 516system.iobus.trans_dist::WriteResp 8166 # Transaction distribution 517system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 518system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) 519system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) 520system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 535system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 536system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 537system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 538system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 539system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 540system.iobus.pkt_count_system.bridge.master::total 2382988 # Packet count per connected master and slave (bytes) 541system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) 542system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) |
| 598system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes) 599system.iobus.pkt_count::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) 600system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes) 601system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) 602system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) 603system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 604system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes) 605system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) 606system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) 607system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 608system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 609system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 610system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) 611system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) 612system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 613system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) 614system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) 615system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) 616system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) 617system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) 618system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 619system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 620system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 621system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) | |
| 622system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes) 623system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 624system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) 625system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) 626system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) 627system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 628system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 629system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 641system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 642system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 643system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 644system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 645system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 646system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) 647system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 648system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) | 543system.iobus.pkt_count::total 33053836 # Packet count per connected master and slave (bytes) 544system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 545system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) 546system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) 547system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) 548system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 549system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 550system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 562system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 563system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 564system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 565system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 566system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 567system.iobus.tot_pkt_size_system.bridge.master::total 2390393 # Cumulative packet size per connected master and slave (bytes) 568system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) 569system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) |
| 649system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes) 650system.iobus.tot_pkt_size::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) 651system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes) 652system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) 653system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) 654system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 655system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) 656system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) 657system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 658system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 659system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 660system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 661system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 662system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) 663system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 664system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 665system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 666system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 667system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 668system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 669system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 670system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 671system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 672system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) | |
| 673system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes) 674system.iobus.data_through_bus 125073785 # Total data (bytes) 675system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) 676system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 677system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) 678system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 679system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) 680system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) --- 36 unchanged lines hidden (view full) --- 717system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 718system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 719system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 720system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 721system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) 722system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 723system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks) 724system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) | 570system.iobus.tot_pkt_size::total 125073785 # Cumulative packet size per connected master and slave (bytes) 571system.iobus.data_through_bus 125073785 # Total data (bytes) 572system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks) 573system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 574system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) 575system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 576system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks) 577system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) --- 36 unchanged lines hidden (view full) --- 614system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) 615system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 616system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) 617system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 618system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks) 619system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) 620system.iobus.respLayer0.occupancy 2374822000 # Layer occupancy (ticks) 621system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 725system.iobus.respLayer1.occupancy 42022039000 # Layer occupancy (ticks) | 622system.iobus.respLayer1.occupancy 42038784500 # Layer occupancy (ticks) |
| 726system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) 727system.cpu.dtb.inst_hits 0 # ITB inst hits 728system.cpu.dtb.inst_misses 0 # ITB inst misses | 623system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) 624system.cpu.dtb.inst_hits 0 # ITB inst hits 625system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 729system.cpu.dtb.read_hits 14996132 # DTB read hits 730system.cpu.dtb.read_misses 7340 # DTB read misses 731system.cpu.dtb.write_hits 11230462 # DTB write hits 732system.cpu.dtb.write_misses 2218 # DTB write misses | 626system.cpu.dtb.read_hits 14996146 # DTB read hits 627system.cpu.dtb.read_misses 7341 # DTB read misses 628system.cpu.dtb.write_hits 11230467 # DTB write hits 629system.cpu.dtb.write_misses 2217 # DTB write misses |
| 733system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 734system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 735system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 736system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 737system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB 738system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions | 630system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 631system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 632system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 633system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 634system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB 635system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| 739system.cpu.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch | 636system.cpu.dtb.prefetch_faults 197 # Number of TLB faults due to prefetch |
| 740system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 741system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions | 637system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 638system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions |
| 742system.cpu.dtb.read_accesses 15003472 # DTB read accesses 743system.cpu.dtb.write_accesses 11232680 # DTB write accesses | 639system.cpu.dtb.read_accesses 15003487 # DTB read accesses 640system.cpu.dtb.write_accesses 11232684 # DTB write accesses |
| 744system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 641system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 745system.cpu.dtb.hits 26226594 # DTB hits | 642system.cpu.dtb.hits 26226613 # DTB hits |
| 746system.cpu.dtb.misses 9558 # DTB misses | 643system.cpu.dtb.misses 9558 # DTB misses |
| 747system.cpu.dtb.accesses 26236152 # DTB accesses 748system.cpu.itb.inst_hits 61492700 # ITB inst hits | 644system.cpu.dtb.accesses 26236171 # DTB accesses 645system.cpu.itb.inst_hits 61492923 # ITB inst hits |
| 749system.cpu.itb.inst_misses 4471 # ITB inst misses 750system.cpu.itb.read_hits 0 # DTB read hits 751system.cpu.itb.read_misses 0 # DTB read misses 752system.cpu.itb.write_hits 0 # DTB write hits 753system.cpu.itb.write_misses 0 # DTB write misses 754system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 755system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 756system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 757system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 758system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 759system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 760system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 761system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 762system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 763system.cpu.itb.read_accesses 0 # DTB read accesses 764system.cpu.itb.write_accesses 0 # DTB write accesses | 646system.cpu.itb.inst_misses 4471 # ITB inst misses 647system.cpu.itb.read_hits 0 # DTB read hits 648system.cpu.itb.read_misses 0 # DTB read misses 649system.cpu.itb.write_hits 0 # DTB write hits 650system.cpu.itb.write_misses 0 # DTB write misses 651system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 652system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 653system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 654system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 655system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 656system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 657system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 658system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 659system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 660system.cpu.itb.read_accesses 0 # DTB read accesses 661system.cpu.itb.write_accesses 0 # DTB write accesses |
| 765system.cpu.itb.inst_accesses 61497171 # ITB inst accesses 766system.cpu.itb.hits 61492700 # DTB hits | 662system.cpu.itb.inst_accesses 61497394 # ITB inst accesses 663system.cpu.itb.hits 61492923 # DTB hits |
| 767system.cpu.itb.misses 4471 # DTB misses | 664system.cpu.itb.misses 4471 # DTB misses |
| 768system.cpu.itb.accesses 61497171 # DTB accesses 769system.cpu.numCycles 5231466570 # number of cpu cycles simulated | 665system.cpu.itb.accesses 61497394 # DTB accesses 666system.cpu.numCycles 5231432444 # number of cpu cycles simulated |
| 770system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 771system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 667system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 668system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 772system.cpu.committedInsts 60198861 # Number of instructions committed 773system.cpu.committedOps 76605713 # Number of ops (including micro ops) committed 774system.cpu.num_int_alu_accesses 68872503 # Number of integer alu accesses | 669system.cpu.committedInsts 60199078 # Number of instructions committed 670system.cpu.committedOps 76605946 # Number of ops (including micro ops) committed 671system.cpu.num_int_alu_accesses 68872726 # Number of integer alu accesses |
| 775system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses | 672system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses |
| 776system.cpu.num_func_calls 2140458 # number of times a function call or return occured 777system.cpu.num_conditional_control_insts 7948408 # number of instructions that are conditional controls 778system.cpu.num_int_insts 68872503 # number of integer instructions | 673system.cpu.num_func_calls 2140465 # number of times a function call or return occured 674system.cpu.num_conditional_control_insts 7948429 # number of instructions that are conditional controls 675system.cpu.num_int_insts 68872726 # number of integer instructions |
| 779system.cpu.num_fp_insts 10269 # number of float instructions | 676system.cpu.num_fp_insts 10269 # number of float instructions |
| 780system.cpu.num_int_register_reads 394778081 # number of times the integer registers were read 781system.cpu.num_int_register_writes 74182147 # number of times the integer registers were written | 677system.cpu.num_int_register_reads 394779183 # number of times the integer registers were read 678system.cpu.num_int_register_writes 74182470 # number of times the integer registers were written |
| 782system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 783system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written | 679system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 680system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written |
| 784system.cpu.num_mem_refs 27394052 # number of memory refs 785system.cpu.num_load_insts 15660178 # Number of load instructions 786system.cpu.num_store_insts 11733874 # Number of store instructions 787system.cpu.num_idle_cycles 4581968820.612248 # Number of idle cycles 788system.cpu.num_busy_cycles 649497749.387752 # Number of busy cycles 789system.cpu.not_idle_fraction 0.124152 # Percentage of non-idle cycles 790system.cpu.idle_fraction 0.875848 # Percentage of idle cycles | 681system.cpu.num_mem_refs 27394080 # number of memory refs 682system.cpu.num_load_insts 15660200 # Number of load instructions 683system.cpu.num_store_insts 11733880 # Number of store instructions 684system.cpu.num_idle_cycles 4581975478.612248 # Number of idle cycles 685system.cpu.num_busy_cycles 649456965.387752 # Number of busy cycles 686system.cpu.not_idle_fraction 0.124145 # Percentage of non-idle cycles 687system.cpu.idle_fraction 0.875855 # Percentage of idle cycles |
| 791system.cpu.kern.inst.arm 0 # number of arm instructions executed 792system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed | 688system.cpu.kern.inst.arm 0 # number of arm instructions executed 689system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed |
| 793system.cpu.icache.tags.replacements 856294 # number of replacements 794system.cpu.icache.tags.tagsinuse 510.881133 # Cycle average of tags in use 795system.cpu.icache.tags.total_refs 60635894 # Total number of references to valid blocks. 796system.cpu.icache.tags.sampled_refs 856806 # Sample count of references to valid blocks. 797system.cpu.icache.tags.avg_refs 70.769689 # Average number of references to valid blocks. 798system.cpu.icache.tags.warmup_cycle 19815360250 # Cycle when the warmup percentage was hit. 799system.cpu.icache.tags.occ_blocks::cpu.inst 510.881133 # Average occupied blocks per requestor 800system.cpu.icache.tags.occ_percent::cpu.inst 0.997815 # Average percentage of cache occupancy 801system.cpu.icache.tags.occ_percent::total 0.997815 # Average percentage of cache occupancy 802system.cpu.icache.ReadReq_hits::cpu.inst 60635894 # number of ReadReq hits 803system.cpu.icache.ReadReq_hits::total 60635894 # number of ReadReq hits 804system.cpu.icache.demand_hits::cpu.inst 60635894 # number of demand (read+write) hits 805system.cpu.icache.demand_hits::total 60635894 # number of demand (read+write) hits 806system.cpu.icache.overall_hits::cpu.inst 60635894 # number of overall hits 807system.cpu.icache.overall_hits::total 60635894 # number of overall hits 808system.cpu.icache.ReadReq_misses::cpu.inst 856806 # number of ReadReq misses 809system.cpu.icache.ReadReq_misses::total 856806 # number of ReadReq misses 810system.cpu.icache.demand_misses::cpu.inst 856806 # number of demand (read+write) misses 811system.cpu.icache.demand_misses::total 856806 # number of demand (read+write) misses 812system.cpu.icache.overall_misses::cpu.inst 856806 # number of overall misses 813system.cpu.icache.overall_misses::total 856806 # number of overall misses 814system.cpu.icache.ReadReq_miss_latency::cpu.inst 11768628750 # number of ReadReq miss cycles 815system.cpu.icache.ReadReq_miss_latency::total 11768628750 # number of ReadReq miss cycles 816system.cpu.icache.demand_miss_latency::cpu.inst 11768628750 # number of demand (read+write) miss cycles 817system.cpu.icache.demand_miss_latency::total 11768628750 # number of demand (read+write) miss cycles 818system.cpu.icache.overall_miss_latency::cpu.inst 11768628750 # number of overall miss cycles 819system.cpu.icache.overall_miss_latency::total 11768628750 # number of overall miss cycles 820system.cpu.icache.ReadReq_accesses::cpu.inst 61492700 # number of ReadReq accesses(hits+misses) 821system.cpu.icache.ReadReq_accesses::total 61492700 # number of ReadReq accesses(hits+misses) 822system.cpu.icache.demand_accesses::cpu.inst 61492700 # number of demand (read+write) accesses 823system.cpu.icache.demand_accesses::total 61492700 # number of demand (read+write) accesses 824system.cpu.icache.overall_accesses::cpu.inst 61492700 # number of overall (read+write) accesses 825system.cpu.icache.overall_accesses::total 61492700 # number of overall (read+write) accesses | 690system.cpu.icache.tags.replacements 856273 # number of replacements 691system.cpu.icache.tags.tagsinuse 510.884220 # Cycle average of tags in use 692system.cpu.icache.tags.total_refs 60636138 # Total number of references to valid blocks. 693system.cpu.icache.tags.sampled_refs 856785 # Sample count of references to valid blocks. 694system.cpu.icache.tags.avg_refs 70.771708 # Average number of references to valid blocks. 695system.cpu.icache.tags.warmup_cycle 19799760250 # Cycle when the warmup percentage was hit. 696system.cpu.icache.tags.occ_blocks::cpu.inst 510.884220 # Average occupied blocks per requestor 697system.cpu.icache.tags.occ_percent::cpu.inst 0.997821 # Average percentage of cache occupancy 698system.cpu.icache.tags.occ_percent::total 0.997821 # Average percentage of cache occupancy 699system.cpu.icache.ReadReq_hits::cpu.inst 60636138 # number of ReadReq hits 700system.cpu.icache.ReadReq_hits::total 60636138 # number of ReadReq hits 701system.cpu.icache.demand_hits::cpu.inst 60636138 # number of demand (read+write) hits 702system.cpu.icache.demand_hits::total 60636138 # number of demand (read+write) hits 703system.cpu.icache.overall_hits::cpu.inst 60636138 # number of overall hits 704system.cpu.icache.overall_hits::total 60636138 # number of overall hits 705system.cpu.icache.ReadReq_misses::cpu.inst 856785 # number of ReadReq misses 706system.cpu.icache.ReadReq_misses::total 856785 # number of ReadReq misses 707system.cpu.icache.demand_misses::cpu.inst 856785 # number of demand (read+write) misses 708system.cpu.icache.demand_misses::total 856785 # number of demand (read+write) misses 709system.cpu.icache.overall_misses::cpu.inst 856785 # number of overall misses 710system.cpu.icache.overall_misses::total 856785 # number of overall misses 711system.cpu.icache.ReadReq_miss_latency::cpu.inst 11770019500 # number of ReadReq miss cycles 712system.cpu.icache.ReadReq_miss_latency::total 11770019500 # number of ReadReq miss cycles 713system.cpu.icache.demand_miss_latency::cpu.inst 11770019500 # number of demand (read+write) miss cycles 714system.cpu.icache.demand_miss_latency::total 11770019500 # number of demand (read+write) miss cycles 715system.cpu.icache.overall_miss_latency::cpu.inst 11770019500 # number of overall miss cycles 716system.cpu.icache.overall_miss_latency::total 11770019500 # number of overall miss cycles 717system.cpu.icache.ReadReq_accesses::cpu.inst 61492923 # number of ReadReq accesses(hits+misses) 718system.cpu.icache.ReadReq_accesses::total 61492923 # number of ReadReq accesses(hits+misses) 719system.cpu.icache.demand_accesses::cpu.inst 61492923 # number of demand (read+write) accesses 720system.cpu.icache.demand_accesses::total 61492923 # number of demand (read+write) accesses 721system.cpu.icache.overall_accesses::cpu.inst 61492923 # number of overall (read+write) accesses 722system.cpu.icache.overall_accesses::total 61492923 # number of overall (read+write) accesses |
| 826system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses 827system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses 828system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses 829system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses 830system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses 831system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses | 723system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses 724system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses 725system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses 726system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses 727system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses 728system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses |
| 832system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13735.464913 # average ReadReq miss latency 833system.cpu.icache.ReadReq_avg_miss_latency::total 13735.464913 # average ReadReq miss latency 834system.cpu.icache.demand_avg_miss_latency::cpu.inst 13735.464913 # average overall miss latency 835system.cpu.icache.demand_avg_miss_latency::total 13735.464913 # average overall miss latency 836system.cpu.icache.overall_avg_miss_latency::cpu.inst 13735.464913 # average overall miss latency 837system.cpu.icache.overall_avg_miss_latency::total 13735.464913 # average overall miss latency | 729system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13737.424792 # average ReadReq miss latency 730system.cpu.icache.ReadReq_avg_miss_latency::total 13737.424792 # average ReadReq miss latency 731system.cpu.icache.demand_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency 732system.cpu.icache.demand_avg_miss_latency::total 13737.424792 # average overall miss latency 733system.cpu.icache.overall_avg_miss_latency::cpu.inst 13737.424792 # average overall miss latency 734system.cpu.icache.overall_avg_miss_latency::total 13737.424792 # average overall miss latency |
| 838system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 839system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 840system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 841system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 842system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 843system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 844system.cpu.icache.fast_writes 0 # number of fast writes performed 845system.cpu.icache.cache_copies 0 # number of cache copies performed | 735system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 736system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 737system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 738system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 739system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 740system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 741system.cpu.icache.fast_writes 0 # number of fast writes performed 742system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 846system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856806 # number of ReadReq MSHR misses 847system.cpu.icache.ReadReq_mshr_misses::total 856806 # number of ReadReq MSHR misses 848system.cpu.icache.demand_mshr_misses::cpu.inst 856806 # number of demand (read+write) MSHR misses 849system.cpu.icache.demand_mshr_misses::total 856806 # number of demand (read+write) MSHR misses 850system.cpu.icache.overall_mshr_misses::cpu.inst 856806 # number of overall MSHR misses 851system.cpu.icache.overall_mshr_misses::total 856806 # number of overall MSHR misses 852system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10049829250 # number of ReadReq MSHR miss cycles 853system.cpu.icache.ReadReq_mshr_miss_latency::total 10049829250 # number of ReadReq MSHR miss cycles 854system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10049829250 # number of demand (read+write) MSHR miss cycles 855system.cpu.icache.demand_mshr_miss_latency::total 10049829250 # number of demand (read+write) MSHR miss cycles 856system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10049829250 # number of overall MSHR miss cycles 857system.cpu.icache.overall_mshr_miss_latency::total 10049829250 # number of overall MSHR miss cycles 858system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 430705250 # number of ReadReq MSHR uncacheable cycles 859system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 430705250 # number of ReadReq MSHR uncacheable cycles 860system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 430705250 # number of overall MSHR uncacheable cycles 861system.cpu.icache.overall_mshr_uncacheable_latency::total 430705250 # number of overall MSHR uncacheable cycles | 743system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856785 # number of ReadReq MSHR misses 744system.cpu.icache.ReadReq_mshr_misses::total 856785 # number of ReadReq MSHR misses 745system.cpu.icache.demand_mshr_misses::cpu.inst 856785 # number of demand (read+write) MSHR misses 746system.cpu.icache.demand_mshr_misses::total 856785 # number of demand (read+write) MSHR misses 747system.cpu.icache.overall_mshr_misses::cpu.inst 856785 # number of overall MSHR misses 748system.cpu.icache.overall_mshr_misses::total 856785 # number of overall MSHR misses 749system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10051263500 # number of ReadReq MSHR miss cycles 750system.cpu.icache.ReadReq_mshr_miss_latency::total 10051263500 # number of ReadReq MSHR miss cycles 751system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10051263500 # number of demand (read+write) MSHR miss cycles 752system.cpu.icache.demand_mshr_miss_latency::total 10051263500 # number of demand (read+write) MSHR miss cycles 753system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10051263500 # number of overall MSHR miss cycles 754system.cpu.icache.overall_mshr_miss_latency::total 10051263500 # number of overall MSHR miss cycles 755system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 414413750 # number of ReadReq MSHR uncacheable cycles 756system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 414413750 # number of ReadReq MSHR uncacheable cycles 757system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 414413750 # number of overall MSHR uncacheable cycles 758system.cpu.icache.overall_mshr_uncacheable_latency::total 414413750 # number of overall MSHR uncacheable cycles |
| 862system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses 863system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses 864system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses 865system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses 866system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses 867system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses | 759system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses 760system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses 761system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses 762system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses 763system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses 764system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses |
| 868system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11729.410450 # average ReadReq mshr miss latency 869system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11729.410450 # average ReadReq mshr miss latency 870system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11729.410450 # average overall mshr miss latency 871system.cpu.icache.demand_avg_mshr_miss_latency::total 11729.410450 # average overall mshr miss latency 872system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11729.410450 # average overall mshr miss latency 873system.cpu.icache.overall_avg_mshr_miss_latency::total 11729.410450 # average overall mshr miss latency | 765system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11731.371931 # average ReadReq mshr miss latency 766system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11731.371931 # average ReadReq mshr miss latency 767system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11731.371931 # average overall mshr miss latency 768system.cpu.icache.demand_avg_mshr_miss_latency::total 11731.371931 # average overall mshr miss latency 769system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11731.371931 # average overall mshr miss latency 770system.cpu.icache.overall_avg_mshr_miss_latency::total 11731.371931 # average overall mshr miss latency |
| 874system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 875system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 876system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 877system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 878system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 771system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 772system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 773system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 774system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 775system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 879system.cpu.l2cache.tags.replacements 62586 # number of replacements 880system.cpu.l2cache.tags.tagsinuse 50732.763816 # Cycle average of tags in use 881system.cpu.l2cache.tags.total_refs 1683068 # Total number of references to valid blocks. 882system.cpu.l2cache.tags.sampled_refs 127970 # Sample count of references to valid blocks. 883system.cpu.l2cache.tags.avg_refs 13.152051 # Average number of references to valid blocks. 884system.cpu.l2cache.tags.warmup_cycle 2564920911000 # Cycle when the warmup percentage was hit. 885system.cpu.l2cache.tags.occ_blocks::writebacks 37695.858347 # Average occupied blocks per requestor 886system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884553 # Average occupied blocks per requestor | 776system.cpu.l2cache.tags.replacements 62587 # number of replacements 777system.cpu.l2cache.tags.tagsinuse 50733.810806 # Cycle average of tags in use 778system.cpu.l2cache.tags.total_refs 1683077 # Total number of references to valid blocks. 779system.cpu.l2cache.tags.sampled_refs 127973 # Sample count of references to valid blocks. 780system.cpu.l2cache.tags.avg_refs 13.151813 # Average number of references to valid blocks. 781system.cpu.l2cache.tags.warmup_cycle 2564904211000 # Cycle when the warmup percentage was hit. 782system.cpu.l2cache.tags.occ_blocks::writebacks 37696.862224 # Average occupied blocks per requestor 783system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.884576 # Average occupied blocks per requestor |
| 887system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000692 # Average occupied blocks per requestor | 784system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000692 # Average occupied blocks per requestor |
| 888system.cpu.l2cache.tags.occ_blocks::cpu.inst 6997.437473 # Average occupied blocks per requestor 889system.cpu.l2cache.tags.occ_blocks::cpu.data 6035.582751 # Average occupied blocks per requestor 890system.cpu.l2cache.tags.occ_percent::writebacks 0.575193 # Average percentage of cache occupancy | 785system.cpu.l2cache.tags.occ_blocks::cpu.inst 6998.396772 # Average occupied blocks per requestor 786system.cpu.l2cache.tags.occ_blocks::cpu.data 6034.666541 # Average occupied blocks per requestor 787system.cpu.l2cache.tags.occ_percent::writebacks 0.575208 # Average percentage of cache occupancy |
| 891system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 892system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 788system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 893system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106772 # Average percentage of cache occupancy 894system.cpu.l2cache.tags.occ_percent::cpu.data 0.092096 # Average percentage of cache occupancy 895system.cpu.l2cache.tags.occ_percent::total 0.774121 # Average percentage of cache occupancy | 790system.cpu.l2cache.tags.occ_percent::cpu.inst 0.106787 # Average percentage of cache occupancy 791system.cpu.l2cache.tags.occ_percent::cpu.data 0.092082 # Average percentage of cache occupancy 792system.cpu.l2cache.tags.occ_percent::total 0.774137 # Average percentage of cache occupancy |
| 896system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8720 # number of ReadReq hits 897system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3535 # number of ReadReq hits | 793system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8720 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3535 # number of ReadReq hits |
| 898system.cpu.l2cache.ReadReq_hits::cpu.inst 844565 # number of ReadReq hits 899system.cpu.l2cache.ReadReq_hits::cpu.data 370151 # number of ReadReq hits 900system.cpu.l2cache.ReadReq_hits::total 1226971 # number of ReadReq hits 901system.cpu.l2cache.Writeback_hits::writebacks 595786 # number of Writeback hits 902system.cpu.l2cache.Writeback_hits::total 595786 # number of Writeback hits | 795system.cpu.l2cache.ReadReq_hits::cpu.inst 844543 # number of ReadReq hits 796system.cpu.l2cache.ReadReq_hits::cpu.data 370162 # number of ReadReq hits 797system.cpu.l2cache.ReadReq_hits::total 1226960 # number of ReadReq hits 798system.cpu.l2cache.Writeback_hits::writebacks 595785 # number of Writeback hits 799system.cpu.l2cache.Writeback_hits::total 595785 # number of Writeback hits |
| 903system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 904system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits | 800system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 801system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits |
| 905system.cpu.l2cache.ReadExReq_hits::cpu.data 113434 # number of ReadExReq hits 906system.cpu.l2cache.ReadExReq_hits::total 113434 # number of ReadExReq hits | 802system.cpu.l2cache.ReadExReq_hits::cpu.data 113425 # number of ReadExReq hits 803system.cpu.l2cache.ReadExReq_hits::total 113425 # number of ReadExReq hits |
| 907system.cpu.l2cache.demand_hits::cpu.dtb.walker 8720 # number of demand (read+write) hits 908system.cpu.l2cache.demand_hits::cpu.itb.walker 3535 # number of demand (read+write) hits | 804system.cpu.l2cache.demand_hits::cpu.dtb.walker 8720 # number of demand (read+write) hits 805system.cpu.l2cache.demand_hits::cpu.itb.walker 3535 # number of demand (read+write) hits |
| 909system.cpu.l2cache.demand_hits::cpu.inst 844565 # number of demand (read+write) hits 910system.cpu.l2cache.demand_hits::cpu.data 483585 # number of demand (read+write) hits 911system.cpu.l2cache.demand_hits::total 1340405 # number of demand (read+write) hits | 806system.cpu.l2cache.demand_hits::cpu.inst 844543 # number of demand (read+write) hits 807system.cpu.l2cache.demand_hits::cpu.data 483587 # number of demand (read+write) hits 808system.cpu.l2cache.demand_hits::total 1340385 # number of demand (read+write) hits |
| 912system.cpu.l2cache.overall_hits::cpu.dtb.walker 8720 # number of overall hits 913system.cpu.l2cache.overall_hits::cpu.itb.walker 3535 # number of overall hits | 809system.cpu.l2cache.overall_hits::cpu.dtb.walker 8720 # number of overall hits 810system.cpu.l2cache.overall_hits::cpu.itb.walker 3535 # number of overall hits |
| 914system.cpu.l2cache.overall_hits::cpu.inst 844565 # number of overall hits 915system.cpu.l2cache.overall_hits::cpu.data 483585 # number of overall hits 916system.cpu.l2cache.overall_hits::total 1340405 # number of overall hits | 811system.cpu.l2cache.overall_hits::cpu.inst 844543 # number of overall hits 812system.cpu.l2cache.overall_hits::cpu.data 483587 # number of overall hits 813system.cpu.l2cache.overall_hits::total 1340385 # number of overall hits |
| 917system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 918system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses | 814system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 815system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses |
| 919system.cpu.l2cache.ReadReq_misses::cpu.inst 10600 # number of ReadReq misses | 816system.cpu.l2cache.ReadReq_misses::cpu.inst 10601 # number of ReadReq misses |
| 920system.cpu.l2cache.ReadReq_misses::cpu.data 9837 # number of ReadReq misses | 817system.cpu.l2cache.ReadReq_misses::cpu.data 9837 # number of ReadReq misses |
| 921system.cpu.l2cache.ReadReq_misses::total 20444 # number of ReadReq misses | 818system.cpu.l2cache.ReadReq_misses::total 20445 # number of ReadReq misses |
| 922system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses 923system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses 924system.cpu.l2cache.ReadExReq_misses::cpu.data 133893 # number of ReadExReq misses 925system.cpu.l2cache.ReadExReq_misses::total 133893 # number of ReadExReq misses 926system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 927system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses | 819system.cpu.l2cache.UpgradeReq_misses::cpu.data 2872 # number of UpgradeReq misses 820system.cpu.l2cache.UpgradeReq_misses::total 2872 # number of UpgradeReq misses 821system.cpu.l2cache.ReadExReq_misses::cpu.data 133893 # number of ReadExReq misses 822system.cpu.l2cache.ReadExReq_misses::total 133893 # number of ReadExReq misses 823system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 824system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses |
| 928system.cpu.l2cache.demand_misses::cpu.inst 10600 # number of demand (read+write) misses | 825system.cpu.l2cache.demand_misses::cpu.inst 10601 # number of demand (read+write) misses |
| 929system.cpu.l2cache.demand_misses::cpu.data 143730 # number of demand (read+write) misses | 826system.cpu.l2cache.demand_misses::cpu.data 143730 # number of demand (read+write) misses |
| 930system.cpu.l2cache.demand_misses::total 154337 # number of demand (read+write) misses | 827system.cpu.l2cache.demand_misses::total 154338 # number of demand (read+write) misses |
| 931system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 932system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses | 828system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 829system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses |
| 933system.cpu.l2cache.overall_misses::cpu.inst 10600 # number of overall misses | 830system.cpu.l2cache.overall_misses::cpu.inst 10601 # number of overall misses |
| 934system.cpu.l2cache.overall_misses::cpu.data 143730 # number of overall misses | 831system.cpu.l2cache.overall_misses::cpu.data 143730 # number of overall misses |
| 935system.cpu.l2cache.overall_misses::total 154337 # number of overall misses | 832system.cpu.l2cache.overall_misses::total 154338 # number of overall misses |
| 936system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 390500 # number of ReadReq miss cycles 937system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122500 # number of ReadReq miss cycles | 833system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 390500 # number of ReadReq miss cycles 834system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122500 # number of ReadReq miss cycles |
| 938system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 745731750 # number of ReadReq miss cycles 939system.cpu.l2cache.ReadReq_miss_latency::cpu.data 700197500 # number of ReadReq miss cycles 940system.cpu.l2cache.ReadReq_miss_latency::total 1446442250 # number of ReadReq miss cycles 941system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 469980 # number of UpgradeReq miss cycles 942system.cpu.l2cache.UpgradeReq_miss_latency::total 469980 # number of UpgradeReq miss cycles 943system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8609650357 # number of ReadExReq miss cycles 944system.cpu.l2cache.ReadExReq_miss_latency::total 8609650357 # number of ReadExReq miss cycles | 835system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 747407000 # number of ReadReq miss cycles 836system.cpu.l2cache.ReadReq_miss_latency::cpu.data 696870750 # number of ReadReq miss cycles 837system.cpu.l2cache.ReadReq_miss_latency::total 1444790750 # number of ReadReq miss cycles 838system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 470980 # number of UpgradeReq miss cycles 839system.cpu.l2cache.UpgradeReq_miss_latency::total 470980 # number of UpgradeReq miss cycles 840system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8609068107 # number of ReadExReq miss cycles 841system.cpu.l2cache.ReadExReq_miss_latency::total 8609068107 # number of ReadExReq miss cycles |
| 945system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 390500 # number of demand (read+write) miss cycles 946system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 122500 # number of demand (read+write) miss cycles | 842system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 390500 # number of demand (read+write) miss cycles 843system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 122500 # number of demand (read+write) miss cycles |
| 947system.cpu.l2cache.demand_miss_latency::cpu.inst 745731750 # number of demand (read+write) miss cycles 948system.cpu.l2cache.demand_miss_latency::cpu.data 9309847857 # number of demand (read+write) miss cycles 949system.cpu.l2cache.demand_miss_latency::total 10056092607 # number of demand (read+write) miss cycles | 844system.cpu.l2cache.demand_miss_latency::cpu.inst 747407000 # number of demand (read+write) miss cycles 845system.cpu.l2cache.demand_miss_latency::cpu.data 9305938857 # number of demand (read+write) miss cycles 846system.cpu.l2cache.demand_miss_latency::total 10053858857 # number of demand (read+write) miss cycles |
| 950system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 390500 # number of overall miss cycles 951system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 122500 # number of overall miss cycles | 847system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 390500 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 122500 # number of overall miss cycles |
| 952system.cpu.l2cache.overall_miss_latency::cpu.inst 745731750 # number of overall miss cycles 953system.cpu.l2cache.overall_miss_latency::cpu.data 9309847857 # number of overall miss cycles 954system.cpu.l2cache.overall_miss_latency::total 10056092607 # number of overall miss cycles | 849system.cpu.l2cache.overall_miss_latency::cpu.inst 747407000 # number of overall miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.data 9305938857 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::total 10053858857 # number of overall miss cycles |
| 955system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8725 # number of ReadReq accesses(hits+misses) 956system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3537 # number of ReadReq accesses(hits+misses) | 852system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8725 # number of ReadReq accesses(hits+misses) 853system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3537 # number of ReadReq accesses(hits+misses) |
| 957system.cpu.l2cache.ReadReq_accesses::cpu.inst 855165 # number of ReadReq accesses(hits+misses) 958system.cpu.l2cache.ReadReq_accesses::cpu.data 379988 # number of ReadReq accesses(hits+misses) 959system.cpu.l2cache.ReadReq_accesses::total 1247415 # number of ReadReq accesses(hits+misses) 960system.cpu.l2cache.Writeback_accesses::writebacks 595786 # number of Writeback accesses(hits+misses) 961system.cpu.l2cache.Writeback_accesses::total 595786 # number of Writeback accesses(hits+misses) | 854system.cpu.l2cache.ReadReq_accesses::cpu.inst 855144 # number of ReadReq accesses(hits+misses) 855system.cpu.l2cache.ReadReq_accesses::cpu.data 379999 # number of ReadReq accesses(hits+misses) 856system.cpu.l2cache.ReadReq_accesses::total 1247405 # number of ReadReq accesses(hits+misses) 857system.cpu.l2cache.Writeback_accesses::writebacks 595785 # number of Writeback accesses(hits+misses) 858system.cpu.l2cache.Writeback_accesses::total 595785 # number of Writeback accesses(hits+misses) |
| 962system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses) 963system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses) | 859system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2898 # number of UpgradeReq accesses(hits+misses) 860system.cpu.l2cache.UpgradeReq_accesses::total 2898 # number of UpgradeReq accesses(hits+misses) |
| 964system.cpu.l2cache.ReadExReq_accesses::cpu.data 247327 # number of ReadExReq accesses(hits+misses) 965system.cpu.l2cache.ReadExReq_accesses::total 247327 # number of ReadExReq accesses(hits+misses) | 861system.cpu.l2cache.ReadExReq_accesses::cpu.data 247318 # number of ReadExReq accesses(hits+misses) 862system.cpu.l2cache.ReadExReq_accesses::total 247318 # number of ReadExReq accesses(hits+misses) |
| 966system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8725 # number of demand (read+write) accesses 967system.cpu.l2cache.demand_accesses::cpu.itb.walker 3537 # number of demand (read+write) accesses | 863system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8725 # number of demand (read+write) accesses 864system.cpu.l2cache.demand_accesses::cpu.itb.walker 3537 # number of demand (read+write) accesses |
| 968system.cpu.l2cache.demand_accesses::cpu.inst 855165 # number of demand (read+write) accesses 969system.cpu.l2cache.demand_accesses::cpu.data 627315 # number of demand (read+write) accesses 970system.cpu.l2cache.demand_accesses::total 1494742 # number of demand (read+write) accesses | 865system.cpu.l2cache.demand_accesses::cpu.inst 855144 # number of demand (read+write) accesses 866system.cpu.l2cache.demand_accesses::cpu.data 627317 # number of demand (read+write) accesses 867system.cpu.l2cache.demand_accesses::total 1494723 # number of demand (read+write) accesses |
| 971system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8725 # number of overall (read+write) accesses 972system.cpu.l2cache.overall_accesses::cpu.itb.walker 3537 # number of overall (read+write) accesses | 868system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8725 # number of overall (read+write) accesses 869system.cpu.l2cache.overall_accesses::cpu.itb.walker 3537 # number of overall (read+write) accesses |
| 973system.cpu.l2cache.overall_accesses::cpu.inst 855165 # number of overall (read+write) accesses 974system.cpu.l2cache.overall_accesses::cpu.data 627315 # number of overall (read+write) accesses 975system.cpu.l2cache.overall_accesses::total 1494742 # number of overall (read+write) accesses | 870system.cpu.l2cache.overall_accesses::cpu.inst 855144 # number of overall (read+write) accesses 871system.cpu.l2cache.overall_accesses::cpu.data 627317 # number of overall (read+write) accesses 872system.cpu.l2cache.overall_accesses::total 1494723 # number of overall (read+write) accesses |
| 976system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000573 # miss rate for ReadReq accesses 977system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000565 # miss rate for ReadReq accesses | 873system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000573 # miss rate for ReadReq accesses 874system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000565 # miss rate for ReadReq accesses |
| 978system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012395 # miss rate for ReadReq accesses 979system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025888 # miss rate for ReadReq accesses 980system.cpu.l2cache.ReadReq_miss_rate::total 0.016389 # miss rate for ReadReq accesses | 875system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012397 # miss rate for ReadReq accesses 876system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025887 # miss rate for ReadReq accesses 877system.cpu.l2cache.ReadReq_miss_rate::total 0.016390 # miss rate for ReadReq accesses |
| 981system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses 982system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses | 878system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991028 # miss rate for UpgradeReq accesses 879system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991028 # miss rate for UpgradeReq accesses |
| 983system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541360 # miss rate for ReadExReq accesses 984system.cpu.l2cache.ReadExReq_miss_rate::total 0.541360 # miss rate for ReadExReq accesses | 880system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541380 # miss rate for ReadExReq accesses 881system.cpu.l2cache.ReadExReq_miss_rate::total 0.541380 # miss rate for ReadExReq accesses |
| 985system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000573 # miss rate for demand accesses 986system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000565 # miss rate for demand accesses | 882system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000573 # miss rate for demand accesses 883system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000565 # miss rate for demand accesses |
| 987system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012395 # miss rate for demand accesses | 884system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012397 # miss rate for demand accesses |
| 988system.cpu.l2cache.demand_miss_rate::cpu.data 0.229119 # miss rate for demand accesses | 885system.cpu.l2cache.demand_miss_rate::cpu.data 0.229119 # miss rate for demand accesses |
| 989system.cpu.l2cache.demand_miss_rate::total 0.103253 # miss rate for demand accesses | 886system.cpu.l2cache.demand_miss_rate::total 0.103255 # miss rate for demand accesses |
| 990system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000573 # miss rate for overall accesses 991system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000565 # miss rate for overall accesses | 887system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000573 # miss rate for overall accesses 888system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000565 # miss rate for overall accesses |
| 992system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012395 # miss rate for overall accesses | 889system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012397 # miss rate for overall accesses |
| 993system.cpu.l2cache.overall_miss_rate::cpu.data 0.229119 # miss rate for overall accesses | 890system.cpu.l2cache.overall_miss_rate::cpu.data 0.229119 # miss rate for overall accesses |
| 994system.cpu.l2cache.overall_miss_rate::total 0.103253 # miss rate for overall accesses | 891system.cpu.l2cache.overall_miss_rate::total 0.103255 # miss rate for overall accesses |
| 995system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78100 # average ReadReq miss latency 996system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61250 # average ReadReq miss latency | 892system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78100 # average ReadReq miss latency 893system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61250 # average ReadReq miss latency |
| 997system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70352.051887 # average ReadReq miss latency 998system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71179.983735 # average ReadReq miss latency 999system.cpu.l2cache.ReadReq_avg_miss_latency::total 70751.430738 # average ReadReq miss latency 1000system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.642061 # average UpgradeReq miss latency 1001system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.642061 # average UpgradeReq miss latency 1002system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64302.468068 # average ReadExReq miss latency 1003system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64302.468068 # average ReadExReq miss latency | 894system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70503.443071 # average ReadReq miss latency 895system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70841.796279 # average ReadReq miss latency 896system.cpu.l2cache.ReadReq_avg_miss_latency::total 70667.192468 # average ReadReq miss latency 897system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.990251 # average UpgradeReq miss latency 898system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.990251 # average UpgradeReq miss latency 899system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64298.119446 # average ReadExReq miss latency 900system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64298.119446 # average ReadExReq miss latency |
| 1004system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency 1005system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency | 901system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency 902system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency |
| 1006system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70352.051887 # average overall miss latency 1007system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64773.170925 # average overall miss latency 1008system.cpu.l2cache.demand_avg_miss_latency::total 65156.719432 # average overall miss latency | 903system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70503.443071 # average overall miss latency 904system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64745.974097 # average overall miss latency 905system.cpu.l2cache.demand_avg_miss_latency::total 65141.824159 # average overall miss latency |
| 1009system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency 1010system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency | 906system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78100 # average overall miss latency 907system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61250 # average overall miss latency |
| 1011system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70352.051887 # average overall miss latency 1012system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64773.170925 # average overall miss latency 1013system.cpu.l2cache.overall_avg_miss_latency::total 65156.719432 # average overall miss latency | 908system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70503.443071 # average overall miss latency 909system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64745.974097 # average overall miss latency 910system.cpu.l2cache.overall_avg_miss_latency::total 65141.824159 # average overall miss latency |
| 1014system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1015system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1016system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1017system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1018system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1019system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1020system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1021system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1022system.cpu.l2cache.writebacks::writebacks 57971 # number of writebacks 1023system.cpu.l2cache.writebacks::total 57971 # number of writebacks 1024system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 1025system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses | 911system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 912system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 913system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 914system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 915system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 916system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 917system.cpu.l2cache.fast_writes 0 # number of fast writes performed 918system.cpu.l2cache.cache_copies 0 # number of cache copies performed 919system.cpu.l2cache.writebacks::writebacks 57971 # number of writebacks 920system.cpu.l2cache.writebacks::total 57971 # number of writebacks 921system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 922system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses |
| 1026system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10600 # number of ReadReq MSHR misses | 923system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10601 # number of ReadReq MSHR misses |
| 1027system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9837 # number of ReadReq MSHR misses | 924system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9837 # number of ReadReq MSHR misses |
| 1028system.cpu.l2cache.ReadReq_mshr_misses::total 20444 # number of ReadReq MSHR misses | 925system.cpu.l2cache.ReadReq_mshr_misses::total 20445 # number of ReadReq MSHR misses |
| 1029system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses 1030system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses 1031system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133893 # number of ReadExReq MSHR misses 1032system.cpu.l2cache.ReadExReq_mshr_misses::total 133893 # number of ReadExReq MSHR misses 1033system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 1034system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses | 926system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2872 # number of UpgradeReq MSHR misses 927system.cpu.l2cache.UpgradeReq_mshr_misses::total 2872 # number of UpgradeReq MSHR misses 928system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133893 # number of ReadExReq MSHR misses 929system.cpu.l2cache.ReadExReq_mshr_misses::total 133893 # number of ReadExReq MSHR misses 930system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 931system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses |
| 1035system.cpu.l2cache.demand_mshr_misses::cpu.inst 10600 # number of demand (read+write) MSHR misses | 932system.cpu.l2cache.demand_mshr_misses::cpu.inst 10601 # number of demand (read+write) MSHR misses |
| 1036system.cpu.l2cache.demand_mshr_misses::cpu.data 143730 # number of demand (read+write) MSHR misses | 933system.cpu.l2cache.demand_mshr_misses::cpu.data 143730 # number of demand (read+write) MSHR misses |
| 1037system.cpu.l2cache.demand_mshr_misses::total 154337 # number of demand (read+write) MSHR misses | 934system.cpu.l2cache.demand_mshr_misses::total 154338 # number of demand (read+write) MSHR misses |
| 1038system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 1039system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses | 935system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 936system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses |
| 1040system.cpu.l2cache.overall_mshr_misses::cpu.inst 10600 # number of overall MSHR misses | 937system.cpu.l2cache.overall_mshr_misses::cpu.inst 10601 # number of overall MSHR misses |
| 1041system.cpu.l2cache.overall_mshr_misses::cpu.data 143730 # number of overall MSHR misses | 938system.cpu.l2cache.overall_mshr_misses::cpu.data 143730 # number of overall MSHR misses |
| 1042system.cpu.l2cache.overall_mshr_misses::total 154337 # number of overall MSHR misses | 939system.cpu.l2cache.overall_mshr_misses::total 154338 # number of overall MSHR misses |
| 1043system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 326500 # number of ReadReq MSHR miss cycles 1044system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97500 # number of ReadReq MSHR miss cycles | 940system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 326500 # number of ReadReq MSHR miss cycles 941system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97500 # number of ReadReq MSHR miss cycles |
| 1045system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 612276250 # number of ReadReq MSHR miss cycles 1046system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 575969500 # number of ReadReq MSHR miss cycles 1047system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1188669750 # number of ReadReq MSHR miss cycles 1048system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28722872 # number of UpgradeReq MSHR miss cycles 1049system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28722872 # number of UpgradeReq MSHR miss cycles 1050system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6933953143 # number of ReadExReq MSHR miss cycles 1051system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6933953143 # number of ReadExReq MSHR miss cycles | 942system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 613945500 # number of ReadReq MSHR miss cycles 943system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 572634250 # number of ReadReq MSHR miss cycles 944system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1187003750 # number of ReadReq MSHR miss cycles 945system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28725872 # number of UpgradeReq MSHR miss cycles 946system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28725872 # number of UpgradeReq MSHR miss cycles 947system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6933351393 # number of ReadExReq MSHR miss cycles 948system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6933351393 # number of ReadExReq MSHR miss cycles |
| 1052system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 326500 # number of demand (read+write) MSHR miss cycles 1053system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 97500 # number of demand (read+write) MSHR miss cycles | 949system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 326500 # number of demand (read+write) MSHR miss cycles 950system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 97500 # number of demand (read+write) MSHR miss cycles |
| 1054system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 612276250 # number of demand (read+write) MSHR miss cycles 1055system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7509922643 # number of demand (read+write) MSHR miss cycles 1056system.cpu.l2cache.demand_mshr_miss_latency::total 8122622893 # number of demand (read+write) MSHR miss cycles | 951system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 613945500 # number of demand (read+write) MSHR miss cycles 952system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7505985643 # number of demand (read+write) MSHR miss cycles 953system.cpu.l2cache.demand_mshr_miss_latency::total 8120355143 # number of demand (read+write) MSHR miss cycles |
| 1057system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 326500 # number of overall MSHR miss cycles 1058system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 97500 # number of overall MSHR miss cycles | 954system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 326500 # number of overall MSHR miss cycles 955system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 97500 # number of overall MSHR miss cycles |
| 1059system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 612276250 # number of overall MSHR miss cycles 1060system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7509922643 # number of overall MSHR miss cycles 1061system.cpu.l2cache.overall_mshr_miss_latency::total 8122622893 # number of overall MSHR miss cycles 1062system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 339357750 # number of ReadReq MSHR uncacheable cycles 1063system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657272750 # number of ReadReq MSHR uncacheable cycles 1064system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166996630500 # number of ReadReq MSHR uncacheable cycles 1065system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702868810 # number of WriteReq MSHR uncacheable cycles 1066system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702868810 # number of WriteReq MSHR uncacheable cycles 1067system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 339357750 # number of overall MSHR uncacheable cycles 1068system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183360141560 # number of overall MSHR uncacheable cycles 1069system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183699499310 # number of overall MSHR uncacheable cycles | 956system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 613945500 # number of overall MSHR miss cycles 957system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7505985643 # number of overall MSHR miss cycles 958system.cpu.l2cache.overall_mshr_miss_latency::total 8120355143 # number of overall MSHR miss cycles 959system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 322980250 # number of ReadReq MSHR uncacheable cycles 960system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657157250 # number of ReadReq MSHR uncacheable cycles 961system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166980137500 # number of ReadReq MSHR uncacheable cycles 962system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16702542535 # number of WriteReq MSHR uncacheable cycles 963system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16702542535 # number of WriteReq MSHR uncacheable cycles 964system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 322980250 # number of overall MSHR uncacheable cycles 965system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183359699785 # number of overall MSHR uncacheable cycles 966system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183682680035 # number of overall MSHR uncacheable cycles |
| 1070system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses 1071system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses | 967system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses 968system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for ReadReq accesses |
| 1072system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for ReadReq accesses 1073system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025888 # mshr miss rate for ReadReq accesses 1074system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016389 # mshr miss rate for ReadReq accesses | 969system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for ReadReq accesses 970system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025887 # mshr miss rate for ReadReq accesses 971system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016390 # mshr miss rate for ReadReq accesses |
| 1075system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses 1076system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses | 972system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991028 # mshr miss rate for UpgradeReq accesses 973system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991028 # mshr miss rate for UpgradeReq accesses |
| 1077system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541360 # mshr miss rate for ReadExReq accesses 1078system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541360 # mshr miss rate for ReadExReq accesses | 974system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541380 # mshr miss rate for ReadExReq accesses 975system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541380 # mshr miss rate for ReadExReq accesses |
| 1079system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses 1080system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses | 976system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses 977system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for demand accesses |
| 1081system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for demand accesses | 978system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for demand accesses |
| 1082system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for demand accesses | 979system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for demand accesses |
| 1083system.cpu.l2cache.demand_mshr_miss_rate::total 0.103253 # mshr miss rate for demand accesses | 980system.cpu.l2cache.demand_mshr_miss_rate::total 0.103255 # mshr miss rate for demand accesses |
| 1084system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses 1085system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses | 981system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses 982system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000565 # mshr miss rate for overall accesses |
| 1086system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for overall accesses | 983system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012397 # mshr miss rate for overall accesses |
| 1087system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for overall accesses | 984system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229119 # mshr miss rate for overall accesses |
| 1088system.cpu.l2cache.overall_mshr_miss_rate::total 0.103253 # mshr miss rate for overall accesses | 985system.cpu.l2cache.overall_mshr_miss_rate::total 0.103255 # mshr miss rate for overall accesses |
| 1089system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average ReadReq mshr miss latency 1090system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48750 # average ReadReq mshr miss latency | 986system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average ReadReq mshr miss latency 987system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48750 # average ReadReq mshr miss latency |
| 1091system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57761.910377 # average ReadReq mshr miss latency 1092system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58551.336790 # average ReadReq mshr miss latency 1093system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58142.719135 # average ReadReq mshr miss latency 1094system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 1095system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 1096system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51787.271500 # average ReadExReq mshr miss latency 1097system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51787.271500 # average ReadExReq mshr miss latency | 988system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57913.923215 # average ReadReq mshr miss latency 989system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58212.285250 # average ReadReq mshr miss latency 990system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58058.388359 # average ReadReq mshr miss latency 991system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.044568 # average UpgradeReq mshr miss latency 992system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.044568 # average UpgradeReq mshr miss latency 993system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51782.777240 # average ReadExReq mshr miss latency 994system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51782.777240 # average ReadExReq mshr miss latency |
| 1098system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency 1099system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency | 995system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency 996system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency |
| 1100system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57761.910377 # average overall mshr miss latency 1101system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52250.209720 # average overall mshr miss latency 1102system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52629.135548 # average overall mshr miss latency | 997system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency 998system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency 999system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency |
| 1103system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency 1104system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency | 1000system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65300 # average overall mshr miss latency 1001system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency |
| 1105system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57761.910377 # average overall mshr miss latency 1106system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52250.209720 # average overall mshr miss latency 1107system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52629.135548 # average overall mshr miss latency | 1002system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57913.923215 # average overall mshr miss latency 1003system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52222.818083 # average overall mshr miss latency 1004system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52614.101148 # average overall mshr miss latency |
| 1108system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1109system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1110system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1111system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1112system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1113system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1114system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1115system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1116system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1005system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1006system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1007system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1008system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1009system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1010system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1011system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1012system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1013system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1117system.cpu.dcache.tags.replacements 626803 # number of replacements 1118system.cpu.dcache.tags.tagsinuse 511.877792 # Cycle average of tags in use 1119system.cpu.dcache.tags.total_refs 23655579 # Total number of references to valid blocks. 1120system.cpu.dcache.tags.sampled_refs 627315 # Sample count of references to valid blocks. 1121system.cpu.dcache.tags.avg_refs 37.709251 # Average number of references to valid blocks. 1122system.cpu.dcache.tags.warmup_cycle 657281250 # Cycle when the warmup percentage was hit. 1123system.cpu.dcache.tags.occ_blocks::cpu.data 511.877792 # Average occupied blocks per requestor 1124system.cpu.dcache.tags.occ_percent::cpu.data 0.999761 # Average percentage of cache occupancy 1125system.cpu.dcache.tags.occ_percent::total 0.999761 # Average percentage of cache occupancy 1126system.cpu.dcache.ReadReq_hits::cpu.data 13195771 # number of ReadReq hits 1127system.cpu.dcache.ReadReq_hits::total 13195771 # number of ReadReq hits 1128system.cpu.dcache.WriteReq_hits::cpu.data 9972807 # number of WriteReq hits 1129system.cpu.dcache.WriteReq_hits::total 9972807 # number of WriteReq hits | 1014system.cpu.dcache.tags.replacements 626805 # number of replacements 1015system.cpu.dcache.tags.tagsinuse 511.881003 # Cycle average of tags in use 1016system.cpu.dcache.tags.total_refs 23655596 # Total number of references to valid blocks. 1017system.cpu.dcache.tags.sampled_refs 627317 # Sample count of references to valid blocks. 1018system.cpu.dcache.tags.avg_refs 37.709158 # Average number of references to valid blocks. 1019system.cpu.dcache.tags.warmup_cycle 640871250 # Cycle when the warmup percentage was hit. 1020system.cpu.dcache.tags.occ_blocks::cpu.data 511.881003 # Average occupied blocks per requestor 1021system.cpu.dcache.tags.occ_percent::cpu.data 0.999768 # Average percentage of cache occupancy 1022system.cpu.dcache.tags.occ_percent::total 0.999768 # Average percentage of cache occupancy 1023system.cpu.dcache.ReadReq_hits::cpu.data 13195774 # number of ReadReq hits 1024system.cpu.dcache.ReadReq_hits::total 13195774 # number of ReadReq hits 1025system.cpu.dcache.WriteReq_hits::cpu.data 9972821 # number of WriteReq hits 1026system.cpu.dcache.WriteReq_hits::total 9972821 # number of WriteReq hits |
| 1130system.cpu.dcache.LoadLockedReq_hits::cpu.data 236302 # number of LoadLockedReq hits 1131system.cpu.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits 1132system.cpu.dcache.StoreCondReq_hits::cpu.data 247801 # number of StoreCondReq hits 1133system.cpu.dcache.StoreCondReq_hits::total 247801 # number of StoreCondReq hits | 1027system.cpu.dcache.LoadLockedReq_hits::cpu.data 236302 # number of LoadLockedReq hits 1028system.cpu.dcache.LoadLockedReq_hits::total 236302 # number of LoadLockedReq hits 1029system.cpu.dcache.StoreCondReq_hits::cpu.data 247801 # number of StoreCondReq hits 1030system.cpu.dcache.StoreCondReq_hits::total 247801 # number of StoreCondReq hits |
| 1134system.cpu.dcache.demand_hits::cpu.data 23168578 # number of demand (read+write) hits 1135system.cpu.dcache.demand_hits::total 23168578 # number of demand (read+write) hits 1136system.cpu.dcache.overall_hits::cpu.data 23168578 # number of overall hits 1137system.cpu.dcache.overall_hits::total 23168578 # number of overall hits 1138system.cpu.dcache.ReadReq_misses::cpu.data 368488 # number of ReadReq misses 1139system.cpu.dcache.ReadReq_misses::total 368488 # number of ReadReq misses 1140system.cpu.dcache.WriteReq_misses::cpu.data 250225 # number of WriteReq misses 1141system.cpu.dcache.WriteReq_misses::total 250225 # number of WriteReq misses | 1031system.cpu.dcache.demand_hits::cpu.data 23168595 # number of demand (read+write) hits 1032system.cpu.dcache.demand_hits::total 23168595 # number of demand (read+write) hits 1033system.cpu.dcache.overall_hits::cpu.data 23168595 # number of overall hits 1034system.cpu.dcache.overall_hits::total 23168595 # number of overall hits 1035system.cpu.dcache.ReadReq_misses::cpu.data 368499 # number of ReadReq misses 1036system.cpu.dcache.ReadReq_misses::total 368499 # number of ReadReq misses 1037system.cpu.dcache.WriteReq_misses::cpu.data 250216 # number of WriteReq misses 1038system.cpu.dcache.WriteReq_misses::total 250216 # number of WriteReq misses |
| 1142system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses 1143system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses | 1039system.cpu.dcache.LoadLockedReq_misses::cpu.data 11500 # number of LoadLockedReq misses 1040system.cpu.dcache.LoadLockedReq_misses::total 11500 # number of LoadLockedReq misses |
| 1144system.cpu.dcache.demand_misses::cpu.data 618713 # number of demand (read+write) misses 1145system.cpu.dcache.demand_misses::total 618713 # number of demand (read+write) misses 1146system.cpu.dcache.overall_misses::cpu.data 618713 # number of overall misses 1147system.cpu.dcache.overall_misses::total 618713 # number of overall misses 1148system.cpu.dcache.ReadReq_miss_latency::cpu.data 5386574000 # number of ReadReq miss cycles 1149system.cpu.dcache.ReadReq_miss_latency::total 5386574000 # number of ReadReq miss cycles 1150system.cpu.dcache.WriteReq_miss_latency::cpu.data 10624198015 # number of WriteReq miss cycles 1151system.cpu.dcache.WriteReq_miss_latency::total 10624198015 # number of WriteReq miss cycles 1152system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 159892750 # number of LoadLockedReq miss cycles 1153system.cpu.dcache.LoadLockedReq_miss_latency::total 159892750 # number of LoadLockedReq miss cycles 1154system.cpu.dcache.demand_miss_latency::cpu.data 16010772015 # number of demand (read+write) miss cycles 1155system.cpu.dcache.demand_miss_latency::total 16010772015 # number of demand (read+write) miss cycles 1156system.cpu.dcache.overall_miss_latency::cpu.data 16010772015 # number of overall miss cycles 1157system.cpu.dcache.overall_miss_latency::total 16010772015 # number of overall miss cycles 1158system.cpu.dcache.ReadReq_accesses::cpu.data 13564259 # number of ReadReq accesses(hits+misses) 1159system.cpu.dcache.ReadReq_accesses::total 13564259 # number of ReadReq accesses(hits+misses) 1160system.cpu.dcache.WriteReq_accesses::cpu.data 10223032 # number of WriteReq accesses(hits+misses) 1161system.cpu.dcache.WriteReq_accesses::total 10223032 # number of WriteReq accesses(hits+misses) | 1041system.cpu.dcache.demand_misses::cpu.data 618715 # number of demand (read+write) misses 1042system.cpu.dcache.demand_misses::total 618715 # number of demand (read+write) misses 1043system.cpu.dcache.overall_misses::cpu.data 618715 # number of overall misses 1044system.cpu.dcache.overall_misses::total 618715 # number of overall misses 1045system.cpu.dcache.ReadReq_miss_latency::cpu.data 5384538000 # number of ReadReq miss cycles 1046system.cpu.dcache.ReadReq_miss_latency::total 5384538000 # number of ReadReq miss cycles 1047system.cpu.dcache.WriteReq_miss_latency::cpu.data 10623511265 # number of WriteReq miss cycles 1048system.cpu.dcache.WriteReq_miss_latency::total 10623511265 # number of WriteReq miss cycles 1049system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158750500 # number of LoadLockedReq miss cycles 1050system.cpu.dcache.LoadLockedReq_miss_latency::total 158750500 # number of LoadLockedReq miss cycles 1051system.cpu.dcache.demand_miss_latency::cpu.data 16008049265 # number of demand (read+write) miss cycles 1052system.cpu.dcache.demand_miss_latency::total 16008049265 # number of demand (read+write) miss cycles 1053system.cpu.dcache.overall_miss_latency::cpu.data 16008049265 # number of overall miss cycles 1054system.cpu.dcache.overall_miss_latency::total 16008049265 # number of overall miss cycles 1055system.cpu.dcache.ReadReq_accesses::cpu.data 13564273 # number of ReadReq accesses(hits+misses) 1056system.cpu.dcache.ReadReq_accesses::total 13564273 # number of ReadReq accesses(hits+misses) 1057system.cpu.dcache.WriteReq_accesses::cpu.data 10223037 # number of WriteReq accesses(hits+misses) 1058system.cpu.dcache.WriteReq_accesses::total 10223037 # number of WriteReq accesses(hits+misses) |
| 1162system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses) 1163system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses) 1164system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses) 1165system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses) | 1059system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247802 # number of LoadLockedReq accesses(hits+misses) 1060system.cpu.dcache.LoadLockedReq_accesses::total 247802 # number of LoadLockedReq accesses(hits+misses) 1061system.cpu.dcache.StoreCondReq_accesses::cpu.data 247801 # number of StoreCondReq accesses(hits+misses) 1062system.cpu.dcache.StoreCondReq_accesses::total 247801 # number of StoreCondReq accesses(hits+misses) |
| 1166system.cpu.dcache.demand_accesses::cpu.data 23787291 # number of demand (read+write) accesses 1167system.cpu.dcache.demand_accesses::total 23787291 # number of demand (read+write) accesses 1168system.cpu.dcache.overall_accesses::cpu.data 23787291 # number of overall (read+write) accesses 1169system.cpu.dcache.overall_accesses::total 23787291 # number of overall (read+write) accesses 1170system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027166 # miss rate for ReadReq accesses 1171system.cpu.dcache.ReadReq_miss_rate::total 0.027166 # miss rate for ReadReq accesses 1172system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024477 # miss rate for WriteReq accesses 1173system.cpu.dcache.WriteReq_miss_rate::total 0.024477 # miss rate for WriteReq accesses | 1063system.cpu.dcache.demand_accesses::cpu.data 23787310 # number of demand (read+write) accesses 1064system.cpu.dcache.demand_accesses::total 23787310 # number of demand (read+write) accesses 1065system.cpu.dcache.overall_accesses::cpu.data 23787310 # number of overall (read+write) accesses 1066system.cpu.dcache.overall_accesses::total 23787310 # number of overall (read+write) accesses 1067system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027167 # miss rate for ReadReq accesses 1068system.cpu.dcache.ReadReq_miss_rate::total 0.027167 # miss rate for ReadReq accesses 1069system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024476 # miss rate for WriteReq accesses 1070system.cpu.dcache.WriteReq_miss_rate::total 0.024476 # miss rate for WriteReq accesses |
| 1174system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses 1175system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses 1176system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses 1177system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses 1178system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses 1179system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses | 1071system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046408 # miss rate for LoadLockedReq accesses 1072system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046408 # miss rate for LoadLockedReq accesses 1073system.cpu.dcache.demand_miss_rate::cpu.data 0.026010 # miss rate for demand accesses 1074system.cpu.dcache.demand_miss_rate::total 0.026010 # miss rate for demand accesses 1075system.cpu.dcache.overall_miss_rate::cpu.data 0.026010 # miss rate for overall accesses 1076system.cpu.dcache.overall_miss_rate::total 0.026010 # miss rate for overall accesses |
| 1180system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14618.044550 # average ReadReq miss latency 1181system.cpu.dcache.ReadReq_avg_miss_latency::total 14618.044550 # average ReadReq miss latency 1182system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42458.579339 # average WriteReq miss latency 1183system.cpu.dcache.WriteReq_avg_miss_latency::total 42458.579339 # average WriteReq miss latency 1184system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13903.717391 # average LoadLockedReq miss latency 1185system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13903.717391 # average LoadLockedReq miss latency 1186system.cpu.dcache.demand_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency 1187system.cpu.dcache.demand_avg_miss_latency::total 25877.542601 # average overall miss latency 1188system.cpu.dcache.overall_avg_miss_latency::cpu.data 25877.542601 # average overall miss latency 1189system.cpu.dcache.overall_avg_miss_latency::total 25877.542601 # average overall miss latency | 1077system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14612.083072 # average ReadReq miss latency 1078system.cpu.dcache.ReadReq_avg_miss_latency::total 14612.083072 # average ReadReq miss latency 1079system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42457.361899 # average WriteReq miss latency 1080system.cpu.dcache.WriteReq_avg_miss_latency::total 42457.361899 # average WriteReq miss latency 1081system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13804.391304 # average LoadLockedReq miss latency 1082system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13804.391304 # average LoadLockedReq miss latency 1083system.cpu.dcache.demand_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency 1084system.cpu.dcache.demand_avg_miss_latency::total 25873.058298 # average overall miss latency 1085system.cpu.dcache.overall_avg_miss_latency::cpu.data 25873.058298 # average overall miss latency 1086system.cpu.dcache.overall_avg_miss_latency::total 25873.058298 # average overall miss latency |
| 1190system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1191system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1192system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1193system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1194system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1195system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1196system.cpu.dcache.fast_writes 0 # number of fast writes performed 1197system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1087system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1088system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1089system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1090system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 1091system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1092system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1093system.cpu.dcache.fast_writes 0 # number of fast writes performed 1094system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 1198system.cpu.dcache.writebacks::writebacks 595786 # number of writebacks 1199system.cpu.dcache.writebacks::total 595786 # number of writebacks 1200system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368488 # number of ReadReq MSHR misses 1201system.cpu.dcache.ReadReq_mshr_misses::total 368488 # number of ReadReq MSHR misses 1202system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250225 # number of WriteReq MSHR misses 1203system.cpu.dcache.WriteReq_mshr_misses::total 250225 # number of WriteReq MSHR misses | 1095system.cpu.dcache.writebacks::writebacks 595785 # number of writebacks 1096system.cpu.dcache.writebacks::total 595785 # number of writebacks 1097system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368499 # number of ReadReq MSHR misses 1098system.cpu.dcache.ReadReq_mshr_misses::total 368499 # number of ReadReq MSHR misses 1099system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250216 # number of WriteReq MSHR misses 1100system.cpu.dcache.WriteReq_mshr_misses::total 250216 # number of WriteReq MSHR misses |
| 1204system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses 1205system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses | 1101system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11500 # number of LoadLockedReq MSHR misses 1102system.cpu.dcache.LoadLockedReq_mshr_misses::total 11500 # number of LoadLockedReq MSHR misses |
| 1206system.cpu.dcache.demand_mshr_misses::cpu.data 618713 # number of demand (read+write) MSHR misses 1207system.cpu.dcache.demand_mshr_misses::total 618713 # number of demand (read+write) MSHR misses 1208system.cpu.dcache.overall_mshr_misses::cpu.data 618713 # number of overall MSHR misses 1209system.cpu.dcache.overall_mshr_misses::total 618713 # number of overall MSHR misses 1210system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4644879500 # number of ReadReq MSHR miss cycles 1211system.cpu.dcache.ReadReq_mshr_miss_latency::total 4644879500 # number of ReadReq MSHR miss cycles 1212system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10059088985 # number of WriteReq MSHR miss cycles 1213system.cpu.dcache.WriteReq_mshr_miss_latency::total 10059088985 # number of WriteReq MSHR miss cycles 1214system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 136816250 # number of LoadLockedReq MSHR miss cycles 1215system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 136816250 # number of LoadLockedReq MSHR miss cycles 1216system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14703968485 # number of demand (read+write) MSHR miss cycles 1217system.cpu.dcache.demand_mshr_miss_latency::total 14703968485 # number of demand (read+write) MSHR miss cycles 1218system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14703968485 # number of overall MSHR miss cycles 1219system.cpu.dcache.overall_mshr_miss_latency::total 14703968485 # number of overall MSHR miss cycles 1220system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050953750 # number of ReadReq MSHR uncacheable cycles 1221system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050953750 # number of ReadReq MSHR uncacheable cycles 1222system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234980190 # number of WriteReq MSHR uncacheable cycles 1223system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234980190 # number of WriteReq MSHR uncacheable cycles 1224system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208285933940 # number of overall MSHR uncacheable cycles 1225system.cpu.dcache.overall_mshr_uncacheable_latency::total 208285933940 # number of overall MSHR uncacheable cycles 1226system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027166 # mshr miss rate for ReadReq accesses 1227system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027166 # mshr miss rate for ReadReq accesses 1228system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024477 # mshr miss rate for WriteReq accesses 1229system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024477 # mshr miss rate for WriteReq accesses | 1103system.cpu.dcache.demand_mshr_misses::cpu.data 618715 # number of demand (read+write) MSHR misses 1104system.cpu.dcache.demand_mshr_misses::total 618715 # number of demand (read+write) MSHR misses 1105system.cpu.dcache.overall_mshr_misses::cpu.data 618715 # number of overall MSHR misses 1106system.cpu.dcache.overall_mshr_misses::total 618715 # number of overall MSHR misses 1107system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4642816500 # number of ReadReq MSHR miss cycles 1108system.cpu.dcache.ReadReq_mshr_miss_latency::total 4642816500 # number of ReadReq MSHR miss cycles 1109system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10058410735 # number of WriteReq MSHR miss cycles 1110system.cpu.dcache.WriteReq_mshr_miss_latency::total 10058410735 # number of WriteReq MSHR miss cycles 1111system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135673500 # number of LoadLockedReq MSHR miss cycles 1112system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135673500 # number of LoadLockedReq MSHR miss cycles 1113system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14701227235 # number of demand (read+write) MSHR miss cycles 1114system.cpu.dcache.demand_mshr_miss_latency::total 14701227235 # number of demand (read+write) MSHR miss cycles 1115system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14701227235 # number of overall MSHR miss cycles 1116system.cpu.dcache.overall_mshr_miss_latency::total 14701227235 # number of overall MSHR miss cycles 1117system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050836250 # number of ReadReq MSHR uncacheable cycles 1118system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050836250 # number of ReadReq MSHR uncacheable cycles 1119system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234094465 # number of WriteReq MSHR uncacheable cycles 1120system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234094465 # number of WriteReq MSHR uncacheable cycles 1121system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284930715 # number of overall MSHR uncacheable cycles 1122system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284930715 # number of overall MSHR uncacheable cycles 1123system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027167 # mshr miss rate for ReadReq accesses 1124system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027167 # mshr miss rate for ReadReq accesses 1125system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024476 # mshr miss rate for WriteReq accesses 1126system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024476 # mshr miss rate for WriteReq accesses |
| 1230system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses 1231system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses 1232system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses 1233system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses 1234system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses 1235system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses | 1127system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046408 # mshr miss rate for LoadLockedReq accesses 1128system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046408 # mshr miss rate for LoadLockedReq accesses 1129system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for demand accesses 1130system.cpu.dcache.demand_mshr_miss_rate::total 0.026010 # mshr miss rate for demand accesses 1131system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026010 # mshr miss rate for overall accesses 1132system.cpu.dcache.overall_mshr_miss_rate::total 0.026010 # mshr miss rate for overall accesses |
| 1236system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12605.239519 # average ReadReq mshr miss latency 1237system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12605.239519 # average ReadReq mshr miss latency 1238system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40200.175782 # average WriteReq mshr miss latency 1239system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40200.175782 # average WriteReq mshr miss latency 1240system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11897.065217 # average LoadLockedReq mshr miss latency 1241system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11897.065217 # average LoadLockedReq mshr miss latency 1242system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency 1243system.cpu.dcache.demand_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency 1244system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23765.410594 # average overall mshr miss latency 1245system.cpu.dcache.overall_avg_mshr_miss_latency::total 23765.410594 # average overall mshr miss latency | 1133system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12599.264856 # average ReadReq mshr miss latency 1134system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12599.264856 # average ReadReq mshr miss latency 1135system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40198.911081 # average WriteReq mshr miss latency 1136system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40198.911081 # average WriteReq mshr miss latency 1137system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11797.695652 # average LoadLockedReq mshr miss latency 1138system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11797.695652 # average LoadLockedReq mshr miss latency 1139system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency 1140system.cpu.dcache.demand_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency 1141system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23760.903219 # average overall mshr miss latency 1142system.cpu.dcache.overall_avg_mshr_miss_latency::total 23760.903219 # average overall mshr miss latency |
| 1246system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1247system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1248system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1249system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1250system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1251system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1252system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1143system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1144system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1145system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1146system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1147system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1148system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1149system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1253system.cpu.toL2Bus.throughput 53012095 # Throughput (bytes/s) 1254system.cpu.toL2Bus.trans_dist::ReadReq 2455185 # Transaction distribution 1255system.cpu.toL2Bus.trans_dist::ReadResp 2455185 # Transaction distribution | 1150system.cpu.toL2Bus.throughput 53011951 # Throughput (bytes/s) 1151system.cpu.toL2Bus.trans_dist::ReadReq 2455175 # Transaction distribution 1152system.cpu.toL2Bus.trans_dist::ReadResp 2455175 # Transaction distribution |
| 1256system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution 1257system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution | 1153system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution 1154system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution |
| 1258system.cpu.toL2Bus.trans_dist::Writeback 595786 # Transaction distribution | 1155system.cpu.toL2Bus.trans_dist::Writeback 595785 # Transaction distribution |
| 1259system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution 1260system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution | 1156system.cpu.toL2Bus.trans_dist::UpgradeReq 2898 # Transaction distribution 1157system.cpu.toL2Bus.trans_dist::UpgradeResp 2898 # Transaction distribution |
| 1261system.cpu.toL2Bus.trans_dist::ReadExReq 247327 # Transaction distribution 1262system.cpu.toL2Bus.trans_dist::ReadExResp 247327 # Transaction distribution 1263system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725213 # Packet count per connected master and slave (bytes) 1264system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5751160 # Packet count per connected master and slave (bytes) 1265system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12463 # Packet count per connected master and slave (bytes) 1266system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27463 # Packet count per connected master and slave (bytes) 1267system.cpu.toL2Bus.pkt_count 7516299 # Packet count per connected master and slave (bytes) 1268system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54757044 # Cumulative packet size per connected master and slave (bytes) 1269system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83692777 # Cumulative packet size per connected master and slave (bytes) 1270system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14148 # Cumulative packet size per connected master and slave (bytes) 1271system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34900 # Cumulative packet size per connected master and slave (bytes) 1272system.cpu.toL2Bus.tot_pkt_size 138498869 # Cumulative packet size per connected master and slave (bytes) 1273system.cpu.toL2Bus.data_through_bus 138498869 # Total data (bytes) | 1158system.cpu.toL2Bus.trans_dist::ReadExReq 247318 # Transaction distribution 1159system.cpu.toL2Bus.trans_dist::ReadExResp 247318 # Transaction distribution 1160system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1725171 # Packet count per connected master and slave (bytes) 1161system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5751163 # Packet count per connected master and slave (bytes) 1162system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12463 # Packet count per connected master and slave (bytes) 1163system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27463 # Packet count per connected master and slave (bytes) 1164system.cpu.toL2Bus.pkt_count::total 7516260 # Packet count per connected master and slave (bytes) 1165system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54755700 # Cumulative packet size per connected master and slave (bytes) 1166system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 83692841 # Cumulative packet size per connected master and slave (bytes) 1167system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14148 # Cumulative packet size per connected master and slave (bytes) 1168system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 34900 # Cumulative packet size per connected master and slave (bytes) 1169system.cpu.toL2Bus.tot_pkt_size::total 138497589 # Cumulative packet size per connected master and slave (bytes) 1170system.cpu.toL2Bus.data_through_bus 138497589 # Total data (bytes) |
| 1274system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes) | 1171system.cpu.toL2Bus.snoop_data_through_bus 166632 # Total snoop data (bytes) |
| 1275system.cpu.toL2Bus.reqLayer0.occupancy 3009752500 # Layer occupancy (ticks) | 1172system.cpu.toL2Bus.reqLayer0.occupancy 3009741500 # Layer occupancy (ticks) |
| 1276system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) | 1173system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) |
| 1277system.cpu.toL2Bus.respLayer0.occupancy 1296058500 # Layer occupancy (ticks) | 1174system.cpu.toL2Bus.respLayer0.occupancy 1296026750 # Layer occupancy (ticks) |
| 1278system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1175system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1279system.cpu.toL2Bus.respLayer1.occupancy 2542947575 # Layer occupancy (ticks) | 1176system.cpu.toL2Bus.respLayer1.occupancy 2542955300 # Layer occupancy (ticks) |
| 1280system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1281system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks) 1282system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1283system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks) 1284system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) | 1177system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1178system.cpu.toL2Bus.respLayer2.occupancy 8926500 # Layer occupancy (ticks) 1179system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1180system.cpu.toL2Bus.respLayer3.occupancy 18739250 # Layer occupancy (ticks) 1181system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) |
| 1285system.iocache.tags.replacements 0 # number of replacements 1286system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1287system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1288system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1289system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1290system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1182system.iocache.tags.replacements 0 # number of replacements 1183system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 1184system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1185system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 1186system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 1187system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1291system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1292system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1293system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1294system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1295system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1296system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1297system.iocache.fast_writes 0 # number of fast writes performed 1298system.iocache.cache_copies 0 # number of cache copies performed | 1188system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1189system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1190system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1191system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1192system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1193system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1194system.iocache.fast_writes 0 # number of fast writes performed 1195system.iocache.cache_copies 0 # number of cache copies performed |
| 1299system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of ReadReq MSHR uncacheable cycles 1300system.iocache.ReadReq_mshr_uncacheable_latency::total 1466807214000 # number of ReadReq MSHR uncacheable cycles 1301system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1466807214000 # number of overall MSHR uncacheable cycles 1302system.iocache.overall_mshr_uncacheable_latency::total 1466807214000 # number of overall MSHR uncacheable cycles | 1196system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of ReadReq MSHR uncacheable cycles 1197system.iocache.ReadReq_mshr_uncacheable_latency::total 1460469685500 # number of ReadReq MSHR uncacheable cycles 1198system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1460469685500 # number of overall MSHR uncacheable cycles 1199system.iocache.overall_mshr_uncacheable_latency::total 1460469685500 # number of overall MSHR uncacheable cycles |
| 1303system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1304system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1305system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1306system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1307system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1308 1309---------- End Simulation Statistics ---------- | 1200system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1201system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1202system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1203system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1204system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1205 1206---------- End Simulation Statistics ---------- |