| stats.txt (9490:e6a09d97bdc9) | stats.txt (9568:cd1351d4d850) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 2.603665 # Number of seconds simulated 4sim_ticks 2603664815000 # Number of ticks simulated 5final_tick 2603664815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 2.603674 # Number of seconds simulated 4sim_ticks 2603674284000 # Number of ticks simulated 5final_tick 2603674284000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 536000 # Simulator instruction rate (inst/s) 8host_op_rate 682052 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 23183028791 # Simulator tick rate (ticks/s) 10host_mem_usage 404656 # Number of bytes of host memory used 11host_seconds 112.31 # Real time elapsed on the host 12sim_insts 60197643 # Number of instructions simulated 13sim_ops 76600583 # Number of ops (including micro ops) simulated | 7host_inst_rate 271279 # Simulator instruction rate (inst/s) 8host_op_rate 345198 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11733407598 # Simulator tick rate (ticks/s) 10host_mem_usage 403640 # Number of bytes of host memory used 11host_seconds 221.90 # Real time elapsed on the host 12sim_insts 60197457 # Number of instructions simulated 13sim_ops 76600355 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory | 14system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory 19system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory | 17system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory 19system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory |
| 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory | 23system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory |
| 24system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory | 24system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory |
| 25system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory | 25system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory | 28system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory 30system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory 31system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory |
| 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory | 32system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory |
| 33system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47119503 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory 34system.physmem.bw_read::realview.clcd 47119332 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) | 35system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) |
| 37system.physmem.bw_read::cpu.inst 270695 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3475919 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 50866314 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 270695 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 270695 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1412434 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1158395 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2570829 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1412434 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47119503 # Total bandwidth to/from this memory (bytes/s) | 37system.physmem.bw_read::cpu.inst 270817 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.data 3475931 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 50866276 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 270817 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 270817 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1412478 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::cpu.data 1158391 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_write::total 2570868 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_total::writebacks 1412478 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::realview.clcd 47119332 # Total bandwidth to/from this memory (bytes/s) |
| 47system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) | 47system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) |
| 49system.physmem.bw_total::cpu.inst 270695 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4634314 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53437143 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15494089 # Total number of read requests seen 53system.physmem.writeReqs 811479 # Total number of write requests seen 54system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 991621696 # Total number of bytes read from memory 56system.physmem.bytesWritten 51934656 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() | 49system.physmem.bw_total::cpu.inst 270817 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.data 4634322 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::total 53437145 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.readReqs 15494095 # Total number of read requests seen 53system.physmem.writeReqs 811481 # Total number of write requests seen 54system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady 55system.physmem.bytesRead 991622080 # Total number of bytes read from memory 56system.physmem.bytesWritten 51934784 # Total number of bytes written to memory 57system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() 58system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() |
| 59system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis | 59system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q 60system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed 61system.physmem.perBankRdReqs::0 974844 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::1 967900 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::2 967764 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::3 968566 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::4 968387 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::5 967635 # Track reads on a per bank basis 67system.physmem.perBankRdReqs::6 967737 # Track reads on a per bank basis 68system.physmem.perBankRdReqs::7 968249 # Track reads on a per bank basis |
| 69system.physmem.perBankRdReqs::8 968097 # Track reads on a per bank basis | 69system.physmem.perBankRdReqs::8 968100 # Track reads on a per bank basis |
| 70system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis | 70system.physmem.perBankRdReqs::9 967668 # Track reads on a per bank basis 71system.physmem.perBankRdReqs::10 967710 # Track reads on a per bank basis 72system.physmem.perBankRdReqs::11 968007 # Track reads on a per bank basis 73system.physmem.perBankRdReqs::12 968101 # Track reads on a per bank basis 74system.physmem.perBankRdReqs::13 967570 # Track reads on a per bank basis |
| 75system.physmem.perBankRdReqs::14 967431 # Track reads on a per bank basis | 75system.physmem.perBankRdReqs::14 967434 # Track reads on a per bank basis |
| 76system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis | 76system.physmem.perBankRdReqs::15 968087 # Track reads on a per bank basis 77system.physmem.perBankWrReqs::0 50753 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::1 50356 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::2 50308 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::3 51002 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::4 50784 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::5 50139 # Track writes on a per bank basis 83system.physmem.perBankWrReqs::6 50212 # Track writes on a per bank basis 84system.physmem.perBankWrReqs::7 50710 # Track writes on a per bank basis |
| 85system.physmem.perBankWrReqs::8 51141 # Track writes on a per bank basis | 85system.physmem.perBankWrReqs::8 51142 # Track writes on a per bank basis |
| 86system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis | 86system.physmem.perBankWrReqs::9 50687 # Track writes on a per bank basis 87system.physmem.perBankWrReqs::10 50724 # Track writes on a per bank basis 88system.physmem.perBankWrReqs::11 51058 # Track writes on a per bank basis 89system.physmem.perBankWrReqs::12 51155 # Track writes on a per bank basis 90system.physmem.perBankWrReqs::13 50650 # Track writes on a per bank basis |
| 91system.physmem.perBankWrReqs::14 50586 # Track writes on a per bank basis | 91system.physmem.perBankWrReqs::14 50587 # Track writes on a per bank basis |
| 92system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 92system.physmem.perBankWrReqs::15 51214 # Track writes on a per bank basis 93system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 94system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 95system.physmem.totGap 2603660455000 # Total gap between requests | 95system.physmem.totGap 2603669924000 # Total gap between requests |
| 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 6652 # Categorize read packet sizes 99system.physmem.readPktSize::3 15335424 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes | 96system.physmem.readPktSize::0 0 # Categorize read packet sizes 97system.physmem.readPktSize::1 0 # Categorize read packet sizes 98system.physmem.readPktSize::2 6652 # Categorize read packet sizes 99system.physmem.readPktSize::3 15335424 # Categorize read packet sizes 100system.physmem.readPktSize::4 0 # Categorize read packet sizes 101system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 102system.physmem.readPktSize::6 152013 # Categorize read packet sizes 103system.physmem.readPktSize::7 0 # Categorize read packet sizes 104system.physmem.readPktSize::8 0 # Categorize read packet sizes 105system.physmem.writePktSize::0 0 # categorize write packet sizes 106system.physmem.writePktSize::1 0 # categorize write packet sizes 107system.physmem.writePktSize::2 754018 # categorize write packet sizes 108system.physmem.writePktSize::3 0 # categorize write packet sizes 109system.physmem.writePktSize::4 0 # categorize write packet sizes 110system.physmem.writePktSize::5 0 # categorize write packet sizes 111system.physmem.writePktSize::6 57461 # categorize write packet sizes 112system.physmem.writePktSize::7 0 # categorize write packet sizes 113system.physmem.writePktSize::8 0 # categorize write packet sizes 114system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 115system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 116system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 117system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 118system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 119system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 120system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes 121system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 122system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 123system.physmem.rdQLenPdf::0 1115727 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::1 960917 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::2 976016 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::3 3645957 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::4 2755251 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::5 2758222 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::6 2725008 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::7 64130 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::8 62311 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::9 112850 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::10 163186 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::11 112416 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::12 10693 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::13 10526 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::14 10327 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::15 10120 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see | 102system.physmem.readPktSize::6 152019 # Categorize read packet sizes 103system.physmem.writePktSize::0 0 # Categorize write packet sizes 104system.physmem.writePktSize::1 0 # Categorize write packet sizes 105system.physmem.writePktSize::2 754018 # Categorize write packet sizes 106system.physmem.writePktSize::3 0 # Categorize write packet sizes 107system.physmem.writePktSize::4 0 # Categorize write packet sizes 108system.physmem.writePktSize::5 0 # Categorize write packet sizes 109system.physmem.writePktSize::6 57463 # Categorize write packet sizes 110system.physmem.rdQLenPdf::0 1115862 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::1 960938 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::2 976049 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::3 3645924 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::4 2755202 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::5 2757935 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::6 2724600 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::7 64133 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::8 62351 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::9 112886 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::10 163253 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::11 112534 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::12 10838 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::13 10625 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::14 10371 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::15 10165 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see |
| 140system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 127system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 155system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 156system.physmem.wrQLenPdf::0 35112 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::1 35261 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::2 35264 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::3 35271 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::4 35275 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::5 35275 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::6 35279 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::7 35281 # What write queue length does an incoming req see | 142system.physmem.wrQLenPdf::0 35038 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::1 35268 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::2 35271 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::3 35273 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::4 35278 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::5 35278 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::6 35280 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::7 35280 # What write queue length does an incoming req see |
| 164system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see | 150system.physmem.wrQLenPdf::8 35282 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::9 35282 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::10 35282 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::11 35282 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::12 35282 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see |
| 172system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see | 158system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see |
| 174system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see | 160system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see |
| 179system.physmem.wrQLenPdf::23 170 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::24 21 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::26 11 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see | 165system.physmem.wrQLenPdf::23 244 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::24 14 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::25 11 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::26 9 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::27 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see |
| 187system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 173system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 188system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 189system.physmem.totQLat 341507754589 # Total cycles spent in queuing delays 190system.physmem.totMemAccLat 436421735839 # Sum of mem lat for all requests 191system.physmem.totBusLat 77468765000 # Total cycles spent in databus access 192system.physmem.totBankLat 17445216250 # Total cycles spent in bank access 193system.physmem.avgQLat 22041.64 # Average queueing delay per request 194system.physmem.avgBankLat 1125.95 # Average bank access latency per request | 174system.physmem.totQLat 341488215750 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 436408620750 # Sum of mem lat for all requests 176system.physmem.totBusLat 77468795000 # Total cycles spent in databus access 177system.physmem.totBankLat 17451610000 # Total cycles spent in bank access 178system.physmem.avgQLat 22040.37 # Average queueing delay per request 179system.physmem.avgBankLat 1126.36 # Average bank access latency per request |
| 195system.physmem.avgBusLat 5000.00 # Average bus latency per request | 180system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 196system.physmem.avgMemAccLat 28167.59 # Average memory access latency 197system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s | 181system.physmem.avgMemAccLat 28166.74 # Average memory access latency 182system.physmem.avgRdBW 380.85 # Average achieved read bandwidth in MB/s |
| 198system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s 199system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s 200system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s 201system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 202system.physmem.busUtil 3.13 # Data bus utilization in percentage 203system.physmem.avgRdQLen 0.17 # Average read queue length over time | 183system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 3.13 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.17 # Average read queue length over time |
| 204system.physmem.avgWrQLen 12.39 # Average write queue length over time 205system.physmem.readRowHits 15418905 # Number of row buffer hits during reads 206system.physmem.writeRowHits 794060 # Number of row buffer hits during writes | 189system.physmem.avgWrQLen 12.40 # Average write queue length over time 190system.physmem.readRowHits 15418728 # Number of row buffer hits during reads 191system.physmem.writeRowHits 794030 # Number of row buffer hits during writes |
| 207system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads 208system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes | 192system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 97.85 # Row buffer hit rate for writes |
| 209system.physmem.avgGap 159679.22 # Average gap between requests | 194system.physmem.avgGap 159679.73 # Average gap between requests |
| 210system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 211system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 212system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 213system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 214system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 215system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 216system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 217system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) --- 4 unchanged lines hidden (view full) --- 222system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 223system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 224system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 225system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 226system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 227system.cf0.dma_write_txs 0 # Number of DMA write transactions. 228system.cpu.dtb.inst_hits 0 # ITB inst hits 229system.cpu.dtb.inst_misses 0 # ITB inst misses | 195system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 196system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 197system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 198system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 199system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 200system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 201system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) 202system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) --- 4 unchanged lines hidden (view full) --- 207system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 208system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 209system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 210system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 211system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 212system.cf0.dma_write_txs 0 # Number of DMA write transactions. 213system.cpu.dtb.inst_hits 0 # ITB inst hits 214system.cpu.dtb.inst_misses 0 # ITB inst misses |
| 230system.cpu.dtb.read_hits 14995667 # DTB read hits | 215system.cpu.dtb.read_hits 14995645 # DTB read hits |
| 231system.cpu.dtb.read_misses 7332 # DTB read misses | 216system.cpu.dtb.read_misses 7332 # DTB read misses |
| 232system.cpu.dtb.write_hits 11230865 # DTB write hits | 217system.cpu.dtb.write_hits 11230857 # DTB write hits |
| 233system.cpu.dtb.write_misses 2203 # DTB write misses 234system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 235system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 236system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 237system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 238system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB 239system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 240system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch 241system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 242system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions | 218system.cpu.dtb.write_misses 2203 # DTB write misses 219system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed 220system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 221system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 222system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 223system.cpu.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB 224system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 225system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch 226system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 227system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions |
| 243system.cpu.dtb.read_accesses 15002999 # DTB read accesses 244system.cpu.dtb.write_accesses 11233068 # DTB write accesses | 228system.cpu.dtb.read_accesses 15002977 # DTB read accesses 229system.cpu.dtb.write_accesses 11233060 # DTB write accesses |
| 245system.cpu.dtb.inst_accesses 0 # ITB inst accesses | 230system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| 246system.cpu.dtb.hits 26226532 # DTB hits | 231system.cpu.dtb.hits 26226502 # DTB hits |
| 247system.cpu.dtb.misses 9535 # DTB misses | 232system.cpu.dtb.misses 9535 # DTB misses |
| 248system.cpu.dtb.accesses 26236067 # DTB accesses 249system.cpu.itb.inst_hits 61491584 # ITB inst hits | 233system.cpu.dtb.accesses 26236037 # DTB accesses 234system.cpu.itb.inst_hits 61491397 # ITB inst hits |
| 250system.cpu.itb.inst_misses 4471 # ITB inst misses 251system.cpu.itb.read_hits 0 # DTB read hits 252system.cpu.itb.read_misses 0 # DTB read misses 253system.cpu.itb.write_hits 0 # DTB write hits 254system.cpu.itb.write_misses 0 # DTB write misses 255system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 256system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 257system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 258system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 259system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 260system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 261system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 262system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 263system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 264system.cpu.itb.read_accesses 0 # DTB read accesses 265system.cpu.itb.write_accesses 0 # DTB write accesses | 235system.cpu.itb.inst_misses 4471 # ITB inst misses 236system.cpu.itb.read_hits 0 # DTB read hits 237system.cpu.itb.read_misses 0 # DTB read misses 238system.cpu.itb.write_hits 0 # DTB write hits 239system.cpu.itb.write_misses 0 # DTB write misses 240system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed 241system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 242system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 243system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 244system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB 245system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 246system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 247system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 248system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 249system.cpu.itb.read_accesses 0 # DTB read accesses 250system.cpu.itb.write_accesses 0 # DTB write accesses |
| 266system.cpu.itb.inst_accesses 61496055 # ITB inst accesses 267system.cpu.itb.hits 61491584 # DTB hits | 251system.cpu.itb.inst_accesses 61495868 # ITB inst accesses 252system.cpu.itb.hits 61491397 # DTB hits |
| 268system.cpu.itb.misses 4471 # DTB misses | 253system.cpu.itb.misses 4471 # DTB misses |
| 269system.cpu.itb.accesses 61496055 # DTB accesses 270system.cpu.numCycles 5207329630 # number of cpu cycles simulated | 254system.cpu.itb.accesses 61495868 # DTB accesses 255system.cpu.numCycles 5207348568 # number of cpu cycles simulated |
| 271system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 272system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 256system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 257system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 273system.cpu.committedInsts 60197643 # Number of instructions committed 274system.cpu.committedOps 76600583 # Number of ops (including micro ops) committed 275system.cpu.num_int_alu_accesses 68868344 # Number of integer alu accesses | 258system.cpu.committedInsts 60197457 # Number of instructions committed 259system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed 260system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses |
| 276system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses | 261system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses |
| 277system.cpu.num_func_calls 2139730 # number of times a function call or return occured 278system.cpu.num_conditional_control_insts 7947806 # number of instructions that are conditional controls 279system.cpu.num_int_insts 68868344 # number of integer instructions | 262system.cpu.num_func_calls 2139722 # number of times a function call or return occured 263system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls 264system.cpu.num_int_insts 68868122 # number of integer instructions |
| 280system.cpu.num_fp_insts 10269 # number of float instructions | 265system.cpu.num_fp_insts 10269 # number of float instructions |
| 281system.cpu.num_int_register_reads 394756284 # number of times the integer registers were read 282system.cpu.num_int_register_writes 74176271 # number of times the integer registers were written | 266system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read 267system.cpu.num_int_register_writes 74176013 # number of times the integer registers were written |
| 283system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 284system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written | 268system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read 269system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written |
| 285system.cpu.num_mem_refs 27393912 # number of memory refs 286system.cpu.num_load_insts 15659685 # Number of load instructions 287system.cpu.num_store_insts 11734227 # Number of store instructions 288system.cpu.num_idle_cycles 4579092870.576241 # Number of idle cycles 289system.cpu.num_busy_cycles 628236759.423759 # Number of busy cycles 290system.cpu.not_idle_fraction 0.120645 # Percentage of non-idle cycles 291system.cpu.idle_fraction 0.879355 # Percentage of idle cycles | 270system.cpu.num_mem_refs 27393871 # number of memory refs 271system.cpu.num_load_insts 15659652 # Number of load instructions 272system.cpu.num_store_insts 11734219 # Number of store instructions 273system.cpu.num_idle_cycles 4579092042.576241 # Number of idle cycles 274system.cpu.num_busy_cycles 628256525.423759 # Number of busy cycles 275system.cpu.not_idle_fraction 0.120648 # Percentage of non-idle cycles 276system.cpu.idle_fraction 0.879352 # Percentage of idle cycles |
| 292system.cpu.kern.inst.arm 0 # number of arm instructions executed 293system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed | 277system.cpu.kern.inst.arm 0 # number of arm instructions executed 278system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed |
| 294system.cpu.icache.replacements 855486 # number of replacements 295system.cpu.icache.tagsinuse 510.979431 # Cycle average of tags in use 296system.cpu.icache.total_refs 60635586 # Total number of references to valid blocks. 297system.cpu.icache.sampled_refs 855998 # Sample count of references to valid blocks. 298system.cpu.icache.avg_refs 70.836130 # Average number of references to valid blocks. | 279system.cpu.icache.replacements 855484 # number of replacements 280system.cpu.icache.tagsinuse 510.979435 # Cycle average of tags in use 281system.cpu.icache.total_refs 60635401 # Total number of references to valid blocks. 282system.cpu.icache.sampled_refs 855996 # Sample count of references to valid blocks. 283system.cpu.icache.avg_refs 70.836080 # Average number of references to valid blocks. |
| 299system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. | 284system.cpu.icache.warmup_cycle 18713179000 # Cycle when the warmup percentage was hit. |
| 300system.cpu.icache.occ_blocks::cpu.inst 510.979431 # Average occupied blocks per requestor | 285system.cpu.icache.occ_blocks::cpu.inst 510.979435 # Average occupied blocks per requestor |
| 301system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy 302system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy | 286system.cpu.icache.occ_percent::cpu.inst 0.998007 # Average percentage of cache occupancy 287system.cpu.icache.occ_percent::total 0.998007 # Average percentage of cache occupancy |
| 303system.cpu.icache.ReadReq_hits::cpu.inst 60635586 # number of ReadReq hits 304system.cpu.icache.ReadReq_hits::total 60635586 # number of ReadReq hits 305system.cpu.icache.demand_hits::cpu.inst 60635586 # number of demand (read+write) hits 306system.cpu.icache.demand_hits::total 60635586 # number of demand (read+write) hits 307system.cpu.icache.overall_hits::cpu.inst 60635586 # number of overall hits 308system.cpu.icache.overall_hits::total 60635586 # number of overall hits 309system.cpu.icache.ReadReq_misses::cpu.inst 855998 # number of ReadReq misses 310system.cpu.icache.ReadReq_misses::total 855998 # number of ReadReq misses 311system.cpu.icache.demand_misses::cpu.inst 855998 # number of demand (read+write) misses 312system.cpu.icache.demand_misses::total 855998 # number of demand (read+write) misses 313system.cpu.icache.overall_misses::cpu.inst 855998 # number of overall misses 314system.cpu.icache.overall_misses::total 855998 # number of overall misses 315system.cpu.icache.ReadReq_miss_latency::cpu.inst 11569304000 # number of ReadReq miss cycles 316system.cpu.icache.ReadReq_miss_latency::total 11569304000 # number of ReadReq miss cycles 317system.cpu.icache.demand_miss_latency::cpu.inst 11569304000 # number of demand (read+write) miss cycles 318system.cpu.icache.demand_miss_latency::total 11569304000 # number of demand (read+write) miss cycles 319system.cpu.icache.overall_miss_latency::cpu.inst 11569304000 # number of overall miss cycles 320system.cpu.icache.overall_miss_latency::total 11569304000 # number of overall miss cycles 321system.cpu.icache.ReadReq_accesses::cpu.inst 61491584 # number of ReadReq accesses(hits+misses) 322system.cpu.icache.ReadReq_accesses::total 61491584 # number of ReadReq accesses(hits+misses) 323system.cpu.icache.demand_accesses::cpu.inst 61491584 # number of demand (read+write) accesses 324system.cpu.icache.demand_accesses::total 61491584 # number of demand (read+write) accesses 325system.cpu.icache.overall_accesses::cpu.inst 61491584 # number of overall (read+write) accesses 326system.cpu.icache.overall_accesses::total 61491584 # number of overall (read+write) accesses | 288system.cpu.icache.ReadReq_hits::cpu.inst 60635401 # number of ReadReq hits 289system.cpu.icache.ReadReq_hits::total 60635401 # number of ReadReq hits 290system.cpu.icache.demand_hits::cpu.inst 60635401 # number of demand (read+write) hits 291system.cpu.icache.demand_hits::total 60635401 # number of demand (read+write) hits 292system.cpu.icache.overall_hits::cpu.inst 60635401 # number of overall hits 293system.cpu.icache.overall_hits::total 60635401 # number of overall hits 294system.cpu.icache.ReadReq_misses::cpu.inst 855996 # number of ReadReq misses 295system.cpu.icache.ReadReq_misses::total 855996 # number of ReadReq misses 296system.cpu.icache.demand_misses::cpu.inst 855996 # number of demand (read+write) misses 297system.cpu.icache.demand_misses::total 855996 # number of demand (read+write) misses 298system.cpu.icache.overall_misses::cpu.inst 855996 # number of overall misses 299system.cpu.icache.overall_misses::total 855996 # number of overall misses 300system.cpu.icache.ReadReq_miss_latency::cpu.inst 11568776000 # number of ReadReq miss cycles 301system.cpu.icache.ReadReq_miss_latency::total 11568776000 # number of ReadReq miss cycles 302system.cpu.icache.demand_miss_latency::cpu.inst 11568776000 # number of demand (read+write) miss cycles 303system.cpu.icache.demand_miss_latency::total 11568776000 # number of demand (read+write) miss cycles 304system.cpu.icache.overall_miss_latency::cpu.inst 11568776000 # number of overall miss cycles 305system.cpu.icache.overall_miss_latency::total 11568776000 # number of overall miss cycles 306system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) 307system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) 308system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses 309system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses 310system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses 311system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses |
| 327system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses 328system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses 329system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses 330system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses 331system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses 332system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses | 312system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses 313system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses 314system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses 315system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses 316system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses 317system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses |
| 333system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13515.573635 # average ReadReq miss latency 334system.cpu.icache.ReadReq_avg_miss_latency::total 13515.573635 # average ReadReq miss latency 335system.cpu.icache.demand_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency 336system.cpu.icache.demand_avg_miss_latency::total 13515.573635 # average overall miss latency 337system.cpu.icache.overall_avg_miss_latency::cpu.inst 13515.573635 # average overall miss latency 338system.cpu.icache.overall_avg_miss_latency::total 13515.573635 # average overall miss latency | 318system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13514.988388 # average ReadReq miss latency 319system.cpu.icache.ReadReq_avg_miss_latency::total 13514.988388 # average ReadReq miss latency 320system.cpu.icache.demand_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency 321system.cpu.icache.demand_avg_miss_latency::total 13514.988388 # average overall miss latency 322system.cpu.icache.overall_avg_miss_latency::cpu.inst 13514.988388 # average overall miss latency 323system.cpu.icache.overall_avg_miss_latency::total 13514.988388 # average overall miss latency |
| 339system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 340system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 341system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 342system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 343system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 344system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 345system.cpu.icache.fast_writes 0 # number of fast writes performed 346system.cpu.icache.cache_copies 0 # number of cache copies performed | 324system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 325system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 326system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 327system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 328system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 329system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 330system.cpu.icache.fast_writes 0 # number of fast writes performed 331system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 347system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855998 # number of ReadReq MSHR misses 348system.cpu.icache.ReadReq_mshr_misses::total 855998 # number of ReadReq MSHR misses 349system.cpu.icache.demand_mshr_misses::cpu.inst 855998 # number of demand (read+write) MSHR misses 350system.cpu.icache.demand_mshr_misses::total 855998 # number of demand (read+write) MSHR misses 351system.cpu.icache.overall_mshr_misses::cpu.inst 855998 # number of overall MSHR misses 352system.cpu.icache.overall_mshr_misses::total 855998 # number of overall MSHR misses 353system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9857308000 # number of ReadReq MSHR miss cycles 354system.cpu.icache.ReadReq_mshr_miss_latency::total 9857308000 # number of ReadReq MSHR miss cycles 355system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9857308000 # number of demand (read+write) MSHR miss cycles 356system.cpu.icache.demand_mshr_miss_latency::total 9857308000 # number of demand (read+write) MSHR miss cycles 357system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9857308000 # number of overall MSHR miss cycles 358system.cpu.icache.overall_mshr_miss_latency::total 9857308000 # number of overall MSHR miss cycles | 332system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855996 # number of ReadReq MSHR misses 333system.cpu.icache.ReadReq_mshr_misses::total 855996 # number of ReadReq MSHR misses 334system.cpu.icache.demand_mshr_misses::cpu.inst 855996 # number of demand (read+write) MSHR misses 335system.cpu.icache.demand_mshr_misses::total 855996 # number of demand (read+write) MSHR misses 336system.cpu.icache.overall_mshr_misses::cpu.inst 855996 # number of overall MSHR misses 337system.cpu.icache.overall_mshr_misses::total 855996 # number of overall MSHR misses 338system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9856784000 # number of ReadReq MSHR miss cycles 339system.cpu.icache.ReadReq_mshr_miss_latency::total 9856784000 # number of ReadReq MSHR miss cycles 340system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9856784000 # number of demand (read+write) MSHR miss cycles 341system.cpu.icache.demand_mshr_miss_latency::total 9856784000 # number of demand (read+write) MSHR miss cycles 342system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9856784000 # number of overall MSHR miss cycles 343system.cpu.icache.overall_mshr_miss_latency::total 9856784000 # number of overall MSHR miss cycles |
| 359system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 298856500 # number of ReadReq MSHR uncacheable cycles 360system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles 361system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 298856500 # number of overall MSHR uncacheable cycles 362system.cpu.icache.overall_mshr_uncacheable_latency::total 298856500 # number of overall MSHR uncacheable cycles 363system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses 364system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses 365system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses 366system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses 367system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses 368system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses | 344system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 298856500 # number of ReadReq MSHR uncacheable cycles 345system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 298856500 # number of ReadReq MSHR uncacheable cycles 346system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 298856500 # number of overall MSHR uncacheable cycles 347system.cpu.icache.overall_mshr_uncacheable_latency::total 298856500 # number of overall MSHR uncacheable cycles 348system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for ReadReq accesses 349system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses 350system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for demand accesses 351system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses 352system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses 353system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses |
| 369system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11515.573635 # average ReadReq mshr miss latency 370system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11515.573635 # average ReadReq mshr miss latency 371system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency 372system.cpu.icache.demand_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency 373system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11515.573635 # average overall mshr miss latency 374system.cpu.icache.overall_avg_mshr_miss_latency::total 11515.573635 # average overall mshr miss latency | 354system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11514.988388 # average ReadReq mshr miss latency 355system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11514.988388 # average ReadReq mshr miss latency 356system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11514.988388 # average overall mshr miss latency 357system.cpu.icache.demand_avg_mshr_miss_latency::total 11514.988388 # average overall mshr miss latency 358system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11514.988388 # average overall mshr miss latency 359system.cpu.icache.overall_avg_mshr_miss_latency::total 11514.988388 # average overall mshr miss latency |
| 375system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 376system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 377system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 378system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 360system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 361system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 362system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 363system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 364system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 380system.cpu.l2cache.replacements 61906 # number of replacements 381system.cpu.l2cache.tagsinuse 50893.814517 # Cycle average of tags in use 382system.cpu.l2cache.total_refs 1682715 # Total number of references to valid blocks. 383system.cpu.l2cache.sampled_refs 127287 # Sample count of references to valid blocks. 384system.cpu.l2cache.avg_refs 13.219850 # Average number of references to valid blocks. 385system.cpu.l2cache.warmup_cycle 2553152311000 # Cycle when the warmup percentage was hit. 386system.cpu.l2cache.occ_blocks::writebacks 37867.919206 # Average occupied blocks per requestor | 365system.cpu.l2cache.replacements 61912 # number of replacements 366system.cpu.l2cache.tagsinuse 50892.966587 # Cycle average of tags in use 367system.cpu.l2cache.total_refs 1682705 # Total number of references to valid blocks. 368system.cpu.l2cache.sampled_refs 127293 # Sample count of references to valid blocks. 369system.cpu.l2cache.avg_refs 13.219148 # Average number of references to valid blocks. 370system.cpu.l2cache.warmup_cycle 2553153097000 # Cycle when the warmup percentage was hit. 371system.cpu.l2cache.occ_blocks::writebacks 37868.000507 # Average occupied blocks per requestor |
| 387system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885514 # Average occupied blocks per requestor 388system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001401 # Average occupied blocks per requestor | 372system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.885514 # Average occupied blocks per requestor 373system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.001401 # Average occupied blocks per requestor |
| 389system.cpu.l2cache.occ_blocks::cpu.inst 6996.279505 # Average occupied blocks per requestor 390system.cpu.l2cache.occ_blocks::cpu.data 6025.728892 # Average occupied blocks per requestor 391system.cpu.l2cache.occ_percent::writebacks 0.577819 # Average percentage of cache occupancy | 374system.cpu.l2cache.occ_blocks::cpu.inst 6995.362387 # Average occupied blocks per requestor 375system.cpu.l2cache.occ_blocks::cpu.data 6025.716777 # Average occupied blocks per requestor 376system.cpu.l2cache.occ_percent::writebacks 0.577820 # Average percentage of cache occupancy |
| 392system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 393system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy | 377system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy 378system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy |
| 394system.cpu.l2cache.occ_percent::cpu.inst 0.106755 # Average percentage of cache occupancy | 379system.cpu.l2cache.occ_percent::cpu.inst 0.106741 # Average percentage of cache occupancy |
| 395system.cpu.l2cache.occ_percent::cpu.data 0.091945 # Average percentage of cache occupancy | 380system.cpu.l2cache.occ_percent::cpu.data 0.091945 # Average percentage of cache occupancy |
| 396system.cpu.l2cache.occ_percent::total 0.776578 # Average percentage of cache occupancy | 381system.cpu.l2cache.occ_percent::total 0.776565 # Average percentage of cache occupancy |
| 397system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8701 # number of ReadReq hits 398system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits | 382system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8701 # number of ReadReq hits 383system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3548 # number of ReadReq hits |
| 399system.cpu.l2cache.ReadReq_hits::cpu.inst 843761 # number of ReadReq hits 400system.cpu.l2cache.ReadReq_hits::cpu.data 370335 # number of ReadReq hits 401system.cpu.l2cache.ReadReq_hits::total 1226345 # number of ReadReq hits 402system.cpu.l2cache.Writeback_hits::writebacks 596039 # number of Writeback hits 403system.cpu.l2cache.Writeback_hits::total 596039 # number of Writeback hits | 384system.cpu.l2cache.ReadReq_hits::cpu.inst 843754 # number of ReadReq hits 385system.cpu.l2cache.ReadReq_hits::cpu.data 370328 # number of ReadReq hits 386system.cpu.l2cache.ReadReq_hits::total 1226331 # number of ReadReq hits 387system.cpu.l2cache.Writeback_hits::writebacks 596040 # number of Writeback hits 388system.cpu.l2cache.Writeback_hits::total 596040 # number of Writeback hits |
| 404system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 405system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits | 389system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 390system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits |
| 406system.cpu.l2cache.ReadExReq_hits::cpu.data 114427 # number of ReadExReq hits 407system.cpu.l2cache.ReadExReq_hits::total 114427 # number of ReadExReq hits | 391system.cpu.l2cache.ReadExReq_hits::cpu.data 114438 # number of ReadExReq hits 392system.cpu.l2cache.ReadExReq_hits::total 114438 # number of ReadExReq hits |
| 408system.cpu.l2cache.demand_hits::cpu.dtb.walker 8701 # number of demand (read+write) hits 409system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits | 393system.cpu.l2cache.demand_hits::cpu.dtb.walker 8701 # number of demand (read+write) hits 394system.cpu.l2cache.demand_hits::cpu.itb.walker 3548 # number of demand (read+write) hits |
| 410system.cpu.l2cache.demand_hits::cpu.inst 843761 # number of demand (read+write) hits 411system.cpu.l2cache.demand_hits::cpu.data 484762 # number of demand (read+write) hits 412system.cpu.l2cache.demand_hits::total 1340772 # number of demand (read+write) hits | 395system.cpu.l2cache.demand_hits::cpu.inst 843754 # number of demand (read+write) hits 396system.cpu.l2cache.demand_hits::cpu.data 484766 # number of demand (read+write) hits 397system.cpu.l2cache.demand_hits::total 1340769 # number of demand (read+write) hits |
| 413system.cpu.l2cache.overall_hits::cpu.dtb.walker 8701 # number of overall hits 414system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits | 398system.cpu.l2cache.overall_hits::cpu.dtb.walker 8701 # number of overall hits 399system.cpu.l2cache.overall_hits::cpu.itb.walker 3548 # number of overall hits |
| 415system.cpu.l2cache.overall_hits::cpu.inst 843761 # number of overall hits 416system.cpu.l2cache.overall_hits::cpu.data 484762 # number of overall hits 417system.cpu.l2cache.overall_hits::total 1340772 # number of overall hits | 400system.cpu.l2cache.overall_hits::cpu.inst 843754 # number of overall hits 401system.cpu.l2cache.overall_hits::cpu.data 484766 # number of overall hits 402system.cpu.l2cache.overall_hits::total 1340769 # number of overall hits |
| 418system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 419system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses | 403system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses 404system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses |
| 420system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses 421system.cpu.l2cache.ReadReq_misses::cpu.data 9858 # number of ReadReq misses 422system.cpu.l2cache.ReadReq_misses::total 20465 # number of ReadReq misses | 405system.cpu.l2cache.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses 406system.cpu.l2cache.ReadReq_misses::cpu.data 9859 # number of ReadReq misses 407system.cpu.l2cache.ReadReq_misses::total 20471 # number of ReadReq misses |
| 423system.cpu.l2cache.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses 424system.cpu.l2cache.UpgradeReq_misses::total 2875 # number of UpgradeReq misses 425system.cpu.l2cache.ReadExReq_misses::cpu.data 133183 # number of ReadExReq misses 426system.cpu.l2cache.ReadExReq_misses::total 133183 # number of ReadExReq misses 427system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 428system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses | 408system.cpu.l2cache.UpgradeReq_misses::cpu.data 2875 # number of UpgradeReq misses 409system.cpu.l2cache.UpgradeReq_misses::total 2875 # number of UpgradeReq misses 410system.cpu.l2cache.ReadExReq_misses::cpu.data 133183 # number of ReadExReq misses 411system.cpu.l2cache.ReadExReq_misses::total 133183 # number of ReadExReq misses 412system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses 413system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses |
| 429system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses 430system.cpu.l2cache.demand_misses::cpu.data 143041 # number of demand (read+write) misses 431system.cpu.l2cache.demand_misses::total 153648 # number of demand (read+write) misses | 414system.cpu.l2cache.demand_misses::cpu.inst 10604 # number of demand (read+write) misses 415system.cpu.l2cache.demand_misses::cpu.data 143042 # number of demand (read+write) misses 416system.cpu.l2cache.demand_misses::total 153654 # number of demand (read+write) misses |
| 432system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 433system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses | 417system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses 418system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses |
| 434system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses 435system.cpu.l2cache.overall_misses::cpu.data 143041 # number of overall misses 436system.cpu.l2cache.overall_misses::total 153648 # number of overall misses | 419system.cpu.l2cache.overall_misses::cpu.inst 10604 # number of overall misses 420system.cpu.l2cache.overall_misses::cpu.data 143042 # number of overall misses 421system.cpu.l2cache.overall_misses::total 153654 # number of overall misses |
| 437system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 315500 # number of ReadReq miss cycles 438system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 151000 # number of ReadReq miss cycles | 422system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 315500 # number of ReadReq miss cycles 423system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 151000 # number of ReadReq miss cycles |
| 439system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 562062000 # number of ReadReq miss cycles 440system.cpu.l2cache.ReadReq_miss_latency::cpu.data 534519000 # number of ReadReq miss cycles 441system.cpu.l2cache.ReadReq_miss_latency::total 1097047500 # number of ReadReq miss cycles 442system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles 443system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles 444system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6075862000 # number of ReadExReq miss cycles 445system.cpu.l2cache.ReadExReq_miss_latency::total 6075862000 # number of ReadExReq miss cycles | 424system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 561610000 # number of ReadReq miss cycles 425system.cpu.l2cache.ReadReq_miss_latency::cpu.data 535948000 # number of ReadReq miss cycles 426system.cpu.l2cache.ReadReq_miss_latency::total 1098024500 # number of ReadReq miss cycles 427system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 462000 # number of UpgradeReq miss cycles 428system.cpu.l2cache.UpgradeReq_miss_latency::total 462000 # number of UpgradeReq miss cycles 429system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6083213000 # number of ReadExReq miss cycles 430system.cpu.l2cache.ReadExReq_miss_latency::total 6083213000 # number of ReadExReq miss cycles |
| 446system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 315500 # number of demand (read+write) miss cycles 447system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 151000 # number of demand (read+write) miss cycles | 431system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 315500 # number of demand (read+write) miss cycles 432system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 151000 # number of demand (read+write) miss cycles |
| 448system.cpu.l2cache.demand_miss_latency::cpu.inst 562062000 # number of demand (read+write) miss cycles 449system.cpu.l2cache.demand_miss_latency::cpu.data 6610381000 # number of demand (read+write) miss cycles 450system.cpu.l2cache.demand_miss_latency::total 7172909500 # number of demand (read+write) miss cycles | 433system.cpu.l2cache.demand_miss_latency::cpu.inst 561610000 # number of demand (read+write) miss cycles 434system.cpu.l2cache.demand_miss_latency::cpu.data 6619161000 # number of demand (read+write) miss cycles 435system.cpu.l2cache.demand_miss_latency::total 7181237500 # number of demand (read+write) miss cycles |
| 451system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 315500 # number of overall miss cycles 452system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 151000 # number of overall miss cycles | 436system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 315500 # number of overall miss cycles 437system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 151000 # number of overall miss cycles |
| 453system.cpu.l2cache.overall_miss_latency::cpu.inst 562062000 # number of overall miss cycles 454system.cpu.l2cache.overall_miss_latency::cpu.data 6610381000 # number of overall miss cycles 455system.cpu.l2cache.overall_miss_latency::total 7172909500 # number of overall miss cycles | 438system.cpu.l2cache.overall_miss_latency::cpu.inst 561610000 # number of overall miss cycles 439system.cpu.l2cache.overall_miss_latency::cpu.data 6619161000 # number of overall miss cycles 440system.cpu.l2cache.overall_miss_latency::total 7181237500 # number of overall miss cycles |
| 456system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8706 # number of ReadReq accesses(hits+misses) 457system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) | 441system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8706 # number of ReadReq accesses(hits+misses) 442system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3551 # number of ReadReq accesses(hits+misses) |
| 458system.cpu.l2cache.ReadReq_accesses::cpu.inst 854360 # number of ReadReq accesses(hits+misses) 459system.cpu.l2cache.ReadReq_accesses::cpu.data 380193 # number of ReadReq accesses(hits+misses) 460system.cpu.l2cache.ReadReq_accesses::total 1246810 # number of ReadReq accesses(hits+misses) 461system.cpu.l2cache.Writeback_accesses::writebacks 596039 # number of Writeback accesses(hits+misses) 462system.cpu.l2cache.Writeback_accesses::total 596039 # number of Writeback accesses(hits+misses) | 443system.cpu.l2cache.ReadReq_accesses::cpu.inst 854358 # number of ReadReq accesses(hits+misses) 444system.cpu.l2cache.ReadReq_accesses::cpu.data 380187 # number of ReadReq accesses(hits+misses) 445system.cpu.l2cache.ReadReq_accesses::total 1246802 # number of ReadReq accesses(hits+misses) 446system.cpu.l2cache.Writeback_accesses::writebacks 596040 # number of Writeback accesses(hits+misses) 447system.cpu.l2cache.Writeback_accesses::total 596040 # number of Writeback accesses(hits+misses) |
| 463system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses) 464system.cpu.l2cache.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) | 448system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2901 # number of UpgradeReq accesses(hits+misses) 449system.cpu.l2cache.UpgradeReq_accesses::total 2901 # number of UpgradeReq accesses(hits+misses) |
| 465system.cpu.l2cache.ReadExReq_accesses::cpu.data 247610 # number of ReadExReq accesses(hits+misses) 466system.cpu.l2cache.ReadExReq_accesses::total 247610 # number of ReadExReq accesses(hits+misses) | 450system.cpu.l2cache.ReadExReq_accesses::cpu.data 247621 # number of ReadExReq accesses(hits+misses) 451system.cpu.l2cache.ReadExReq_accesses::total 247621 # number of ReadExReq accesses(hits+misses) |
| 467system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8706 # number of demand (read+write) accesses 468system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses | 452system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8706 # number of demand (read+write) accesses 453system.cpu.l2cache.demand_accesses::cpu.itb.walker 3551 # number of demand (read+write) accesses |
| 469system.cpu.l2cache.demand_accesses::cpu.inst 854360 # number of demand (read+write) accesses 470system.cpu.l2cache.demand_accesses::cpu.data 627803 # number of demand (read+write) accesses 471system.cpu.l2cache.demand_accesses::total 1494420 # number of demand (read+write) accesses | 454system.cpu.l2cache.demand_accesses::cpu.inst 854358 # number of demand (read+write) accesses 455system.cpu.l2cache.demand_accesses::cpu.data 627808 # number of demand (read+write) accesses 456system.cpu.l2cache.demand_accesses::total 1494423 # number of demand (read+write) accesses |
| 472system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8706 # number of overall (read+write) accesses 473system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses | 457system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8706 # number of overall (read+write) accesses 458system.cpu.l2cache.overall_accesses::cpu.itb.walker 3551 # number of overall (read+write) accesses |
| 474system.cpu.l2cache.overall_accesses::cpu.inst 854360 # number of overall (read+write) accesses 475system.cpu.l2cache.overall_accesses::cpu.data 627803 # number of overall (read+write) accesses 476system.cpu.l2cache.overall_accesses::total 1494420 # number of overall (read+write) accesses | 459system.cpu.l2cache.overall_accesses::cpu.inst 854358 # number of overall (read+write) accesses 460system.cpu.l2cache.overall_accesses::cpu.data 627808 # number of overall (read+write) accesses 461system.cpu.l2cache.overall_accesses::total 1494423 # number of overall (read+write) accesses |
| 477system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses 478system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses | 462system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000574 # miss rate for ReadReq accesses 463system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000845 # miss rate for ReadReq accesses |
| 479system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012406 # miss rate for ReadReq accesses 480system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025929 # miss rate for ReadReq accesses 481system.cpu.l2cache.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses | 464system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012412 # miss rate for ReadReq accesses 465system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025932 # miss rate for ReadReq accesses 466system.cpu.l2cache.ReadReq_miss_rate::total 0.016419 # miss rate for ReadReq accesses |
| 482system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses 483system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses | 467system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991038 # miss rate for UpgradeReq accesses 468system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991038 # miss rate for UpgradeReq accesses |
| 484system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537874 # miss rate for ReadExReq accesses 485system.cpu.l2cache.ReadExReq_miss_rate::total 0.537874 # miss rate for ReadExReq accesses | 469system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.537850 # miss rate for ReadExReq accesses 470system.cpu.l2cache.ReadExReq_miss_rate::total 0.537850 # miss rate for ReadExReq accesses |
| 486system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses 487system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses | 471system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000574 # miss rate for demand accesses 472system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000845 # miss rate for demand accesses |
| 488system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012406 # miss rate for demand accesses | 473system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012412 # miss rate for demand accesses |
| 489system.cpu.l2cache.demand_miss_rate::cpu.data 0.227844 # miss rate for demand accesses | 474system.cpu.l2cache.demand_miss_rate::cpu.data 0.227844 # miss rate for demand accesses |
| 490system.cpu.l2cache.demand_miss_rate::total 0.102814 # miss rate for demand accesses | 475system.cpu.l2cache.demand_miss_rate::total 0.102818 # miss rate for demand accesses |
| 491system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses 492system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses | 476system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000574 # miss rate for overall accesses 477system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000845 # miss rate for overall accesses |
| 493system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012406 # miss rate for overall accesses | 478system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012412 # miss rate for overall accesses |
| 494system.cpu.l2cache.overall_miss_rate::cpu.data 0.227844 # miss rate for overall accesses | 479system.cpu.l2cache.overall_miss_rate::cpu.data 0.227844 # miss rate for overall accesses |
| 495system.cpu.l2cache.overall_miss_rate::total 0.102814 # miss rate for overall accesses | 480system.cpu.l2cache.overall_miss_rate::total 0.102818 # miss rate for overall accesses |
| 496system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 63100 # average ReadReq miss latency 497system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 50333.333333 # average ReadReq miss latency | 481system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 63100 # average ReadReq miss latency 482system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 50333.333333 # average ReadReq miss latency |
| 498system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53029.719785 # average ReadReq miss latency 499system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54221.850274 # average ReadReq miss latency 500system.cpu.l2cache.ReadReq_avg_miss_latency::total 53606.034693 # average ReadReq miss latency 501system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160 # average UpgradeReq miss latency 502system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160 # average UpgradeReq miss latency 503system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45620.402003 # average ReadExReq miss latency 504system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45620.402003 # average ReadExReq miss latency | 483system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52962.089777 # average ReadReq miss latency 484system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54361.294249 # average ReadReq miss latency 485system.cpu.l2cache.ReadReq_avg_miss_latency::total 53638.048947 # average ReadReq miss latency 486system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 160.695652 # average UpgradeReq miss latency 487system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 160.695652 # average UpgradeReq miss latency 488system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45675.596735 # average ReadExReq miss latency 489system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45675.596735 # average ReadExReq miss latency |
| 505system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency 506system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency | 490system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency 491system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency |
| 507system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53029.719785 # average overall miss latency 508system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46213.190624 # average overall miss latency 509system.cpu.l2cache.demand_avg_miss_latency::total 46684.040795 # average overall miss latency | 492system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52962.089777 # average overall miss latency 493system.cpu.l2cache.demand_avg_miss_latency::cpu.data 46274.248123 # average overall miss latency 494system.cpu.l2cache.demand_avg_miss_latency::total 46736.417536 # average overall miss latency |
| 510system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency 511system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency | 495system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 63100 # average overall miss latency 496system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 50333.333333 # average overall miss latency |
| 512system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53029.719785 # average overall miss latency 513system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46213.190624 # average overall miss latency 514system.cpu.l2cache.overall_avg_miss_latency::total 46684.040795 # average overall miss latency | 497system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52962.089777 # average overall miss latency 498system.cpu.l2cache.overall_avg_miss_latency::cpu.data 46274.248123 # average overall miss latency 499system.cpu.l2cache.overall_avg_miss_latency::total 46736.417536 # average overall miss latency |
| 515system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 516system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 517system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 518system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 519system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 520system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 521system.cpu.l2cache.fast_writes 0 # number of fast writes performed 522system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 500system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 501system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 502system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 503system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 504system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 505system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 506system.cpu.l2cache.fast_writes 0 # number of fast writes performed 507system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 523system.cpu.l2cache.writebacks::writebacks 57461 # number of writebacks 524system.cpu.l2cache.writebacks::total 57461 # number of writebacks | 508system.cpu.l2cache.writebacks::writebacks 57463 # number of writebacks 509system.cpu.l2cache.writebacks::total 57463 # number of writebacks |
| 525system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 526system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses | 510system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses 511system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses |
| 527system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses 528system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9858 # number of ReadReq MSHR misses 529system.cpu.l2cache.ReadReq_mshr_misses::total 20465 # number of ReadReq MSHR misses | 512system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10604 # number of ReadReq MSHR misses 513system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9859 # number of ReadReq MSHR misses 514system.cpu.l2cache.ReadReq_mshr_misses::total 20471 # number of ReadReq MSHR misses |
| 530system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses 531system.cpu.l2cache.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses 532system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133183 # number of ReadExReq MSHR misses 533system.cpu.l2cache.ReadExReq_mshr_misses::total 133183 # number of ReadExReq MSHR misses 534system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 535system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses | 515system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2875 # number of UpgradeReq MSHR misses 516system.cpu.l2cache.UpgradeReq_mshr_misses::total 2875 # number of UpgradeReq MSHR misses 517system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133183 # number of ReadExReq MSHR misses 518system.cpu.l2cache.ReadExReq_mshr_misses::total 133183 # number of ReadExReq MSHR misses 519system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses 520system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses |
| 536system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses 537system.cpu.l2cache.demand_mshr_misses::cpu.data 143041 # number of demand (read+write) MSHR misses 538system.cpu.l2cache.demand_mshr_misses::total 153648 # number of demand (read+write) MSHR misses | 521system.cpu.l2cache.demand_mshr_misses::cpu.inst 10604 # number of demand (read+write) MSHR misses 522system.cpu.l2cache.demand_mshr_misses::cpu.data 143042 # number of demand (read+write) MSHR misses 523system.cpu.l2cache.demand_mshr_misses::total 153654 # number of demand (read+write) MSHR misses |
| 539system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 540system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses | 524system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses 525system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses |
| 541system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses 542system.cpu.l2cache.overall_mshr_misses::cpu.data 143041 # number of overall MSHR misses 543system.cpu.l2cache.overall_mshr_misses::total 153648 # number of overall MSHR misses 544system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 253760 # number of ReadReq MSHR miss cycles 545system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 113756 # number of ReadReq MSHR miss cycles 546system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 430665051 # number of ReadReq MSHR miss cycles 547system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 411778800 # number of ReadReq MSHR miss cycles 548system.cpu.l2cache.ReadReq_mshr_miss_latency::total 842811367 # number of ReadReq MSHR miss cycles 549system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28850324 # number of UpgradeReq MSHR miss cycles 550system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28850324 # number of UpgradeReq MSHR miss cycles 551system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4437954325 # number of ReadExReq MSHR miss cycles 552system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4437954325 # number of ReadExReq MSHR miss cycles 553system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 253760 # number of demand (read+write) MSHR miss cycles 554system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 113756 # number of demand (read+write) MSHR miss cycles 555system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 430665051 # number of demand (read+write) MSHR miss cycles 556system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4849733125 # number of demand (read+write) MSHR miss cycles 557system.cpu.l2cache.demand_mshr_miss_latency::total 5280765692 # number of demand (read+write) MSHR miss cycles 558system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 253760 # number of overall MSHR miss cycles 559system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 113756 # number of overall MSHR miss cycles 560system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 430665051 # number of overall MSHR miss cycles 561system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4849733125 # number of overall MSHR miss cycles 562system.cpu.l2cache.overall_mshr_miss_latency::total 5280765692 # number of overall MSHR miss cycles 563system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209122550 # number of ReadReq MSHR uncacheable cycles 564system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166688445815 # number of ReadReq MSHR uncacheable cycles 565system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166897568365 # number of ReadReq MSHR uncacheable cycles 566system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9173753597 # number of WriteReq MSHR uncacheable cycles 567system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9173753597 # number of WriteReq MSHR uncacheable cycles 568system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209122550 # number of overall MSHR uncacheable cycles 569system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175862199412 # number of overall MSHR uncacheable cycles 570system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176071321962 # number of overall MSHR uncacheable cycles | 526system.cpu.l2cache.overall_mshr_misses::cpu.inst 10604 # number of overall MSHR misses 527system.cpu.l2cache.overall_mshr_misses::cpu.data 143042 # number of overall MSHR misses 528system.cpu.l2cache.overall_mshr_misses::total 153654 # number of overall MSHR misses 529system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 253755 # number of ReadReq MSHR miss cycles 530system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 113753 # number of ReadReq MSHR miss cycles 531system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 430132104 # number of ReadReq MSHR miss cycles 532system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 413197859 # number of ReadReq MSHR miss cycles 533system.cpu.l2cache.ReadReq_mshr_miss_latency::total 843697471 # number of ReadReq MSHR miss cycles 534system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28847322 # number of UpgradeReq MSHR miss cycles 535system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28847322 # number of UpgradeReq MSHR miss cycles 536system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4445123890 # number of ReadExReq MSHR miss cycles 537system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4445123890 # number of ReadExReq MSHR miss cycles 538system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 253755 # number of demand (read+write) MSHR miss cycles 539system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 113753 # number of demand (read+write) MSHR miss cycles 540system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 430132104 # number of demand (read+write) MSHR miss cycles 541system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4858321749 # number of demand (read+write) MSHR miss cycles 542system.cpu.l2cache.demand_mshr_miss_latency::total 5288821361 # number of demand (read+write) MSHR miss cycles 543system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 253755 # number of overall MSHR miss cycles 544system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 113753 # number of overall MSHR miss cycles 545system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 430132104 # number of overall MSHR miss cycles 546system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4858321749 # number of overall MSHR miss cycles 547system.cpu.l2cache.overall_mshr_miss_latency::total 5288821361 # number of overall MSHR miss cycles 548system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 209116116 # number of ReadReq MSHR uncacheable cycles 549system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166689052786 # number of ReadReq MSHR uncacheable cycles 550system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166898168902 # number of ReadReq MSHR uncacheable cycles 551system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 9175171345 # number of WriteReq MSHR uncacheable cycles 552system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 9175171345 # number of WriteReq MSHR uncacheable cycles 553system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 209116116 # number of overall MSHR uncacheable cycles 554system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 175864224131 # number of overall MSHR uncacheable cycles 555system.cpu.l2cache.overall_mshr_uncacheable_latency::total 176073340247 # number of overall MSHR uncacheable cycles |
| 571system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses 572system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses | 556system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for ReadReq accesses |
| 573system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for ReadReq accesses 574system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025929 # mshr miss rate for ReadReq accesses 575system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016414 # mshr miss rate for ReadReq accesses | 558system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for ReadReq accesses 559system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025932 # mshr miss rate for ReadReq accesses 560system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016419 # mshr miss rate for ReadReq accesses |
| 576system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses 577system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses | 561system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991038 # mshr miss rate for UpgradeReq accesses 562system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991038 # mshr miss rate for UpgradeReq accesses |
| 578system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537874 # mshr miss rate for ReadExReq accesses 579system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537874 # mshr miss rate for ReadExReq accesses | 563system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.537850 # mshr miss rate for ReadExReq accesses 564system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.537850 # mshr miss rate for ReadExReq accesses |
| 580system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses 581system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses | 565system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for demand accesses 566system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for demand accesses |
| 582system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for demand accesses | 567system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for demand accesses |
| 583system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for demand accesses | 568system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for demand accesses |
| 584system.cpu.l2cache.demand_mshr_miss_rate::total 0.102814 # mshr miss rate for demand accesses | 569system.cpu.l2cache.demand_mshr_miss_rate::total 0.102818 # mshr miss rate for demand accesses |
| 585system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses 586system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses | 570system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000574 # mshr miss rate for overall accesses 571system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000845 # mshr miss rate for overall accesses |
| 587system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012406 # mshr miss rate for overall accesses | 572system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012412 # mshr miss rate for overall accesses |
| 588system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for overall accesses | 573system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.227844 # mshr miss rate for overall accesses |
| 589system.cpu.l2cache.overall_mshr_miss_rate::total 0.102814 # mshr miss rate for overall accesses 590system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average ReadReq mshr miss latency 591system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average ReadReq mshr miss latency 592system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40632.611661 # average ReadReq mshr miss latency 593system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41771.028606 # average ReadReq mshr miss latency 594system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41183.062155 # average ReadReq mshr miss latency 595system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10034.895304 # average UpgradeReq mshr miss latency 596system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10034.895304 # average UpgradeReq mshr miss latency 597system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33322.228250 # average ReadExReq mshr miss latency 598system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33322.228250 # average ReadExReq mshr miss latency 599system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency 600system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency 601system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency 602system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency 603system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency 604system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50752 # average overall mshr miss latency 605system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37918.666667 # average overall mshr miss latency 606system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40632.611661 # average overall mshr miss latency 607system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33904.496788 # average overall mshr miss latency 608system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34369.244585 # average overall mshr miss latency | 574system.cpu.l2cache.overall_mshr_miss_rate::total 0.102818 # mshr miss rate for overall accesses 575system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average ReadReq mshr miss latency 576system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average ReadReq mshr miss latency 577system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40563.193512 # average ReadReq mshr miss latency 578system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41910.727153 # average ReadReq mshr miss latency 579system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41214.277319 # average ReadReq mshr miss latency 580system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10033.851130 # average UpgradeReq mshr miss latency 581system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10033.851130 # average UpgradeReq mshr miss latency 582system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33376.060683 # average ReadExReq mshr miss latency 583system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33376.060683 # average ReadExReq mshr miss latency 584system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency 585system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency 586system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency 587system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency 588system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency 589system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 50751 # average overall mshr miss latency 590system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 37917.666667 # average overall mshr miss latency 591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40563.193512 # average overall mshr miss latency 592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33964.302436 # average overall mshr miss latency 593system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34420.329838 # average overall mshr miss latency |
| 609system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 610system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 611system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 612system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 613system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 614system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 615system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 616system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 617system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 594system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 595system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 596system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 597system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 598system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 599system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 600system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 601system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 602system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 618system.cpu.dcache.replacements 627291 # number of replacements | 603system.cpu.dcache.replacements 627296 # number of replacements |
| 619system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use | 604system.cpu.dcache.tagsinuse 511.912639 # Cycle average of tags in use |
| 620system.cpu.dcache.total_refs 23655046 # Total number of references to valid blocks. 621system.cpu.dcache.sampled_refs 627803 # Sample count of references to valid blocks. 622system.cpu.dcache.avg_refs 37.679090 # Average number of references to valid blocks. | 605system.cpu.dcache.total_refs 23655010 # Total number of references to valid blocks. 606system.cpu.dcache.sampled_refs 627808 # Sample count of references to valid blocks. 607system.cpu.dcache.avg_refs 37.678733 # Average number of references to valid blocks. |
| 623system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. 624system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor 625system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy 626system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy | 608system.cpu.dcache.warmup_cycle 472186000 # Cycle when the warmup percentage was hit. 609system.cpu.dcache.occ_blocks::cpu.data 511.912639 # Average occupied blocks per requestor 610system.cpu.dcache.occ_percent::cpu.data 0.999829 # Average percentage of cache occupancy 611system.cpu.dcache.occ_percent::total 0.999829 # Average percentage of cache occupancy |
| 627system.cpu.dcache.ReadReq_hits::cpu.data 13195134 # number of ReadReq hits 628system.cpu.dcache.ReadReq_hits::total 13195134 # number of ReadReq hits 629system.cpu.dcache.WriteReq_hits::cpu.data 9973055 # number of WriteReq hits 630system.cpu.dcache.WriteReq_hits::total 9973055 # number of WriteReq hits 631system.cpu.dcache.LoadLockedReq_hits::cpu.data 236278 # number of LoadLockedReq hits 632system.cpu.dcache.LoadLockedReq_hits::total 236278 # number of LoadLockedReq hits | 612system.cpu.dcache.ReadReq_hits::cpu.data 13195118 # number of ReadReq hits 613system.cpu.dcache.ReadReq_hits::total 13195118 # number of ReadReq hits 614system.cpu.dcache.WriteReq_hits::cpu.data 9973036 # number of WriteReq hits 615system.cpu.dcache.WriteReq_hits::total 9973036 # number of WriteReq hits 616system.cpu.dcache.LoadLockedReq_hits::cpu.data 236277 # number of LoadLockedReq hits 617system.cpu.dcache.LoadLockedReq_hits::total 236277 # number of LoadLockedReq hits |
| 633system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits 634system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits | 618system.cpu.dcache.StoreCondReq_hits::cpu.data 247678 # number of StoreCondReq hits 619system.cpu.dcache.StoreCondReq_hits::total 247678 # number of StoreCondReq hits |
| 635system.cpu.dcache.demand_hits::cpu.data 23168189 # number of demand (read+write) hits 636system.cpu.dcache.demand_hits::total 23168189 # number of demand (read+write) hits 637system.cpu.dcache.overall_hits::cpu.data 23168189 # number of overall hits 638system.cpu.dcache.overall_hits::total 23168189 # number of overall hits 639system.cpu.dcache.ReadReq_misses::cpu.data 368792 # number of ReadReq misses 640system.cpu.dcache.ReadReq_misses::total 368792 # number of ReadReq misses 641system.cpu.dcache.WriteReq_misses::cpu.data 250511 # number of WriteReq misses 642system.cpu.dcache.WriteReq_misses::total 250511 # number of WriteReq misses 643system.cpu.dcache.LoadLockedReq_misses::cpu.data 11401 # number of LoadLockedReq misses 644system.cpu.dcache.LoadLockedReq_misses::total 11401 # number of LoadLockedReq misses 645system.cpu.dcache.demand_misses::cpu.data 619303 # number of demand (read+write) misses 646system.cpu.dcache.demand_misses::total 619303 # number of demand (read+write) misses 647system.cpu.dcache.overall_misses::cpu.data 619303 # number of overall misses 648system.cpu.dcache.overall_misses::total 619303 # number of overall misses 649system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222508000 # number of ReadReq miss cycles 650system.cpu.dcache.ReadReq_miss_latency::total 5222508000 # number of ReadReq miss cycles 651system.cpu.dcache.WriteReq_miss_latency::cpu.data 8035214500 # number of WriteReq miss cycles 652system.cpu.dcache.WriteReq_miss_latency::total 8035214500 # number of WriteReq miss cycles 653system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155940000 # number of LoadLockedReq miss cycles 654system.cpu.dcache.LoadLockedReq_miss_latency::total 155940000 # number of LoadLockedReq miss cycles 655system.cpu.dcache.demand_miss_latency::cpu.data 13257722500 # number of demand (read+write) miss cycles 656system.cpu.dcache.demand_miss_latency::total 13257722500 # number of demand (read+write) miss cycles 657system.cpu.dcache.overall_miss_latency::cpu.data 13257722500 # number of overall miss cycles 658system.cpu.dcache.overall_miss_latency::total 13257722500 # number of overall miss cycles 659system.cpu.dcache.ReadReq_accesses::cpu.data 13563926 # number of ReadReq accesses(hits+misses) 660system.cpu.dcache.ReadReq_accesses::total 13563926 # number of ReadReq accesses(hits+misses) 661system.cpu.dcache.WriteReq_accesses::cpu.data 10223566 # number of WriteReq accesses(hits+misses) 662system.cpu.dcache.WriteReq_accesses::total 10223566 # number of WriteReq accesses(hits+misses) | 620system.cpu.dcache.demand_hits::cpu.data 23168154 # number of demand (read+write) hits 621system.cpu.dcache.demand_hits::total 23168154 # number of demand (read+write) hits 622system.cpu.dcache.overall_hits::cpu.data 23168154 # number of overall hits 623system.cpu.dcache.overall_hits::total 23168154 # number of overall hits 624system.cpu.dcache.ReadReq_misses::cpu.data 368785 # number of ReadReq misses 625system.cpu.dcache.ReadReq_misses::total 368785 # number of ReadReq misses 626system.cpu.dcache.WriteReq_misses::cpu.data 250522 # number of WriteReq misses 627system.cpu.dcache.WriteReq_misses::total 250522 # number of WriteReq misses 628system.cpu.dcache.LoadLockedReq_misses::cpu.data 11402 # number of LoadLockedReq misses 629system.cpu.dcache.LoadLockedReq_misses::total 11402 # number of LoadLockedReq misses 630system.cpu.dcache.demand_misses::cpu.data 619307 # number of demand (read+write) misses 631system.cpu.dcache.demand_misses::total 619307 # number of demand (read+write) misses 632system.cpu.dcache.overall_misses::cpu.data 619307 # number of overall misses 633system.cpu.dcache.overall_misses::total 619307 # number of overall misses 634system.cpu.dcache.ReadReq_miss_latency::cpu.data 5224078000 # number of ReadReq miss cycles 635system.cpu.dcache.ReadReq_miss_latency::total 5224078000 # number of ReadReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::cpu.data 8042704500 # number of WriteReq miss cycles 637system.cpu.dcache.WriteReq_miss_latency::total 8042704500 # number of WriteReq miss cycles 638system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 155711000 # number of LoadLockedReq miss cycles 639system.cpu.dcache.LoadLockedReq_miss_latency::total 155711000 # number of LoadLockedReq miss cycles 640system.cpu.dcache.demand_miss_latency::cpu.data 13266782500 # number of demand (read+write) miss cycles 641system.cpu.dcache.demand_miss_latency::total 13266782500 # number of demand (read+write) miss cycles 642system.cpu.dcache.overall_miss_latency::cpu.data 13266782500 # number of overall miss cycles 643system.cpu.dcache.overall_miss_latency::total 13266782500 # number of overall miss cycles 644system.cpu.dcache.ReadReq_accesses::cpu.data 13563903 # number of ReadReq accesses(hits+misses) 645system.cpu.dcache.ReadReq_accesses::total 13563903 # number of ReadReq accesses(hits+misses) 646system.cpu.dcache.WriteReq_accesses::cpu.data 10223558 # number of WriteReq accesses(hits+misses) 647system.cpu.dcache.WriteReq_accesses::total 10223558 # number of WriteReq accesses(hits+misses) |
| 663system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) 664system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) 665system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) 666system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) | 648system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247679 # number of LoadLockedReq accesses(hits+misses) 649system.cpu.dcache.LoadLockedReq_accesses::total 247679 # number of LoadLockedReq accesses(hits+misses) 650system.cpu.dcache.StoreCondReq_accesses::cpu.data 247678 # number of StoreCondReq accesses(hits+misses) 651system.cpu.dcache.StoreCondReq_accesses::total 247678 # number of StoreCondReq accesses(hits+misses) |
| 667system.cpu.dcache.demand_accesses::cpu.data 23787492 # number of demand (read+write) accesses 668system.cpu.dcache.demand_accesses::total 23787492 # number of demand (read+write) accesses 669system.cpu.dcache.overall_accesses::cpu.data 23787492 # number of overall (read+write) accesses 670system.cpu.dcache.overall_accesses::total 23787492 # number of overall (read+write) accesses | 652system.cpu.dcache.demand_accesses::cpu.data 23787461 # number of demand (read+write) accesses 653system.cpu.dcache.demand_accesses::total 23787461 # number of demand (read+write) accesses 654system.cpu.dcache.overall_accesses::cpu.data 23787461 # number of overall (read+write) accesses 655system.cpu.dcache.overall_accesses::total 23787461 # number of overall (read+write) accesses |
| 671system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses 672system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses | 656system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027189 # miss rate for ReadReq accesses 657system.cpu.dcache.ReadReq_miss_rate::total 0.027189 # miss rate for ReadReq accesses |
| 673system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024503 # miss rate for WriteReq accesses 674system.cpu.dcache.WriteReq_miss_rate::total 0.024503 # miss rate for WriteReq accesses 675system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046031 # miss rate for LoadLockedReq accesses 676system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046031 # miss rate for LoadLockedReq accesses | 658system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024504 # miss rate for WriteReq accesses 659system.cpu.dcache.WriteReq_miss_rate::total 0.024504 # miss rate for WriteReq accesses 660system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046035 # miss rate for LoadLockedReq accesses 661system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046035 # miss rate for LoadLockedReq accesses |
| 677system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses 678system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses 679system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses 680system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses | 662system.cpu.dcache.demand_miss_rate::cpu.data 0.026035 # miss rate for demand accesses 663system.cpu.dcache.demand_miss_rate::total 0.026035 # miss rate for demand accesses 664system.cpu.dcache.overall_miss_rate::cpu.data 0.026035 # miss rate for overall accesses 665system.cpu.dcache.overall_miss_rate::total 0.026035 # miss rate for overall accesses |
| 681system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14161.120632 # average ReadReq miss latency 682system.cpu.dcache.ReadReq_avg_miss_latency::total 14161.120632 # average ReadReq miss latency 683system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32075.296095 # average WriteReq miss latency 684system.cpu.dcache.WriteReq_avg_miss_latency::total 32075.296095 # average WriteReq miss latency 685system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13677.747566 # average LoadLockedReq miss latency 686system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13677.747566 # average LoadLockedReq miss latency 687system.cpu.dcache.demand_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency 688system.cpu.dcache.demand_avg_miss_latency::total 21407.489549 # average overall miss latency 689system.cpu.dcache.overall_avg_miss_latency::cpu.data 21407.489549 # average overall miss latency 690system.cpu.dcache.overall_avg_miss_latency::total 21407.489549 # average overall miss latency | 666system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14165.646650 # average ReadReq miss latency 667system.cpu.dcache.ReadReq_avg_miss_latency::total 14165.646650 # average ReadReq miss latency 668system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32103.785296 # average WriteReq miss latency 669system.cpu.dcache.WriteReq_avg_miss_latency::total 32103.785296 # average WriteReq miss latency 670system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13656.463778 # average LoadLockedReq miss latency 671system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13656.463778 # average LoadLockedReq miss latency 672system.cpu.dcache.demand_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency 673system.cpu.dcache.demand_avg_miss_latency::total 21421.980536 # average overall miss latency 674system.cpu.dcache.overall_avg_miss_latency::cpu.data 21421.980536 # average overall miss latency 675system.cpu.dcache.overall_avg_miss_latency::total 21421.980536 # average overall miss latency |
| 691system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 692system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 693system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 694system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 695system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 696system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 697system.cpu.dcache.fast_writes 0 # number of fast writes performed 698system.cpu.dcache.cache_copies 0 # number of cache copies performed | 676system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 677system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 678system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 679system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 680system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 681system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 682system.cpu.dcache.fast_writes 0 # number of fast writes performed 683system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 699system.cpu.dcache.writebacks::writebacks 596039 # number of writebacks 700system.cpu.dcache.writebacks::total 596039 # number of writebacks 701system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368792 # number of ReadReq MSHR misses 702system.cpu.dcache.ReadReq_mshr_misses::total 368792 # number of ReadReq MSHR misses 703system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250511 # number of WriteReq MSHR misses 704system.cpu.dcache.WriteReq_mshr_misses::total 250511 # number of WriteReq MSHR misses 705system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11401 # number of LoadLockedReq MSHR misses 706system.cpu.dcache.LoadLockedReq_mshr_misses::total 11401 # number of LoadLockedReq MSHR misses 707system.cpu.dcache.demand_mshr_misses::cpu.data 619303 # number of demand (read+write) MSHR misses 708system.cpu.dcache.demand_mshr_misses::total 619303 # number of demand (read+write) MSHR misses 709system.cpu.dcache.overall_mshr_misses::cpu.data 619303 # number of overall MSHR misses 710system.cpu.dcache.overall_mshr_misses::total 619303 # number of overall MSHR misses 711system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4484924000 # number of ReadReq MSHR miss cycles 712system.cpu.dcache.ReadReq_mshr_miss_latency::total 4484924000 # number of ReadReq MSHR miss cycles 713system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7534192500 # number of WriteReq MSHR miss cycles 714system.cpu.dcache.WriteReq_mshr_miss_latency::total 7534192500 # number of WriteReq MSHR miss cycles 715system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 133138000 # number of LoadLockedReq MSHR miss cycles 716system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 133138000 # number of LoadLockedReq MSHR miss cycles 717system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12019116500 # number of demand (read+write) MSHR miss cycles 718system.cpu.dcache.demand_mshr_miss_latency::total 12019116500 # number of demand (read+write) MSHR miss cycles 719system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12019116500 # number of overall MSHR miss cycles 720system.cpu.dcache.overall_mshr_miss_latency::total 12019116500 # number of overall MSHR miss cycles 721system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082004500 # number of ReadReq MSHR uncacheable cycles 722system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082004500 # number of ReadReq MSHR uncacheable cycles 723system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18708047000 # number of WriteReq MSHR uncacheable cycles 724system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18708047000 # number of WriteReq MSHR uncacheable cycles 725system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200790051500 # number of overall MSHR uncacheable cycles 726system.cpu.dcache.overall_mshr_uncacheable_latency::total 200790051500 # number of overall MSHR uncacheable cycles | 684system.cpu.dcache.writebacks::writebacks 596040 # number of writebacks 685system.cpu.dcache.writebacks::total 596040 # number of writebacks 686system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368785 # number of ReadReq MSHR misses 687system.cpu.dcache.ReadReq_mshr_misses::total 368785 # number of ReadReq MSHR misses 688system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250522 # number of WriteReq MSHR misses 689system.cpu.dcache.WriteReq_mshr_misses::total 250522 # number of WriteReq MSHR misses 690system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11402 # number of LoadLockedReq MSHR misses 691system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses 692system.cpu.dcache.demand_mshr_misses::cpu.data 619307 # number of demand (read+write) MSHR misses 693system.cpu.dcache.demand_mshr_misses::total 619307 # number of demand (read+write) MSHR misses 694system.cpu.dcache.overall_mshr_misses::cpu.data 619307 # number of overall MSHR misses 695system.cpu.dcache.overall_mshr_misses::total 619307 # number of overall MSHR misses 696system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4486508000 # number of ReadReq MSHR miss cycles 697system.cpu.dcache.ReadReq_mshr_miss_latency::total 4486508000 # number of ReadReq MSHR miss cycles 698system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7541660500 # number of WriteReq MSHR miss cycles 699system.cpu.dcache.WriteReq_mshr_miss_latency::total 7541660500 # number of WriteReq MSHR miss cycles 700system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 132907000 # number of LoadLockedReq MSHR miss cycles 701system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 132907000 # number of LoadLockedReq MSHR miss cycles 702system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12028168500 # number of demand (read+write) MSHR miss cycles 703system.cpu.dcache.demand_mshr_miss_latency::total 12028168500 # number of demand (read+write) MSHR miss cycles 704system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12028168500 # number of overall MSHR miss cycles 705system.cpu.dcache.overall_mshr_miss_latency::total 12028168500 # number of overall MSHR miss cycles 706system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182082624500 # number of ReadReq MSHR uncacheable cycles 707system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182082624500 # number of ReadReq MSHR uncacheable cycles 708system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 18709226000 # number of WriteReq MSHR uncacheable cycles 709system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 18709226000 # number of WriteReq MSHR uncacheable cycles 710system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200791850500 # number of overall MSHR uncacheable cycles 711system.cpu.dcache.overall_mshr_uncacheable_latency::total 200791850500 # number of overall MSHR uncacheable cycles |
| 727system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses 728system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses | 712system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027189 # mshr miss rate for ReadReq accesses 713system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027189 # mshr miss rate for ReadReq accesses |
| 729system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses 730system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses 731system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046031 # mshr miss rate for LoadLockedReq accesses 732system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046031 # mshr miss rate for LoadLockedReq accesses | 714system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024504 # mshr miss rate for WriteReq accesses 715system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024504 # mshr miss rate for WriteReq accesses 716system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses 717system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses |
| 733system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses 734system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses 735system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses 736system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses | 718system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for demand accesses 719system.cpu.dcache.demand_mshr_miss_rate::total 0.026035 # mshr miss rate for demand accesses 720system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026035 # mshr miss rate for overall accesses 721system.cpu.dcache.overall_mshr_miss_rate::total 0.026035 # mshr miss rate for overall accesses |
| 737system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12161.120632 # average ReadReq mshr miss latency 738system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12161.120632 # average ReadReq mshr miss latency 739system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30075.296095 # average WriteReq mshr miss latency 740system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30075.296095 # average WriteReq mshr miss latency 741system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11677.747566 # average LoadLockedReq mshr miss latency 742system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11677.747566 # average LoadLockedReq mshr miss latency 743system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency 744system.cpu.dcache.demand_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency 745system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19407.489549 # average overall mshr miss latency 746system.cpu.dcache.overall_avg_mshr_miss_latency::total 19407.489549 # average overall mshr miss latency | 722system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12165.646650 # average ReadReq mshr miss latency 723system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12165.646650 # average ReadReq mshr miss latency 724system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30103.785296 # average WriteReq mshr miss latency 725system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30103.785296 # average WriteReq mshr miss latency 726system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11656.463778 # average LoadLockedReq mshr miss latency 727system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11656.463778 # average LoadLockedReq mshr miss latency 728system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency 729system.cpu.dcache.demand_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency 730system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19421.980536 # average overall mshr miss latency 731system.cpu.dcache.overall_avg_mshr_miss_latency::total 19421.980536 # average overall mshr miss latency |
| 747system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 748system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 749system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 750system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 751system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 752system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 753system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 754system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 760system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 761system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 762system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 763system.iocache.blocked::no_targets 0 # number of cycles access was blocked 764system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 765system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 766system.iocache.fast_writes 0 # number of fast writes performed 767system.iocache.cache_copies 0 # number of cache copies performed | 732system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 733system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 734system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 735system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 736system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 737system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 738system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 739system.iocache.replacements 0 # number of replacements --- 5 unchanged lines hidden (view full) --- 745system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 746system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 747system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 748system.iocache.blocked::no_targets 0 # number of cycles access was blocked 749system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 750system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 751system.iocache.fast_writes 0 # number of fast writes performed 752system.iocache.cache_copies 0 # number of cache copies performed |
| 768system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of ReadReq MSHR uncacheable cycles 769system.iocache.ReadReq_mshr_uncacheable_latency::total 1199398748332 # number of ReadReq MSHR uncacheable cycles 770system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199398748332 # number of overall MSHR uncacheable cycles 771system.iocache.overall_mshr_uncacheable_latency::total 1199398748332 # number of overall MSHR uncacheable cycles | 753system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of ReadReq MSHR uncacheable cycles 754system.iocache.ReadReq_mshr_uncacheable_latency::total 1199377224257 # number of ReadReq MSHR uncacheable cycles 755system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1199377224257 # number of overall MSHR uncacheable cycles 756system.iocache.overall_mshr_uncacheable_latency::total 1199377224257 # number of overall MSHR uncacheable cycles |
| 772system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 773system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 774system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 775system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 776system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 777 778---------- End Simulation Statistics ---------- | 757system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 758system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 759system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 760system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 761system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 762 763---------- End Simulation Statistics ---------- |